Protection method, protection circuit, electronic device, and program product for a storage system

Abstract

The application relates to the technical field of data storage, and provides a protection method, a protection circuit, an electronic device and a program product of a storage system, the storage system comprising a main storage medium, the protection method comprising the following steps: monitoring, in real time, an operating state parameter of the main storage medium through a state monitoring circuit; when the operating state parameter meets a preset risk triggering condition, making the main storage medium enter a protection state by applying a preset level state to a control pin; wherein the protection state is used for preventing data in the main storage medium from being modified. According to the application, the operating state of the storage medium is acquired through the state monitoring circuit, and when the risk triggering condition is met, the main storage medium enters the protection state by using the level state of the control pin, so that the risk of accidental modification of data is reduced, and the reliability of the storage system is improved.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to methods, circuits, electronic devices and software products for protecting storage systems. Background Technology

[0002] Existing storage systems typically include primary storage media, which stores system data, operating parameters, or firmware code. During the daily operation of a storage system, the primary storage media may encounter some abnormal operating conditions.

[0003] In existing technologies, when storage media is in a specific abnormal or risky state, if write protection is implemented using software-level or indirect control methods, there is usually a certain response delay. During this delay, if write operations are not restricted in time, there is a possibility that data may be accidentally modified, overwritten, or corrupted, thereby affecting the normal operation of the system. Summary of the Invention

[0004] This application provides a method, circuit, electronic device, and program product for protecting storage systems, in order to solve the technical problem in the prior art where the protection response of storage systems is delayed when facing operational risks, resulting in the risk of data being accidentally modified.

[0005] This application provides a protection method for a storage system, the storage system including a main storage medium, the protection method including: real-time monitoring of the operating status parameters of the main storage medium through a status monitoring circuit; when the operating status parameters meet a preset risk triggering condition, applying a preset level state to a control pin to cause the main storage medium to enter a protection state; wherein, the protection state is used to prevent the data in the main storage medium from being modified.

[0006] According to the protection method for a storage system provided in this application, the operating status parameters include the bus communication status of the main storage medium, and the preset risk triggering conditions include the bus access signal being in an idle state; determining that the operating status parameters meet the preset risk triggering conditions includes: determining that the bus access signal of the main storage medium is in an idle state based on the bus communication status.

[0007] According to the protection method for a storage system provided in this application, the operating status parameters include the power supply voltage status of the main storage medium; the preset risk triggering conditions include the power supply voltage being less than the operating voltage threshold; determining that the operating status parameters meet the preset risk triggering conditions includes: determining, based on the power supply voltage status, that the power supply voltage of the main storage medium is less than the operating voltage threshold.

[0008] According to a storage system protection method provided in this application, the control pin includes a first protection pin and / or a second protection pin; the main storage medium is put into a protection state by applying a preset level state to the control pin, including: applying a preset level state to the first protection pin and / or the second protection pin to put the main storage medium into a protection state; wherein, the first protection pin is used to disable write / erase operations when in the preset level state; and the second protection pin is used to pause the current operation when in the preset level state.

[0009] According to the storage system protection method provided in this application, the main storage medium is put into a protection state by applying a preset level state to the control pin, including: directly pulling down the control pin of the main storage medium through hardware circuitry to block any erase or write operation, thereby putting the main storage medium into a protection state.

[0010] According to the protection method for a storage system provided in this application, the storage system further includes a backup storage medium, and the protection method for the storage system further includes: monitoring the startup status of the main control chip during the power-on boot phase; if no signal indicating successful startup of the main control chip is detected within a preset time period, automatically switching to the backup storage medium for booting.

[0011] According to the storage system protection method provided in this application, after automatically switching to the backup storage medium for booting, the method further includes: after the backup storage medium starts successfully, performing data repair on the primary storage medium, and after the repair verification passes, switching the next power-on boot to the primary storage medium.

[0012] According to the storage system protection method provided in this application, the automatic switching to the backup storage medium for booting includes: connecting the read channel of the main control chip to the backup storage medium by switching the multiplexing circuit.

[0013] This application also provides a protection circuit for a storage system, including: a main storage medium; a status monitoring circuit connected to the main storage medium for real-time monitoring of the operating status parameters of the main storage medium; when the operating status parameters meet preset risk triggering conditions, the main storage medium enters a protection state by applying a preset level state to a control pin; wherein the protection state is used to prevent data in the main storage medium from being modified.

[0014] The protection circuit of the storage system provided in this application further includes: a backup storage medium; a multiplexing circuit, which is connected to the main storage medium and the backup storage medium respectively, for monitoring the startup status of the main control chip during the power-on boot phase; if no signal of successful startup of the main control chip is detected within a preset time period, the circuit automatically switches to the backup storage medium for booting.

[0015] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements a protection method for the storage system as described above.

[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the protection method for the storage system as described above.

[0017] The storage system protection method, protection circuit, electronic device, and program product provided in this application include a main storage medium. This application acquires the operating status parameters of the main storage medium through a status monitoring circuit, enabling direct acquisition of the operating status at the hardware level and reducing latency in status monitoring and response. When the operating status parameters meet preset risk triggering conditions, this application triggers the protection mechanism by applying a preset level to the control pin. This control method based on physical pin levels is more direct and helps the main storage medium enter the protection state quickly and stably. Through the above-mentioned mechanism combining status monitoring and pin level control, this application can prevent data in the main storage medium from being modified when risk triggering conditions are identified, thereby reducing the probability of accidental data tampering or corruption and improving the security of the storage system during operation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is one of the flowcharts illustrating the storage system protection method provided in the embodiments of this application.

[0020] Figure 2 This is a schematic diagram of the process for risk monitoring based on operating status parameters provided in the embodiments of this application.

[0021] Figure 3 This is a second flowchart illustrating the storage system protection method provided in this application embodiment.

[0022] Figure 4 This is one of the structural schematic diagrams of the protection circuit of the storage system provided in the embodiments of this application.

[0023] Figure 5 This is a second schematic diagram of the protection circuit of the storage system provided in the embodiments of this application.

[0024] Figure 6 This is a schematic diagram of the physical structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of the embodiments of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, it can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0027] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0028] In various electronic devices, storage media, such as Flash Memory and Electrically Erasable Programmable Read-Only Memory (EEPROM), are non-volatile memories typically used to store device firmware, boot loaders, system configurations, and critical business data.

[0029] In the event of abnormal power loss, voltage drop, bus signal disorder, software malfunction, or malicious attack, the data in the storage medium may be unexpectedly erased or tampered with, which may lead to the device failing to start or malfunctioning.

[0030] Based on this, embodiments of this application provide a protection method and protection circuit for a storage system. The system can monitor the operating status of the main storage medium in real time through a status monitoring circuit. When a risk is identified, the main storage medium can be quickly put into a protection state by hardware, thereby preventing data from being modified. Furthermore, an automatic switching and repair mechanism between the main and backup storage media is provided, which improves the reliability of the storage system.

[0031] In this embodiment, the storage system can be laid out on the circuit board of electronic devices such as terminal devices or servers, and may include a main control chip and a main storage medium.

[0032] The main control chip can be connected to the main storage medium via a bus (such as SPI bus, I2C bus, parallel bus, etc.) to perform read, write, or erase operations on the main storage medium. The protection circuit is connected to the main storage medium to protect the data in the main storage medium in the event of a risk.

[0033] Optionally, the aforementioned electronic device can be any electronic device product with storage requirements, such as a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, smart car system, smart TV, server, industrial control equipment, or IoT device. This application does not limit the type of electronic device.

[0034] This application provides a method for protecting a storage system, which includes a main storage medium, and the method can be executed by a status monitoring circuit.

[0035] Please see Figure 1 , Figure 1 This is one of the flowcharts illustrating a storage system protection method provided in this application embodiment. In this embodiment, the storage system protection method may include steps S110 to S120, each step of which is as follows: S110: Monitors the operating status parameters of the main storage medium in real time through a status monitoring circuit.

[0036] S120: When the operating status parameter meets the preset risk triggering condition, the main storage medium enters the protection state by applying a preset level state to the control pin; wherein, the protection state is used to prevent the data in the main storage medium from being modified.

[0037] In this embodiment, the operating status parameter refers to a physical quantity or logical state that can characterize the current working status of the main storage medium and is associated with data security risks. The status monitoring circuit can collect the above-mentioned operating status parameters in real time or periodically through sampling pins, detection circuits, or sensors.

[0038] For example, the operating status parameters include, but are not limited to, at least one of the following: bus communication status of the main storage medium, power supply voltage status, temperature status, clock status, or access frequency status.

[0039] The preset risk trigger conditions refer to the pre-defined criteria used to determine whether the main storage medium is at risk of data modification. When the running status parameters meet the risk trigger conditions, it indicates that the main storage medium is currently facing the risk of unexpected data modification, and protection of the main storage medium is required.

[0040] The status monitoring circuit puts the main storage medium into a protection state by applying a preset level to the control pin. The control pin refers to the functional pin on the main storage medium used to control its read, write, and erase operations.

[0041] Specifically, the preset level state refers to the level state required for the main storage medium to enter the protection state, such as low level (logic 0) or high level (logic 1), which can be determined according to the pin definition of the main storage medium in actual situation.

[0042] The protected state refers to a state in which data in the main storage medium cannot be written to, erased, or tampered with. In the protected state, even if the main control chip or external circuitry issues write or erase commands to the main storage medium, the main storage medium will not perform the corresponding operations, thus ensuring data integrity and security.

[0043] It should be noted that, compared to purely software-based data protection schemes, the embodiments of this application use a status monitoring circuit to monitor the operating status and apply level signals in hardware, resulting in a faster response speed and independence from the normal operation of the software.

[0044] In the event of software malfunction, system crash, or even power failure, the hardware circuitry of this application embodiment can still reliably trigger protection, thereby overcoming the defect of software protection schemes failing in specific scenarios and improving the reliability of data protection.

[0045] In some embodiments, the operating status parameters include the bus communication status of the main storage medium, and the preset risk triggering conditions include the bus access signal being in an idle state.

[0046] Accordingly, the step of determining whether the operating status parameters meet the preset risk triggering conditions may specifically include: Based on the bus communication status, it is determined that the bus access signal of the main storage medium is in an idle state.

[0047] In this embodiment, the bus communication state refers to the communication activity state on the data bus between the main control chip and the main storage medium, which can be characterized by chip select signals, clock signals, data line signals or handshake signals on the bus.

[0048] Bus access signals are signals used to indicate whether there is a valid bus access, such as the chip select signal (CS / SS) and clock signal (SCLK) in the SPI bus.

[0049] The status monitoring circuit can acquire the chip select signal or clock signal on the bus and determine whether the bus access signal is in an idle state based on the chip select signal or clock signal.

[0050] For example, for the SPI bus, when the chip select signal remains at an invalid level (e.g., high level) for a preset duration, or when the clock signal does not change for a preset duration, it indicates that there is no valid bus access in progress, i.e., the bus access signal is in an idle state.

[0051] Understandably, during normal business operations, write or erase operations on the main storage medium are usually accompanied by continuous and regular bus accesses. However, if write or erase operations on the main storage medium still occur when the bus access signal is in an idle state, the write or erase operation is likely an unexpected operation triggered by an abnormal state or malicious behavior.

[0052] Based on this, the embodiments of this application use the bus access signal being in an idle state as one of the risk triggering conditions. When it is determined that the bus access signal is in an idle state, the state monitoring circuit applies a preset level to the control pin, causing the main storage medium to enter a protected state, thereby preventing unexpected data erasure and write operations during bus idle periods.

[0053] This application embodiment uses the idle state of the bus access signal as a risk triggering condition to identify the risk of data modification caused by unexpected bus access. It can quickly determine the risk without relying on complex protocol parsing, thus reducing the implementation complexity of the status monitoring circuit.

[0054] In some embodiments, the operating status parameters include the power supply voltage status of the main storage medium; the preset risk triggering conditions include the power supply voltage being less than the operating voltage threshold.

[0055] Accordingly, the step of determining whether the operating status parameters meet the preset risk triggering conditions may specifically include: Based on the power supply voltage status, it is determined that the power supply voltage of the main storage medium is less than the operating voltage threshold.

[0056] In this embodiment, the power supply voltage state refers to the voltage level on the power supply pin of the main storage medium, such as the VCC pin. The operating voltage threshold refers to the minimum voltage value required to ensure that the main storage medium reliably and correctly performs read, write, and erase operations.

[0057] For example, for a Flash chip with an operating voltage range of 2.7V-3.3V, the operating voltage threshold can be set to 2.7V; for a Flash chip with an operating voltage range of 1.6V-1.8V, the operating voltage threshold can be set to 1.6V. This application does not limit the specific value of the operating voltage threshold; those skilled in the art can adjust it according to the actual operating parameters of the main storage medium.

[0058] The status monitoring circuit can acquire the supply voltage of the main storage medium through a voltage detection circuit and compare the acquired supply voltage with the operating voltage threshold. When the supply voltage is less than the operating voltage threshold, it is determined that the operating status parameter meets the risk triggering condition.

[0059] Alternatively, the voltage detection circuit may employ a comparator, a voltage monitoring chip, or an analog-to-digital converter.

[0060] It is understandable that when the supply voltage drops below the operating voltage threshold, the charge pump, decoding circuit, and other components inside the main storage medium may be in an unstable state. If an erase or write operation is in progress or is accidentally triggered at this time, it can easily cause data bit flipping, page damage, or even the loss of the entire data.

[0061] Based on this, the embodiments of this application use a power supply voltage lower than the operating voltage threshold as one of the risk triggering conditions. When it is determined that the power supply voltage is lower than the operating voltage threshold, the status monitoring circuit applies a preset level to the control pin before the main storage medium loses stable power supply, causing the main storage medium to enter a protection state, thereby avoiding data corruption during power failure.

[0062] In some embodiments, in order to ensure that the protection action is completed before the supply voltage drops completely, the status monitoring circuit may be configured with an energy storage element (e.g., a capacitor) to provide power to the status monitoring circuit and the control pin for the short period of time after the main power supply drops, thereby ensuring that the protection action is reliably completed.

[0063] This embodiment uses a power supply voltage lower than the operating voltage threshold as a risk triggering condition to identify the risk of data modification under abnormal power supply scenarios such as power outages and undervoltage, effectively preventing data corruption during power outages.

[0064] It should be noted that the risk assessment based on bus communication status and the risk assessment based on power supply voltage status described above can be implemented individually or in combination. When implemented in combination, the status monitoring circuit can trigger the protection action when either the bus access signal is in an idle state or the power supply voltage is less than the operating voltage threshold is met; alternatively, it can trigger the protection action only when both conditions are met simultaneously. This application does not limit the specific combination logic and can be configured according to actual risk protection needs.

[0065] In some embodiments, the control pin includes a first protection pin and / or a second protection pin; the step of putting the main storage medium into a protection state by applying a preset level state to the control pin may specifically include: A preset level is applied to the first protection pin and / or the second protection pin to put the main storage medium into a protected state; wherein the first protection pin is used to disable write / erase operations when the preset level is applied; and the second protection pin is used to pause the current operation when the preset level is applied.

[0066] In this embodiment of the application, the first protection pin refers to a functional pin on the main storage medium used to disable write and / or erase operations. For example, the first protection pin may include a write protection pin (WP_N).

[0067] When a preset level (e.g., low level) is applied to the first protection pin, the status register of the main storage medium is locked, and any write or erase commands to the storage array are rejected, thus preventing subsequent data modification at the source.

[0068] The second protection pin refers to a function pin on the main storage medium used to pause the currently ongoing operation. For example, the second protection pin includes a reset pin or a hold pin (HOLD_N).

[0069] When a preset level (e.g., low level) is applied to the second protection pin, the main storage medium suspends the currently executing operation and maintains its internal state, thereby interrupting the ongoing erase / write operation that could cause data corruption.

[0070] It should be noted that the first protection pin and the second protection pin can be applied selectively, or both can be applied simultaneously. Specifically: In one possible implementation, a preset voltage level is applied only to the first protection pin to disable subsequent write / erase operations. This method is suitable for scenarios where there is no ongoing write / erase activity and only the need to prevent future write / erase operations is required.

[0071] In one possible implementation, a preset level is applied only to the second protection pin to pause the currently running operation. This method is suitable for scenarios where the current erase / write operation needs to be frozen immediately.

[0072] In one possible implementation, a preset voltage level is applied to both the first and second protection pins simultaneously. This approach immediately suspends the ongoing operation via the second protection pin and simultaneously disables any subsequent write / erase operations via the first protection pin, thus achieving dual and comprehensive protection for both the current and future operations.

[0073] In the above embodiments, by setting a first protection pin and a second protection pin, and selectively or in combination applying a preset level state, flexible protection for different risk scenarios is achieved.

[0074] In some embodiments, the step of putting the main storage medium into a protection state by applying a preset level state to the control pin may specifically include: By directly pulling the control pin of the main storage medium low through hardware circuitry, any erase or write operation is blocked, putting the main storage medium into a protection state.

[0075] In this embodiment, hardware circuit refers to a physical circuit composed of discrete components or integrated circuits that operates independently of software. Optionally, the hardware circuit may include at least one of a comparator, logic gate circuit, transistor, field-effect transistor (MOSFET), or programmable logic device (e.g., CPLD, FPGA).

[0076] Direct pull-low means that the hardware circuit forces the level of the control pin to a low level (logic 0) without the need for software instructions.

[0077] For example, the hardware circuit may include a comparator and a switching transistor. The first input of the comparator receives a sampled signal characterizing an operating state parameter, and the second input receives a reference signal characterizing a risk triggering condition. The output of the comparator is connected to the control terminal of the switching transistor, and the controlled terminal of the switching transistor is connected to the control pin of the main storage medium. When the operating state parameter meets the risk triggering condition, the comparator output flips, controlling the switching transistor to conduct, thereby directly pulling the control pin low, causing the main storage medium to enter a protection state.

[0078] By directly pulling the control pin low through hardware circuitry, the entire protection process does not depend on the normal operation of the processor, operating system, or application. Therefore, even in the event of software crashes, system failures, or malicious program attacks, the hardware circuitry can still reliably block erase and write operations.

[0079] Furthermore, the response time of hardware circuits is typically in the nanosecond to microsecond range, much faster than the millisecond response time of software interrupts. This allows them to complete protection in a very short time after a risk occurs, minimizing the possibility of data modification.

[0080] This application embodiment achieves data protection that is independent of software, has a fast response, and is highly reliable by directly pulling the control pin low using hardware circuitry, thus overcoming the shortcomings of software protection schemes that fail in extreme scenarios.

[0081] Please see Figure 2 , Figure 2 This is a schematic diagram of the process for risk monitoring based on operating status parameters provided in the embodiments of this application.

[0082] In this embodiment, the status monitoring circuit monitors the operating status parameters of the main storage medium ROM in real time through two parallel hardware detection logics to achieve microsecond-level rapid protection. The specific steps are as follows: In the power supply status monitoring branch, the hardware circuit monitors the power supply voltage in real time. This embodiment continuously determines whether the currently acquired power supply voltage parameter meets the preset risk triggering conditions, that is, whether the voltage is less than the set operating voltage threshold.

[0083] If the power supply voltage is determined to be not less than the threshold, it indicates that the power supply in this embodiment is normal and the logic returns to continue the monitoring operation; if the power supply voltage is determined to be less than the threshold, it indicates that this embodiment is experiencing an abnormal power outage or power drop, and at this time, the subsequent hardware protection action is immediately triggered.

[0084] In the bus communication monitoring branch, the hardware circuit monitors the ROM bus communication status in real time. Specifically, the chip select signal of the main storage medium can be detected by hardware logic devices. This embodiment continuously determines whether the operating status parameter meets the preset risk triggering condition, that is, whether the ROM is in an idle state.

[0085] If the ROM is not in an idle state, it means that the main control chip is performing a legal read / write access to the ROM, and the logic returns to continue executing the bus monitoring operation; if the ROM is detected to be in an idle state, it does not need to wait for software instructions and immediately triggers the subsequent hardware protection actions.

[0086] If the risk trigger condition of any of the above branches is met, i.e. a voltage drop occurs or the bus is idle, a physical-level blocking operation is performed, i.e., the first protection pin (WP_N) and the second protection pin (Hold_N) are pulled low.

[0087] Specifically, by directly applying a low-level state to WP_N and Hold_N of the main storage medium through hardware circuitry, the main storage medium ROM immediately enters a protection state that disables writing, erasing, and suspends the current operation.

[0088] Through the parallel hardware monitoring and execution logic described above, this embodiment not only solves the protection delay window problem caused by software polling in related solutions, but also automatically prevents random write / erase risks caused by system crashes or resets when the bus is idle. At the same time, it can immediately intercept incomplete page programming or sector erase operations at the moment of abnormal power failure, thereby fully protecting the data integrity of the main storage medium.

[0089] For example, SPI Flash, a commonly used serial non-volatile memory, is typically equipped with a write-protect pin (WP_N) and a hold pin (HOLD_N) that are active low. When the WP_N pin is low, the memory is prohibited from performing write or erase operations; when the HOLD_N pin is low, the memory suspends the current operation.

[0090] In related schemes, the WP_N and HOLD_N pins are mostly directly controlled by the general purpose input / output (GPIO) pins of the master control chip. When access to the SPI Flash is required, the master control chip will release the level limit of these two pins; after the access is completed, some master control chips will pull them low to limit subsequent access, while others will not process their state.

[0091] However, this technical solution, which relies on the main control chip software and GPIO status, has certain limitations. During system software crashes or resets, the GPIO status is often uncertain, which may cause the Flash to lose write protection. At the same time, software polling or interrupt responses usually have a time window delay, and in multi-tasking operating systems, multiple tasks may compete for GPIO control, thereby increasing the risk of protection failure.

[0092] Secondly, during firmware upgrades (OTA) or data burning, if the system experiences an unexpected power outage or restart, the ongoing page programming or block erasure operations will be forced to stop, which can easily cause Flash data corruption and thus affect the normal booting of the device.

[0093] In comparison, the storage system protection method provided in this application embodiment can achieve proactive protection of the storage medium and stable system boot, mainly including the following mechanisms: 1) Automatic hardware protection mechanism when the bus is idle.

[0094] The chip select signal (CS_N) of the SPI Flash is monitored in real time by introducing hardware logic. When the SPI bus is detected to be idle, the hardware logic automatically pulls low the WP_N and HOLD_N pins of the Flash, causing it to quickly enter write-protected mode. This hardware-based monitoring method does not rely on software state and can effectively shorten the delay time of protection response.

[0095] 2) Instant protection mechanism in case of abnormal power failure.

[0096] A detection circuit for the Flash power supply has been added to the circuit. When this detection circuit detects a drop in the Flash power supply voltage, which falls below the set normal operating voltage range, the hardware logic will immediately pull down the Flash's WP_N and HOLD_N pins. This operation can prevent incomplete write operations in the initial stage of a power failure, thereby protecting the data inside the Flash.

[0097] In some embodiments, the storage system further includes a backup storage medium.

[0098] Accordingly, the protection method for the storage system also includes the following steps: During the power-on boot phase, the startup status of the main control chip is monitored; if no signal indicating successful startup of the main control chip is detected within a preset time period, the system automatically switches to the backup storage medium for booting.

[0099] In this embodiment, the backup storage medium refers to a non-volatile memory that is independent of the main storage medium and stores a backup boot program and critical data. The backup storage medium can be the same as or a different type of memory as the main storage medium.

[0100] For example, storage media may include read-only memory (ROM), SPI Flash (Serial Peripheral Interface Flash) chips, etc.

[0101] The power-on boot phase refers to the stage after the electronic device is powered on, where the main control chip reads the boot program from the storage medium and completes the system startup. The startup status refers to the operating state of the main control chip during the power-on boot phase, such as startup in progress, startup successful, or startup failed.

[0102] A successful boot signal is a signal used to indicate that the main control chip has successfully completed the boot process. For example, a successful boot signal may include a specific level signal output by the main control chip, a handshake signal, or a heartbeat signal.

[0103] The preset time period refers to the maximum duration allowed for the main control chip to complete normal boot from the moment of power-on. The preset time period can be determined by adding a certain margin to the time required for the main control chip to boot normally; for example, the preset time period can be 500 milliseconds, 1 second, or 3 seconds, etc. This application does not limit the specific value of the preset time period.

[0104] Specifically, after the electronic device is powered on, it enters the power-on boot phase, where the main control chip begins reading the boot program from the main storage medium. A status monitoring circuit, or a dedicated switching control circuit, starts timing and monitors the boot status of the main control chip.

[0105] If a startup success signal is detected from the main control chip within the preset time period, it indicates that the boot program in the main storage medium is intact and the main control chip is booting normally. At this time, the main storage medium will continue to boot.

[0106] If no signal indicating successful startup of the main control chip is detected within the preset time period, it indicates that the main storage medium may have abnormalities such as boot program corruption or data corruption, which prevents the main control chip from starting normally.

[0107] At this point, the system automatically switches to the backup storage medium for booting, allowing the main control chip to read the backup boot program from the backup storage medium to complete the startup, thus ensuring that the electronic device can still be powered on normally even if the main storage medium is damaged.

[0108] This embodiment adopts a redundant design with dual storage media. For example, the SMS (System Management Subsystem) can be responsible for detecting the status of the main chip. When the switching condition is triggered, the switching between the main storage media and the backup storage media can be completed automatically through the underlying hardware circuitry.

[0109] This hardware-based redundancy switching scheme can effectively solve the problems of errors or startup failures that may occur in embedded devices during the power-on boot (bootstrap) stage, thereby improving the fault tolerance and operational reliability of the device.

[0110] It should be noted that the above-described automatic switching boot mechanism based on backup storage media can be implemented in combination with the protection methods of any of the above embodiments. The former provides fault tolerance and recovery capabilities during the power-on boot phase, while the latter provides data tamper-proof capabilities during the runtime phase. The two work together to form the protection of the storage system.

[0111] This application embodiment monitors the startup status of the main control chip during the power-on boot phase and automatically switches to the backup storage medium if the boot process fails to start within a timeout period. This achieves automatic fault-tolerant booting when the main storage medium is damaged, thereby improving the availability of the storage system and the startup reliability of electronic devices.

[0112] In some embodiments, the steps following automatic switching to the backup storage medium for booting may further include: Once the backup storage medium boots successfully, data repair is performed on the primary storage medium, and after the repair verification passes, the next power-on boot will switch to the primary storage medium.

[0113] In this embodiment, data repair refers to the process of overwriting, rewriting, or restoring damaged or abnormal data in the primary storage medium using backup data stored in the backup storage medium. For example, after successfully booting from the backup storage medium, the main control chip reads the backup boot program and key data from the backup storage medium and rewrites them to the damaged storage area in the primary storage medium, thereby completing the data repair of the primary storage medium.

[0114] Repair verification refers to the process of verifying the integrity of data in the repaired main storage medium.

[0115] For example, the repair verification may include the following: Calculate the checksum of the data in the primary storage medium after repair, and compare this checksum with the standard checksum of the corresponding data in the backup storage medium. If they match, the repair checksum passes, indicating that the data in the primary storage medium has been correctly repaired; if they do not match, the repair checksum fails, indicating that the repair was unsuccessful, and the data repair can be re-executed or an alarm can be output.

[0116] Once the repair verification passes, the next power-on boot will switch to the primary storage medium. In other words, after the primary storage medium is repaired during this boot cycle from the backup storage medium, the next time the electronic device is powered on, it will boot again from the repaired primary storage medium.

[0117] In this way, on the one hand, the backup medium maintains the operation and ensures the continuity of this operation, and on the other hand, the main storage medium is restored to normal through background repair, avoiding the loss of redundancy protection capabilities due to long-term reliance on the backup storage medium.

[0118] This application embodiment achieves automatic self-healing of the storage system by performing data repair on the primary storage medium after the backup storage medium has successfully started up, and switching back to the primary storage medium after verification. This restores the primary and backup redundancy capability and further improves the long-term reliability of the storage system.

[0119] In some embodiments, the step of automatically switching to an alternative storage medium for booting may specifically include: By switching the multiplexing circuit, the read channel of the main control chip is connected to the backup storage medium.

[0120] In this application embodiment, a multiplexing circuit refers to a circuit that can selectively connect multiple signal channels. For example, a multiplexing circuit may include a multiplexer (MUX), an analog switch, a bus switcher, or a programmable logic device, etc.

[0121] A read channel refers to the bus channel used by the main control chip to read data from the storage medium, such as the SPI bus channel or the chip select signal channel.

[0122] For example, the common terminal of the multiplexing circuit is connected to the read channel of the main control chip, the first selection terminal of the multiplexing circuit is connected to the main storage medium, and the second selection terminal is connected to the backup storage medium. In the default state, the multiplexing circuit connects the read channel of the main control chip to the main storage medium, and the main control chip is booted by the main storage medium.

[0123] When it is necessary to switch to the backup storage medium, the multiplexing circuit is switched to change the read channel of the main control chip from being connected to the main storage medium to being connected to the backup storage medium, so that the main control chip is now booted by the backup storage medium.

[0124] It should be noted that the switching action of the multiplexing circuit can be triggered by a status monitoring circuit, a dedicated switching control circuit, or the reset logic of the main control chip. In this embodiment, because the switching process is completed through hardware circuitry, the switching speed is fast, the reliability is high, and it does not depend on the currently potentially damaged main storage medium.

[0125] For example, when no signal indicating successful startup of the main control chip is detected within a preset time period, the switching control circuit outputs a switching control signal to control the multiplexing circuit to complete the channel switching.

[0126] By using a multiplexing circuit to switch the main control chip's read channel between the main storage medium and the backup storage medium, the hardware-based and fast switching of the main and backup storage media is realized. The switching of the boot source can be completed without complex software intervention, which improves the reliability of the switching.

[0127] The embodiments of this application employ a dual-ROM redundancy backup and self-repair mechanism. Specifically, a design with two ROMs (e.g., two SPI Flash) is used, and a ROM Select MUX logic line is configured for switching between the primary and backup media.

[0128] For example, after the system powers on, it detects the boot status of the main control chip. If the main control chip fails to boot successfully within a specified time window, the system will automatically control the multiplexer to switch to the backup ROM for booting, and record the time of boot failure and the time of starting the backup ROM. The system then controls the main control chip to reboot again; when the main control chip successfully boots based on the backup ROM, the multiplexer will automatically switch the control channel back to the main ROM, and the system will perform repair operations on the damaged data in the main ROM under successful boot status. After the main ROM is repaired, the system will configure the default boot path for the next power-on to be restored to the main ROM.

[0129] Please see Figure 3 , Figure 3This is a second flowchart illustrating the storage system protection method provided in this application embodiment.

[0130] First, the main chip of the electronic device boots up. The multiplexing circuit (MUX) connects the main chip's read channel to the main storage medium (main ROM), performs a boot operation from the main ROM, and attempts to load the boot firmware.

[0131] During this power-on boot phase, the system management module (SMS) works synchronously to detect the boot status of the main chip. The SMS module continuously monitors the boot parameters of the main chip within a preset time period and determines whether the boot process was successful based on the monitoring results. If a boot success signal is detected from the main chip within the preset time period, it indicates that the main ROM data is complete and the system boots normally. At this point, the system enters the normal operation phase and performs real-time ROM protection.

[0132] Specifically, the system hardware will monitor the bus communication status of the main ROM (such as the CS_N chip select signal being in an idle state) and the power supply voltage status (such as the voltage dropping below the operating threshold) in real time. Once any of the above risk triggering conditions are met, the hardware circuit will immediately pull down the first protection pin (WP_N) or the second protection pin (HOLD_N) to force the main ROM into write protection state, thereby preventing data from being tampered with in case of accidents.

[0133] If no signal indicating successful startup of the main chip is detected within the preset time period, or if an abnormal reset is detected, it is determined that the main ROM failed to boot due to data corruption.

[0134] At this point, without manual intervention, the system automatically switches to the backup storage medium ROM (standby ROM). The SMS module controls the multiplexing circuit to switch the main chip's read channel to the standby ROM for rebooting; at the same time, the SMS module can also record the event and time of the main ROM boot failure, providing reliable data support for subsequent system diagnosis and problem traceability.

[0135] After the main chip successfully boots the system using the healthy firmware in the backup ROM, it switches to the main ROM after a successful main chip boot. At this point, the system is already in a normal operating environment.

[0136] Next, the main ROM is repaired. The main chip uses software logic to re-flash the correct firmware data or the image from the backup ROM into the main ROM, overwriting the original damaged or incomplete data, thus completing the repair.

[0137] Finally, after the repair and verification are successful, the main chip informs the SMS module to boot from the main ROM on the next boot. The main chip will reset the relevant boot flags to ensure that the MUX channel points back to the main ROM by default when the device is powered on and restarted next time, thus completing a closed-loop high-reliability process from fault detection, isolation, backup boot to main media repair.

[0138] The above-described embodiments of this application provide a method for protecting a storage system, which has the following beneficial effects: (1) Improve system security and protection response speed. The embodiments of this application adopt a hardware-level automatic protection mechanism, which reduces the dependence on the main control chip software and operating system. When the bus is detected to be idle, the WP_N and / or HOLD_N pins are automatically pulled low, thereby reducing the risk of protection failure caused by software abnormalities or uncertain GPIO states during reset; at the same time, the hardware logic detection achieves microsecond-level response, which effectively improves the response speed and shortens the protection delay window compared with the traditional software polling method; in addition, the embodiments of this application have power failure transient protection capability, which can quickly take effect when the power supply voltage drops to block incomplete write operations; through the built-in filter circuit design, it can resist external electromagnetic noise and voltage interference to a certain extent, reduce the probability of the protection mechanism being falsely triggered, and maintain the stable operation of the system in complex environments.

[0139] (2) Enhanced equipment reliability and recovery capability. This application embodiment introduces a primary and backup dual storage media (dual ROM) redundancy architecture, which effectively reduces the risk of single point of failure. When one storage media suffers physical damage or data abnormality, it can attempt to start through the other storage media; in conjunction with status monitoring and multiplexing circuits, automatic switching is realized when the system fails to start, reducing the need for manual intervention; at the same time, this application embodiment establishes a recovery mechanism that includes detection, switching and repair. After the system successfully boots from the backup storage media, it can autonomously attempt to repair the primary storage media, which helps to reduce the equipment return rate and daily maintenance costs.

[0140] (3) Ensuring the integrity and traceability of system-level data. On the one hand, the present invention can effectively reduce the risk of the device failing to start due to firmware damage. In scenarios such as OTA upgrades, firmware burning failures, or abnormal power outages, the device can still be started and the basic operation of the system can be maintained. On the other hand, the fast locking mechanism helps to protect the integrity of the original data during abnormal power outages and avoids the problem of random values ​​or address ranges being abnormally locked. In addition, the embodiments of this application support recording the event timestamps of startup failures and switching to backup boot, which facilitates the tracing of fault nodes and provides effective data support for the subsequent operation and maintenance, troubleshooting, and device lifecycle management of the system.

[0141] This application also provides a protection circuit for a storage system. The protection circuit for the storage system provided in this application is described below. The protection circuit for the storage system described below can be referred to in correspondence with the protection method for the storage system described above.

[0142] Please see Figure 4 , Figure 4 This is one of the structural schematic diagrams of the protection circuit of the storage system provided in the embodiments of this application. In this embodiment, the protection circuit of the storage system may include the main storage medium 410 and the status monitoring circuit 420.

[0143] The status monitoring circuit 420 is connected to the main storage medium 410 and is used to monitor the operating status parameters of the main storage medium 410 in real time. When the operating status parameters meet the preset risk triggering conditions, the main storage medium 410 enters the protection state by applying a preset level state to the control pin. The protection state is used to prevent the data in the main storage medium from being modified.

[0144] The main storage medium 410 is used to store the boot program, system configuration and critical business data of the electronic device.

[0145] In this embodiment, the implementation method and working principle of the status monitoring circuit are similar to those of the status monitoring circuit in the aforementioned protection method embodiment. For example, the status monitoring circuit can determine the risk triggering condition based on the bus communication status and / or power supply voltage status, can apply a preset level to the first protection pin and / or the second protection pin, and can directly pull down the control pin through hardware circuit, etc., which will not be elaborated here.

[0146] In some embodiments, the protection circuit of the storage system further includes: a backup storage medium; a multiplexing circuit connected to the main storage medium and the backup storage medium respectively, used to monitor the startup status of the main control chip during the power-on boot phase; if no signal of successful startup of the main control chip is detected within a preset time period, the system automatically switches to the backup storage medium for booting.

[0147] The backup storage medium is used to store backup boot programs and critical data.

[0148] In this embodiment, the implementation and working principle of the multiplexing circuit are similar to those of the primary / backup switching method implemented through the multiplexing circuit in the aforementioned protection method embodiments, and will not be repeated here. It should be noted that the function of the multiplexing circuit in monitoring the startup status of the main control chip can be implemented by the timing and judgment logic built into the multiplexing circuit, or by a switching control circuit that works in conjunction with the multiplexing circuit; this embodiment does not limit this implementation.

[0149] It should be noted that the protection circuit provided in this application embodiment can be laid out on the circuit board of an electronic device or integrated into a chip. The chip may include at least one of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), or power management chips (PMICs). This application embodiment does not limit the specific carrier form of the protection circuit.

[0150] Please see Figure 5 , Figure 5 This is a second schematic diagram of the protection circuit of the storage system provided in this application embodiment. In this embodiment, the protection circuit of the storage system may include a main storage medium 510, a status monitoring circuit 520, a backup storage medium 530, and a multiplexing circuit 540.

[0151] The multiplexing circuit 540 is connected to the main control chip 500, the main storage medium 510 and the backup storage medium 530 respectively, and the status monitoring circuit 520 is connected to the main storage medium 510.

[0152] The multiplexing circuit 540 is used to monitor the startup status of the main control chip 500 during the power-on boot phase; if no signal of successful startup of the main control chip 500 is detected within a preset time period, the circuit will automatically switch to the backup storage medium 530 for booting.

[0153] The protection circuit provided in this application embodiment monitors the operating status of the main storage medium in real time through a status monitoring circuit and quickly applies a protection level when a risk occurs, thus achieving data anti-tampering protection that is independent of software and responds quickly. Furthermore, through a backup storage medium and a multiplexing circuit, it achieves automatic fault-tolerant booting when the main storage medium is damaged, thereby providing reliable protection during both the operation phase and the power-on booting phase, significantly improving the data security and availability of the storage system.

[0154] On the other hand, this application also provides an electronic device, please refer to... Figure 6 , Figure 6 This is a schematic diagram of the physical structure of the electronic device provided in the embodiments of this application, such as... Figure 6 As shown, the electronic device may include a memory 620, a processor 610, and a computer program stored in the memory 620 and executable on the processor 610. When the processor 610 executes the program, it can implement a method for protecting the storage system, which may include: The operating status parameters of the main storage medium are monitored in real time by a status monitoring circuit. When the operating status parameters meet the preset risk triggering conditions, the main storage medium enters a protection state by applying a preset level to the control pin. The protection state is used to prevent the data in the main storage medium from being modified.

[0155] Optionally, the electronic device may further include a communication bus 630 and a communication interface 640, wherein the processor 610, the communication interface 640, and the memory 620 communicate with each other via the communication bus 630. The processor 610 can call the computer program in the memory 620 to execute the storage system protection methods provided by the above methods.

[0156] Furthermore, the logical instructions in the aforementioned memory 620 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0157] On the other hand, this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can perform the storage system protection method provided by the above methods. The steps and principles of the method have been described in detail in the above methods and will not be repeated here.

[0158] Non-transitory computer-readable storage media can be any available medium or data storage device that can be accessed by a processor, including but not limited to magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MOs), etc.), optical storage (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs)).

[0159] The circuit embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0160] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for protecting a storage system, characterized in that, The storage system includes a main storage medium, and the protection method for the storage system includes: The operating status parameters of the main storage medium are monitored in real time through a status monitoring circuit. When the operating status parameter meets the preset risk triggering condition, the main storage medium enters a protection state by applying a preset level state to the control pin; wherein, the protection state is used to prevent the data in the main storage medium from being modified.

2. The method for protecting a storage system according to claim 1, characterized in that, The operating status parameters include the bus communication status of the main storage medium, and the preset risk triggering conditions include the bus access signal being in an idle state. Determining whether the operating status parameter meets the preset risk triggering conditions includes: Based on the bus communication status, it is determined that the bus access signal of the main storage medium is in an idle state.

3. The method for protecting a storage system according to claim 1, characterized in that, The operating status parameters include the power supply voltage status of the main storage medium; The preset risk triggering conditions include a power supply voltage that is less than the operating voltage threshold; Determining whether the operating status parameters meet preset risk triggering conditions includes: Based on the power supply voltage status, it is determined that the power supply voltage of the main storage medium is less than the operating voltage threshold.

4. The method for protecting a storage system according to claim 1, characterized in that, The control pin includes a first protection pin and / or a second protection pin; the step of applying a preset level to the control pin to put the main storage medium into a protection state includes: A preset level is applied to the first protection pin and / or the second protection pin to cause the main storage medium to enter a protection state. The first protection pin is used to disable write / erase operations when the preset level is reached; the second protection pin is used to pause the current operation when the preset level is reached.

5. The method for protecting a storage system according to claim 1, characterized in that, The step of putting the main storage medium into a protection state by applying a preset level to the control pin includes: By directly pulling down the control pin of the main storage medium through hardware circuitry, any erase or write operation is blocked, thus putting the main storage medium into a protected state.

6. The method for protecting a storage system according to any one of claims 1 to 5, characterized in that, The storage system further includes a backup storage medium, and the protection method for the storage system further includes: During the power-on boot phase, the startup status of the main control chip is monitored; If no signal indicating successful startup of the main control chip is detected within a preset time period, the system will automatically switch to the backup storage medium for booting.

7. The method for protecting a storage system according to claim 6, characterized in that, After automatically switching to the backup storage medium for booting, the process also includes: Once the backup storage medium starts up successfully, data repair is performed on the primary storage medium, and after the repair verification passes, the next power-on boot is switched to the primary storage medium.

8. The method for protecting a storage system according to claim 6, characterized in that, The automatic switching to the backup storage medium for booting includes: By switching the multiplexing circuit, the read channel of the main control chip is connected to the backup storage medium.

9. A protection circuit for a storage system, characterized in that, include: Main storage medium; A status monitoring circuit, connected to the main storage medium, is used to monitor the operating status parameters of the main storage medium in real time. When the operating status parameter meets the preset risk triggering condition, the main storage medium enters a protection state by applying a preset level state to the control pin; wherein, the protection state is used to prevent the data in the main storage medium from being modified.

10. The protection circuit of the storage system according to claim 9, characterized in that, Also includes: Backup storage media; A multiplexing circuit, connected to the main storage medium and the backup storage medium respectively, is used to monitor the startup status of the main control chip during the power-on boot phase; If no signal indicating successful startup of the main control chip is detected within a preset time period, the system will automatically switch to the backup storage medium for booting.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the protection method for the storage system as described in any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the protection method for the storage system as described in any one of claims 1 to 8.

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