A method and system for delayed carry processing for ternary computation

Abstract

The present application relates to the technical field of computer arithmetic and digital circuit, and particularly relates to a delay carry processing method and system for ternary calculation. At least two ternary operands are obtained and are split by bit; a delay carry representation including a value layer field and a carry layer field is established for each bit, wherein the value layer field records a ternary remainder of the bit, and the carry layer field records a number of value carries to be passed to a higher bit; in an intermediate accumulation stage, a bit sum is performed on the same bit input, the sum result is decomposed into a ternary remainder of the bit and a value carry of the bit, and the carry layer field is accumulated; the carry layer field is propagated from a lower bit to a higher bit, and a standard ternary accumulation result is generated. The present application can solve or at least alleviate the problem that in the existing ternary multi-operand accumulation process, frequent cross-bit carry propagation in the intermediate accumulation stage leads to increased inter-bit dependence and increased combinatorial logic path, and provides a delay carry processing method and system for ternary calculation.

Description

Technical Field

[0001] This invention relates to the field of computer arithmetic and digital circuit technology, and in particular to a delayed carry processing method and system for ternary calculations. Background Technology

[0002] In the field of digital circuits and computer arithmetic, adders are fundamental components in arithmetic logic units, multipliers, matrix operation units, and signal processing circuits. For binary systems, structures such as ripple carry adders, carry-lookahead adders, carry-select adders, and carry-preserving adders have formed relatively mature design systems. Among them, the carry-preserving adder reduces the impact of the carry chain on combinational delay in multi-operand addition by storing part and carry separately in the intermediate stages and performing carry propagation uniformly in the final stage.

[0003] In a ternary arithmetic system, each bit can represent three numerical states, theoretically providing high information density for the same bit width. When performing multi-operand accumulation, the ternary arithmetic unit also needs to handle issues such as summing the current bit, generating the current ternary remainder, and propagating the carry to higher bits. If the successive binary ternary addition structure is directly adopted, a carry must be generated immediately after each local addition, and this carry must be sent to the adjacent higher bit. In multi-bit, multi-operand accumulation scenarios, the carry from lower bits propagates serially to higher bits, forming a carry chain proportional to the bit width. The length of the carry chain directly affects the total delay of the critical path.

[0004] In scenarios such as ternary matrix operations, ternary multi-operand accumulators, and ternary parallel reduction trees, the frequent cross-carry propagation significantly lengthens the combinational logic path as the number of operands and bit width increase. For tree-shaped reduction structures, if instant cross-carry propagation is performed at each intermediate node, each node contains not only its own summation logic but also cross-carry propagation logic. When multiple reduction levels are cascaded, the carry chains within each level overlap with the inter-level structure, making it difficult to reduce the overall carry propagation path's logic level to the same order of magnitude as the tree height, thus limiting the scalability of the reduction tree in terms of clock frequency and parallelism.

[0005] In existing engineering projects, common methods to reduce addition delay include: using carry-lookahead or segmented carry structures to decompose or compress the carry chain; using a tree structure and a high-performance adder at each node; and in some schemes, converting ternary numbers to binary numbers, using mature binary adder and multiplier structures to complete the operation, and then restoring them to ternary form through a conversion circuit.

[0006] However, these solutions still have limitations: carry-lookahead and segmented carry require additional carry generation and propagation logic, increasing circuit area and design complexity; the conversion from ternary to binary introduces encoding conversion and bit width adaptation overhead, affecting overall resource utilization; if instantaneous cross-bit carry is still performed at each intermediate node of the tree reduction, the inter-bit dependency still exists, and the intermediate level cannot save only the current bit result and carry information as in carry-saving addition.

[0007] At its core, the key constraint in ternary multi-operand accumulators lies in coupling the generation of the current ternary remainder and the propagation of carry across bits into the same computational path during the intermediate accumulation stage. For the i-th bit, the summation of the current bit directly yields the current ternary remainder and the carry to be passed to the (i+1)-th bit. In the traditional instantaneous carry-across structure, this carry is immediately injected into the (i+1)-th bit, causing the intermediate operation of the (i+1)-th bit to wait for the carry result of the i-th bit. This bit-by-bit dependency makes it difficult to process each bit in complete parallelism during the intermediate accumulation stage, and also makes multi-operand accumulators more prone to timing bottlenecks when both the bit width and the number of operands increase simultaneously.

[0008] In summary, a new carry processing scheme is urgently needed in scenarios such as ternary multi-operand accumulation, ternary matrix operations, and ternary parallel reduction. During the intermediate accumulation stage, the ternary remainder of each bit should be stored separately from the carry count to be passed to higher bits. This allows each bit to complete its own summation and carry count accumulation without relying on immediate carry counts from adjacent lower bits. In the final normalization stage, the accumulated carry layer field of each bit should be propagated uniformly from lower to higher bits, converting it into a standard ternary higher-order value. This scheme should directly apply to the ternary numerical path, without replacing carry propagation with state flips or carry parity cancellation, and should be mappable to software algorithms, RTL logic, FPGA structures, or application-specific integrated circuits to balance numerical correctness, structural realizability, and parallel reduction capabilities. Summary of the Invention

[0009] To achieve the above-mentioned objectives, this invention provides a delayed carry processing method and system for ternary calculations, aiming to solve or at least alleviate the problems caused by frequent cross-bit carry propagation during the intermediate accumulation stage in existing ternary multi-operand accumulation processes, which leads to enhanced inter-bit dependencies, increased combinational logic paths, and limited parallel reduction.

[0010] To achieve the above objectives, the present invention provides the following technical solution: a delayed carry processing method for ternary calculation, comprising: acquiring at least two ternary operands and splitting them bit by bit; establishing a delayed carry representation for each bit, wherein the delayed carry representation includes a value layer field recording the ternary remainder of the current bit and a carry layer field recording the number of numerical carry to be passed to higher bits; in the intermediate accumulation stage, performing a bit-by-bit summation on the same input bit, decomposing the bit-by-bit summation result into the ternary remainder of the current bit and the numerical carry of the current bit, writing the ternary remainder of the current bit into the value layer field, and accumulating the numerical carry of the current bit with the carry layer field in the input delayed carry representation to form an updated carry layer field, without performing cross-bit carry propagation; in the final normalization stage, propagating each carry layer field from the least significant bit to the most significant bit to generate a standard ternary accumulation result.

[0011] To further realize the present invention, the following technical solutions may be preferred:

[0012] Preferably, establishing a delayed carry representation for each bit includes: mapping a normal ternary input bit to an initial delayed carry representation, wherein the value layer field records the value of the normal ternary input bit, and the carry layer field is set to an initial state indicating no carry to be propagated; mapping intermediate accumulation results to subsequent delayed carry representations, wherein the value layer field records the ternary remainder of the intermediate accumulation, and the carry layer field records the number of carry values ​​generated by one or more local summations that have not yet been propagated across bits.

[0013] Preferably, the step of performing local summation on the same input in the intermediate accumulation stage includes: reading the value layer field in the delayed carry representation of each input participating in this accumulation; summing the local ternary values ​​represented by the value layer field to obtain the local sum value; generating a new value layer field based on the remainder of the local sum value relative to the ternary base; and generating the local carry value based on the integer quotient of the local sum value relative to the ternary base.

[0014] Preferably, the step of accumulating the carry of the local value with the carry-in field in the input delayed carry representation includes: reading the carry-in field in each input delayed carry representation participating in this accumulation; accumulating the carry quantity to be transmitted represented by each carry-in field with the local value carry as an integer; and writing the integer accumulation result into the carry-in field of the output delayed carry representation; wherein the carry-in field is stored as the carry quantity with high bit weight and is not subject to parity cancellation, state replacement, or truncation processing.

[0015] Preferably, the non-execution of cross-bit carry propagation includes: in the same level intermediate accumulation circuit or the same intermediate accumulation operation, each bit generates the corresponding value layer field and carry layer field only according to its own input; the carry generated by the lower bit is not used as the immediate input of the higher bit in the intermediate accumulation stage of that level; the intermediate accumulation results of each bit can be generated in parallel, and cross-bit dependencies are postponed to the final normalization stage for processing.

[0016] Preferably, the final normalization stage includes: starting from the least significant bit, reading the value layer field of the current bit and the input carry from the lower bit; adding the value layer field of the current bit to the input carry from the lower bit to obtain a temporary sum for the current bit; generating a standard ternary output value for the current bit and an additional carry generated by the temporary sum for the current bit based on the temporary sum for the current bit; adding the additional carry to the number of carry to be transferred represented by the carry layer field of the current bit to obtain the input carry to be transferred to the next higher bit; and processing the higher bits sequentially until all bits and the remaining carry have been processed.

[0017] Preferably, when there is still a carry to be transmitted after the most significant bit has been processed, one or more extended high bits are generated according to the ternary carry rules until the carry to be transmitted is completely converted into standard ternary bits; the extended high bits are output as part of the standard ternary accumulation result.

[0018] A delayed carry processing system for ternary calculations includes:

[0019] The input splitting module is used to obtain at least two ternary operands and split them into multiple ternary bits according to their bit order;

[0020] The delayed carry representation storage module is used to store the value layer field and the carry layer field bit by bit. The value layer field is used to record the ternary remainder of the current position, and the carry layer field is used to record the carry quantity of the value to be transferred to the higher bit.

[0021] The bit-level delayed accumulation module is used to perform local summation on the same bit input during the intermediate accumulation stage, and generate the local ternary remainder and local value carry.

[0022] The carry counter accumulation module is used to accumulate the carry of the current value with the carry layer field in the input delayed carry representation;

[0023] The final normalization module is used to propagate the carry-level field from the least significant bit to the most significant bit and generate a standard ternary summation result;

[0024] Specifically, the bit-level delay accumulation module does not output instant carry to adjacent higher bits during the intermediate accumulation stage.

[0025] Preferably, the bit-level delay accumulation module and the carry-count accumulation module are configured in parallel as an array structure; each bit operation unit in the array structure generates the corresponding value layer field and carry layer field in the same intermediate accumulation stage; the final normalization module is configured to start after one or more intermediate accumulation stages are completed, and convert the carry layer field into a standard ternary high-bit value by means of ripple propagation, segmented propagation or prefix propagation.

[0026] A ternary delayed carry hardware circuit for implementing the above method or system includes: a ternary bit input circuit, a bit-level local summation circuit, a local remainder generation circuit, a numerical carry generation circuit, a carry count accumulation circuit, a delayed carry register array, and a final normalization circuit.

[0027] The ternary bit input circuit is connected to the bit-level summation circuit; the bit-level summation circuit is connected to the bit-level remainder generation circuit and the carry generation circuit respectively; the carry generation circuit is connected to the carry counting accumulation circuit; the bit-level remainder generation circuit and the carry counting accumulation circuit are connected to the delayed carry register array respectively; the final normalization circuit is connected to the delayed carry register array, used to read the bit-level ternary remainder and the carry quantity of each bit, and output the standard ternary accumulation result.

[0028] The beneficial effects of this invention are:

[0029] This invention separates and stores the local ternary remainder and the number of carry to be transmitted by using a value layer field and a carry layer field. This allows the intermediate accumulation stage to perform only local summation, remainder generation, and carry count accumulation, without relying on real-time carry feedback from lower bits. As a result, each arithmetic unit can generate delayed carry representations in parallel at the same intermediate accumulation stage, and cross-bit dependencies are handled in the final normalization stage. This is beneficial for constructing ternary multi-operand reduction trees, pipelined accumulators, and array-type ternary arithmetic units.

[0030] In this invention, the carry-level field is always stored as the numerical carry quantity and propagated completely to the higher bits according to the ternary carry rules during the final normalization stage. Therefore, the problem of canceling out numerical carries due to parity or converting them to a non-numerical state will not occur. This processing method keeps the ternary accumulation result consistent with standard ternary numerical operations, while providing a clear data path division for hardware implementation: the intermediate stage is completed by the bit-level local summation circuit, the remainder generation circuit, and the carry counting accumulation circuit, and the final stage is completed by the normalization circuit to propagate the cross-bit carry. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the delayed ternary data structure of the present invention.

[0032] Figure 2 This is a flowchart of the bit-level delayed addition of the present invention.

[0033] Figure 3 This is the final standardized processing flowchart of the present invention.

[0034] Figure 4 This is a schematic diagram illustrating the consistency of different reduction orders in this invention. Detailed Implementation

[0035] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Example 1

[0038] This embodiment provides a delayed carry processing system for ternary calculations. The system is used to perform multi-operand ternary accumulation, ternary parallel reduction, local accumulation in ternary matrix operations, and intermediate addition processing in ternary arithmetic logic units. The core processing object of the system is the bit-organized delayed carry representation, such as... Figure 1 As shown, the delayed carry representation includes a value layer field and a carry layer field. The value layer field records the ternary remainder of the current bit, and the carry layer field records the number of carry values ​​generated by the summation of the current bits and waiting to be passed to higher bits.

[0039] The system includes an input splitting module, a delayed carry representation storage module, a bit-level delayed accumulation module, a carry count accumulation module, a final normalization module, and an output module. In the hardware implementation, it may further include a ternary bit input circuit, a bit-level local summation circuit, a local remainder generation circuit, a numerical carry generation circuit, a carry count accumulation circuit, a delayed carry register array, and a final normalization circuit.

[0040] The input splitting module is used to acquire at least two ternary operands and split each ternary operand into multiple ternary bits according to bit order. Preferably, the system adopts a bit order organization method of least significant bit first and most significant bit last, so that the i-th bit corresponds to the ternary weight. The input splitting module can receive standard ternary encoding, non-negative ternary encoding converted from balanced ternary encoding, or bit-level data from the previous level ternary arithmetic unit. If the lengths of the input operands are different, the input splitting module can pad the more significant bits with ternary bits representing zero values ​​to form a uniform bit width.

[0041] The delayed carry representation storage module is used to store the value layer field and carry layer field bit by bit. For ordinary ternary input bits, the value layer field records the ternary value of the input bit, and the carry layer field is set to an initial state indicating that no carry is yet to be propagated. For intermediate accumulation results, the value layer field records the ternary remainder after the summation of the current bit, and the carry layer field records the number of carry generated by the summation of the current bit that has not yet been propagated across bits. This storage module can be implemented by a register array, latch array, FPGA lookup table register, on-chip SRAM, or software structure.

[0042] The bit-level delayed accumulation module performs local summation on the same bit input during intermediate accumulation stages. This module reads the value-layer fields from one or more delayed carry representations involved in the current accumulation and sums the ternary values ​​represented by these value-layer fields. The resulting local summation value is not directly propagated to higher bits; instead, it is sent to the local remainder generation path and the carry generation path. Therefore, the arithmetic units in the same intermediate accumulation stage can work in parallel without waiting for the carry result from lower bits.

[0043] The local remainder generation circuit is used to generate a new value layer field based on the local summation value. For a ternary system, this circuit outputs the remainder of the local summation value relative to the ternary base. This circuit can be implemented using combinational logic, lookup tables, small-scale read-only memory, or programmable logic units. If the bit-level delayed accumulation module combines two inputs at a time, the range of the local summation value is small, and remainder generation can be completed by simple decoding logic; if multiple inputs are combined at a time, the local summation value can be obtained first through a local summation tree, and then the remainder can be generated.

[0044] A carry generation circuit is used to generate a carry-in for the current bit based on the summation value. The carry-in is the integer quotient of the summation value relative to a ternary base. This carry-in is not used as an immediate input for the higher bit during the intermediate accumulation stage; instead, it is output to the carry-counting accumulation circuit. This configuration eliminates the immediate carry chain between the lower and higher bits during the intermediate accumulation stage, deferring cross-bit dependencies to the final normalization stage.

[0045] The carry-counting and accumulating module is used to accumulate the carry of the current bit value with the carry-level field in the input delayed carry representation. This module reads each input carry-level field participating in the current accumulation and adds it to the current bit value carry output by the carry generation circuit to obtain the updated carry-level field. The carry-level field represents the number of carry values ​​to be passed to higher bits and should be stored as a numerical value without parity cancellation, state replacement, or truncation.

[0046] In a typical architecture, the bit-level delayed accumulation module and the carry-counting accumulation module are arranged in parallel as an array structure. Each arithmetic unit in this array structure includes a bit-level local summation circuit, a local remainder generation circuit, a carry generation circuit, and a carry-counting accumulation circuit. Each arithmetic unit receives the input value layer field and carry layer field of the corresponding bit, and generates the corresponding updated value layer field and updated carry layer field in the intermediate accumulation stage at the same level. No instant carry transfer line is set between adjacent bit arithmetic units in the intermediate accumulation stage.

[0047] For multi-operand inputs, the system can employ either a cascaded array structure or a tree array structure. A cascaded array structure sequentially adds multiple operands to intermediate delayed carry representations; a tree array structure groups multiple operands, reduces them in parallel, and then further reduces the outputs of each group. Regardless of whether a cascaded or tree structure is used, the intermediate accumulation at each level maintains the same rules: the remainder of the current position is written to the value layer field, and the carry of the current position is accumulated to the carry layer field; no cross-position carry propagation is performed at intermediate levels.

[0048] The final normalization module is initiated after one or more intermediate accumulation stages have completed. Starting with the least significant bit, this module reads the value layer field, the carry layer field, and the input carry from the least significant bit. The final normalization module adds the current bit's value layer field to the input carry from the least significant bit to obtain a temporary sum; it then generates the current bit's standard ternary output value and an additional carry based on this temporary sum; finally, it adds this additional carry to the current bit's carry layer field to form the input carry to be passed to the next higher bit. This process continues bit by bit until all significant bits and remaining carries have been processed.

[0049] The final normalization module can employ a ripple propagation structure, a segmented propagation structure, or a prefix propagation structure. The ripple propagation structure is simple to implement, processing carry bits sequentially from low to high. The segmented propagation structure divides the bit width into multiple segments, performing local normalization within each segment before processing inter-segment carry bits. The prefix propagation structure can calculate some carry relationships using a parallel prefix network. All of these implementations do not alter the system's basic data flow: cross-bit carry bits are not propagated in intermediate stages, and normalization is uniformly performed in the final stage.

[0050] The output module outputs the standard ternary summation result generated by the final normalization module. If there are still carry bits to be transmitted after the most significant bit has been processed, the output module, in conjunction with the final normalization module, continues to generate extended high-order bits until the remaining carry bits are completely converted to standard ternary bits. The extended high-order bits are output as part of the final ternary summation result. If the system interface bit width is fixed, the output module can simultaneously output an overflow flag or a bit width extension request.

[0051] In the hardware circuit, the ternary bit input circuit is connected to the bit-level summation circuit. The bit-level summation circuit is connected to both the bit-level remainder generation circuit and the carry generation circuit. The output of the bit-level remainder generation circuit is connected to the value layer field storage location in the delayed carry register array. The output of the carry generation circuit is connected to the carry counter accumulation circuit. The carry counter accumulation circuit also receives the carry layer field from the input delayed carry representation and writes the accumulation result to the carry layer field storage location in the delayed carry register array. Finally, the normalization circuit is connected to the delayed carry register array and reads each bit of the value layer field and carry layer field to generate a standard ternary output.

[0052] The delayed carry register array is organized bit-by-bit, with each bit containing at least one value-level field register and one carry-level field register. The value-level field register stores the ternary remainder of the current bit. The carry-level field register stores the carry count to be passed to the higher bits. For scenarios where a large carry count may be generated in a single reduction, the bit width of the carry-level field register can be configured according to the maximum number of inputs per level and the number of reduction levels. If the carry-level field exceeds the preset representation range, the system can output an overflow flag and prevent erroneous results from being submitted.

[0053] In the software implementation, the delayed carry representation storage module can be implemented as an array, structure, or vector object. Value-level fields can use integer or enumeration types capable of representing three states, while carry-level fields can use integer types. The bit-level delayed accumulation module can be implemented as a loop or SIMD vector operation, and the final normalization module can be implemented as a scanning process from the least significant bit to the most significant bit. This software implementation follows the same data semantics as the hardware implementation.

[0054] In the pipelined implementation, the system can set input splitting, bit-level delayed accumulation, carry-count accumulation, and final normalization as different pipeline stages. The intermediate accumulation pipeline stage does not need to wait for cross-bit carry feedback, making it suitable for parallel timing in multi-bit arrays. The final normalization pipeline stage can be set as a separate final stage, or it can be divided into multiple segmented pipeline stages based on the bit width. The pipeline control logic is responsible for ensuring that the value layer field and carry layer field corresponding to the same operand set remain version consistent upon commit.

[0055] The system can also be configured with a state accumulation field and a state merging module to merge abnormal, invalid, uncertain, or reserved states associated with input operands. This state accumulation field is not part of the carry path, does not participate in the calculation of carry-level fields, and does not perform parity cancellation or state replacement on carry values. This optional state path is only passed as additional diagnostic information along with the delayed carry representation and does not affect the final ternary numerical accumulation result.

[0056] During system operation, the input splitting module first splits the ternary operand into bitwise data and writes it to the delayed carry representation storage module. Subsequently, the bit-level delayed accumulation module and the carry-counting accumulation module perform parallel intermediate accumulation on each bit to obtain the updated value layer field and carry layer field. After all intermediate accumulation or reduction stages are completed, the final normalization module performs carry propagation starting from the least significant bit and outputs the standard ternary accumulation result. The entire system avoids cross-bit instant carry chains in the intermediate stages and completes carry normalization uniformly at the final stage.

[0057] Example 2

[0058] This embodiment provides a delayed carry processing method for ternary calculations. This method is applicable to the accumulation of at least two ternary operands, and is particularly suitable for continuous accumulation of multiple operands, tree reduction, matrix element accumulation, partial ternary accumulation, and accumulation of intermediate results in ternary arithmetic logic units. This method does not change the standard ternary numerical addition rules, but rather changes the way carry is stored during the intermediate accumulation stage: the carry is not immediately propagated to higher bits during the intermediate stage, and the carry is propagated uniformly in the final stage.

[0059] Obtain at least two ternary operands and split them bit by bit; establish a delayed carry representation for each bit, wherein the delayed carry representation includes a value layer field that records the ternary remainder of the current bit and a carry layer field that records the number of carry values ​​to be passed to higher bits.

[0060] For a ternary operand, it can be divided into multiple ternary bits in ascending order of the least significant bit. Each bit establishes a deferred carry representation. This representation includes at least two fields: a value field and a carry field. The value field stores the ternary remainder of the current bit, and the carry field stores the number of carry values ​​generated by the current bit but not yet propagated to the higher bits.

[0061] For ordinary input bits, the delayed carry representation can be initialized as follows:

[0062]

[0063] in, Indicates the first Bit-level value layer field, Indicates the first The carry-level field of the bit. During normal input bit initialization, This is equivalent to inputting a ternary bit value. Setting it to '0' indicates a state where no carry needs to be passed. For intermediate accumulation results, Preserve the remainder in the base ternary representation. Store the carry-to-be-transmitted quantity generated from one or more summations of the current position.

[0064] This delayed carry representation has a clear numerical interpretation. For a given set of... A 3-bit delayed ternary number can be represented as:

[0065]

[0066] This formula explains that the carry-level field is the carry quantity of a value with a higher weight, provided that all carry-in values ​​are included in the final normalization stage. The value is passed to the high-order bit according to the ternary carry rule, and the delay representation is consistent with the standard ternary numerical representation.

[0067] If the carry is propagated immediately in each traditional intermediate accumulation stage, then the... The position needs to wait for the first... The carry result is a bitwise operation. Delayed carry means that the remainder and carry amount are stored separately, so that the processing of this bit does not depend on the immediate output of adjacent lower bits. This structure provides the data foundation for subsequent bit-level parallel accumulation.

[0068] If an illegal encoding occurs in the input ternary bits, the input parsing logic should flag the exception before writing it to the value layer field. If the carry layer field exceeds its representable range, an overflow flag should be output or the result submission should be prevented; truncating the carry layer field before normalization is not allowed. This constraint is used to ensure that numerical interpretation is not violated.

[0069] During the intermediate accumulation phase, a local summation is performed on the same input bit. The local summation result is decomposed into the local ternary remainder and the local numerical carry. The local ternary remainder is written into the value layer field, and the local numerical carry is accumulated with the carry layer field in the input delayed carry representation to form the updated carry layer field. No cross-bit carry propagation is performed.

[0070] Let the two inputs involved in this accumulation be represented by delayed carry as follows:

[0071]

[0072]

[0073] First, read the two input value fields and perform a local summation:

[0074]

[0075] Then Decompose the ternary base into the remainder and carry-over of the current value:

[0076]

[0077]

[0078] in, Write the value layer field with delayed carry representation to the output. This is the carry-over value generated by this local summation. Then, Integer accumulation with the existing carry layer field in the input delayed carry representation:

[0079]

[0080] The output delay carry representation is obtained as follows:

[0081]

[0082] The above calculations only involve the first... The input field of the digit does not need to read the digit. The instant carry-out of the first bit does not send a signal to the second bit. The carry is output immediately. Therefore, in the intermediate accumulation stage at the same level, each bit can perform the summation of its own bit, the generation of the remainder, and the accumulation of the carry count in parallel.

[0083] For cases where more than two inputs are accumulated at once, two methods can be used. The first method constructs a tree-like reduction structure using a two-input delayed accumulator, with each node executing the aforementioned rules. The second method uses a multi-input local summer to read multiple value layers at once, obtain the local sum value, and then regenerate the local remainder and local carry; simultaneously, all input carry layers are added to the local carry. Both methods have the same numerical semantics and do not perform cross-bit carry propagation in the intermediate stages.

[0084] The carry-level field stores the number of carry-in values ​​without parity cancellation, state replacement, or truncation. If a bit generates two carry-ins during consecutive reductions, the carry-level field for that bit records two carry-ins to be passed, instead of setting it to zero. This constraint differs from schemes that treat carry events as state flips, ensuring that the final normalized result is a correct standard ternary value.

[0085] This step can be implemented using software loops, SIMD vector operations, RTL combinational logic, FPGA lookup tables, or application-specific integrated circuits (ASICs). In hardware, local summation, local remainder generation, local carry generation, and carry count accumulation can be arranged within the same bit-level arithmetic unit. No instantaneous carry chains are established between different bit-level arithmetic units in intermediate stages, thereby reducing cross-bit dependencies in the same-level reduction.

[0086] When multiple ternary operands are continuously accumulated or reduced in a tree structure, the delayed carry representation obtained from each intermediate accumulation is used as the input for the next intermediate accumulation, and the value layer field and carry layer field are kept separate.

[0087] This step is used to handle multi-operand inputs. For Each ternary operand can be reduced using serial concatenation, binary tree reduction, multi-input tree reduction, or group reduction, depending on the number of operands and hardware resources. Regardless of the reduction structure used, each stage outputs the same delayed carry representation. This representation can either participate in the next bitwise summation or be sent to the final normalization stage after reduction.

[0088] For example, when multiple single Trit inputs are continuously added to the same bit, the value layer field only stores the remainder at the current bit, while the carry layer field accumulates all carry values ​​generated at that bit. For multi-bit ternary operands, each bit forms its own delayed carry representation, and carry values ​​are not propagated between bits during the intermediate reduction phase. This concentrates the propagation of cross-bit carry values, which would otherwise occur multiple times, into the final normalization phase.

[0089] In a tree-based reduction structure, different branches can process different operand arrays simultaneously. Each tree node only performs its own field processing. Since the output of a tree node is still a deferred carry representation, subsequent nodes do not need to distinguish whether the input comes from the original ternary number or from an intermediate result. This unified input / output format facilitates RTL multiplexing, pipelined insertion, and array-based routing.

[0090] In a contiguous structure, the system absorbs input operands one by one. During each absorption, the current cumulative result and the new input operand are performed bit-wise with a delay. Since a full cross-bit carry propagation is not required after each absorption, the bit-to-bit dependencies in the contiguous accumulation phase are reduced. Ultimately, normalization is performed only once after all operands have been absorbed.

[0091] The bit width of the carry layer field can be configured based on the maximum number of inputs per level, the reduction depth, and the maximum acceptable accumulation size of the system. In engineering implementations, a fixed-width carry layer field can be used, or an expandable field with overflow detection can be used. If the carry layer field is detected to exceed its representable range, an overflow should be reported or the system should switch to processing a wider field; high-order carry bits should not be discarded directly.

[0092] In the final normalization stage, each carry-level field is propagated from the least significant bit to the most significant bit to generate a standard ternary summation result.

[0093] After one or more intermediate accumulation stages, the system obtains multiple bit-delayed carry representations:

[0094]

[0095] These representations do not yet form a standard ternary result because the carry-level fields for each bit are still in their original positions. The final normalization stage is used to convert all carry-level fields into high-order ternary values.

[0096] Let the input carry from the least significant bit be... Starting from the least significant bit, first calculate the temporary sum of the current bit:

[0097]

[0098] The current standard ternary output value is:

[0099]

[0100] The additional carry generated by the temporary sum of the current bit is:

[0101]

[0102] The input carry passed to the next higher bit is:

[0103]

[0104] in, This represents the number of carry bits to be transmitted, as indicated by the carry layer field of the current bit. This formula demonstrates that the carry layer field of the current bit is fully incorporated into the carry path of the higher bit.

[0105] The final normalization process is repeated bit by bit until all significant bits have been processed. If the most significant bit has been processed... If the result is still non-zero, the extended high-order bits are generated according to the ternary carry rules. The generation process of the extended high-order bits is the same as that of ordinary ternary carry expansion, that is, the remaining carry is further decomposed into the current extended bit output and the next extended bit carry, until the remaining carry is zero. The extended high-order bits are output as part of the standard ternary accumulation result.

[0106] The final normalization stage can be implemented using a ripple structure, a segmented structure, or a prefix structure. The ripple structure propagates carry sequentially from the least significant bit to the most significant bit, resulting in a simple structure. The segmented structure divides the bit width into multiple segments, normalizing within each segment first, and then processing carry between segments. The prefix structure allows for parallel computation of carry propagation relationships. Regardless of the structure used, the same numerical relationship must be satisfied: the value layer field generates the current bit output, and the carry layer field fully participates in the propagation of carry from higher bits.

[0107] The numerical correctness of this method is based on ternary factorization with remainder. For any non-negative integer... All can be decomposed into:

[0108]

[0109] During the intermediate accumulation phase Decomposed into and .in Keep it in the current position. It is stored in the form of a carry-level field, and its place value is equivalent to Therefore, no numerical information is lost during the intermediate accumulation.

[0110] For the Bit delay carry representation Its numerical contribution is:

[0111]

[0112] The total number of digits is:

[0113]

[0114] The final normalization stage simply converts the aforementioned redundant representation into a standard ternary positional representation, without changing the total value. Therefore, as long as both the intermediate and final stages follow the above rules, the output standard ternary result is consistent with the result of directly performing ordinary ternary numerical accumulation.

[0115] This correctness specification also defines the boundaries of this method: the carry-level field must be stored as a numerical carry quantity. Any processing that cancels out the carry-level field by parity, converts it to a non-numerical state, or truncates it before final normalization is not considered part of the numerically correct path defined in this implementation.

[0116] Take the addition of four single Trit values ​​of 2 as an example. All four inputs are the least significant bit value of 2, and their decimal sum is 8. The standard ternary result should be... .

[0117] Left-associative accumulation is performed using delayed carry processing. In the first accumulation, 2+2, the sum of the current position is 4, resulting in value layer field 1. The current position carries over 1, and the carry layer field is 1. In the second accumulation, value layer field 1 is added to the third input 2, the sum of the current position is 3, resulting in value layer field 0. The current position carries over 1, and the carry layer field is 2. In the third accumulation, value layer field 0 is added to the fourth input 2, the sum of the current position is 2, resulting in value layer field 2. The current position carries over 0, and the carry layer field remains 2.

[0118] After the intermediate accumulation is completed, the least significant bit with delayed carry is represented as: In the final normalization stage, the least significant bit receives a carry-in of 0 from the lower-order input, and the current bit outputs a value of 2. The carry-in field 2 is passed to the higher-order bits. The higher-order bits receive the carry-in 2 and generate a higher-order output of 2. Therefore, the final result is... It is consistent with the decimal number 8.

[0119] Then use two ternary numbers and Taking addition as an example. The least significant bit 2 + 1 = 3, resulting in the least significant bit value layer field 0 and the carry layer field 1. The most significant bit 2 + 1 = 3, resulting in the most significant bit value layer field 0 and the carry layer field 1. During final normalization, the least significant bit is output as 0, and 1 is passed to the most significant bit; the most significant bit temporarily sums to 1, outputs 1, and its carry layer field 1 continues to be passed to higher bits; the most significant bit is extended and output as 1. The final result is... ,and The results are consistent with the standard numerical values.

[0120] In one alternative implementation, the delayed carry representation may further include a state accumulation field. The state accumulation field records any abnormal, invalid, uncertain, or reserved states carried by the input operands. This field may be stored and transmitted along with the value layer field and the carry layer field, but it does not participate in numerical carry calculations.

[0121] The merging rules for the state accumulation field can be defined according to the specific system, such as using OR operations to propagate abnormal states or using lookup tables to merge multiple types of states. Regardless of the state merging rule used, the state field must not replace the carry-level field, nor can the carry-level field be parity canceled, zeroed out, or truncated based on the state field. The numerical carry is always stored in the carry-level field and converted into a high-order ternary value in the final normalization stage.

[0122] This optional status field is only used for diagnosis, control, or anomaly propagation. If the system does not require additional status output, this field can be omitted, and the method can still perform ternary delayed carry accumulation through the value layer field and carry layer field.

[0123] This method is applicable to non-negative ternary encoding, and can also be applied to balanced ternary or other ternary encoding systems after encoding conversion. If the input is represented in balanced ternary, the encoding conversion module should first map it to the bit values ​​and carry rules suitable for this method, or redefine the corresponding remainder generation and carry generation rules.

[0124] This method does not require a fixed two-input structure for the intermediate accumulation stage. When hardware resources permit, a multi-input local summation structure can be used; when hardware resources are limited, a two-input cascaded or tree-structured reduction structure can be used. Different structures only affect the implementation method and do not change the delayed carry representation or the final normalization rules.

[0125] Example 3 Verification Test

[0126] This embodiment provides a set of examples and simulation schemes for verifying the numerical correctness and structural characteristics of the delayed carry processing method and system of the present invention. The verification focuses on: firstly, proving that the delayed carry representation remains equivalent to the standard ternary value before and after the final normalization; and secondly, demonstrating that the bit-level arithmetic unit can still correctly accumulate multiple operand inputs when cross-bit carry propagation is not performed in the intermediate accumulation stage.

[0127] 1. Example of ternary digit summation

[0128] This embodiment selects multiple single Trit inputs to verify the behavior of delayed carry representation in a unit accumulation scenario.

[0129] (1) The sum of four single Trit values ​​2

[0130] The input consists of four single Trit numbers:

[0131] Given a=2, b=2, c=2, d=2, their decimal sum is 8, which corresponds to the standard ternary result of: .

[0132] The method of this invention is used for left-associative delay accumulation. Each single Trit input is initialized with a delayed carry representation:

[0133]

[0134]

[0135]

[0136]

[0137] First accumulation and :

[0138]

[0139]

[0140]

[0141]

[0142] Obtain intermediate results .

[0143] Second accumulation and :

[0144]

[0145]

[0146]

[0147]

[0148] Obtain intermediate results .

[0149] Third accumulation and :

[0150]

[0151]

[0152]

[0153]

[0154] The final intermediate result is At this point, the value layer field is 2, and the carry layer field is 2.

[0155] Entering the final normalization stage. The least significant bit has a carry-in of 0 from the lower-order input, and the temporary sum of the current bits is:

[0156]

[0157] The current bit output value is The carry-in is:

[0158]

[0159] The input carry passed to the higher bit is:

[0160]

[0161] In the high-order bits, the initial value layer field is 0 (the high-order bits do not participate in the intermediate accumulation), and the temporary sum is:

[0162]

[0163] The high-order bit outputs 2, with no carry remaining. The final standard ternary result is: It is consistent with the decimal number 8.

[0164] This example shows that during the intermediate accumulation stage, all carry-in bits are only recorded in the carry-level field without parity cancellation; the final normalization stage propagates the carry-level field to the higher bits in its entirety, maintaining numerical correctness.

[0165] (2) Consistency of different reduction orders

[0166] for Another reduction order can be to use pairwise parallel reduction: first calculate 2+2 and 2+2, and then accumulate the two intermediate results.

[0167] The first summation of both groups yielded... and Add again:

[0168]

[0169]

[0170]

[0171]

[0172] get The delayed carry representation is completely consistent with the left-associative result. The final normalization process is the same, and the output is... .

[0173] This example illustrates that, without performing intermediate carry propagation, different intermediate reduction orders do not affect the combination of the final value layer field and the carry layer field, thus having no impact on the final ternary result.

[0174] 2. Example of summing multiple ternary numbers

[0175] This embodiment selects multiple ternary operands to verify the behavior of delayed carry representation in multi-digit scenarios.

[0176] (1) Two-digit ternary number and accumulation

[0177] Input is:

[0178]

[0179] In order of least significant bit first, the least significant bit and the most significant bit are as follows:

[0180]

[0181]

[0182] When initializing the delayed carry representation, each carry layer field is set to 0.

[0183] Accumulate from the middle of the 0th position:

[0184]

[0185]

[0186]

[0187]

[0188] get .

[0189] The first digit is accumulated in the middle:

[0190]

[0191]

[0192]

[0193]

[0194] get .

[0195] After the intermediate accumulation phase ends, the delayed carry is represented as:

[0196]

[0197] The final normalization phase begins from bit 0. The temporary sum of bit 0 is:

[0198]

[0199] Output Additional carry Inputting a carry into the first bit is:

[0200]

[0201] The first temporary sum is:

[0202]

[0203] Output Additional carry Inputting a carry to the second bit is:

[0204]

[0205] The second initial value layer field is 0, and the temporary sum is... Output No further carry-over. The final standard ternary result is: This corresponds to decimal 12, and is calculated directly. The results were consistent.

[0206] This example illustrates that in multi-bit scenarios, delayed carry means that each bit retains a carry-level field and propagates it uniformly to the higher bits during the final normalization stage to ensure the correctness of the result.

[0207] 3. Comparative Analysis with Instant Carry-Across Schemes

[0208] This embodiment illustrates the characteristics of the method of the present invention in the carry propagation path through a logical structure comparison.

[0209] In traditional real-time carry-across schemes, a carry is generated immediately after each summation of the current operand and sent to the higher-order input path. If a tree structure is used for multi-operand accumulation, the output of each intermediate node includes not only the current operand result but also the carry-across output. When multiple levels of nodes are cascaded, the carry propagation path may span multiple cascaded nodes, causing the overall delay to include multiple carry-across segments.

[0210] In the method of this invention, the bit-level delayed accumulation module in the intermediate accumulation stage generates the current bit's ternary remainder and the current bit's carry, but does not output the carry to higher bits in this stage. Each carry-level field is only stored in its current bit. The final normalization stage centrally completes the cross-bit carry propagation. Therefore, from the perspective of the intermediate accumulation level, the input to each arithmetic unit is only the current bit's value layer field and the current bit's carry layer field, and the intermediate carry chain is removed.

[0211] For the same multi-operand accumulation task, the method of this invention can construct multi-level intermediate accumulation stages into a parallel array with a large width, without embedding cross-carry chains in each array level; cross-carry propagation is instead executed uniformly in the final normalization stage. This comparison illustrates the technical effectiveness of this invention in reconstructing carry propagation paths, without relying on specific delay values ​​or specific hardware process parameters.

[0212] 4. Numerical boundary conditions and handling of anomalies

[0213] This embodiment illustrates how to maintain numerical accuracy and debuggability using the structure of the present invention in the event of overflow or anomalies.

[0214] (1) Overflow of carry-level field

[0215] If the carry-level field width at a certain bit is insufficient to represent the maximum number of carry required to represent the current reduction size, the carry counter accumulation module should check for overflow before writing to the updated carry-level field. The detection method could be to check if the accumulated result exceeds the maximum value that the carry-level field can represent. If overflow is detected, the system should output an overflow flag, trigger error handling, or switch to a wider bit-width mode, rather than simply truncating the high-order carry.

[0216] (2) Input an illegal code

[0217] If the input splitting module receives a bit value that does not conform to the expected ternary encoding rules, an encoding check should be performed before writing it into the value layer field. For detected illegal encodings, methods such as marking the bit as invalid, marking the entire operand as invalid, or issuing a diagnostic signal can be used. Regardless of the strategy adopted, illegal bits should not be mapped to valid ternary values ​​and then continue to participate in delayed carry processing, so as not to compromise the correctness of the numerical value.

[0218] (3) Optional validation of status fields

[0219] In implementing the configuration state accumulation field, simulation or testing can be used to verify that the state path does not affect the numerical path. For example, abnormal states can be injected into some inputs to check whether the final ternary numerical result is still consistent with that without abnormal states, while observing whether the state output correctly reflects the propagation of abnormalities. This verification proves that the state accumulation field only serves as additional diagnostic information and does not insert into the calculation path of carry-level or value-level fields.

[0220] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A delayed carry processing method for ternary calculations, characterized in that, include: Obtain at least two ternary operands and split them bit by bit; establish a delayed carry representation for each bit, the delayed carry representation including a value layer field recording the current ternary remainder and a carry layer field recording the number of numerical carry to be passed to higher bits; in the intermediate accumulation stage, perform a bit-by-bit summation on the same input, decompose the bit-by-bit summation result into the current ternary remainder and the current numerical carry, write the current ternary remainder into the value layer field, and accumulate the current numerical carry with the carry layer field in the input delayed carry representation to form an updated carry layer field, without performing cross-bit carry propagation; in the final normalization stage, propagate each carry layer field from the least significant bit to the most significant bit to generate a standard ternary accumulation result.

2. The delayed carry processing method according to claim 1, characterized in that, The step of establishing a delayed carry representation for each bit includes: mapping a normal ternary input bit to an initial delayed carry representation, wherein the value layer field records the value of the normal ternary input bit, and the carry layer field is set to an initial state indicating no carry to be propagated; mapping intermediate accumulation results to subsequent delayed carry representations, wherein the value layer field records the ternary remainder of the current bit after intermediate accumulation, and the carry layer field records the number of carry values ​​generated by one or more current bit summations that have not yet been propagated across bits.

3. The delayed carry processing method according to claim 1, characterized in that, The step of performing local summation on the same input during the intermediate accumulation phase includes: reading the value layer field from the delayed carry representation of each input participating in this accumulation; summing the local ternary values ​​represented by the value layer field to obtain the local sum value; generating a new value layer field based on the remainder of the local sum value relative to the ternary base; and generating the local carry value based on the integer quotient of the local sum value relative to the ternary base.

4. The delayed carry processing method according to claim 3, characterized in that, The step of accumulating the carry of the local value with the carry-in field in the input delayed carry representation includes: reading the carry-in field in each input delayed carry representation participating in this accumulation; accumulating the carry quantity to be transmitted represented by each carry-in field with the local value carry as an integer; and writing the integer accumulation result into the carry-in field of the output delayed carry representation; wherein the carry-in field is stored as the carry quantity with high bit weight and is not subject to parity cancellation, state replacement or truncation processing.

5. The delayed carry processing method according to claim 1, characterized in that, The non-execution of cross-bit carry propagation includes: in the same level intermediate accumulation circuit or the same intermediate accumulation operation, each bit generates the corresponding value layer field and carry layer field only based on its own input; the carry generated by the lower bit is not used as the immediate input of the higher bit in the intermediate accumulation stage of that level; the intermediate accumulation results of each bit can be generated in parallel, and cross-bit dependencies are postponed to the final normalization stage for processing.

6. The delayed carry processing method according to claim 1, characterized in that, The final normalization stage includes: starting from the least significant bit, reading the value layer field of the current bit and the input carry from the lower bit; adding the value layer field of the current bit to the input carry from the lower bit to obtain a temporary sum for the current bit; generating a standard ternary output value for the current bit and an additional carry generated by the temporary sum for the current bit based on the temporary sum for the current bit; adding the additional carry to the number of carry to be transferred represented by the carry layer field of the current bit to obtain the input carry to be transferred to the next higher bit; processing the higher bits in sequence until all bits and the remaining carry have been processed.

7. The delayed carry processing method according to claim 6, characterized in that, If there is still a carry to be transmitted after the most significant bit has been processed, one or more extended high bits are generated according to the ternary carry rules until the carry to be transmitted is completely converted into standard ternary bits; the extended high bits are output as part of the standard ternary accumulation result.

8. A delayed carry processing system for ternary calculations, characterized in that, include: The input splitting module is used to obtain at least two ternary operands and split them into multiple ternary bits according to their bit order; The delayed carry representation storage module is used to store the value layer field and the carry layer field bit by bit. The value layer field is used to record the ternary remainder of the current position, and the carry layer field is used to record the carry quantity of the value to be transferred to the higher bit. The bit-level delayed accumulation module is used to perform local summation on the same bit input during the intermediate accumulation stage, and generate the local ternary remainder and local value carry. The carry counter accumulation module is used to accumulate the carry of the current value with the carry layer field in the input delayed carry representation; The final normalization module is used to propagate the carry-level field from the least significant bit to the most significant bit and generate a standard ternary summation result; Specifically, the bit-level delay accumulation module does not output instant carry to adjacent higher bits during the intermediate accumulation stage.

9. The delayed carry processing system according to claim 8, characterized in that, The bit-level delay accumulation module and the carry-count accumulation module are configured in parallel bit-by-bit array structure; each bit operation unit in the array structure generates the value layer field and carry layer field corresponding to the bit in the intermediate accumulation stage of the same level. The final normalization module is configured to start after one or more intermediate accumulation stages have been completed, and to convert the carry-level field into a standard ternary high-order value using wavy propagation, segmented propagation, or prefix propagation.

10. A ternary delayed carry hardware circuit for implementing the method of any one of claims 1 to 7, characterized in that, include: The circuit consists of a ternary bit input circuit, a bit-level summation circuit, a bit-level remainder generation circuit, a numerical carry generation circuit, a carry count accumulation circuit, a delayed carry register array, and a final normalization circuit. The ternary bit input circuit is connected to the bit-level summation circuit; the bit-level summation circuit is connected to the bit-level remainder generation circuit and the carry generation circuit respectively; the carry generation circuit is connected to the carry counting accumulation circuit. The remainder generation circuit and the carry counting accumulation circuit are respectively connected to the delayed carry register array; the final normalization circuit is connected to the delayed carry register array and is used to read the ternary remainder and carry quantity of each bit, and output the standard ternary accumulation result.

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