Loop statement oriented recording and replay instruction prefetching method and apparatus

Abstract

The application relates to the technical field of computer architecture, in particular to a recording and replay instruction prefetch method and device for a loop statement, wherein the method comprises the following steps: when a branch misjudgment is detected, determining whether a current branch instruction meets a preset check condition; when it is determined that the preset check condition is met, inserting the current branch instruction into a stall address queue, and then inserting a cache line address into the stall address queue; when a new loop branch misjudgment is detected, calling a prefetch trigger and a prefetch target to write a loop-outside prefetch table; when a current loop branch instruction enters a pipeline, querying a branch target buffer; when the branch target buffer is hit and a prefetch identification bit is valid, querying the loop-outside prefetch table to obtain a corresponding prefetch target, and initiating an instruction prefetch request. Therefore, the problem that, in the related art, a loop branch misjudgment causes a FDIP to repeatedly prefetch loop body content, a loop- outside instruction cannot be prefetched, and a front-end blockage is caused, is solved.

Description

Technical Field

[0001] This application relates to the field of computer architecture technology, and in particular to a method and apparatus for prefetching recording and replaying instructions for loop statements. Background Technology

[0002] As data centers and cloud applications become increasingly complex, program execution footprints are growing larger, with working sets far exceeding the size of I-cache or even L2 cache. This leads to severe front-end bottlenecks in processors. If the front end cannot guarantee a sufficient and accurate supply of instructions, the entire pipeline back end will stagnate, severely impacting overall processor performance. Therefore, mitigating front-end congestion has become one of the core issues in modern high-performance processor design.

[0003] To alleviate processor front-end congestion, instruction prefetching is a common and efficient solution. In related technologies, commercial processors employ an FDIP (Fetch Directed Instruction Prefetcher) design for their front-ends. FDIP decouples the IFU (Instruction Fetch Unit) and BPU (Branch Predictor Unit) by introducing an FTQ (Fetch Target Queue), and utilizes look-ahead execution information provided by the BPU to prefetch instructions for potential future execution paths.

[0004] When the BPU's accuracy is high enough, deeply filled FTQs can cover the prefetch latency of lower-level caches, thus providing accurate and efficient instruction supply to the backend. However, in reality, the BPU cannot provide perfectly ideal branch prediction. When the BPU provides an incorrect prediction path, FDIP will also issue useless prefetch instructions along the incorrect path. When the pipeline detects a branch misjudgment, the pipeline flush signal from the decoding or execution unit will clear the FTQ and redirect the front-end fetch location to the correct path. However, because FDIP has not issued a prefetch on the correct path, it will cause an I-cache miss on the correct path. It has been proven that processors equipped with FDIP still have significant front-end bottlenecks. To improve FDIP prefetch performance, a deeper analysis of the BPU's bottlenecks is needed.

[0005] As the champion of CBP-1 (Championship Branch Prediction-1), TAGE-SC-L (TAgged GEometric history length predictor, Statistical Corrector, Loop predictor) is considered the most successful BPU and is widely used in modern high-performance processors. TAGE consists of multiple tables recording different history lengths, using the branch's PC (Program Counter) and the hash value of the global history information as indexes. For each branch, TAGE uses the longest global history hit result from multiple tables as the branch jump direction. However, most loop branch instructions are "jumps," with only the loop exit condition being "no jump." TAGE cannot accurately capture and determine the loop exit condition.

[0006] In summary, among the related technologies, the instruction prefetching performance of FDIP heavily depends on the accuracy of BPU. However, BPU cannot provide perfect branch prediction, especially for loop branch instructions. Misjudgment of loop branches will cause FDIP to repeatedly prefetch the loop body and fail to prefetch instructions outside the loop, thus causing unavoidable front-end blocking, which urgently needs to be solved. Summary of the Invention

[0007] This application provides a recording and replay instruction prefetching method and apparatus for loop statements, in order to solve the problem in related technologies where misjudgment of loop branches causes FDIP to repeatedly prefetch the loop body content and fail to prefetch instructions outside the loop, resulting in front-end blocking.

[0008] The first aspect of this application provides a recording and replay instruction prefetching method for loop statements, comprising the following steps: when a branch misjudgment is detected, determining whether the misjudged current branch instruction meets a preset verification condition; if the current branch instruction meets the preset verification condition, inserting the current branch instruction into a pause address queue as a candidate prefetch trigger; inserting the cache line address that caused the front-end pause into the pause address queue as a candidate prefetch target, so that when a new loop branch misjudgment is detected, the prefetch trigger and the prefetch target are retrieved from the pause address queue and written into the loop-out prefetch table; when the current loop branch instruction enters the pipeline, querying the branch target buffer; if the branch target buffer is hit and the prefetch flag in the branch target buffer is valid, querying the loop-out prefetch table according to the current loop branch instruction to obtain the corresponding prefetch target, and initiating an instruction prefetch request according to the corresponding prefetch target.

[0009] Based on the above technical means, this embodiment of the application, after detecting a branch misjudgment, filters the current branch instruction through preset verification conditions, stores the loop branches that meet the conditions into the pause address queue, and records the cache line address that causes front-end blocking. It does not require capturing the complete program instruction stream, which greatly reduces the total amount of metadata and saves on-chip storage resources. Then, when a new loop branch misjudgment is detected, the prefetch trigger and prefetch target are retrieved from the pause address queue and written into the loop prefetch table, avoiding invalid data occupying the storage space of the loop prefetch table. Then, during the pipeline instruction fetching stage, when the branch target buffer is hit and the prefetch flag is valid, the loop prefetch table is retrieved to obtain the prefetch target and an instruction prefetch request is initiated. This reduces invalid retrieval of the loop prefetch table, reduces hardware access power consumption, and specifically solves the instruction cache missing problem caused by loop branch prediction misjudgment, alleviates front-end blocking, and balances hardware area overhead and processor instruction supply efficiency.

[0010] Optionally, in one embodiment of this application, the preset verification conditions include: the jump target address of the current branch instruction is less than the address of the current branch instruction, and the current branch instruction is a direct conditional jump instruction, and the current branch instruction has not been taken.

[0011] Based on the above technical means, the embodiments of this application retain loop branch instructions with jump target addresses less than their own addresses, direct conditional jump instructions, and branch instructions that have not been executed in the current run. They filter out ordinary judgment branches and branches without front-end blocking risks, reduce the invalid storage occupation of the pause address queue and the prefetch table outside the loop, accurately lock loop branch instructions with instruction fetch blocking, and effectively improve pipeline instruction fetch efficiency.

[0012] Optionally, in one embodiment of this application, before inserting the cache line address that caused the front-end pause into the pause address queue, the method further includes: determining whether there is an empty space in the pause address queue, so that if there is an empty space in the pause address queue, the cache line address is inserted into the pause address queue.

[0013] Based on the above technical means, in this embodiment of the application, before storing the cache line address that causes front-end blocking into the pause address queue, it first determines whether there is an empty space in the pause address queue. If there is an empty space in the queue, the write is performed to avoid the pause address queue overflow causing the prefetch target to be lost. At the same time, it avoids the additional hardware power consumption caused by invalid write operations, completely saves the prefetch target address, and provides a complete data source for the subsequent construction of prefetch metadata.

[0014] Optionally, in one embodiment of this application, before writing to the prefetch table outside the loop, the method further includes: truncating bits that satisfy a preset truncation condition at the program counter address corresponding to the prefetch trigger to obtain a truncated address; and aligning the truncated address according to a preset cache line boundary to write it to the prefetch table outside the loop.

[0015] Based on the above technical means, the embodiments of this application extract bits that meet the preset extraction conditions and then write them into the out-of-loop prefetch table after aligning them with the preset cache line boundaries. This significantly shortens the address storage bit width, saves hardware storage space of the out-of-loop prefetch table, and adapts to the cache line addressing rules, thereby improving the query speed of the out-of-loop prefetch table.

[0016] Optionally, in one embodiment of this application, the method further includes setting the prefetch flag in the branch target buffer to an active state when writing to the out-of-loop prefetch table.

[0017] Based on the above technical means, the embodiments of this application extract bits that meet the preset extraction conditions and then write them into the out-of-loop prefetch table after aligning them with the preset cache line boundaries. This significantly shortens the address storage bit width, saves hardware storage space of the out-of-loop prefetch table, and adapts to the cache line addressing rules, thereby improving the query speed of the out-of-loop prefetch table.

[0018] A second aspect of this application provides a recording and replay instruction prefetching apparatus for loop statements, comprising: a first construction module, configured to, upon detecting a branch misjudgment, determine whether the misjudged current branch instruction meets a preset verification condition; if the current branch instruction meets the preset verification condition, insert the current branch instruction into a pause address queue as a candidate prefetch trigger; a second construction module, configured to insert the cache line address that causes the front-end pause into the pause address queue as a candidate prefetch target, so that, upon detecting a new loop branch misjudgment, the prefetch trigger and the prefetch target are retrieved from the pause address queue and written into an out-of-loop prefetch table; and a prefetch module, configured to, upon the current loop branch instruction entering the pipeline, query a branch target buffer; if the branch target buffer is hit and the prefetch flag in the branch target buffer is valid, query the out-of-loop prefetch table according to the current loop branch instruction to obtain the corresponding prefetch target, and initiate an instruction prefetch request according to the corresponding prefetch target.

[0019] Based on the above technical means, this embodiment of the application, after detecting a branch misjudgment, filters the current branch instruction through preset verification conditions, stores the loop branches that meet the conditions into the pause address queue, and records the cache line address that causes front-end blocking. It does not require capturing the complete program instruction stream, which greatly reduces the total amount of metadata and saves on-chip storage resources. Then, when a new loop branch misjudgment is detected, the prefetch trigger and prefetch target are retrieved from the pause address queue and written into the loop prefetch table, avoiding invalid data occupying the storage space of the loop prefetch table. Then, during the pipeline instruction fetching stage, when the branch target buffer is hit and the prefetch flag is valid, the loop prefetch table is retrieved to obtain the prefetch target and an instruction prefetch request is initiated. This reduces invalid retrieval of the loop prefetch table, reduces hardware access power consumption, and specifically solves the instruction cache missing problem caused by loop branch prediction misjudgment, alleviates front-end blocking, and balances hardware area overhead and processor instruction supply efficiency.

[0020] Optionally, in one embodiment of this application, it further includes: a truncation module, used to truncate bits on the program counter address corresponding to the prefetch trigger that satisfy a preset truncation condition to obtain a truncation address; and an alignment module, used to align the truncation address according to a preset cache line boundary to write it into the out-of-loop prefetch table.

[0021] Based on the above technical means, the embodiments of this application extract bits that meet the preset extraction conditions and then write them into the out-of-loop prefetch table after aligning them with the preset cache line boundaries. This significantly shortens the address storage bit width, saves hardware storage space of the out-of-loop prefetch table, and adapts to the cache line addressing rules, thereby improving the query speed of the out-of-loop prefetch table.

[0022] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the program to implement the recording and replay instruction prefetching method for loop-oriented statements as described in the above embodiments.

[0023] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for recording and replaying instructions for loop-oriented statements.

[0024] A fifth aspect of this application provides a computer program product, including a computer program that, when executed, implements the above-described method for recording and replaying instructions for loop-oriented statements.

[0025] This embodiment of the application, upon detecting a branch misjudgment, filters the current branch instruction using preset verification conditions, stores eligible loop branches in a pause address queue, and records the cache line address that caused front-end blocking. This eliminates the need to capture the complete program instruction stream, significantly reducing the total amount of metadata and saving on-chip storage resources. Furthermore, only when a new loop branch misjudgment is detected is the prefetch trigger retrieved from the pause address queue and the prefetch target written to the loop prefetch table. This avoids invalid data occupying the loop prefetch table's storage space. Then, during the pipeline instruction fetching stage, when the branch target buffer is hit and the prefetch flag is valid, the loop prefetch table is retrieved to obtain the prefetch target and an instruction prefetch request is initiated. This reduces invalid searches of the loop prefetch table, lowers hardware access power consumption, and specifically addresses the instruction cache miss problem caused by loop branch prediction misjudgment, alleviating front-end blocking and balancing hardware area overhead with processor instruction supply efficiency. Therefore, it solves the problem in related technologies where loop branch misjudgment leads to repeated prefetching of the loop body by the FDIP, preventing the prefetching of instructions outside the loop and causing front-end blocking.

[0026] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0027] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a processor architecture employing a fetch-directed instruction prefetcher according to an embodiment of this application; Figure 2 This is a flowchart of a recording and replay instruction prefetching method for loop statements provided according to an embodiment of this application; Figure 3 A flowchart illustrating the construction of out-of-cycle prefetcher metadata according to one embodiment of this application; Figure 4 This is a schematic diagram of the BTB (Branch Target Buffer) and the metadata format (digital unit: bits) of the prefetch table outside the loop provided according to an embodiment of this application; Figure 5 This is a flowchart of out-of-loop prefetch triggering according to one embodiment of this application; Figure 6 This is a schematic diagram of a CPU architecture design equipped with an out-of-cycle prefetcher according to an embodiment of this application; Figure 7 This is a block diagram of a recording and replay instruction prefetching device for loop-oriented statements provided in an embodiment of this application; Figure 8This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application.

[0028] Figure label: 70 - Recording and replaying instruction prefetching device for loop statements; 100 - First building block, 200 - Second building block, 300 - Prefetching module; 801 - Memory, 802 - Processor, 803 - Communication interface. Detailed Implementation

[0029] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0030] Based on background technologies, such as Figure 1 The diagram illustrates a processor architecture employing FDIP. FDIP decouples the IFU and BPU by introducing FTQ. FDIP first queries the BTB to identify branch instructions in the instruction stream. The BPU then performs branch prediction, generating speculative execution path information, which is stored in the FTQ as candidate prefetch targets. Based on this, an instruction prefetch request is initiated to the instruction cache. The IFU retrieves the prefetch target from the head of the FTQ queue and accesses the corresponding cache line for instruction predecoding. When a branch prediction error occurs, and the decoding or execution unit issues a pipeline refresh signal, the FTQ is flushed, and the instruction fetch location is redirected to the correct path. As explained in the background, FDIP can alleviate front-end blocking caused by I-cache misses, but its drawback is its high dependence on the accuracy of the BPU.

[0031] To further alleviate front-end bottlenecks, RnR (Record and Replay) instruction prefetchers are a common solution. These prefetchers involve two processes: "recording" and "replaying." During processor execution, the instruction flow is dynamically recorded. Cache lines causing front-end blocking are selected as prefetch targets, and a suitable predecessor state is chosen from the instruction flow as the trigger signature for prefetching. The relevant metadata is then stored on-chip or in memory. When the processor runs again to an instruction state matching the trigger signature, the front-end automatically prefetches the previously "recorded" cache line. PDIP (Priority Directed Instruction Prefetching) and EIP (Entangling Instruction Prefetcher) are representative instruction prefetchers. PDIP primarily identifies cache lines causing decoding starvation and uses a previous misjudged branch as the prefetch trigger condition. EIP aims to improve the timeliness of instruction prefetching by recording the instruction cache access sequence and calculating the optimal trigger predecessor signature by combining the cache lines causing I-cache misses and their access latency.

[0032] However, RnR instruction prefetchers have drawbacks. On the one hand, these prefetchers typically need to capture the entire program instruction stream in real time and generate a large amount of metadata, which consumes additional on-chip resources. On the other hand, these prefetchers usually do not focus on the fundamental factor limiting FDIP prefetch efficiency, namely the accuracy of the BPU. Recording and replaying all cache lines that cause I-cache misses makes it difficult to balance area overhead and performance gains.

[0033] To address the aforementioned shortcomings, this application proposes a method and apparatus for recording and replaying instructions for loop statements, which can dynamically detect loop branch instructions during program execution and perform targeted instruction prefetching for I-cache errors that may be caused by misjudgments of loop branches.

[0034] The following describes a method and apparatus for prefetching recording and replaying instructions for loop-oriented statements according to embodiments of this application, with reference to the accompanying drawings.

[0035] Figure 2 This is a flowchart of a recording and replay instruction prefetching method for loop statements provided according to an embodiment of this application.

[0036] like Figure 2 As shown, this method for prefetching recording and replay instructions for loop statements includes the following steps: In step S201, if a branch misjudgment is detected, it is determined whether the misjudged current branch instruction meets the preset verification conditions. If it is determined that the current branch instruction meets the preset verification conditions, the current branch instruction is inserted into the pause address queue as a candidate prefetch trigger.

[0037] It is understood that the embodiments of this application distinguish the branch type based on the numerical relationship between the jump target address and the current branch instruction address: if the jump target address is greater than the current branch instruction address, it represents a downward sequential jump, and the current branch instruction belongs to a decision branch instruction; if the jump target address is less than the current branch instruction address, it represents an upward backtracking jump, and the current branch instruction belongs to a loop branch instruction.

[0038] Optionally, in one embodiment of this application, preset verification conditions include: the jump target address of the current branch instruction is less than the address of the current branch instruction, the current branch instruction is a direct conditional jump instruction, and the current branch instruction has not been taken.

[0039] In actual execution, after the execution unit detects a branch misjudgment, this embodiment first determines whether the misjudged current branch instruction meets the preset jump conditions: the jump target address of the current branch instruction is less than the address of the current branch instruction (the current branch instruction belongs to a loop statement branch instruction); the current branch instruction is a direct conditional jump instruction (a direct conditional jump instruction has condition judgment logic and a jump target address); the current branch instruction was not taken (no jump was executed in this run). Then, if this embodiment determines that the current branch instruction meets the preset verification conditions, it stores it in the pause address queue as a candidate loop out-of-loop prefetch trigger.

[0040] This application retains loop branch instructions with a target address less than their own address, direct conditional jump instructions, and branch instructions that were not executed in the current run. It filters out ordinary judgment branches and branches without front-end blocking risk, reduces the invalid storage occupation of the pause address queue and the prefetch table outside the loop, accurately locks loop branch instructions with instruction fetch blocking, and effectively improves pipeline instruction fetch efficiency.

[0041] In step S202, the cache line address that causes the front-end pause is inserted into the pause address queue as a candidate prefetch target. In the event of a new loop branch misjudgment, the prefetch trigger and prefetch target are retrieved from the pause address queue and written into the loop out-of-loop prefetch table.

[0042] In actual execution, when a loop branch misjudgment is detected, the execution unit sends a pipeline flush signal to the pipeline predecessor stage, and the IFU redirects the instruction fetch address to the correct path outside the loop. Subsequently, this embodiment of the application begins recording the addresses of cache lines that cause front-end pauses and writes them into the pause address queue as candidate prefetch targets. If multiple cache lines cause front-end pauses, only the cache lines that meet the preset recording conditions are recorded. It should be noted that the preset recording conditions are set by those skilled in the art based on the number of cache lines that fill the FTQ and cover the critical path delay, and this application does not impose specific limitations. In some cases, the cache lines that meet the preset recording conditions are the three earliest occurring cache lines.

[0043] Furthermore, when the execution unit detects a new misjudgment of a loop branch, this embodiment of the application stops the pause address queue from recording cache lines, retrieves the previously recorded loop branch instruction as the current prefetch trigger, and matches the corresponding cache line as the prefetch target. This embodiment of the application encodes the prefetch trigger and prefetch target and writes them into the loop-outside prefetch table; the two together constitute the prefetch metadata.

[0044] Optionally, in one embodiment of this application, before inserting the cache line address that causes the front-end pause into the pause address queue, the method further includes: determining whether there is an empty space in the pause address queue, so as to insert the cache line address into the pause address queue if there is an empty space in the pause address queue.

[0045] In actual execution, the embodiments of this application can first determine whether there is an empty space in the pause address queue, and then insert the cache line address into the pause address queue if there is an empty space in the pause address queue.

[0046] In conjunction with the description of other embodiments, to Figure 3 For example, this application provides a detailed description of how to construct prefetch metadata.

[0047] S301, Begin.

[0048] S302, determine whether the misjudged current branch instruction meets the preset verification conditions.

[0049] If the current branch instruction meets the preset verification conditions, proceed to S303; otherwise, proceed to S307.

[0050] S303 inserts the current branch instruction into the pause address queue as a candidate prefetch trigger.

[0051] S304, IFU detects front-end blockage.

[0052] S305, determine if there is an empty space in the pause address queue.

[0053] If there is an empty space in the pause address queue, proceed to S306; otherwise, proceed to S307.

[0054] S306 inserts the cache line address that caused the front-end pause into the pause address queue as a candidate prefetch target.

[0055] In this embodiment of the application, after inserting the cache line address that caused the front-end pause into the pause address queue as a candidate prefetch target, the process returns to S304.

[0056] S307, End.

[0057] Before storing the cache line address that causes front-end blocking into the pause address queue, this embodiment first determines whether there is an empty space in the pause address queue. If there is an empty space in the queue, the write is performed to avoid the pause address queue overflow causing the prefetch target to be lost. At the same time, it avoids the additional hardware power consumption caused by invalid write operations, completely saves the prefetch target address, and provides a complete data source for the subsequent construction of prefetch metadata.

[0058] Optionally, in one embodiment of this application, before writing to the prefetch table outside the loop, the method further includes: truncating bits at the program counter address corresponding to the prefetch trigger that satisfy a preset truncating condition to obtain a truncated address; and aligning the truncated address according to a preset cache line boundary to write it to the prefetch table outside the loop.

[0059] like Figure 4 As shown, the prefetch table outside the loop is a set-associative cache used to store prefetched metadata. In this embodiment, before writing the metadata into the prefetch table outside the loop, bits that satisfy a preset truncation condition at the PC address corresponding to the prefetch trigger (i.e., the loop branch instruction) are truncated to obtain the truncated address, which is then aligned to a preset cache line boundary. In some cases, the preset truncation condition is to truncate the lower 16 bits of the PC address; in other cases, the number of bits truncated can be flexibly adjusted according to storage overhead requirements. The preset cache line boundary can be 32 bytes, 64 bytes, or 128 bytes; this application does not impose specific limitations.

[0060] This application embodiment significantly shortens the address storage bit width and saves hardware storage space for the out-of-loop prefetch table by truncating bits that meet preset truncation conditions and then aligning them with preset cache line boundaries. At the same time, it adapts to cache line addressing rules and improves the query speed of the out-of-loop prefetch table.

[0061] Optionally, in one embodiment of this application, the method further includes setting the prefetch flag in the branch target buffer to an active state when writing to the prefetch table outside the loop.

[0062] Continue as Figure 4As shown, since only a very small number of loop branch instructions cause front-end bottlenecks, to reduce the number of invalid lookups in the loop prefetch table, this embodiment configures a prefetch flag of a preset number of bits in each BTB entry. This prefetch flag is used to identify whether the current loop branch instruction is a loop prefetch trigger. In some cases, the preset number of bits is 1 bit; a prefetch flag of 1 indicates that the prefetch flag is valid, and a prefetch flag of 0 indicates that the prefetch flag is invalid. Of course, in other cases, the preset number of bits can be flexibly adjusted according to the lookup overhead, and this embodiment does not impose specific limitations.

[0063] This application embodiment sets the prefetch flag in the branch target buffer to an active state when writing to the prefetch table outside the loop. This facilitates quick identification of whether there is a matching prefetch target in the current loop branch when querying the BTB in the pipeline, avoids invalid retrieval operations in the prefetch table outside the loop, reduces redundant hardware access, lowers processor power consumption, and simultaneously synchronizes the prefetch flag with the data state of the prefetch table outside the loop, simplifying hardware control logic.

[0064] In step S203, when the current loop branch instruction enters the pipeline, the branch target buffer is queried. If the branch target buffer is hit and the prefetch flag in the branch target buffer is valid, the prefetch table outside the loop is queried according to the current loop branch instruction to obtain the corresponding prefetch target, and an instruction prefetch request is initiated according to the corresponding prefetch target.

[0065] In actual execution, after the current loop branch instruction enters the pipeline, this embodiment of the application uses FDIP to query the BTB and read the prefetch flag. When the BTB is hit and the prefetch flag is valid, the PC address of the current loop branch instruction is used to query the loop prefetch table. When the loop prefetch table is hit, all prefetch targets under the hit entry are obtained, and the prefetch targets are decoded and written sequentially into the loop prefetch queue. An instruction prefetch request is then sent to the instruction cache.

[0066] It should be noted that when FDIP processes loop statements, it usually issues repeated prefetches for the loop body. However, in the embodiment of this application, there are enough idle MSHR (misses tatus holding register) entries in the I-cache to ensure that the instruction cache can receive prefetch requests from the prefetch queue normally, thereby effectively reducing the front-end fetch pause after exiting the loop.

[0067] by Figure 5 For example, this application embodiment details how to trigger an out-of-loop prefetch request.

[0068] S501, Begin.

[0069] S502 uses the PC address to query the BTB and read the prefetch flag.

[0070] S503 determines whether BTB has been hit and whether the prefetch flag is valid.

[0071] If BTB is hit and the prefetch flag is valid, proceed to S504; otherwise, proceed to S507.

[0072] S504 uses the PC address to query the prefetch table outside the loop.

[0073] S505 checks if the prefetch table outside the loop has been hit.

[0074] If the prefetch table outside the loop is hit, proceed to S506; otherwise, proceed to S507.

[0075] S506 initiates an instruction prefetch request to the instruction cache.

[0076] S507, End.

[0077] Based on the above description, it can be understood that the application scenarios of the embodiments of this application include, but are not limited to, Web services, databases, and online transaction processing.

[0078] In application scenario 1, database systems (such as MySQL, PostgreSQL, and Cassandra) often involve deep function calls, loop checks, and conditional jumps during complex queries or transaction processing, resulting in a large instruction working set and significant I-cache pressure. This method can accurately prefetch structures in the database query path that are prone to triggering cache misses, reducing instruction fetch latency.

[0079] Application Scenario 2: In Web service and microservice architectures, a large number of requests trigger dynamic control logic and system calls, exhibiting high path diversity and unpredictable behavior, often leading to insufficient front-end command supply. This method can significantly improve the front-end command flow supply capacity in multi-user, high-concurrency scenarios, thereby enhancing request response performance and system throughput.

[0080] Application Scenario 3 addresses data sharding tasks supported by computing frameworks such as Spark and GraphX, as well as graph computing models in scenarios like social graphs and recommendation graphs. These tasks feature highly dynamic execution paths and unstructured control flows, which can easily lead to obstacles in obtaining front-end instructions. This method optimizes the prefetch logic for complex dynamic loop branching scenarios, ensuring the efficient and stable operation of large-scale parallel computing tasks.

[0081] like Figure 6As shown, taking a CPU architecture design for processor front-end optimization as an example, this application embodiment adds a lightweight out-of-loop prefetch design based on the relevant FDIP architecture. The relevant FDIP architecture includes a BTB, a fetch target queue, fetch logic, an instruction cache, a decoding unit, and an execution unit. The lightweight out-of-loop prefetch design includes a pause address queue (also known as a blocking address queue), an out-of-loop prefetch table, and an out-of-loop prefetch queue. The principle of the recording and replay instruction prefetching method for loop statements is illustrated below.

[0082] In this embodiment of the application, after the execution unit detects a branch misjudgment, it determines whether the misjudged branch instruction meets the preset verification conditions. If the misjudged branch instruction meets the preset verification conditions, it determines that the misjudged branch instruction belongs to a loop branch instruction and stores it in the pause address queue.

[0083] After the execution unit detects a misjudgment of a loop branch, it sends a pipeline flushing signal to the pipeline predecessor stage. The fetching unit then redirects the fetch address to the correct path outside the loop. Subsequently, in this embodiment, the cache line address that meets the preset number of records is written to the pause address queue. Further, if the execution unit detects another misjudgment of a loop branch, the pause address queue stops recording, retrieves the previously stored loop branch instruction as a prefetch trigger, matches the corresponding cache line as the prefetch target, and then encodes the prefetch trigger and prefetch target and writes them to the prefetch table outside the loop, completing metadata storage.

[0084] When a loop branch instruction is sent into the pipeline, the embodiment of this application first queries the BTB and reads the corresponding prefetch flag according to the PC of the loop branch instruction. When the query is successful and the prefetch flag is valid, the PC queries the loop prefetch table, reads the corresponding prefetch target, and writes the prefetch target into the loop prefetch queue in sequence, and initiates an instruction prefetch request to the instruction cache.

[0085] According to the instruction prefetching and replay method for loop statements proposed in this application, after detecting a branch misjudgment, the current branch instruction is filtered by preset verification conditions. Loop branches that meet the conditions are stored in the pause address queue, and the cache line address that caused the front-end blocking is recorded. This eliminates the need to capture the complete program instruction stream, significantly reducing the total amount of metadata and saving on-chip storage resources. Furthermore, when a new loop branch misjudgment is detected, the prefetch trigger and prefetch target are retrieved from the pause address queue and written to the loop prefetch table, avoiding invalid data occupying the loop prefetch table's storage space. Then, during the pipeline instruction fetching stage, when the branch target buffer is hit and the prefetch flag is valid, the loop prefetch table is retrieved to obtain the prefetch target and an instruction prefetch request is initiated. This reduces invalid searches of the loop prefetch table, lowers hardware access power consumption, and specifically addresses the instruction cache miss problem caused by loop branch prediction misjudgment, alleviating front-end blocking and balancing hardware area overhead and processor instruction supply efficiency. Therefore, this solves the problem in related technologies where loop branch misjudgment causes FDIP to repeatedly prefetch the loop body content, preventing the prefetching of loop-outside instructions and causing front-end blocking.

[0086] Next, referring to the accompanying drawings, a recording and replay instruction prefetching device for loop-oriented statements is described according to an embodiment of this application.

[0087] Figure 7 This is a block diagram of a recording and replay instruction prefetching device for loop-oriented statements provided according to an embodiment of this application.

[0088] like Figure 7 As shown, the recording and replay instruction prefetching device 70 for loop statements includes: a first construction module 100, a second construction module 200, and a prefetching module 300.

[0089] The first construction module 100 is used to determine whether the misjudged current branch instruction meets the preset verification conditions when a branch misjudgment is detected. If the current branch instruction meets the preset verification conditions, the current branch instruction is inserted into the pause address queue as a candidate prefetch trigger.

[0090] The second building module 200 is used to insert the cache line address that causes the front-end pause into the pause address queue as a candidate prefetch target, so that if a new loop branch is detected as a misjudgment, the prefetch trigger and prefetch target can be retrieved from the pause address queue and written into the loop out-of-loop prefetch table.

[0091] The prefetch module 300 is used to query the branch target buffer when the current loop branch instruction enters the pipeline. If the branch target buffer is hit and the prefetch flag in the branch target buffer is valid, the module queries the prefetch table outside the loop according to the current loop branch instruction to obtain the corresponding prefetch target and initiates an instruction prefetch request according to the corresponding prefetch target.

[0092] Optionally, in one embodiment of this application, preset verification conditions include: the jump target address of the current branch instruction is less than the address of the current branch instruction, the current branch instruction is a direct conditional jump instruction, and the current branch instruction has not been taken.

[0093] Optionally, in one embodiment of this application, it further includes: a judgment module, used to determine whether there is an empty space in the pause address queue, so as to insert the cache line address into the pause address queue if there is an empty space in the pause address queue.

[0094] Optionally, in one embodiment of this application, it further includes: a truncation module and an alignment module.

[0095] The interception module is used to intercept bits at the program counter address corresponding to the prefetch trigger that meet the preset interception conditions, and obtain the interception address.

[0096] The alignment module is used to align the truncated address to a preset cache line boundary for writing to the out-of-loop prefetch table.

[0097] Optionally, in one embodiment of this application, it further includes: a setting module, used to set the prefetch flag in the branch target buffer to an active state when writing to the prefetch table outside the loop.

[0098] It should be noted that the foregoing explanation of the method for prefetching recording and replaying instructions for loop-oriented statements also applies to the device for prefetching recording and replaying instructions for loop-oriented statements in this embodiment, and will not be repeated here.

[0099] The instruction prefetching and replay device for loop statements proposed in this application, upon detecting a branch misjudgment, filters the current branch instruction using preset verification conditions, stores eligible loop branches in a pause address queue, and records the cache line address that caused front-end blocking. This eliminates the need to capture the complete program instruction stream, significantly reducing the total amount of metadata and saving on-chip storage resources. Furthermore, when a new loop branch misjudgment is detected, the prefetch trigger and prefetch target are retrieved from the pause address queue and written to the loop prefetch table, avoiding invalid data occupying the loop prefetch table's storage space. Then, during the pipeline fetch stage, when the branch target buffer is hit and the prefetch flag is valid, the loop prefetch table is retrieved to obtain the prefetch target and an instruction prefetch request is initiated. This reduces invalid searches of the loop prefetch table, lowers hardware access power consumption, and specifically addresses the instruction cache miss problem caused by loop branch prediction misjudgment, alleviating front-end blocking and balancing hardware area overhead with processor instruction supply efficiency. Therefore, it solves the problem in related technologies where loop branch misjudgment leads to repeated prefetching of the loop body by the FDIP, preventing the prefetching of instructions outside the loop and causing front-end blocking.

[0100] Figure 8 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. The electronic device may include: The memory 801, the processor 802, and the computer program stored on the memory 801 and capable of running on the processor 802.

[0101] When the processor 802 executes the program, it implements the recording and replay instruction prefetching method for loop-oriented statements provided in the above embodiments.

[0102] Furthermore, electronic devices also include: Communication interface 803 is used for communication between memory 801 and processor 802.

[0103] The memory 801 is used to store computer programs that can run on the processor 802.

[0104] The memory 801 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0105] If the memory 801, processor 802, and communication interface 803 are implemented independently, then the communication interface 803, memory 801, and processor 802 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized into address buses, data buses, control buses, etc. For ease of representation, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0106] Optionally, in a specific implementation, if the memory 801, processor 802, and communication interface 803 are integrated on a single chip, then the memory 801, processor 802, and communication interface 803 can communicate with each other through an internal interface.

[0107] The processor 802 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0108] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for recording and replaying instructions for loop-oriented statements.

[0109] This application also provides a computer program product, including a computer program that, when executed, implements the above-described method for recording and replaying instructions for loop-oriented statements.

[0110] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0111] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0112] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0113] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0114] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or more of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0115] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0116] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0117] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for prefetching recording and replay instructions for loop statements, characterized in that, Includes the following steps: If a branch misjudgment is detected, it is determined whether the misjudged current branch instruction meets the preset verification condition. If the current branch instruction meets the preset verification condition, the current branch instruction is inserted into the pause address queue as a candidate prefetch trigger. The cache line address that causes the front-end pause is inserted into the pause address queue as a candidate prefetch target. In the event of a new loop branch misjudgment, the prefetch trigger and the prefetch target are retrieved from the pause address queue and written into the loop out-of-loop prefetch table. When the current loop branch instruction enters the pipeline, the branch target buffer is queried. If the branch target buffer is hit and the prefetch flag in the branch target buffer is valid, the loop prefetch table is queried according to the current loop branch instruction to obtain the corresponding prefetch target, and an instruction prefetch request is initiated according to the corresponding prefetch target.

2. The method according to claim 1, characterized in that, The preset verification conditions include: The target address of the current branch instruction is less than the address of the current branch instruction, and the current branch instruction is a direct conditional jump instruction, and the current branch instruction has not been taken.

3. The method according to claim 1, characterized in that, Before inserting the cache line address that caused the front-end pause into the pause address queue, the method further includes: Determine if there is an empty space in the pause address queue, and if there is an empty space in the pause address queue, insert the cache line address into the pause address queue.

4. The method according to claim 1, characterized in that, Before writing to the prefetch table outside the loop, the following is also included: Extract the bits at the program counter address corresponding to the prefetch trigger that satisfy the preset extraction condition to obtain the extraction address; The intercepted address is aligned with the preset cache line boundary and written into the out-of-loop prefetch table.

5. The method according to claim 1, characterized in that, Also includes: When writing to the prefetch table outside the loop, the prefetch flag in the branch target buffer is set to an active state.

6. A recording and replay instruction prefetching device for loop statements, characterized in that, include: The first construction module is used to determine whether the misjudged current branch instruction meets the preset verification conditions when a branch misjudgment is detected. If the current branch instruction meets the preset verification conditions, the current branch instruction is inserted into the pause address queue as a candidate prefetch trigger. The second construction module is used to insert the cache line address that causes the front-end pause into the pause address queue as a candidate prefetch target, so that if a new loop branch is detected as a misjudgment, the prefetch trigger and the prefetch target can be retrieved from the pause address queue and written into the loop out-of-loop prefetch table. The prefetch module is used to query the branch target buffer when the current loop branch instruction enters the pipeline. If the branch target buffer is hit and the prefetch flag in the branch target buffer is valid, the module queries the loop prefetch table according to the current loop branch instruction to obtain the corresponding prefetch target, and initiates an instruction prefetch request according to the corresponding prefetch target.

7. The apparatus according to claim 6, characterized in that, Also includes: The interception module is used to intercept bits that meet preset interception conditions at the program counter address corresponding to the prefetch trigger to obtain the interception address; The alignment module is used to align the truncated address according to the preset cache line boundary so as to write it into the out-of-loop prefetch table.

8. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and capable of running on the processor, the processor executing the program to implement the recording and replay instruction prefetching method for loop-oriented statements as described in any one of claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the recording and replay instruction prefetching method for loop-oriented statements as described in any one of claims 1-5.

10. A computer program product, comprising a computer program, characterized in that, The computer program is executed to implement the recording and replay instruction prefetching method for loop-oriented statements as described in any one of claims 1-5.

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