Branch target buffer prefetch system, method, and electronic device

Abstract

The application relates to the technical field of computer processor micro-architecture design, in particular to a branch target buffer prefetch system, method and electronic equipment, wherein the system comprises: a cache unit comprising a first-level cache and a second-level cache, both of which comprise at least one cache module, the module comprises at least one instruction cache line, the instruction cache line generates an in-line offset marker in a pre-decoding stage when at least one of a prefetch operation and a load operation is performed on the instruction cache line, and a metadata area of the instruction cache line stores an offset vector of a jump branch corresponding to the in-line offset marker; a selection decoder is used for decoding an instruction cache line prefetched into a front end based on an offset vector of a jump branch provided by the cache unit to obtain pre-padding information; and a branch prediction unit is used for performing a padding operation of the branch target buffer based on the pre-padding information. Thus, the problem that a large number of invalid branches are introduced due to full-amount pre-decoding and padding of the branch target buffer in the related art, thereby leading to low branch prediction accuracy, is solved.

Description

Technical Field

[0001] This application relates to the field of computer processor microarchitecture design technology, and in particular to a prefetching system, method and electronic device for a branch target cache. Background Technology

[0002] While the pre-decoding method based on prefetch cache lines in related technologies can extract branch instructions and fill the branch target cache, it fails to effectively filter historical jump information from execution feedback, resulting in a large number of invalid branches being written into the branch target cache, causing capacity pollution and thus reducing the effective coverage and prediction accuracy of the branch target cache. Summary of the Invention

[0003] This application provides a prefetching system, method, and electronic device for branch target caches to solve the problems in related technologies, such as the prefetching mechanism of branch target caches performing full pre-decoding and filling of branch instructions in the prefetch cache line, introducing a large number of invalid branches, resulting in low branch prediction accuracy.

[0004] The first aspect of this application provides a prefetching system for a branch target cache, comprising: a cache unit, the cache unit including a first-level cache and a second-level cache, each of the first-level cache and the second-level cache including at least one cache module, the cache module including at least one instruction cache line, wherein when the instruction cache line is subjected to at least one prefetch operation and a load operation, an inline offset marker is generated in the pre-decoding stage, and the metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker; a decoder, configured to perform a decoding operation on the instruction cache line prefetched into the front end based on the offset vector of the jump branch provided by the cache unit to obtain pre-fill information; and a branch prediction unit, configured to perform a filling operation on the branch target cache based on the pre-fill information.

[0005] Optionally, the offset vector of the jump branch is used as a bitmap structure to identify the branch location in the instruction cache line where a jump has occurred.

[0006] Optionally, the process of selecting a decoder to perform the decoding operation includes: reading the offset vector from the metadata area of ​​the cache line of the first-level cache; filtering out the target branch that has jumped from the corresponding cache line according to the offset vector; decoding the jump target and PC (Program Counter) information according to the instruction slot of the target branch; and decoding the jump target and PC information into pre-filled information.

[0007] Optionally, the branch prediction unit includes a branch target cache and a jump verification cache. The jump verification cache is used to store pre-filled information. When the branch prediction unit performs branch prediction, it searches both the branch target cache and the jump verification cache. After the prefetched instruction cache line is hit during the search, it waits for the jump verification cache to store the corresponding pre-filled information before switching to the branch target cache.

[0008] Optionally, the cache unit is also provided with a branch offset table, which stores the offset vector and address of the first jump branch in each cache line in the second-level cache.

[0009] Optionally, the pipeline unit responds to the front-end instruction and triggers a prefetch operation on the instruction cache line through the prefetch mechanism, and writes the instruction cache line returned by the prefetch operation into the first-level cache.

[0010] Optionally, the pipeline unit includes a target queue, an instruction fetch unit, and a commit unit. The target queue caches instruction cache lines. The instruction fetch unit triggers a prefetch operation on the instruction cache lines and writes the instruction cache lines returned by the prefetch operation into the first-level cache. The commit unit is used to set the jump branch of the first-level cache.

[0011] Optionally, the pipeline unit is also used to recover the offset vector of the instruction cache line from the branch offset table when at least one of the operations of backfilling the instruction cache line to the first-level cache and prefetching it back to the first-level cache is performed.

[0012] A second aspect of this application provides an electronic device including a prefetching system for a branch target cache as described in the above embodiments.

[0013] A third aspect of this application provides a prefetching method for a branch target cache. The method is applied to the branch target cache prefetching system of the above embodiment to execute the branch prefetching unit of the branch target cache. The method includes: sending a front-end instruction to a pipeline module; responding to the front-end instruction through the pipeline module, triggering a prefetching operation on the instruction cache line through a prefetching mechanism, and writing the instruction cache line returned by the prefetching operation into a first-level cache. When at least one prefetching operation and a loading operation are performed on the instruction cache line, an inline offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. By selecting a decoder based on the offset vector of the jump branch provided by the cache unit, the prefetched instruction cache line entering the front end is decoded to obtain pre-filling information. A filling operation of the branch target cache is performed based on the pre-filling information.

[0014] Therefore, this application has at least the following beneficial effects: In this embodiment, the caching unit includes a first-level cache and a second-level cache. Both the first-level cache and the second-level cache include at least one caching module. Each caching module includes at least one instruction cache line. When the instruction cache line is subjected to at least one prefetch operation and one load operation, an inline offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. A selection decoder is used to decode the prefetched instruction cache line entering the front end based on the offset vector of the jump branch provided by the caching unit to obtain pre-filled information. A branch prediction unit is used to perform a branch target cache filling operation based on the pre-filled information. By generating and storing the inline offset marker and the corresponding jump branch offset vector during the pre-decoding stage, the selection decoder can accurately select the target branch that has undergone a jump for decoding based on the offset vector, thereby effectively filtering invalid branches and avoiding branch target cache capacity pollution. Combining the branch prediction unit with the pre-filled information to perform the branch target cache filling operation significantly improves the prefetch accuracy and effective coverage of the branch target cache. This solves the problem in related technologies where the prefetching mechanism of the branch target cache performs full pre-decoding and filling of branch instructions in the prefetch cache line, introducing a large number of invalid branches and resulting in low branch prediction accuracy.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a processor architecture employing a fetching instruction prefetcher in the related art according to an embodiment of this application; Figure 2 This is a block diagram of a prefetching system for a branch target cache provided according to an embodiment of this application; Figure 3 This is a schematic diagram of a CPU architecture equipped with a branch target cache prefetch filtering mechanism according to an embodiment of this application; Figure 4 This is a schematic diagram of a branch prediction and jump verification process provided according to an embodiment of this application; Figure 5 This is a schematic diagram of an offset vector recovery process based on a branch offset table according to an embodiment of this application; Figure 6 This is a flowchart of a prefetching method for a branch target cache provided according to an embodiment of this application; Figure 7This is a schematic diagram of the process for setting the jump branch offset vector according to an embodiment of this application. Detailed Implementation

[0017] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0018] Applications such as database systems and data warehouses, transaction processing in web services and microservice architectures, and large-scale data processing and graph computing platforms, contain massive execution engines, multi-layered function calls, dynamic branching, and complex loop structures, resulting in extremely large instruction working sets and highly dispersed paths. The instruction space of these systems typically far exceeds the capacity of the L1I-Cache and branch target cache. Frequent jumps or changes in request patterns can not only rapidly exhaust the branch target cache capacity but also cause severe branch target cache misses due to frequent replacement of old entries.

[0019] like Figure 1 The diagram illustrates a processor front-end branch prediction and instruction fetch architecture in related technologies. The architecture primarily includes a Branch Prediction Unit (BFU), a Fetch Target Queue (FTQ), and an Instruction Fetch Unit (IFU). The branch prediction unit utilizes components such as TAGE_SC_L (Tagged Geometric Predictor - Statistical Corrector - Loop), RAS (Return Address Stack), ITTAGE (Indirect Target Tagged GEnometric Length Predictor), and a branch target cache to perform branch prediction and store the results in the instruction fetch target queue. The instruction fetch unit retrieves instructions from the instruction cache based on the queue information and sends them to the decoder for execution. Simultaneously, it resets the state via a rollback signal when a prediction error occurs. This architecture demonstrates the fundamental working mechanism by which the processor front-end maintains pipeline efficiency in related technologies, namely, a high dependence on the branch target cache hit rate.

[0020] Data center applications, due to their large code size and complex control flow, exacerbate the problem of limited branch target cache capacity in the processor front end. Architectures based on instruction prefetching heavily rely on the branch target cache hit rate. Current pre-decoding methods based on prefetch cache lines lack effective filtering mechanisms, easily leading to the writing of numerous invalid branches into the branch target cache, causing capacity pollution and reducing prefetch accuracy and effective coverage. Boomerang proposed a metadata-free control flow prefetching method, extracting branch information from cache blocks through a pre-decoder and temporarily storing it in the branch target cache prefetch buffer, but this did not solve the problem of insufficient prefetch accuracy.

[0021] Shotgun employs a hierarchical branch target cache architecture and spatial footprint-driven prefetching. It utilizes the Unified Branch Target Buffer (U-BTB) to record the spatial footprint of the target region to trigger batch prefetching. While this expands the coverage, it increases the complexity of storage organization. Skia, on the other hand, introduces a shadow branch decoder and shadow branch buffer for "shadow branches," decoding branch instructions in undecoded regions within the cache block in parallel to supplement the branch target cache coverage. This significantly improves the issue of missing cold branches, but its mechanism relies on additional decoding hardware and does not filter out worthless branches at the source. None of these techniques achieve accurate filtering and efficient filling of branch target cache prefetch entries with low hardware overhead.

[0022] The following description, with reference to the accompanying drawings, describes a branch target cache prefetching system, method, and electronic device according to embodiments of this application. Addressing the problem mentioned in the background art where the branch target cache prefetching mechanism performs full pre-decoding and padding of branch instructions within the prefetch cache line, introducing a large number of invalid branches and resulting in low branch prediction accuracy, this application provides a branch target cache prefetching system. In this system, the cache unit includes a first-level cache and a second-level cache. Both the first-level cache and the second-level cache include at least one cache module. The cache module includes at least one instruction cache line. When the instruction cache line is subjected to at least one prefetch operation and a load operation, an in-line offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the in-line offset marker. A decoder is selected to decode the instruction cache line prefetched into the front end based on the offset vector of the jump branch provided by the cache unit to obtain pre-paddling information. A branch prediction unit is used to perform a branch target cache padding operation based on the pre-paddling information. By generating and storing inline offset markers and corresponding jump branch offset vectors during the pre-decoding stage, the selection decoder can accurately select target branches that have undergone jumps for decoding based on these offset vectors, thereby effectively filtering invalid branches and avoiding branch target cache capacity pollution. Combined with the branch prediction unit using pre-filling information to perform branch target cache filling operations, the prefetch accuracy and effective coverage of the branch target cache are significantly improved. This solves the problem in related technologies where the branch target cache prefetch mechanism performs full pre-decoding and filling of branch instructions within the prefetch cache line, introducing a large number of invalid branches and resulting in low branch prediction accuracy.

[0023] Specifically, Figure 2 This is a block diagram of a prefetching system for a branch target cache according to an embodiment of this application.

[0024] like Figure 2 As shown, the prefetch system 10 for the branch target cache includes: a cache unit 100, a first-level cache 101, a second-level cache 102, a selection decoder 200, and a branch prediction unit 300.

[0025] The cache unit 100 includes a first-level cache 101 and a second-level cache 102. Both the first-level cache 101 and the second-level cache 102 include at least one cache module. Each cache module includes at least one instruction cache line. When the instruction cache line is subjected to at least one prefetch operation and a load operation, an inline offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. The select decoder 200 is used to decode the instruction cache line prefetched into the front end based on the offset vector of the jump branch provided by the cache unit 100 to obtain pre-fill information. The branch prediction unit 300 is used to perform a filling operation on the branch target cache based on the pre-fill information.

[0026] Specifically, Level 1 cache 101 refers to the front-end storage level of cache unit 100, used to temporarily store instruction cache lines that are prefetched or loaded; Level 2 cache 102 refers to the back-end storage level of cache unit 100, used to provide historical branch information when instruction cache lines are backfilled; instruction cache line refers to the basic data unit of the cache; prefetch operation refers to the process of loading instructions from the back end to the front end; load operation refers to the process of loading instruction cache lines from Level 2 cache 102 back to Level 1 cache 101; in-line offset marker refers to the identifier of the instruction cache line identified during the pre-decoding stage during prefetching or loading, indicating the position of the jump branch instruction within the cache line; prefill information refers to the data result generated by the selector after decoding the prefetched instruction cache line based on the jump branch offset vector.

[0027] The decoder selection module is a key control module for prefetching branch target cache entries. Its main function is to filter the branches decoded within the cache lines prefetched into the front end based on the information provided by the jump branch offset vector, determining which branches are eligible to trigger the branch target cache filling operation. Therefore, only the branches marked by the offset vector are valid branches.

[0028] It is understood that, in this embodiment of the application, the cache unit 100, including a first-level cache 101 and a second-level cache 102, generates an in-line offset marker using the pre-decoding mechanism of the instruction cache line during prefetching or loading operations, and accurately stores the corresponding jump branch offset vector in the metadata area. Then, the selective decoder 200 performs targeted decoding on the instructions entering the front end based on this offset vector to obtain pre-filling information, and finally, the branch prediction unit 300 completes the filling of the branch target cache. Utilizing metadata to guide selective decoding avoids the resource waste caused by full scanning, thereby improving the accuracy of branch target cache entry prefetching, reducing branch target cache pollution caused by invalid branches or erroneous paths, and improving the processor front-end instruction supply efficiency and system performance.

[0029] It should be noted that the branch target cache prefetching system is integrated into the instruction fetch subsystem of modern high-performance CPUs (Central Processing Units) as a hardware unit. By comprehensively utilizing the pre-decoding results of prefetch cache lines, branch execution feedback information, and lightweight filtering structures, it achieves dynamic filtering and replenishment of branch target cache entries, thereby significantly improving the effective capacity of the branch target cache and the front-end instruction supply capability. This application can be deployed in products such as server CPUs, data center dedicated processors, and high-performance computing nodes.

[0030] Specifically, such as Figure 3As shown, the BPU (Branch Prediction Unit) integrates a main branch target buffer, a return instruction branch target buffer, ITTAGE, RAS, and a jump verification cache. The L2 cache stores an L2 jump branch offset table containing addresses and branch offset vectors, used to record branch information and support eviction operations. The selection decoder connects the L2 jump branch offset table to the instruction fetch target queue, responsible for filtering and decoding branch data. The instruction fetch unit retrieves instructions from the L1 instruction cache through cache line prefetching and front-end requirements, sets the jump branch in conjunction with the jump branch offset vector, and finally sends the instructions to the commit unit, thereby realizing dynamic filtering and replenishment of entries in the branch target buffer to improve the front-end instruction supply capability.

[0031] In some embodiments, the offset vector of a jump branch is used as a bitmap structure to identify the location of a branch in the instruction cache line where a jump has occurred.

[0032] It is understood that, in this embodiment of the application, the offset vector of the jump branch can be set as a bitmap structure to identify the branch position in the instruction cache line where a jump has occurred. By using the bitmap structure to compactly map and identify the specific branch position in the instruction cache line, a direct data foundation is provided for quickly and accurately locating the target branch where a jump has occurred.

[0033] Specifically, the jump branch offset is a lightweight bitmap structure used to identify valid branch locations where jumps have occurred within an instruction cache line. Each prefetched or loaded cache line generates a 6-bit in-line offset marker during the pre-decoding phase, indicating which instruction slots within that line contain branch instructions that may trigger control flow changes. The jump branch offset bitmap serves as auxiliary masking information for the instruction cache, enabling fast filtering in subsequent branch target cache lookups, cache line speculative access, and front-end prediction paths. This offset vector is directly stored in the instruction cache's metadata area, providing hardware filtering for subsequent selective branch target cache filling, thereby significantly reducing the generation of worthless branch target cache entries.

[0034] In some embodiments, the process of selecting decoder 200 to perform decoding operations includes: reading offset vectors from the metadata area of ​​cache lines in the first-level cache 101; filtering out target branches that have undergone jumps from the corresponding cache lines based on the offset vectors; decoding the jump target and PC information based on the instruction slots of the target branches; and decoding the jump target and PC information into pre-filled information.

[0035] Among them, the metadata area refers to the area in the cache line of the first-level cache 101 used to store the offset vector; the target branch refers to the branch that has jumped from the corresponding cache line according to the offset vector; the instruction slot refers to the instruction position of the target branch in the cache line; the jump target refers to the branch jump address information obtained after decoding the target branch; and the PC information refers to the program counter information obtained after decoding the target branch.

[0036] It is understood that this embodiment reads the offset vector from the metadata area of ​​the cache line of the first-level cache 101, filters out the target branch that has jumped from the corresponding cache line based on the offset vector, and decodes the jump target and PC information based on the instruction slot of the target branch. The jump target and PC information are then decoded into pre-filled information. Thus, the target branch is located directly through the offset vector, avoiding invalid traversal and decoding of all instructions in the cache line. At the same time, the jump target and PC information are converted into pre-filled information in advance, providing directly usable data support for fast branch processing in the subsequent pipeline stage.

[0037] Specifically, the set jump branch offset vector is read from the metadata of the cache line, and conditional filtering is performed based on the jump branch offset vector: if the offset vector shows that the line contains at least one valid branch, the line is allowed to enter the pre-decoding path; if the offset vector is completely empty (indicating that none of the included branches have ever jumped), the line is blocked from entering the branch target cache filling process. The selected decoder only pre-decodes the instruction slots marked as valid by the offset vector, extracts the jump target and PC information, and inserts the relevant entries into the jump verification cache. The above selective pre-decoding mechanism effectively avoids performing meaningless pre-decoding and filling on conditional branches that never jump, significantly reduces the probability of branch target cache pollution, and improves the utilization rate of branch target cache capacity.

[0038] In some embodiments, the branch prediction unit 300 includes a branch target cache and a jump verification cache. The jump verification cache is used to store pre-filled information. When the branch prediction unit 300 performs branch prediction, it searches the branch target cache and the jump verification cache at the same time. After the prefetched instruction cache line is hit during the search, it waits for the jump verification cache to store the corresponding pre-filled information before switching to the branch target cache.

[0039] Among them, the branch target cache refers to the cache in the branch prediction unit 300 used to store branch prediction information; the jump verification cache refers to the cache in the branch prediction unit 300 used to save pre-filled information.

[0040] It is understood that this embodiment of the application sets up a branch target cache and a jump verification cache in the branch prediction unit 300. The jump verification cache stores pre-filled information, and both caches are searched simultaneously during branch prediction. After the prefetched instruction cache line is hit, the system waits for the corresponding pre-filled information to be stored in the jump verification cache before switching to the branch target cache. Thus, by temporarily storing and verifying the pre-filled information through the jump verification cache, it ensures that accurate and ready branch information can be obtained after the prefetched instruction cache line is hit, thereby providing reliable data assurance for subsequent switching to the branch target cache for accurate branch prediction.

[0041] Specifically, the jump verification cache is a small cache used to store branch instructions decoded by the select decoder. When the BPU performs branch prediction, it simultaneously searches the verification cache and the branch target cache. If a prefetched entry is hit during the search, it is not immediately swapped back into the main branch target cache, but rather waits until the branch is verified and a jump actually occurs before being swapped back into the main branch target cache.

[0042] Specifically, such as Figure 4 As shown, the branch prediction and jump verification process includes: In step 401, the instruction cache line and the jump branch offset vector stored in the metadata area of ​​the cache line are read.

[0043] In step 402, the instructions in the cache line are decoded according to the position indicated by the offset vector to obtain branch information.

[0044] In step 403, the corresponding branch entry obtained from the decoding is inserted into the jump verification cache.

[0045] In step 404, the branch prediction unit performs a parallel query to check whether the jump verification cache has been hit while making a prediction.

[0046] In step 405, it is determined whether a jump occurs during the actual execution of the branch instruction corresponding to the entry hit in the jump verification cache.

[0047] In step 406, if a redirect actually occurs, the priority of the entry in the redirect verification cache is set to high priority for removal.

[0048] In step 407, valid entries in the jump verification cache are swapped to the main branch target cache.

[0049] It's important to note that valid candidate branch target cache entries generated by the selector are first written to the jump verification cache, rather than directly to the main branch target cache. When the program execution flow actually reaches the branch instruction and a jump occurs, the execution unit sends a "jump confirmation" signal to the verification cache. Upon receiving the confirmation signal, the verification cache swaps the corresponding entry from the verification cache to the main branch target cache. If a conflict occurs in the main branch target cache, the least recently used replacement strategy is used for eviction. If the branch does not actually jump during execution, no information is set in the verification cache, and the entry is preferentially removed from the verification cache. This "candidate verification swapping" mechanism ensures that the branch target cache is only filled with valid branches that have actually been executed, thus avoiding wasted branch target cache capacity caused by incorrect prefetch paths, misleading branch predictions, or low-value branches.

[0050] In some embodiments, the cache unit 100 is further provided with a branch offset table, which stores the offset vector and address of the first jump branch in each cache line in the second-level cache 102.

[0051] The first jump branch refers to the branch that jumps first in each cache line in the second-level cache 102 according to the instruction execution order.

[0052] It is understood that, in this embodiment of the application, a branch offset table is set in the cache unit 100 to store the offset vector and address of the first jump branch in each cache line within the second-level cache 102. This achieves the storage of the offset vector and address of the first jump branch in each cache line within the second-level cache 102, thereby improving the accuracy of prefetching the branch target cache entry.

[0053] Specifically, the L2 jump branch offset table is used to maintain the branch offset bitmap information for each cache line in the L2 cache. It is the main structure for implementing branch target cache filtering prefetching in this application under a multi-level storage hierarchy. Since the L2 cache has a large capacity, allocating a complete offset vector to each cache line would introduce significant metadata overhead. However, based on the observation that only a few branches within a cache line will jump, the L2 jump branch offset table only stores the offset of the first branch in the branch offset vector that will jump.

[0054] In some embodiments, the pipeline unit responds to the front-end instruction and triggers a prefetch operation on the instruction cache line through the prefetch mechanism, and writes the instruction cache line returned by the prefetch operation into the first-level cache 101.

[0055] Here, a pipeline unit refers to a processing unit used to respond to front-end instructions; a front-end instruction refers to an instruction that is responded to by the pipeline unit and triggers the prefetch mechanism.

[0056] It is understood that in this embodiment, the pipeline unit responds to front-end instructions, triggers a prefetch operation on the instruction cache line using a prefetch mechanism, and writes the instruction cache line returned by the prefetch operation into the first-level cache 101. This achieves automatic triggering of instruction cache line prefetching when the pipeline unit responds to front-end instructions, and directly writes the prefetched instruction cache line into the first-level cache 101, thereby completing the instruction cache line prefetching and writing operation. This accurately triggers the prefetching of instruction cache lines and writes them to the first-level cache 101, improving the accuracy of branch target cache entry prefetching.

[0057] In some embodiments, the pipeline unit includes a target queue, an instruction fetch unit, and a commit unit. The target queue caches instruction cache lines. The instruction fetch unit triggers a prefetch operation on the instruction cache lines and writes the instruction cache lines returned by the prefetch operation into the first-level cache 101. The commit unit is used to set the jump branch of the first-level cache 101.

[0058] The target queue refers to the queue in the pipeline unit used to cache instruction cache lines; the fetch unit refers to the unit in the pipeline unit used to trigger the prefetch operation on the instruction cache line and write the instruction cache line returned by the prefetch operation into the first-level cache 101; and the commit unit refers to the unit in the pipeline unit used to set the jump branch of the first-level cache 101.

[0059] It is understood that, in this embodiment of the application, a target queue, an instruction fetch unit, and a commit unit are set in the pipeline unit. The target queue is used to cache instruction cache lines. The instruction fetch unit triggers a prefetch operation on the instruction cache lines and writes the instruction cache lines returned by the prefetch operation into the first-level cache 101. The commit unit is used to set the jump branch of the first-level cache 101. Thus, through the coordinated cooperation of the target queue, the instruction fetch unit, and the commit unit, an orderly connection and complete processing from instruction cache line prefetching, writing to the first-level cache 101, to setting the jump branch is achieved.

[0060] In some embodiments, the pipeline unit is further configured to recover the offset vector of the instruction cache line from the branch offset table when at least one of the operations of backfilling the instruction cache line to the first level cache 101 and prefetching it back to the first level cache 101 is performed.

[0061] It is understood that, in this embodiment of the application, the offset vector of the instruction cache line is recovered from the branch offset table during at least one of the operations of backfilling the instruction cache line to the first-level cache 101 and prefetching it again to the first-level cache 101. This ensures that the corresponding offset vector can be recovered from the branch offset table in a timely manner when the instruction cache line is backfilled or prefetched to the first-level cache 101, thereby ensuring the accuracy and integrity of the branch position identification of the instruction cache line in the first-level cache 101.

[0062] Specifically, such as Figure 5 As shown, the offset vector recovery process based on the branch offset table includes: In step 501, the FDIP (Fetch-Directed Instruction Prefetching) triggers an instruction prefetching operation.

[0063] In step 502, it is determined whether the prefetched cache line already exists in the L1 I-Cache (i.e., the first-level cache).

[0064] In step 503, if the cache line is not in the L1 I-Cache, the prefetched cache line will be backfilled into the L1 I-Cache.

[0065] In step 504, the PC index L2 (i.e., the second-level cache) of the cache line is used to jump to the offset table (i.e., the branch offset table).

[0066] In step 505, it is determined whether the entry corresponding to the cache line is hit in the L2 jump offset table.

[0067] In step 506, if a hit occurs, data is read from the L2 jump offset table and the jump offset vector of the corresponding row in the L1 I-Cache is backfilled.

[0068] In step 507, it is determined whether the corresponding row in the L1 I-Cache has been successfully set (or exists) with an offset vector. If the offset vector has not been set, the process ends directly.

[0069] In step 508, if an offset vector has been set, the select decoder is triggered to decode the buffer line.

[0070] It's important to note that the cross-layer history retention mechanism ensures that even if an instruction line is not permanently stored in the L1 I-Cache, its branch behavior history can still be retained in L2. When this cache line is prefetched again or backfilled from L2 to L1, the system can directly recover its jump offset vector from the L2 offset table without relearning its taken behavior, thus providing a filtering basis for subsequent backfilling. Furthermore, the cross-layer history retention mechanism helps maintain a cross-layer jump branch set in large-scale server applications, maintaining branch filtering across a larger working set, thereby improving the effective coverage of the branch target cache.

[0071] According to the branch target cache prefetching system proposed in this application, the cache unit includes a first-level cache and a second-level cache. Both the first-level cache and the second-level cache include at least one cache module. Each cache module includes at least one instruction cache line. When the instruction cache line is subjected to at least one prefetch operation and one load operation, an inline offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. A selection decoder is used to decode the prefetched instruction cache line entering the front end based on the offset vector of the jump branch provided by the cache unit to obtain pre-filled information. A branch prediction unit is used to perform a branch target cache filling operation based on the pre-filled information. By generating and storing the inline offset marker and the corresponding jump branch offset vector during the pre-decoding stage, the selection decoder can accurately select the target branch that has undergone a jump for decoding based on the offset vector, thereby effectively filtering invalid branches and avoiding branch target cache capacity pollution. Combining the branch prediction unit with the pre-filled information to perform the branch target cache filling operation significantly improves the prefetch accuracy and effective coverage of the branch target cache. This solves the problem in related technologies where the prefetching mechanism of the branch target cache performs full pre-decoding and filling of branch instructions in the prefetch cache line, introducing a large number of invalid branches and resulting in low branch prediction accuracy.

[0072] Specifically, Figure 6 This is a flowchart illustrating a prefetching method for a branch target cache provided in an embodiment of this application.

[0073] like Figure 6 As shown, the branch target cache prefetching method is applied to the branch target cache prefetching system of the branch target cache as described in the above embodiment to execute the branch prefetching unit of the branch target cache. The branch target cache prefetching method includes the following steps: In step S601, a front-end instruction is sent to the pipeline module.

[0074] It is understood that, in this embodiment of the application, by sending the front-end instructions to the pipeline module, the connection between the processor's front-end instruction fetch / decode stage and the back-end execution stage is realized, so that the front-end instructions can smoothly enter the pipeline for subsequent processing, thereby ensuring the normal operation and continuity of the instruction processing flow.

[0075] In step S602, the pipeline module responds to the front-end instruction and triggers a prefetch operation on the instruction cache line through the prefetch mechanism. The instruction cache line returned by the prefetch operation is written into the first-level cache. When the instruction cache line is subjected to at least one prefetch operation and loading operation, an inline offset marker is generated in the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker.

[0076] It is understood that the embodiments of this application respond to front-end instructions through a pipeline module and use a prefetch mechanism to write instruction cache lines into the first-level cache. At the same time, in the pre-decoding stage, an inline offset marker is generated and the offset vector of the corresponding jump branch is stored in the metadata area. This enables the branch jump information to be obtained and saved in advance when the instruction cache line is prefetched or loaded, thereby providing accurate offset vector guidance for subsequent decoding and branch prediction, effectively improving the prefetch accuracy and the effective coverage of the branch target cache.

[0077] Specifically, such as Figure 7 As shown, the process of setting the jump branch offset vector includes: In step 701, the Commit component commits the branches sequentially.

[0078] In step 702, it is determined whether a branch instruction has resulted in a jump. If no jump has occurred, the process returns to step 701.

[0079] In step 703, if a branch instruction jumps, the offset of the branch instruction in the cache line is calculated.

[0080] In step 704, the offset vector of the cache line is set based on the offset.

[0081] In step S603, the decoder selects the offset vector of the jump branch provided by the cache unit, performs a decoding operation on the instruction cache line prefetched into the front end to obtain pre-fill information, and performs a filling operation on the branch target cache based on the pre-fill information.

[0082] It is understood that, in this embodiment of the application, the decoder performs a decoding operation on the instruction cache line prefetched into the front end based on the offset vector of the jump branch provided by the cache unit to obtain pre-fill information, and performs a filling operation on the branch target cache based on the pre-fill information. This achieves accurate decoding of the prefetch instruction cache line and extraction of effective branch information, thereby avoiding capacity pollution caused by writing invalid branches into the branch target cache and significantly improving the prefetch accuracy and effective coverage of the branch target cache.

[0083] It should be noted that the foregoing explanation of the prefetching system embodiment for the branch target cache also applies to the prefetching method for the branch target cache in this embodiment, and will not be repeated here.

[0084] According to the branch target cache prefetching method proposed in this application, the cache unit includes a first-level cache and a second-level cache. Both the first-level cache and the second-level cache include at least one cache module. Each cache module includes at least one instruction cache line. When the instruction cache line is subjected to at least one prefetch operation and one load operation, an inline offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. A selection decoder is used to decode the prefetched instruction cache line entering the front end based on the offset vector of the jump branch provided by the cache unit to obtain pre-filled information. A branch prediction unit is used to perform a branch target cache filling operation based on the pre-filled information. By generating and storing the inline offset marker and the corresponding jump branch offset vector during the pre-decoding stage, the selection decoder can accurately select the target branch that has undergone a jump for decoding based on the offset vector, thereby effectively filtering invalid branches and avoiding branch target cache capacity pollution. Combining the branch prediction unit with the pre-filled information to perform the branch target cache filling operation significantly improves the prefetch accuracy and effective coverage of the branch target cache. This solves the problem in related technologies where the prefetching mechanism of the branch target cache performs full pre-decoding and filling of branch instructions in the prefetch cache line, introducing a large number of invalid branches and resulting in low branch prediction accuracy.

[0085] This application also provides an electronic device, including a prefetching system for a branch target cache as described in the above embodiments.

[0086] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0087] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0088] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0089] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (FPGAs), field-programmable gate arrays (FPGAs), etc.

[0090] Those skilled in the art will understand that all or part of the steps of the methods implementing the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0091] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A prefetching system for a branch target cache, characterized in that, include: The cache unit includes a first-level cache and a second-level cache. Both the first-level cache and the second-level cache include at least one cache module. The cache module includes at least one instruction cache line. When the instruction cache line is subjected to at least one prefetch operation and one load operation, an inline offset marker is generated during the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. Select a decoder to perform a decoding operation on the instruction cache line prefetched into the front end based on the offset vector of the jump branch provided by the cache unit to obtain pre-filled information; The branch prediction unit is used to perform a filling operation on the branch target cache based on the pre-filled information.

2. The prefetching system for branch target cache according to claim 1, characterized in that, The offset vector of the jump branch is a bitmap structure used to identify the branch positions in the instruction cache line where jumps have occurred.

3. The prefetching system for branch target cache according to claim 1, characterized in that, The process of selecting a decoder to perform the decoding operation includes: The offset vector is read from the metadata area of ​​the cache line in the first-level cache; Based on the offset vector, the target branch that has undergone a jump is selected from the corresponding cache line; The jump target and PC information are obtained by decoding the instruction slot of the target branch, and the jump target and PC information are decoded into the pre-filled information.

4. The prefetching system for branch target cache according to claim 1, characterized in that, The branch prediction unit includes a branch target cache and a jump verification cache. The jump verification cache is used to store the pre-filled information. When the branch prediction unit performs branch prediction, it simultaneously searches the branch target cache and the jump verification cache. After the prefetched instruction cache line is hit during the search, it waits for the jump verification cache to store the corresponding pre-filled information before switching to the branch target cache.

5. The prefetching system for branch target cache according to claim 1, characterized in that, The cache unit is also provided with a branch offset table, which is used to store the offset vector and address of the first jump branch in each cache line in the second level cache.

6. The prefetching system for branch target cache according to claim 5, characterized in that, The pipeline unit responds to the front-end instruction and triggers a prefetch operation on the instruction cache line through the prefetch mechanism, and writes the instruction cache line returned by the prefetch operation into the first-level cache.

7. The prefetching system for branch target cache according to claim 6, characterized in that, The pipeline unit includes a target queue, an instruction fetch unit, and a commit unit. The target queue caches instruction cache lines. The instruction fetch unit performs a prefetch operation on the instruction cache lines triggered by the trigger and writes the instruction cache lines returned by the prefetch operation into the first-level cache. The commit unit is used to set the jump branch of the first-level cache.

8. The prefetching system for branch target cache according to claim 6, characterized in that, The pipeline unit is also used to recover the offset vector of the instruction cache line from the branch offset table at least once the instruction cache line is backfilled to the first-level cache and then prefetched to the first-level cache again.

9. An electronic device, characterized in that, The prefetching system includes the branch target cache as described in any one of claims 1-8.

10. A prefetching method for a branch target cache, characterized in that, The method is applied to the branch target cache prefetching system of any one of claims 1-8 to execute the branch prefetching unit of the branch target cache, wherein the method includes: Send front-end commands to the pipeline module; The pipeline module responds to front-end instructions and triggers a prefetch operation on the instruction cache line through a prefetch mechanism. The instruction cache line returned by the prefetch operation is written into the first-level cache. When the instruction cache line is subjected to at least one of the prefetch operation and the load operation, an inline offset marker is generated in the pre-decoding stage. The metadata area of ​​the instruction cache line stores the offset vector of the jump branch corresponding to the inline offset marker. By selecting the decoder based on the offset vector of the jump branch provided by the cache unit, the prefetched instruction cache line is decoded to obtain pre-fill information, and the branch target cache is filled based on the pre-fill information.

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