Memory access optimization, register renaming, and physical register file port arbitration devices

Abstract

The application relates to the computer technical field and provides a memory access optimization, register renaming and physical register stack port arbitration device, which comprises a virtual address configuration unit configured to configure a virtual address space for a storage queue, the number of entries of the virtual address space is greater than the physical depth of the storage queue, so as to realize repeated allocation of the logical address of the storage queue; a relative instruction detection circuit coupled to the virtual address configuration unit, the relative instruction detection circuit is configured to generate a relative instruction address based on the negation result of the high bit round trip distinguishing bit of a target memory access instruction and the low bit physical index bit of the target memory access instruction when the target memory access instruction is written into the storage queue; the occupation state of the relative instruction address is detected and an occupation flag bit is set, and when the occupation flag bit indicates that no relative instruction is occupied, the target memory access instruction is allowed to be emitted and executed. In this way, the physical space utilization efficiency of the storage queue is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a memory access optimization, register renaming, and physical register file port arbitration device. Background Technology

[0002] Currently, processors commonly employ techniques such as out-of-order execution and superscalar issue to improve instruction throughput and computational performance. However, the execution efficiency of memory access instructions (Load / Store) has become a key bottleneck restricting the overall performance improvement of processors. In traditional out-of-order superscalar processors, memory access instructions need to be uniformly scheduled and managed through a Load-Store Queue (LSQ), which performs memory address comparison, data dependency detection, and memory access violation judgment. There are three main types of data dependencies among memory access instructions: Write After Write (WAW), Read After Write (RAW), and Write After Read (WAR). Accurate dependency detection and age determination are essential to ensure the sequential consistency of memory accesses.

[0003] Because traditional LSQs use a First-In, First-Out (FIFO) management model, logical address allocation is tightly coupled with physical memory units, and the address allocation depth is limited by the physical memory depth. Therefore, when logical address allocation is exhausted, even if there are still free resources in the physical memory, new memory access instructions cannot be allocated, causing the pipeline to be blocked. This pseudo-blocking phenomenon results in the effective utilization rate of LSQs being far lower than their physical capacity, leading to a waste of hardware resources.

[0004] It is evident that the LSQ storage space in related technologies suffers from low utilization efficiency. Summary of the Invention

[0005] This application aims to solve the problem of low utilization efficiency of LSQ storage space in related technologies, and provides a memory access optimization, register renaming and physical register file port arbitration device.

[0006] To solve the above problems, this application is implemented as follows:

[0007] In a first aspect, this application provides a memory access optimization apparatus, comprising: A virtual address configuration unit is configured to configure a virtual address space for a storage queue. The number of entries in the virtual address space is greater than the physical depth of the storage queue, so as to realize the repeated allocation of logical addresses of the storage queue. The virtual address of the virtual address space includes a low-order physical index bit and a high-order round-separation bit. The low-order physical index bit is used to index the physical entries of the storage queue, and the high-order round-separation bit is used to distinguish different memory access instructions that reuse the same physical entry. A relative instruction detection circuit, coupled to the virtual address configuration unit, is configured to generate a relative instruction address based on the inverted result of the high-order round-separation bits of the target memory access instruction and the low-order physical index bits of the target memory access instruction when the target memory access instruction is written to the memory queue; detect the occupancy status of the relative instruction address and set an occupancy flag; and allow the target memory access instruction to be issued and executed when the occupancy flag indicates that no relative instruction is occupied.

[0008] Secondly, this application provides a fast recovery device for a register renaming mapping table, comprising: The vector register is configured to dynamically update a first vector and a second vector on the branch prediction path. Each bit of the first vector corresponds to a logical register and is used to indicate whether the mapping of the logical register has been modified. Each bit of the second vector corresponds to an instruction entry in the reordering cache and is used to mark the instruction entry that first modifies the mapping of the corresponding logical register on the branch path. A renaming control circuit, coupled to the vector register, is configured to, during the renaming phase, for the current instruction, determine the corresponding bit of the destination register of the current instruction in the first vector. If the corresponding bit is a first state value, indicating that the logic register has not been modified on the branch prediction path, then the corresponding position of the reorder cache entry corresponding to the current instruction in the second vector is marked as valid, and the corresponding bit in the first vector is updated to a second state value. If the corresponding bit is the second state value, indicating that the logic register has been modified, then the second vector is not marked. A recovery execution circuit, coupled to the vector register, is configured to, in response to a branch prediction error signal, read only the old physical register mapping stored in the reordered cache entries with valid tags in the second vector and write it back to the rename mapping table.

[0009] Thirdly, this application provides a physical register file port arbitration device, comprising: The read port bypass prediction circuit is configured to set a lifetime indicator for each source operand in the issue queue. The lifetime indicator remains valid for a predetermined period after the operand is woken up. When an instruction is issued, if the lifetime indicator indicates that the operand can be obtained through the bypass network, the operand is prohibited from competing for the read port of the physical register file. The write-back buffer is configured to set up a write-back buffer between the execution level and the write-back level to temporarily store the execution results of multiple instructions; A flow control state machine, coupled to the write-back buffer, is configured to dynamically adjust the instruction quota allowed to be written to the write-back buffer each cycle based on the current occupancy depth of the write-back buffer.

[0010] Fourthly, this application provides a dual-issue out-of-order superscalar microprocessor, comprising: The memory access optimization device as described in the first aspect; The register renaming mapping table fast recovery device as described in the second aspect; and... As described by the third party, the physical register file port arbitration device.

[0011] Compared with existing technologies, this application has the following advantages: By configuring a virtual address space with a number of entries greater than the physical depth for the storage queue, and using the bit inversion operation of high-order rounds to generate relative instruction addresses, combined with the detection and issuance control of the occupancy flag, the logical capacity of the storage queue is effectively expanded. Compared with the traditional management method where the logical capacity of the storage queue is strictly equal to the physical depth, the physical space utilization efficiency of the storage queue is significantly improved. At the same time, through the accurate positioning and occupancy detection of relative instructions, data security is ensured in the scenario of repeated address allocation, providing a low-cost and high-efficiency resource management solution for the memory access unit of out-of-order superscalar processors. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the memory access optimization device provided in one embodiment of this application; Figure 2 This is a schematic diagram of a storage queue address duplication allocation circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of a relative instruction detection circuit provided in an embodiment of this application; Figure 4 This is a diagram of a dual-issue, seven-stage pipelined superscalar processor architecture provided in one embodiment of this application; Figure 5 This is a schematic diagram of right shifting of the flag vector according to an embodiment of this application; Figure 6 This is a schematic diagram illustrating an example of age comparison provided in an embodiment of this application; Figure 7 This is an example diagram of an age comparison process provided in an embodiment of this application; Figure 8 This is a schematic diagram of an LDQ address compression algorithm provided in an embodiment of this application; Figure 9 This is a diagram illustrating a conflict example of the LDQ address compression algorithm provided in an embodiment of this application; Figure 10 This is a circuit diagram of a mapping table recovery method based on reordered cache tags provided in an embodiment of this application; Figure 11 This is a schematic diagram of a read port arbitration circuit provided in an embodiment of this application; Figure 12 This is a schematic diagram illustrating the timing relationship between instruction wake-up and bypass acquisition provided in an embodiment of this application; Figure 13 This is a schematic diagram of a write port arbitration circuit provided in an embodiment of this application; Figure 14 This is a write port arbitration flow control state machine provided in one embodiment of this application. Detailed Implementation

[0014] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] The terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Additionally, the use of "and / or" in this application indicates at least one of the connected objects, such as A and / or B and / or C, representing seven possibilities: including A alone, B alone, C alone, and the presence of both A and B, both B and C, both A and C, and the presence of A, B, and C.

[0016] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0017] See Figure 1 , Figure 1 This is a schematic diagram of the memory access optimization device provided in one embodiment of this application. Figure 1 The memory access optimization device shown includes: The virtual address configuration unit 101 is configured to configure a virtual address space for a storage queue, wherein the number of entries in the virtual address space is greater than the physical depth of the storage queue, so as to realize the repeated allocation of logical addresses of the storage queue.

[0018] The virtual address space includes a low-order physical index bit and a high-order round-separation bit. The low-order physical index bit is used to index the physical entries of the storage queue, and the high-order round-separation bit is used to distinguish different memory access instructions that reuse the same physical entry.

[0019] The aforementioned store queue (STQ) can be understood as a physical hardware queue with a fixed physical depth, i.e., a fixed number of physical entries. Each physical entry corresponds to an independent hardware storage unit used to temporarily store non-retired memory access instructions, such as temporarily storing load instructions and store instructions. Each entry needs to be accessed through a physical address index. The bit width of the physical address is determined by the physical depth. For example, a store queue with 8 physical entries corresponds to a 3-bit physical address, which can cover the physical entry indices from 0 to 7.

[0020] The Load and Store instructions mentioned above are core instructions in computer architecture used to transfer data between registers and memory.

[0021] In some embodiments, the number of entries in the virtual address space is twice the physical depth, and the bit width of the virtual address is one bit greater than the bit width of the physical address of the storage queue.

[0022] In some embodiments, the number of entries in the virtual address space can be N times the physical depth of the storage queue, where N is an integer greater than 1. For example, when N is 2, 8 physical queue entries correspond to 16 virtual address space entries. That is, when the physical depth of the storage queue is 8, the number of entries in the virtual address space is 16, thereby realizing the repeated allocation of logical addresses in the storage queue, allowing the same physical entry to be reused in multiple rounds of memory access instructions.

[0023] Specifically, if the storage queue has 8 entries (i.e., a physical depth of 8) and a physical address of 3 bits, and the virtual address space has 16 entries and a virtual address of 4 bits, then the lower 3 bits of the virtual address can be set as physical index bits to index the 8 physical entries, and the higher 1 bit of the virtual address can be set as a round-separating bit to distinguish memory access instructions that reuse the same physical entry in two rounds. For example, when the higher 1 bit is 0, it corresponds to the first round instruction; when the higher 1 bit is 1, it corresponds to the second round instruction, thus realizing the cyclical use of physical entries.

[0024] The relative instruction detection circuit 102 is coupled to the virtual address configuration unit 101. The relative instruction detection circuit 102 is configured to generate a relative instruction address based on the inversion result of the high-order round distinction bit of the target memory access instruction and the low-order physical index bit of the target memory access instruction when the target memory access instruction is written to the memory queue; detect the occupancy status of the relative instruction address and set an occupancy flag bit; and allow the target memory access instruction to be issued and executed when the occupancy flag bit indicates that no relative instruction is occupied.

[0025] In some embodiments, if the high-order rounds of the target memory access instruction is 1, then its inversion result is to set the high-order rounds of the target memory access instruction from 1 to 0; correspondingly, if the high-order rounds of the target memory access instruction is 0, then its inversion result is to set the high-order rounds of the target memory access instruction from 0 to 1.

[0026] The low-order address of the generated relative instruction address is the same as the low-order address of the target memory access instruction, while its high-order address is the inverted result of the high-order round distinction of the target memory access instruction.

[0027] In some embodiments, if the high-order address of the target memory access instruction is 1 and the low-order address is 011, then the relative instruction address is 1011; correspondingly, if the high-order address of the target memory access instruction is 0 and the low-order address is 011, then the relative instruction address is 0011.

[0028] In some embodiments, a relative instruction can be defined as a memory access instruction that reuses the same physical entry as the target memory access instruction and is in the previous round. Therefore, after inverting the high-order round identifier of the target memory access instruction, it can correspond exactly to the round identifier of the previous round, thereby accurately locating the relative instruction that reuses the physical entry in the previous round, providing an accurate address basis for subsequent occupancy status detection.

[0029] Before executing the target memory access instruction, it is necessary to check the occupancy status of the relative instruction address and set the occupancy flag (Occupied bit) of the target memory access instruction. This is to avoid data overwriting when multiple rounds of instructions reuse the same physical entry. For example, it is to prevent the situation where the relative instruction from the previous round has not retired and is still occupying the physical entry, and the target memory access instruction in the next round directly writes it, resulting in data loss.

[0030] In some embodiments, detecting the occupancy status of the relative instruction address and setting the occupancy flag includes: Check the busy vector of the storage queue or load queue (LDQ) to see if the relative instruction address is occupied; If the memory is occupied, the occupancy flag of the target memory access instruction is set to prevent the target memory access instruction from being issued; If the memory is not occupied, the occupancy flag of the target memory access instruction is cleared to allow the target memory access instruction to be issued.

[0031] like Figure 1 As shown, the logic of the memory access optimization mechanism is as follows: as long as the occupancy flag is 1, the arbitrator guarantees that the instruction will not be executed. Therefore, by setting the occupancy flag to 1, two instructions can be prevented from using the same register simultaneously. Setting the occupancy flag to 0 allows subsequent instructions to use the register address.

[0032] Therefore, when reading an instruction, a register address is allocated sequentially in the Virtual Address Configuration Unit. Then, it's necessary to check if this register is already in use. This requires converting it to a relative instruction and checking if the corresponding relative instruction is in the queue. If it is, it means the register is in use, so its own in-use flag is set to 1, preventing the current memory access instruction from being issued and thus avoiding conflicts caused by multiple instructions sharing the same address resource. If the register is not in use, its own in-use flag is set to 0, allowing the instruction to be issued normally.

[0033] Then, after an instruction is executed, its physical register address is converted to a relative instruction address, and the occupancy flag of that address is set to 0, which means that the relative instruction is released from occupancy and allowed to execute.

[0034] In some embodiments, a busyvec bit vector of the same length as the virtual address space is maintained in the storage queue. Each bit of the bit vector corresponds to a virtual address and is used to mark whether the memory access instruction corresponding to the virtual address is in an occupied state, that is, the instruction has not retired and still occupies a physical entry. After generating the relative instruction address of the target memory access instruction, the bit corresponding to the relative instruction address in the busyvec bit vector can be queried. If the bit is 1, it means that the relative instruction is still in an occupied state, that is, it has not retired, and the occupancy flag of the target memory access instruction is set to 1, that is, marked as "blocked"; if the bit is 0, it means that the relative instruction has retired and the physical entry has been released, and the occupancy flag of the target memory access instruction is set to 0, that is, marked as "issueable".

[0035] In some embodiments, when a target memory access instruction enters the issue phase, the processor needs to simultaneously verify two conditions: first, the operand ready signal (rdy), ensuring that the operands and computation data of the target memory access instruction are ready; and second, the occupancy flag status, ensuring that no relative instruction occupies the corresponding physical entry. The target memory access instruction is only allowed to be issued and executed when both conditions are met simultaneously (rdy=1 and occupancy flag=0). If the occupancy flag=1, the target memory access instruction is blocked until the relative instruction retires and the physical entry is released, at which point the issue conditions are re-verified.

[0036] In some embodiments, when a relative instruction finishes execution and retires, it generates its own relative instruction address according to the same logic as in step 102, clears the bit corresponding to that address in the busyvec bit vector, and clears the occupancy flag bit of the target memory access instruction to release the blocking of the target memory access instruction, ensuring that the physical entry can be reused in the next round of instructions.

[0037] In some embodiments, the above process may refer to Figure 2 The schematic diagram of the storage queue address redundancy allocation circuit shown is as follows: Figure 3 The diagram shows a relative command detection circuit.

[0038] In this application, by configuring a virtual address space with a number of entries greater than the physical depth for the storage queue, and by using the bit inversion operation of the high-order round to generate relative instruction addresses, combined with the detection and issuance control of the occupancy flag, the logical capacity of the storage queue is effectively expanded. Compared with the traditional management method where the logical capacity of the storage queue is strictly equal to the physical depth, the physical space utilization efficiency of the storage queue is significantly improved. At the same time, through the precise location and occupancy detection of relative instructions, data security is ensured in the scenario of repeated address allocation, providing a low-cost and high-efficiency resource management solution for the memory access unit of the out-of-order superscalar processor.

[0039] In some embodiments, the memory access optimization apparatus provided in this application can be applied to, for example... Figure 4 The processor architecture shown includes a seven-stage pipeline, specifically comprising instruction fetch, decode, register renaming, issue, register read, execution, and write-back stages.

[0040] In some embodiments, the instruction fetch stage fetches four instructions per cycle according to PC[3:2], and the PC-Gshare algorithm can be used for branch prediction to reduce the impact of control hazards; the decoding stage can use two parallel decoders to decode instructions; register renaming can map logical registers to physical registers to eliminate the false data dependency of out-of-order execution; a recovery circuit is implemented to handle the state recovery of register renaming units during branch error prediction; the issue stage and the register renaming stage together constitute an efficient instruction scheduling module, which can use a specific arbitration algorithm to select executable instructions from the queue; in the register read stage, physical registers can be read and bypass operations can be performed. In view of the reduced number of read ports of the Physical Register File (PRF) in this application, a port arbitration mechanism is introduced before this stage to resolve access conflicts; in the execution stage, various execution units execute instruction functions, and the results are written back to the physical register file in the write-back stage; after renaming, the instructions enter the reorder cache (ROB) in sequence, and are committed in order after execution.

[0041] In some embodiments, under a dual-issue architecture, memory access instructions are enqueued in the original program order, so that the entries within the LSQ naturally maintain a physical arrangement from oldest to newest according to instruction age.

[0042] In some embodiments, LSQ uses write pointers and read pointers to implement entry address allocation and resource status management. There are two typical relative relationships between read and write pointers: when the write pointer leads the read pointer, the LSQ entries within the two pointer intervals are occupied, and the remaining entries are idle; when the read pointer surrounds and leads the write pointer, the entries within the two pointer intervals are idle, and the remaining entries remain occupied. Regarding the two relative pointer positions in the above-mentioned circular FIFO, this design performs the following processing in memory access violation and data forwarding checks: the access address of the Load instruction is compared in parallel with the entry address of the STQ section to obtain the address matching vector matchvec; then, matchvec is cyclically shifted right based on the read pointer to align it. After alignment, the lower address of the vector corresponds to the older instruction in the program sequence, and the higher address corresponds to the younger instruction. This organizes the circularly distributed queue entries into a logically monotonically ordered layout from old to new, facilitating rapid division of instruction age boundaries and completion of correlation judgment. The right-shift mapping method of the flag vector is shown in Figure 5.

[0043] In some embodiments, when dependency checks are performed during the execution phase, there exists a dividing line in the STQ for a load instruction, with older store instructions on one side of this dividing line and newer store instructions on the other side.

[0044] In some embodiments, it can be based on Figure 6 The illustrated example of age comparison shows how to obtain this dividing line. Specifically, during the register renaming phase, when a Load instruction is allocated, the current STQ allocation pointer, i.e., the position of the latest Store instruction, is written to last_st_RAM and saved as an "age snapshot" of the Load instruction; similarly, when a Store instruction is allocated, the current LDQ allocation pointer is recorded in last_ld_RAM.

[0045] In some embodiments, during the register renaming phase, when a Load instruction is allocated, the system writes the position of the latest preceding Store instruction in the STQ to a dedicated last_st RAM for storage; similarly, when a Store instruction is allocated, the allocation address of the current LDQ is also written to last_ld RAM. During the dependency check in the execution phase, the Load instruction reads a pre-stored pointer snapshot from last_st RAM and subtracts it from the current STQ's read pointer. The calculated difference completes the linearization mapping of the circular queue, essentially shifting the queue logic to the right to a state starting from the current read pointer, logically establishing the boundary between old and new instruction sequences. Then, based on this difference, a bitmask vector either older_mask or younger_mask is generated through comparison logic. In older_mask, all positions with indices less than the difference are marked as 1, indicating they are older, while positions with logical indices greater than or equal to the difference are marked as 0, indicating they are newer. The judgment logic for younger_mask is the opposite.

[0046] In some embodiments, for the Load instruction, the result of a bitwise AND operation between `older_mask` and `matchvec_shift` is used to obtain the `older` vector. If the `older` vector is all 0s, it means there is no Store instruction older than the current Load instruction at the same address, so Load reads data from memory. Otherwise, it is necessary to determine whether it is a data forwarding or a data violation. If the corresponding Store instruction has not been completed, it is a memory access violation, and the execution of the Load instruction needs to be paused, waiting for the old Store to be committed before rereading the data. If the corresponding Store instruction has been completed, data forwarding can be performed, and the temporary data of the Store can be directly forwarded to Load without waiting for the Store to write content. When there are multiple bits of 1 in the `older` vector, it indicates that there are multiple Store instructions that meet the conditions. In this case, the Store instruction corresponding to the set bit with the largest index value in the `older` vector should be selected, that is, the one that is closest to the Load instruction in program order among all matching Store instructions, for subsequent data forwarding or dependency judgment.

[0047] In some embodiments, for Store instructions, a bitwise AND operation is performed using `younger_mask` and `matchvec_shift` to obtain a younger vector. If there is a bit set to 1 in the younger vector, it indicates that there is a Load instruction that is sequentially placed after the Store but has been executed beforehand and has an address conflict with it. This suggests that these Load instructions may have read incorrect data, and therefore, after the current Store completes, these Load instructions need to be rolled back or re-executed to ensure memory consistency.

[0048] In some embodiments, such as Figure 7 The example shown illustrates how to distinguish between older and newer instructions during the forward check. S0-S5 are Store instructions, L0 and L1 are Load instructions, and the Store instruction following L1 is S4. S4's address in the STQ is 5, therefore L1's last_st equals 5. Assuming that when L1 executes, the STQ read pointer points to address 2, the difference is 3, and the value of older_mask is 0x03. If the addresses of S1, S2, and S5 are the same as L1's, then matchvec is 0x4C, and matchvec_shift is 0x13. The result of ANDing older_mask and matchvec_shift is 0x03, indicating that there are two Store instructions that both match L1's address and are pre-ordered by L1. In this case, the Store instruction corresponding to the largest set bit in the older vector is selected, i.e., the Store instruction closest to L1 in order (S2). Then, based on S2, it is determined whether to trigger data forwarding or execute a wait mechanism.

[0049] In some embodiments, the memory access optimization apparatus further includes a load queue address compression detection circuit, which is configured to: The physical addresses in the loading queue are compressed into address tags using a hash folding algorithm, and the address tags are stored in the loading queue. Generate a byte mask based on the instruction type and physical address; During memory access violation detection, the address label and the byte mask are compared in parallel, and the candidate violation instruction is determined by combining the age order condition.

[0050] In this embodiment, the physical address stored in the loading queue is compressed into an address label by a hash folding algorithm, such as reducing the storage bit width from 32 bits to 15 bits, which significantly reduces the storage overhead of the loading queue. At the same time, the byte mask can be used to accurately determine the overlapping of access areas, and the violation candidate instructions can be screened by combining the age order condition.

[0051] Thus, even if hash folding introduces false positive collisions, the detection logic based on age conditions and prioritizing the oldest match ensures the correctness of program execution. Collisions may only trigger safe but unnecessary pipeline flushing, without causing data errors. Therefore, this application achieves a significant reduction in LDQ storage area and comparator power consumption with minimal performance loss while maintaining functional correctness, making it particularly suitable for resource-constrained embedded processor designs.

[0052] In some embodiments, this application provides a method such as Figure 8The diagram shown illustrates the LDQ address compression algorithm, which includes an address compressor, a mask generator, and hash folding logic.

[0053] Specifically, in order to reduce the bit width of full address comparison during violation detection, the LDQ stores compressed address tags instead of the complete 32-bit physical address.

[0054] Since processors are typically 32-bit or 64-bit, and memory units are typically 32 bits (4 bytes), the higher 30 bits of the address are represented in 4-byte increments. The address is in units of 8 (32 bits), with the lower 2 bits being the word offset. By separating the word offset and excluding it from the high-order address XOR compression, and only performing address compression comparison on the high 30 bits, the accuracy of address compression comparison can be effectively improved, and the probability of false positives and false collisions in violation checks can be reduced.

[0055] In some embodiments, the address compressor employs a hash folding algorithm: for a 32-bit physical address, the high 30 bits [31:2] are taken, and the high 15 bits are XORed with the low 15 bits [16:2] to generate a 15-bit compressed tag. Simultaneously, the mask generator uses the lowest 2 bits [1:0] of the address combined with the instruction type (word, half-word, byte) to generate a 4-bit byte mask. When the Store instruction is executed and violation detection is performed, its address also undergoes the same compression and mask generation process.

[0056] The violation comparator searches for a Load instruction in the LDQ that meets all three of the following conditions: 1) the compression tag matches; 2) the byte mask overlaps; and 3) the Load instruction is younger than the Store instruction.

[0057] Understandably, while hash folding may introduce hash collisions (False Positives), only Load instructions younger than Store will be flagged as violations.

[0058] In some embodiments, this application provides a method such as Figure 9The diagram illustrates a conflict example in the LDQ address compression algorithm. For a store instruction, assuming that load2 is the only instruction that truly constitutes its RAW data dependency, other load instructions that might cause misjudgments can be categorized into three cases: one is like load0, where the program order precedes the store instruction; another is like load1, where the program order follows the store instruction but precedes load2; and the third is like load3, where the program order follows load2. Since violation checks have two conditions—address and age—and load0 can be removed based on the condition that the load instruction is newer than the store instruction, misjudgments caused by instructions like load0 will not have any impact. When load3 causes a misjudgment, since violation checks select the oldest instruction as the result when there are multiple matches (i.e., load2), this misjudgment will still not have any impact. Only when a load instruction, such as load1, occurs between store and load2 instructions, does it cause an address misjudgment, leading to a change in the final selected result. In this case, the violation check will select load1 and mark it as an exception. This misjudgment only causes safe but unnecessary pipeline flushing and will not affect the correctness of program execution. Thus, the area and power consumption of the LDQ comparator are significantly reduced while maintaining correct functionality.

[0059] In related technologies, out-of-order superscalar processors rely on register renaming techniques to improve instruction execution parallelism. To implement register renaming, a renaming mapping table is needed to maintain the mapping relationship between logical and physical registers. Speculative execution based on branch prediction is a common performance improvement technique in processor design. However, when a branch prediction error occurs, in addition to re-fetching instructions, the renaming mapping table also needs to be restored. Among existing recovery methods, the WALK method suffers from long blocking cycles, while the checkpointing method has high resource overhead. Both methods struggle to balance recovery efficiency and resource consumption, thus hindering the overall performance improvement of the processor.

[0060] To address the problems existing in the above-mentioned register renaming process, this application also provides a register renaming mapping table fast recovery device, comprising: The vector register is configured to dynamically update a first vector and a second vector on the branch prediction path. Each bit of the first vector corresponds to a logical register and is used to indicate whether the mapping of the logical register has been modified. Each bit of the second vector corresponds to an instruction entry in the reordering cache and is used to mark the instruction entry that first modifies the mapping of the corresponding logical register on the branch path. A renaming control circuit, coupled to the vector register, is configured to, during the renaming phase, for the current instruction, determine the corresponding bit of the destination register of the current instruction in the first vector. If the corresponding bit is a first state value, indicating that the logic register has not been modified on the branch prediction path, then the corresponding position of the reorder cache entry corresponding to the current instruction in the second vector is marked as valid, and the corresponding bit in the first vector is updated to a second state value. If the corresponding bit is the second state value, indicating that the logic register has been modified, then the second vector is not marked. A recovery execution circuit, coupled to the vector register, is configured to, in response to a branch prediction error signal, read only the old physical register mapping stored in the reordered cache entries with valid tags in the second vector and write it back to the rename mapping table.

[0061] In this embodiment, by dynamically updating the first and second vectors, the instruction entries that "modify" each logic register for the first time are accurately identified and marked on the branch prediction path. Therefore, when a branch prediction error occurs, only these marked key ROB entries are read to restore the mapping table, avoiding the traditional WALK method's traversal of a large number of invalid or redundant intermediate states.

[0062] With this configuration, the solution provided in this application can achieve a balance between recovery speed and hardware resources, and is particularly suitable for embedded out-of-order superscalar processor designs that require high branch prediction performance but are resource-constrained.

[0063] In some embodiments, the vector register includes a first vector register and a second vector register, the first vector register being configured to dynamically update a first vector and the second vector register being configured to dynamically update a second vector; wherein, the recovery execution circuitry may be coupled to the second vector register to read only the old physical register mapping stored in the reordered cache entries with valid tags in the second vector and write it back to the rename mapping table in response to a branch prediction error signal.

[0064] In some embodiments, not all ROB entries contribute to the recovery of the mapping table during the implementation of the WALK method. The specific analysis in this application is as follows: instructions without a destination register (such as store, branch) have no effect on the mapping table; in the instruction sequence with the same destination register, only the last one is valid, and the instructions in between are only temporary states; the truly valid recovery entries are those instructions that "modify" the mapping of a certain logical register for the first time.

[0065] In some embodiments, this application provides a method such as Figure 10The diagram shows the circuit structure of the mapping table recovery method based on reordered cache tags. In hardware, two key data structures can be maintained for each branch instruction: the arf_GC (Architectural Register File Garbage Collection) vector and the rob_GC (Reorder Buffer Garbage Collection) bit vector. arf_GC is a 32-bit register, with each bit corresponding to a logical register, indicating whether the register's mapping has been modified. rob_GC is a bit vector of the same length as the ROB (Reorder Buffer Garbage Collection) and is used to mark the ROB entry that first modified the register mapping.

[0066] In some embodiments, during the renaming phase, for each instruction, the corresponding bit in the arrf_GC of its destination register is queried. If the bit is 0 (indicating the first modification), the rob_GC bit of the corresponding ROB entry for that instruction is set to 1, and the corresponding bit in the arrf_GC of that register is also set to 1. If the bit is already 1 (indicating it has been modified), the ROB entry is not marked. When a branch prediction error is detected, the processor only reads the mapping in the ROB entries marked by rob_GC and writes it back to the rename mapping table (RMT), thereby quickly restoring the mapping relationship.

[0067] With this configuration, only 10-20% of the total number of ROB items need to be restored, achieving a significant speedup compared to the item-by-item scanning of WALK. Experimental data shows that compared to the WALK method, the blocking cycle is reduced by 94%, and the performance is improved by 2.6% (CoreMark) and 0.8% (Dhrystone); compared to the Checkpointing method, the LUT and FF overhead are reduced by 6.8% and 10.5% respectively, but the performance is only 0.45% (CoreMark) and 0.86% (Dhrystone) lower, achieving an ideal balance between performance and resource consumption.

[0068] In some embodiments, the recovery of the free list can be achieved using a method similar to checkpointing: maintaining the freelist_GC vector to record the physical registers allocated after each branch, and achieving fast recovery by performing a bitwise AND operation between freelist_GC and the current free list when a branch error occurs.

[0069] In related technologies, the power consumption and area of ​​the physical register file are crucial to the overall performance of high-performance, multi-issue processors. A larger number of physical registers and access ports can improve instruction execution parallelism, but it negatively impacts processor clock speed, chip area, and power consumption. Therefore, reducing the number of physical register file access ports, and thus reducing its area and power consumption, while ensuring instruction execution parallelism has become a significant technical challenge in current processor design. Existing technologies lack sufficient optimization for port scheduling of the physical register file, making it difficult to effectively balance parallelism and hardware overhead; therefore, an efficient port arbitration scheme is urgently needed.

[0070] To address the problems existing in the aforementioned arbitration schemes, this application also provides a physical register file port arbitration device, comprising: The read port bypass prediction circuit is configured to set a lifetime indicator for each source operand in the issue queue. The lifetime indicator remains valid for a predetermined period after the operand is woken up. When an instruction is issued, if the lifetime indicator indicates that the operand can be obtained through the bypass network, the operand is prohibited from competing for the read port of the physical register file. The write-back buffer is configured to set up a write-back buffer between the execution level and the write-back level to temporarily store the execution results of multiple instructions; A flow control state machine, coupled to the write-back buffer, is configured to dynamically adjust the instruction quota allowed to be written to the write-back buffer each cycle based on the current occupancy depth of the write-back buffer.

[0071] In this embodiment, by setting a lifecycle indicator for each source operand, operands that can be obtained through the bypass network are accurately identified, and their contention for physical register stack read ports is prohibited, thereby reducing the read port requirement from 8 to 4. Moreover, by setting a write-back buffer between the execution stage and the write-back stage, and cooperating with the flow control state machine to dynamically adjust the write quota, the burst write-back traffic can be smoothed, and the write port requirement can be further reduced from 4 to 2.

[0072] With this setup, near-lossless performance can be achieved using only half the port resources of a traditional design, greatly reducing the design complexity and power consumption of multi-port register files. It is particularly suitable for resource-constrained embedded high-performance processors, IoT terminals, and edge computing devices.

[0073] In some embodiments, for read ports, to simplify the arbitration logic and reduce the latency caused by port arbitration, each read port in this application is contested by only two transmit queues. The read port arbitration circuit is as follows: Figure 11As shown in Table 1, after arbitration, four physical register numbers are obtained and sent to the physical register file read port, along with a read port grant signal indicating whether the ALU / DIV / CSR and ALU / MUL queues have competed for the read port. Arbitration is performed with a fixed priority, assigning higher priority to memory access instructions and branch instructions, as shown in Table 1.

[0074] Table 1: Arbitration Priority for Register Stack Read Ports

[0075] In some embodiments, a bypass prediction mechanism for the read port may be introduced.

[0076] Understandably, although theoretically 8 read ports are needed, in practice there is redundancy in read operations: not all 4 issue queues issue instructions simultaneously in each cycle; some operands are immediate values ​​and do not need to be read from the register file; a large number of operands can be obtained directly through the bypass network without accessing the physical register file.

[0077] like Figure 12 As shown, if an instruction is issued in the first and second cycles after each register is woken up, the register value is obtained through the bypass network. Subsequently, the corresponding value has been written to the physical register file and needs to be read from it. To achieve bypass identification, this application adds a 2-bit shift register to the source register of each instruction in the issue queue. When the register is woken up in the ROB, this shift register will be non-zero for the next two cycles. The shift register state is checked during instruction issuance: if one bit is still non-zero, it indicates that the operand can be obtained through the bypass network without contention for the read port. Through this bypass prediction, the number of read ports can be reduced from 8 to 4, with a negligible performance impact.

[0078] In some embodiments, the reason for redundancy in the write port is: (1) not every cycle has instructions issued from the four issue queues; (2) some instructions do not need to be written back, such as store instructions and conditional branch instructions.

[0079] In some embodiments, if write port arbitration is performed after instruction wake-up, instructions that have not won the write port need to be blocked, causing a delay in the time it takes for these instructions to obtain their operation results. Instructions woken up by these instructions will also be unable to execute because they cannot obtain the source operands in time. This requires additional logic to track these woken-up instructions, similar to speculative wake-up of load instructions, increasing resource overhead. Therefore, in this application, the write port arbitration time is the same as the instruction wake-up time. ALU instructions are woken up during the issue phase and are delayed if they do not win the write port. Multiplication instructions are woken up during the register read phase and are blocked during the register read phase if they do not win the write port, while simultaneously stopping the issue of the ALU / MUL queue. Division instructions are blocked when they do not win the write port. Branch instructions and memory access instructions have the highest priority and can write back two instructions per cycle, so they will not encounter situations where they cannot win the write port. For details, please refer to [reference needed]. Figure 13 The diagram shows the write port arbitration circuit.

[0080] In some embodiments, the physical register file is configured with only 2 write ports, and the instructions in each queue are arbitrated according to the priority in Table 2. Instructions that do not compete for a write port are delayed in execution.

[0081] Table 2: Register Write Port Arbitration Priority

[0082] Unlike read ports, write ports need to handle bursts of write-back traffic. If the number of write-back instructions allowed during arbitration is limited to two or fewer, it will significantly impact processor performance. Therefore, this application sets up a write-back buffer with a capacity of 4 in front of the physical register file to store the results of instruction execution, so as to allow more instructions that need to be written back to be sent at the same time and reduce pipeline congestion caused by insufficient number of write ports.

[0083] In some embodiments, since the buffer outputs a fixed two write-back results per cycle, a maximum of four instructions are allowed to write results to the write-back buffer per execution cycle. Furthermore, to prevent buffer overflow, a state machine can be used to control the maximum number of instructions allowed to write at any given time.

[0084] In some embodiments, this application also provides a method such as Figure 14The write port arbitration flow control state machine shown strictly follows the dynamic changes in buffer occupancy during state transitions. Specifically, IDLE indicates that there are 0-2 results in the current buffer with a capacity of 4, GOT_3 indicates 3 results, and GOT_4 indicates 4 results. In IDLE, the state transitions to GOT_3 when three write-back instructions are added to the buffer, or to GOT_4 when four are added. In the GOT_3 state, it means that there is 1 space remaining in the buffer. When three write-back instructions are added to the buffer, because two instructions will be sent simultaneously, the buffer will reach 4 instructions, and the state transitions to GOT_4. This state is maintained when two instructions are sent, and returns to IDLE when there are fewer than two. In the GOT_4 state, the state continues when two write-back instructions are added to the buffer, falls back to GOT_3 when one is added, and returns to IDLE when there are none.

[0085] In this embodiment, through joint optimization of bypass prediction and write-back buffer, the area of ​​the physical register file is reduced from 129,645 μm² to 78,820 μm², a reduction of 39.2%, accounting for 7.8% of the total processor area. Performance remains at 99.1% (CoreMark) and 99.13% (Dhrystone), with only about 3.1% of issue requests delayed due to read port contention, achieving a 39.2% area reduction at a performance cost of less than 1%.

[0086] In some embodiments, the solution provided in this application can reduce hardware resource consumption through systematic resource optimization. On the Zynq-7000, only 14506 LUTs and 5602FFs are required, providing a high-performance, low-power processor solution for embedded, IoT and edge computing applications.

[0087] This application also provides a dual-issue out-of-order superscalar microprocessor, including the above-mentioned memory access optimization device, the above-mentioned register renaming mapping table fast recovery device, and the above-mentioned physical register file port arbitration device.

[0088] The dual-issue out-of-order superscalar microprocessor can implement the various processes of the memory access optimization device, the register renaming mapping table fast recovery device, and the physical register file port arbitration device embodiments in this application, and achieve the same beneficial effects. To avoid repetition, these will not be described in detail here.

[0089] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0091] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A memory access optimization device, characterized in that, include: A virtual address configuration unit is configured to configure a virtual address space for a storage queue. The number of entries in the virtual address space is greater than the physical depth of the storage queue, so as to realize the repeated allocation of logical addresses of the storage queue. The virtual address of the virtual address space includes a low-order physical index bit and a high-order round-separation bit. The low-order physical index bit is used to index the physical entries of the storage queue, and the high-order round-separation bit is used to distinguish different memory access instructions that reuse the same physical entry. A relative instruction detection circuit, coupled to the virtual address configuration unit, is configured to generate a relative instruction address based on the inverted result of the high-order round distinction bit of the target memory access instruction and the low-order physical index bit of the target memory access instruction when the target memory access instruction is written to the memory queue; detect the occupancy status of the relative instruction address and set an occupancy flag bit; and allow the target memory access instruction to be issued and executed when the occupancy flag bit indicates that no relative instruction is occupied.

2. The apparatus according to claim 1, characterized in that, The device further includes a load queue address compression detection circuit, configured as follows: The physical addresses in the loading queue are compressed into address tags using a hash folding algorithm, and the address tags are stored in the loading queue. Generate a byte mask based on the instruction type and physical address; During memory access violation detection, the address label and the byte mask are compared in parallel, and the candidate violation instruction is determined by combining the age order condition.

3. The apparatus according to claim 1, characterized in that, The step of detecting the occupancy status of the relative instruction address and setting the occupancy flag includes: Check whether the relative instruction address is occupied in the busy vector of the storage queue or load queue; If the memory is occupied, the occupancy flag of the target memory access instruction is set to prevent the target memory access instruction from being issued; If the memory is not occupied, the occupancy flag of the target memory access instruction is cleared to allow the target memory access instruction to be issued.

4. The apparatus according to any one of claims 1 to 3, characterized in that, The number of entries in the virtual address space is twice the physical depth, and the bit width of the virtual address is one bit greater than the bit width of the physical address of the storage queue.

5. A fast recovery device for a register renaming mapping table, characterized in that, include: The vector register is configured to dynamically update a first vector and a second vector on the branch prediction path. Each bit of the first vector corresponds to a logical register and is used to indicate whether the mapping of the logical register has been modified. Each bit of the second vector corresponds to an instruction entry in the reordering cache and is used to mark the instruction entry that first modifies the mapping of the corresponding logical register on the branch path. A renaming control circuit, coupled to the vector register, is configured to, during the renaming phase, for the current instruction, determine the corresponding bit of the destination register of the current instruction in the first vector. If the corresponding bit is a first state value, indicating that the logic register has not been modified on the branch prediction path, then the corresponding position of the reorder cache entry corresponding to the current instruction in the second vector is marked as valid, and the corresponding bit in the first vector is updated to a second state value. If the corresponding bit is the second state value, indicating that the logic register has been modified, then the second vector is not marked. A recovery execution circuit, coupled to the vector register, is configured to, in response to a branch prediction error signal, read only the old physical register mapping stored in the reordered cache entries with valid tags in the second vector and write it back to the rename mapping table.

6. A physical register file port arbitration device, characterized in that, include: The read port bypass prediction circuit is configured to set a lifetime indicator for each source operand in the issue queue. The lifetime indicator remains valid for a predetermined period after the operand is woken up. When an instruction is issued, if the lifetime indicator indicates that the operand can be obtained through the bypass network, the operand is prohibited from competing for the read port of the physical register file. The write-back buffer is configured to set up a write-back buffer between the execution level and the write-back level to temporarily store the execution results of multiple instructions; A flow control state machine, coupled to the write-back buffer, is configured to dynamically adjust the instruction quota allowed to be written to the write-back buffer each cycle based on the current occupancy depth of the write-back buffer.

7. A dual-issue out-of-order superscalar microprocessor, characterized in that, include: The memory access optimization apparatus as described in any one of claims 1 to 4; The register renaming mapping table fast recovery apparatus as described in claim 5; and, The physical register file port arbitration device as described in claim 6.

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