Processor, register renaming method, chip and device

Abstract

The application discloses a processor, a register renaming method, a chip and equipment, and relates to the technical field of processors. The processor comprises an instruction processing unit and a plurality of execution modules. Each execution module comprises a register file, a bypass network, a plurality of functional units and a plurality of emission queues. In the execution module, the functional units and the emission queues correspond to each other, the emission queues are connected with the instruction processing unit and the corresponding functional units of the emission queues respectively, the bypass network is connected with each functional unit and the register file respectively, the instructions output by the instruction processing unit are cached through the emission queues, the instructions are executed through the functional units, the data of the instructions are stored through the register file, and the data is transmitted through the bypass network, so as to realize the functions of the back end of the processor. Since the different execution modules are independent of each other, the connection lines between the functional units of the different execution modules are reduced, and therefore, the design difficulty of the bypass network is reduced.

Description

Technical Field

[0001] This application belongs to the field of processor technology, specifically relating to a processor, a register renaming method, a chip, and a device. Background Technology

[0002] The processor backend is an important component of modern processor architecture, primarily responsible for instruction execution, data processing, and result generation.

[0003] In related technologies, the design of the bypass network in the processor backend is difficult because each functional unit in the processor backend is interconnected and requires a large number of lines. Summary of the Invention

[0004] This application aims to provide a processor, register renaming method, chip, and device, which at least solves the problem in the related art that the large number of lines required due to the interconnection of each functional unit in the back end of the processor leads to the difficulty in designing the bypass network in the back end of the processor.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, embodiments of this application provide a processor, including an instruction processing unit and multiple execution modules, each execution module including a register file, a bypass network, multiple functional units, and multiple issue queues; in each execution module, the functional units and the issue queues correspond to each other; In the execution module, the issue queue is connected to the instruction processing unit and the corresponding functional unit, respectively. The issue queue is used to buffer the instructions output by the instruction processing unit. The bypass network is connected to each functional unit and the register file, respectively. The bypass network is used to transfer data stored in the register file to the input of the functional unit, transfer data output from the output of the functional unit to the input of the functional unit, transfer data output from the output of one functional unit to the input of another functional unit, and transfer data output from the output of the functional unit to the register file for storage. The functional unit is used to execute the instruction. The register file is used to store the data of the instruction.

[0006] Secondly, embodiments of this application also provide a register renaming method, applied to the processor as described in the first aspect, wherein the register file of the execution module includes multiple physical registers, and the method includes: Get the first logical register pointed to by each first source operand of the instruction; Based on the processor's register renaming table, obtain the first physical register mapped to each of the first logical registers; the register renaming table is used to record the mapping relationship between logical registers and physical registers; Obtain the first execution module to which each of the first physical registers belongs, and determine the target execution module from the first execution modules according to a preset strategy; Obtain the second logical register pointed to by the destination operand of the instruction, and in the register renaming table, create a mapping relationship between the second logical register and the second physical register of the target execution module.

[0007] Thirdly, embodiments of this application also provide a chip, including the processor described in the first aspect.

[0008] Fourthly, embodiments of this application also provide an electronic device, including the chip described in the third aspect.

[0009] In this embodiment, the processor includes an instruction processing unit and multiple execution modules. Each execution module includes a register file, a bypass network, multiple functional units, and multiple issue queues. Within each execution module, functional units and issue queues correspond to each other. Issue queues are connected to the instruction processing unit and the corresponding functional units, respectively. The bypass network is connected to each functional unit and the register file. The issue queues buffer the instructions output by the instruction processing unit, and the functional units execute the instructions. The register file stores the instruction data. The bypass network transmits data stored in the register file to the input of the functional unit, transmits data output from the functional unit to the input of the functional unit, transmits data output from one functional unit to the input of another functional unit, and transmits data output from the functional unit to the register file for storage. This achieves the backend functionality of the processor. Furthermore, because different execution modules are independent of each other, the connection lines between the functional units of different execution modules are reduced, thereby lowering the design complexity of the bypass network. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a processor provided in an embodiment of this application; Figure 2 This is a schematic diagram of another processor structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of a bypass network structure provided in an embodiment of this application; Figure 4 This is a schematic diagram of a register file provided in an embodiment of this application; Figure 5This is a flowchart illustrating the steps of a register renaming method provided in an embodiment of this application; Figure 6 This is a flowchart of another register renaming method provided in an embodiment of this application; Figure 7 This is a schematic diagram of the processing flow of an instruction provided in an embodiment of this application.

[0011] Figure label: 10-Execution module; 11-Register file; 12-Bypass network; 121-First multiplexer; 122-Second multiplexer; 13-Functional unit; 14-Issue queue; 20-Instruction processing unit. Detailed Implementation

[0012] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0013] Reference Figure 1 This application provides a processor including an instruction processing unit 20 and multiple execution modules 10 (slices). Each execution module 10 includes a register file 11, a bypass network 12, multiple functional units 13, and multiple issue queues 14. In each execution module 10, the functional units 13 and the issue queues 14 correspond to each other. In each execution module 10, the issue queues 14 are connected to both the instruction processing unit 20 and the corresponding functional units 13, and the issue queues 14 are used to buffer the instructions output by the instruction processing unit 20. The bypass network 12 is connected to each... The functional unit 13 is connected to the register file 11. The bypass network 12 is used to transfer data stored in the register file 11 to the input of the functional unit 13, and to transfer data output from the output of the functional unit 13 to the input of the functional unit 13, as well as to transfer data output from the output of one functional unit 13 to the input of another functional unit 13, and to transfer data output from the output of the functional unit 13 to the register file 11 for storage. The functional unit 13 is used to execute the instruction. The register file 11 is used to store the data of the instruction.

[0014] It should be noted that register file 11 is the physical register file, which includes multiple physical registers. Register file 11 is used to store instruction data, including integers, instruction addresses, intermediate results of arithmetic and logical operations, etc. In addition, register file 11 is used to store status information and other data, such as status information related to processor control. Bypass network 12 is a high-speed network used for data transmission. Functional Unit 13 (FU) includes various types such as Arithmetic Logic Unit (ALU), Address Generation Unit (AGU), Load / Store Unit (LSU), Floating Point Unit (FPU), Branch Unit (BRU), Multiplier Unit (MUL), and Divider Unit (DIV). The Arithmetic Logic Unit performs integer arithmetic operations (such as addition and subtraction) and logical operations (such as AND, OR, and NOT). The Address Generation Unit calculates the address for memory access. The Branch Unit (BRU) processes branch instructions, checks branch conditions, and updates the program counter. The Load / Store Unit processes load and store instructions and interacts with memory. The floating-point arithmetic unit is used to handle floating-point operations, including floating-point addition, subtraction, multiplication, division, square root, and complex operations such as trigonometric functions; the branch unit is used to handle control flow instructions, such as branching, jumping, calling, and returning; the multiplication unit is used to perform integer multiplication operations, supporting various multiplication instructions, including signed and unsigned multiplication, as well as obtaining the high or low byte of the multiplication result; the division unit is used to perform integer division and modulo operations, supporting signed and unsigned division, as well as modulo operations.

[0015] Issue Queue 14 is a buffer used to store instructions that are about to be scheduled for execution. It acts as a buffer between instruction decoding and execution, allowing the processor to dynamically schedule instructions while satisfying dependencies and resource availability.

[0016] In some embodiments, the instruction processing unit 20 is of the type of processor frontend, which is an important component of modern processor architecture.

[0017] In some embodiments, the instruction processing unit 20 is primarily responsible for fetching instructions from the instruction cache, decoding instructions, and preparing instructions for subsequent execution phases (i.e., instruction execution phases). The instruction processing unit 20 ensures that instructions can efficiently enter the processor pipeline, providing a continuous instruction flow for the functional units 13 in the processor, thereby improving the overall performance of the processor.

[0018] For example, refer to Figure 2The processor includes an instruction processing unit 20 and two execution modules 10. Each execution module 10 includes a register file 11, a bypass network 12, five functional units 13, and five issue queues 14. The instruction processing unit 20 is connected to each issue queue 14. In each execution module 10, the first issue queue 14 is connected to the first functional unit 13, the second issue queue 14 is connected to the second functional unit 13, the third issue queue 14 is connected to the third functional unit 13, the fourth issue queue 14 is connected to the fourth functional unit 13, and the fifth issue queue 14 is connected to the fifth functional unit 13. The first functional unit 13 is a multiplication unit, the second functional unit 13 is a branch unit, the third functional unit 13 is a division unit, the fourth functional unit 13 is a floating-point arithmetic unit, and the fifth functional unit 13 is a floating-point arithmetic unit. The bypass network 12 is connected to each functional unit 13 and the register file 11.

[0019] In this embodiment, the processor includes an instruction processing unit 20 and multiple execution modules 10. Each execution module 10 includes a register file 11, a bypass network 12, multiple functional units 13, and multiple issue queues 14. In each execution module 10, the functional units 13 correspond to the issue queues 14. The issue queues 14 are connected to the instruction processing unit 20 and the corresponding functional units 13, respectively. The bypass network 12 is connected to each functional unit 13 and the register file 11. The issue queues 14 buffer the instructions output by the instruction processing unit 20, the functional units 13 execute the instructions, and the register file 11 stores the instructions. The data is transmitted through the bypass network 12, which transmits the data stored in the register file 11 to the input of the functional unit 13, transmits the data output from the functional unit 13 to the input of the functional unit 13, transmits the data output from the output of one functional unit 13 to the input of another functional unit 13, and transmits the data output from the output of the functional unit 13 to the register file 11 for storage, thereby realizing the functions of the processor backend. Since the different execution modules 10 are independent of each other, the connection lines between the functional units 13 of the different execution modules 10 are reduced, thereby reducing the design difficulty of the bypass network 12.

[0020] Optionally, in some embodiments, the bypass network 12 includes a plurality of first multiplexers 121 and at least one second multiplexer 122; in the execution module 10, each functional unit 13 has a corresponding first multiplexer 121 and second multiplexer 122; the output terminal of the first multiplexer 121 corresponding to the functional unit 13 is connected to one input terminal of the functional unit 13, the output terminal of the functional unit 13 is connected to one input terminal of each of the first multiplexers 121, and the output terminal of the functional unit 13 is also connected to one input terminal of the second multiplexer 122 corresponding to the functional unit 13; the output terminal of the second multiplexer 122 is connected to one input terminal of the register file 11; and the other input terminal of the first multiplexer 121 is connected to one output terminal of the register file 11.

[0021] It should be noted that both the first multiplexer 121 and the second multiplexer 122 are multiplexers (Mux, Multiplexer).

[0022] For example, refer to Figure 3 The processor includes an instruction processing unit 20 and two execution modules 10. Each execution module 10 includes a register file 11, a bypass network 12, two functional units 13, and two issue queues 14. The bypass network 12 includes four first multiplexers 121 and two second multiplexers 122. The instruction processing unit 20 is connected to each issue queue 14. In each execution module 10, the first transmit queue 14 is connected to the first functional unit 13, and the second transmit queue 14 is connected to the second functional unit 13; the first input of the first multiplexer 121 is connected to the output of the first functional unit 13, the second input of the first multiplexer 121 is connected to the first output of the register file 11, the third input of the first multiplexer 121 is connected to the output of the second functional unit 13, and the output of the first multiplexer 121 is connected to the first input of the first functional unit 13. The first input of the second first multiplexer 121 is connected to the output of the first functional unit 13, the second input of the second first multiplexer 121 is connected to the second output of the register file 11, the third input of the second first multiplexer 121 is connected to the output of the second functional unit 13, and the output of the second first multiplexer 121 is connected to the second input of the first functional unit 13. The first input of the third first multiplexer 121 is connected to the output of the first functional unit 13, the second input of the third first multiplexer 121 is connected to the third output of the register file 11, the third input of the third first multiplexer 121 is connected to the output of the second functional unit 13, and the output of the third first multiplexer 121 is connected to the first input of the second functional unit 13. The first input of the fourth first multiplexer 121 is connected to the output of the first functional unit 13, the second input of the fourth first multiplexer 121 is connected to the fourth output of the register file 11, the third input of the fourth first multiplexer 121 is connected to the output of the second functional unit 13, and the output of the fourth first multiplexer 121 is connected to the second input of the second functional unit 13. The first input of the second multiplexer 122 is connected to the output of the first functional unit 13, the second input of the second multiplexer 122 is connected to the output of the second functional unit 13, and the output of the second multiplexer 122 is connected to one input of the register file 11.

[0023] In this embodiment, the first multiplexer 121 can be used to input the data stored in the register file 11 to the functional unit 13, input the output of the functional unit 13 to the functional unit 13, and input the output of one functional unit 13 to another functional unit 13; the second multiplexer 122 can be used to input the output of the functional unit 13 to the register file 11 for storage.

[0024] Optionally, in some embodiments, the register files 11 of each of the execution modules 10 are interconnected.

[0025] In some embodiments, the connection between the two register files 11 is as follows: the read port of one register file 11 is connected to the write port of the other register file 11 to enable one register file 11 to obtain data from the other register file 11, and the write port of one register file 11 is connected to the read port of the other register file 11 to enable the other register file 11 to obtain data from one register file 11; wherein, the write port of register file 11 is the input terminal of register file 11, and the read port of register file 11 is the output terminal of register file 11.

[0026] In some embodiments, each physical register has a corresponding identifier, and the identifiers of each physical register in the processor are arranged in order to form an identifier set.

[0027] For example, refer to Figure 4The processor includes two execution modules 10, each execution module 10 having a register file 11 with three write ports and five read ports; the register file 11 of the first execution module 10 includes write port A1, write port A2, write port A3, read port B1, read port B2, read port B3, read port B4 and read port B5, and the register file 11 of the second execution module 10 includes write port A4, write port A5, write port A6, read port B6, read port B7, read port B8, read port B9 and read port B10; In the register file 11 of the first execution module 10, write ports A1 and A2 are both used to connect to the output of the second multiplexer 122 in the first execution module 10, and write port A3 is used to connect to the read port B10 of the register file 11 of the second execution module 10; read ports B1, B2, B3, and B4 are all used to connect to the input of the first multiplexer 121 in the first execution module 10, and read port B5 is used to connect to the write port A6 of the register file 11 of the second execution module 10. In the register file 11 of the second execution module 10, write ports A4 and A5 are both used to connect to the output of the second multiplexer 122 in the second execution module 10, and write port A6 is used to connect to the read port B5 of the register file 11 of the first execution module 10; read ports B6, B7, B8, and B9 are all used to connect to the input of the first multiplexer 121 in the second execution module 10, and read port B10 is used to connect to the write port A3 of the register file 11 of the first execution module 10. The register file 11 of the first execution module 10 can obtain data from the register file 11 of the second execution module 10 through the write port A3 of the register file 11 of the first execution module 10 and the read port B10 of the register file 11 of the second execution module 10; the register file 11 of the second execution module 10 can obtain data from the register file 11 of the first execution module 10 through the write port A6 of the register file 11 of the second execution module 10 and the read port B5 of the register file 11 of the first execution module 10. Each physical register in the processor is identified by an identifier set arranged in sequence. The identifiers of the physical registers in the identifier set are from 0 to 183, that is, the identifier set includes 0, 1, 2, ..., 182, 183. The register file 11 of the first execution module 10 includes 92 physical registers. The identifiers of the physical registers in the register file 11 of the first execution module 10 are from 0 to 91, that is, the identifiers of the physical registers include 0, 1, 2, ..., 90, 91. Therefore, the 92 physical registers in the register file 11 of the first execution module 10 include physical register 0, physical register 182, physical register 183, physical register 183, physical register 184, physical register 185, physical register 186, physical register 187, physical register 188, physical register 189 ... Register 1, physical register 2, ..., physical register 90, physical register 91; the register file 11 of the second execution module 10 includes 92 physical registers. In the register file 11 of the second execution module 10, the physical registers are identified as 92 to 183, that is, the physical registers are identified as 92, 93, 94, ..., 182, 183. Therefore, the 92 physical registers in the register file 11 of the second execution module 10 include physical register 92, physical register 93, physical register 94, ..., physical register 182, physical register 183.

[0028] In this embodiment of the application, since the register files 11 of each execution module 10 are interconnected, data exchange between the register files 11 of each execution module 10 can be realized.

[0029] Optionally, in some embodiments, each of the execution modules 10 corresponds to the same Register Alias ​​Table (RAT); each of the execution modules 10 has a corresponding Free List (FL).

[0030] It should be noted that the register renaming table is used to store the mapping relationship between logical registers and physical registers, and the free list corresponding to execution module 10 is used to store the identifiers of the free physical registers available for allocation in execution module 10. The free physical registers belong to the register file 11 in execution module 10. Among them, logical registers are registers visible in the program, defined by the instruction set architecture, and are the basis for program design and compiler optimization; physical registers are registers that actually exist in the processor hardware and are used to store data and status information.

[0031] In this embodiment, since each execution module 10 corresponds to the same register renaming table, each execution module 10 obtains the mapping relationship between the instruction-related logical registers and physical registers from the same register renaming table when executing an instruction, and then obtains the operands and stores the result of instruction execution according to the mapping relationship, which can realize unified management of the mapping relationship between the instruction-related logical registers and physical registers; since each execution module 10 has a corresponding free list, the free lists of each execution module 10 can be made independent of each other.

[0032] In summary, in this embodiment, the processor includes an instruction processing unit 20 and multiple execution modules 10. Each execution module 10 includes a register file 11, a bypass network 12, multiple functional units 13, and multiple issue queues 14. In each execution module 10, the functional units 13 and issue queues 14 correspond to each other. The issue queues 14 are connected to the instruction processing unit 20 and the corresponding functional units 13, respectively. The bypass network 12 is connected to each functional unit 13 and the register file 11. The issue queues 14 buffer the instructions output by the instruction processing unit 20, and then the functional units 13 execute the instructions. The instructions are stored in the register file 11. The system stores instruction data and transmits data stored in register file 11 to the input of functional unit 13 via bypass network 12, transmits data output from functional unit 13 to the input of functional unit 13, transmits data output from one functional unit 13 to the input of another functional unit 13, and transmits data output from the output of functional unit 13 to register file 11 for storage, thereby realizing the functions of the processor backend. Since the different execution modules 10 are independent of each other, the connection lines between the functional units 13 of the different execution modules 10 are reduced, thereby reducing the design difficulty of bypass network 12.

[0033] Figure 5 This is a flowchart illustrating the steps of a register renaming method provided in an embodiment of this application. The register renaming method is applied to a processor as described above, such as... Figure 5 As shown, the method may include: Step 101: Obtain the first logical register pointed to by each first source operand of the instruction.

[0034] It should be noted that the first source operand is a type of source operand. Source operands are operands that provide input data during instruction execution. The types of operands include logical register identifiers, memory addresses, immediate values, etc.; the number of source operands for an instruction is at least one.

[0035] For example, the instruction "ADD R1, R2, R3" adds the values ​​pointed to by logical register R2 and logical register R3, and stores the result in the physical register mapped by logical register R1. Here, the value pointed to by logical register R2 is the value stored in the physical register mapped by logical register R2, and the value pointed to by logical register R3 is the value stored in the physical register mapped by logical register R3. Both the values ​​pointed to by logical register R2 and logical register R3 are input data required for instruction execution, and the result of the addition is the output result of instruction execution. This instruction has two first source operands, "R2" and "R3". The first logical register pointed to by the first source operand "R2" is logical register R2, and the first logical register pointed to by the first source operand "R3" is logical register R3.

[0036] In this embodiment, storing the result of the instruction execution output of the functional unit 13 in one execution module 10 in the register file 11 of that execution module 10 results in a shorter transmission distance compared to storing the result of the instruction execution output of the functional unit 13 in one execution module 10 in the register file 11 of another execution module 10. Therefore, the execution efficiency of the instruction is higher. That is, storing at least one input data required for instruction execution and the result of instruction execution output in the same execution module 10 results in higher execution efficiency compared to storing each input data required for instruction execution and the result of instruction execution output in different execution modules 10. In order to store at least one input data required for instruction execution and the result of instruction execution output in the same execution module 10, it is first necessary to obtain the first logical register pointed to by each first source operand of the instruction. Then, based on the processor's register renaming table, the first physical register mapped to each first logical register is obtained, that is, the physical register where each input data of the instruction is located. Then, according to a preset strategy, a first execution module is selected as the target execution module from the first execution modules to which the first physical register belongs. In the register renaming table, a mapping relationship is created between the second logical register pointed to by the destination operand and the second physical register of the target execution module, so that the instruction can be executed through the target execution module, thereby storing at least one input data required for instruction execution and the result of instruction execution output in the same execution module 10.

[0037] Step 102: Based on the processor's register renaming table, obtain the first physical register mapped to each of the first logical registers; the register renaming table is used to record the mapping relationship between logical registers and physical registers.

[0038] In this embodiment of the application, since the register renaming table records the mapping relationship between logical registers and physical registers, after obtaining the first logical register pointed to by each first source operand of the instruction, the first physical register mapped to each first logical register can be obtained based on the processor's register renaming table, so as to obtain the first execution module to which each first physical register belongs.

[0039] Step 103: Obtain the first execution module to which each of the first physical registers belongs, and determine the target execution module from the first execution modules according to a preset strategy.

[0040] It should be noted that the first physical register is the physical register in register file 11 of the first execution module.

[0041] In this embodiment of the application, the first execution module to which each first physical register belongs is obtained, and the target execution module is determined from the first execution module according to a preset strategy. Then, after obtaining the second logical register pointed to by the destination operand of the instruction, a mapping relationship between the second logical register pointed to by the destination operand and the second physical register of the target execution module is created in the register renaming table.

[0042] Step 104: Obtain the second logical register pointed to by the destination operand of the instruction, and create a mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table.

[0043] It should be noted that the destination operand is the operand used to store the result of the instruction execution. For example, the instruction "ADD R1, R2, R3" adds the values ​​pointed to by logical register R2 and logical register R3, and stores the result in the physical register mapped by logical register R1. Here, the value pointed to by logical register R2 is the value stored in the physical register mapped by logical register R2, and the value pointed to by logical register R3 is the value stored in the physical register mapped by logical register R3. The values ​​pointed to by logical register R2 and logical register R3 are both input data required for instruction execution, and the result of the addition is the result of instruction execution. The destination operand of this instruction is "R1", and the second logical register is logical register R1.

[0044] In this embodiment of the application, by obtaining the second logical register pointed to by the destination operand of the instruction, and creating a mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table, at least one input data required for instruction execution and the result of instruction execution output are stored in the same execution module 10.

[0045] For example, in the instruction “ADD R1, R2, R3”, the first source operands include “R2” and “R3”. The first logical register pointed to by the first source operand “R2” is logical register R2, and the first logical register pointed to by the first source operand “R3” is logical register R3. The destination operand of this instruction is “R1”, and the second logical register is logical register R1. Based on the processor's register renaming table, the first physical register mapped to logical register R2 is physical register P2, and the first physical register mapped to logical register R3 is physical register P3. From the first execution module to which physical register P2 belongs and the first execution module to which physical register P3 belongs, the target execution module is determined to be the first execution module to which physical register P2 belongs, according to a preset strategy. The second physical register of the first execution module to which physical register P2 belongs is physical register P1. Then, in the register renaming table, a mapping relationship between logical register R1 and physical register P1 is created. Thus, the value pointed to by logical register R2 is obtained from physical register P2, and the value pointed to by logical register R3 is obtained from physical register P3. The instruction is executed by the first execution module to which physical register P2 belongs, and the values ​​pointed to by logical register R2 and logical register R3 are added together. The result of the addition is stored in physical register P1. Here, physical register P2 and physical register P1 are in the same first execution module.

[0046] In this embodiment, by obtaining the first logical register pointed to by each first source operand of the instruction, and then obtaining the first physical register mapped to each first logical register based on the processor's register renaming table, and then obtaining the first execution module to which each first physical register belongs, and determining the target execution module from the first execution module according to a preset strategy, and then obtaining the second logical register pointed to by the destination operand of the instruction, and creating a mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table, so as to realize register renaming, and in the register renaming stage, storing at least one input data required for instruction execution and the result of instruction execution output in the same execution module 10, compared with storing the result of instruction execution output of the functional unit 13 in one execution module 10 in the register file 11 of another execution module 10, the transmission distance is shorter, so the efficiency of instruction execution is higher. That is, storing at least one input data required for instruction execution and the result of instruction execution output in the same execution module 10, compared with storing each input data required for instruction execution and the result of instruction execution output in different execution modules 10, the efficiency of instruction execution is higher.

[0047] Figure 6This is a flowchart illustrating the specific steps of a data storage method provided in an embodiment of this application, as follows: Figure 6 As shown, the method may include: Step 201: Obtain each source operand of the instruction.

[0048] In this embodiment of the application, each source operand of the instruction is obtained, and then it is determined whether the first source operand exists among the source operands.

[0049] Step 202: If the first source operand exists among the source operands, obtain the first logical register pointed to by each of the first source operands.

[0050] The first source operand is an identifier of a logical register.

[0051] For example, the instruction "ADD R1, [R3], #5, R2" adds the value in the memory pointed to by the memory address in logical register R3, the immediate value "5", and the value pointed to by logical register R2, and stores the result in the physical register mapped by logical register R1. Here, [R3] is the source operand of type memory address, "#5" is the source operand of type immediate value, and "R2" is the source operand of type "identifier of logical register". The first source operand is "R2", and the first logical register is logical register R2.

[0052] In this embodiment of the application, since the type of the first source operand is the identifier of a logical register, the first source operand points to the first logical register, and the first physical register mapped by the first logical register is located in the first execution module.

[0053] Step 203: Based on the processor's register renaming table, obtain the first physical register mapped to each of the first logical registers; the register renaming table is used to record the mapping relationship between logical registers and physical registers.

[0054] The implementation method of this step is similar to that of step 102 above, and will not be repeated here.

[0055] Step 204: Obtain the first execution module to which each of the first physical registers belongs, and determine the target execution module from the first execution modules according to a preset strategy.

[0056] The implementation method of this step is similar to that of step 103 above, and will not be repeated here.

[0057] Step 205: Obtain the second logical register pointed to by the destination operand of the instruction, and create a mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table.

[0058] The implementation method of this step is similar to that of step 104 above, and will not be repeated here.

[0059] Optionally, in some embodiments, each of the physical registers has a corresponding status bit, which is preset to a first value; the step of determining the target execution module from the first execution module according to a preset strategy includes the following sub-steps: Sub-step 2041: When at least a portion of the first physical registers belong to different first execution modules, and the status bit of each first physical register is the first value, the first execution module with the most free physical registers among the first execution modules is determined as the target execution module, or the first execution module selected from the first execution modules using the ping-pong algorithm is determined as the target execution module.

[0060] Wherein, the idle physical register is a physical register that has not established a mapping relationship with a logical register; It should be noted that the idle physical registers do not store data; the status bit is stored in a physical register of register file 11. In some embodiments, the status bit is a binary bit with a first value of binary "0" and a second value of binary "1".

[0061] In some embodiments, the status bit of the physical register is a first value, which is used to characterize the mapping relationship between the physical register and the logical register pointed to by the destination operand of other instructions. This mapping is created in an instruction cycle earlier than the previous instruction cycle, meaning that the instructions processed in the current instruction cycle are unrelated to the instructions processed in the previous instruction cycle.

[0062] In some embodiments, the status bit of the physical register is a second value used to characterize the mapping relationship between the physical register and the logical register pointed to by the destination operand of other instructions. This mapping relationship was created in the previous instruction cycle, meaning that the instruction processed in the current instruction cycle is related to other instructions processed in the previous instruction cycle.

[0063] Ping-pong algorithm is a processing technique commonly used in data flow control. It achieves seamless buffering and processing of data by alternating between two or more buffers.

[0064] For example, in the instruction "ADD R1, R2, R3", the first source operands include "R2" and "R3", the first logical register pointed to by the first source operand "R2" is logical register R2, and the first logical register pointed to by the first source operand "R3" is logical register R3; the destination operand of this instruction is "R1", and the second logical register is logical register R1. Based on the processor's register renaming table, the first physical register mapped by logical register R2 is physical register P2, and the first physical register mapped by logical register R3 is physical register P3. The first execution module to which physical register P2 belongs and the first execution module to which physical register P3 belongs are two different first execution modules, and the status bits of physical register P2 and physical register P3 are both at the first value. The number of free physical registers in the first execution module to which physical register P2 belongs is greater than the number of free physical registers in the first execution module to which physical register P3 belongs. Therefore, the first execution module to which physical register P2 belongs is determined as the target execution module, and the second physical register of the first execution module to which physical register P2 belongs is physical register P1.

[0065] For example, in the instruction "ADD R1, R2, R3", the first source operands include "R2" and "R3", the first logical register pointed to by the first source operand "R2" is logical register R2, and the first logical register pointed to by the first source operand "R3" is logical register R3; the destination operand of this instruction is "R1", and the second logical register is logical register R1. Based on the processor's register renaming table, the first physical register mapped by logical register R2 is physical register P2, and the first physical register mapped by logical register R3 is physical register P3. The first execution module to which physical register P2 belongs and the first execution module to which physical register P3 belongs are two different first execution modules, and the status bits of physical register P2 and physical register P3 are both at the first value. Therefore, the ping-pong algorithm is used to select the first execution module to which physical register P2 belongs from the first execution modules to which physical register P2 belongs and the first execution modules to which physical register P3 belongs. Thus, the first execution module to which physical register P2 belongs is determined as the target execution module, and the second physical register of the first execution module to which physical register P2 belongs is physical register P1.

[0066] In this embodiment, at least a portion of the first physical registers belong to different first execution modules, indicating that at least a portion of the instruction input data is stored in different first execution modules, and a first execution module needs to be selected as the target execution module; the status bits of the first physical registers are all first values, indicating that the mapping relationship between the first physical registers and the logical registers pointed to by the destination operands of other instructions was created in an instruction cycle earlier than the previous instruction cycle. Therefore, the instructions processed in the current instruction cycle are unrelated to the instructions processed in the previous instruction cycle. To balance the resources of physical registers, the first execution module with the most free physical registers is identified as the target execution module. Alternatively, the first execution module selected using the ping-pong algorithm is identified as the target execution module. Then, after obtaining the second logical register pointed to by the destination operand of the instruction, a mapping relationship between the second logical register and the second physical register of the target execution module is created in the register renaming table. Thus, the instruction is executed through the target execution module, and at least one input data required for instruction execution and the result of instruction execution are stored in the same execution module 10.

[0067] For example, the processing flow of instruction D1 is carried out in the first instruction cycle. In the first instruction cycle, the mapping relationship between the logical register pointed to by the destination operand of instruction D1 and the physical register P1 is created. The processing flow of instruction D3 is carried out in the third instruction cycle. In the third instruction cycle, the first logical register pointed to by the first source operand of instruction D3 has a mapping relationship with the physical register P1. Therefore, in the third instruction cycle, the status bit of physical register P1 is the first value.

[0068] Sub-step 2042: If at least a portion of the first physical registers belong to different first execution modules, and among the first physical registers there is a target physical register with the status bit set to the second value, then the first execution module to which the target physical register belongs is determined as the target execution module. The second value is used to characterize the mapping relationship between the physical register and the logical register pointed to by the destination operand of other instructions, and is created in the previous instruction cycle.

[0069] For example, in the instruction "ADD R1, R2, R3", the first source operands include "R2" and "R3", the first logical register pointed to by the first source operand "R2" is logical register R2, and the first logical register pointed to by the first source operand "R3" is logical register R3; the destination operand of this instruction is "R1", and the second logical register is logical register R1. Based on the processor's register renaming table, the first physical register mapped by logical register R2 is physical register P2, and the first physical register mapped by logical register R3 is physical register P3. The first execution module to which physical register P2 belongs and the first execution module to which physical register P3 belongs are two different first execution modules. Furthermore, the status bit of physical register P2 is the second value, and the status bit of physical register P3 is the first value. Therefore, physical register P2 is the target physical register, and the first execution module to which physical register P2 belongs is determined as the target execution module. The second physical register of the first execution module to which physical register P2 belongs is physical register P1.

[0070] In this embodiment, at least a portion of the first physical registers belong to different first execution modules, indicating that at least a portion of the instruction input data is stored in different first execution modules, and a first execution module needs to be selected as the target execution module. Among the first physical registers, there is a target physical register with a status bit of the second value. Since the mapping relationship between the target physical register and the logical registers pointed to by the destination operands of other instructions is created in the previous instruction cycle, the instructions processed in the current instruction cycle are related to other instructions processed in the previous instruction cycle. By determining the first execution module to which the target physical register belongs as the target execution module, the instructions in the current instruction cycle are executed through the target execution module. Since other instructions processed in the previous instruction cycle are also executed in the target execution module, the related instructions are executed in the same execution module 10. Compared with the related instructions being executed in different execution modules 10, the transmission distance of the instruction input data is shorter, which can improve the processing efficiency of the related instructions.

[0071] For example, in the first instruction cycle, the processing flow of instruction D1 is carried out. In the first instruction cycle, the mapping relationship between the logical register pointed to by the destination operand of instruction D1 and the physical register P1 is created. In the second instruction cycle, the processing flow of instruction D2 is carried out. In the second instruction cycle, the first logical register pointed to by the first source operand of instruction D2 has a mapping relationship with the physical register P1. Therefore, in the second instruction cycle, the status bit of physical register P1 is the second value.

[0072] This can be achieved by executing sub-steps 2041 to 2042, which allows the target execution module to be determined from the first execution module.

[0073] Optionally, in some embodiments, after creating the mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table during the current instruction cycle, the method further includes the following steps: Step 206: Set the status bit of the second physical register to the second value.

[0074] In this embodiment of the application, after creating a mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table in the current instruction cycle, the status bit of the second physical register is set to a second value. Then, in the next instruction cycle, the status bit of the second physical register is the second value, which is used to characterize the mapping relationship between the second physical register and the logical register pointed to by the destination operand of other instructions. This is created in the previous instruction cycle of the next instruction cycle.

[0075] At the end of the next instruction cycle, the method further includes the following steps: Step 207: If the second physical register has not been mapped to any other logical register, set the status bit of the second physical register to the first value.

[0076] In some embodiments, the other logic registers are the logic registers pointed to by the destination operand of the instruction to be processed in the next instruction cycle.

[0077] In this embodiment, since the mapping relationship between the second logical register and the second physical register of the target execution module is created in the register renaming table during the current instruction cycle, the status bit of the second physical register is set to the second value. By setting the status bit of the second physical register to the first value at the end of the next instruction cycle when the second physical register has not created a mapping relationship with other logical registers, it is indicated that the instruction processed in the second instruction cycle after the current instruction cycle is unrelated to the instruction processed in the next instruction cycle.

[0078] Optionally, in some embodiments, determining the target execution module from the first execution module according to a preset strategy includes the following sub-steps: Sub-step 2043: If the number of the first source operands is one, determine the first execution module as the target execution module.

[0079] In this embodiment of the application, since there is only one first source operand, there is only one first execution module. Therefore, the first execution module is determined as the target execution module, so that the input data required for instruction execution and the result of instruction execution output are stored in the same execution module 10.

[0080] For example, the instruction "NOT R1, R2" inverts the value pointed to by logical register R2 and stores the result in the physical register mapped by logical register R1. Here, the value pointed to by logical register R2 is the value stored in the physical register mapped by logical register R2. The value pointed to by logical register R2 is the input data required for instruction execution, and the result of the bit inversion is the output result of the instruction execution. This instruction has one first source operand "R2", which points to the first logical register R2. The destination operand of this instruction is "R1", and the second logical register is logical register R1. Since the instruction has a first source operand "R2", based on the processor's register renaming table, the first physical register mapped by logical register R2 is physical register P2. Therefore, the first execution module to which physical register P2 belongs is determined as the target execution module. The second physical register of the first execution module to which physical register P2 belongs is physical register P1. In the register renaming table, a mapping relationship between logical register R1 and physical register P1 is created, thereby obtaining the value pointed to by logical register R2 from physical register P2. The instruction is executed through the first execution module to which physical register P2 belongs, and the value pointed to by logical register R2 is bitwise inverted. The bitwise inverted result is stored in physical register P1. Here, physical register P2 and physical register P1 are in the same first execution module. Sub-step 2044: If each of the first execution modules is the same execution module 10, then the same execution module 10 is determined as the target execution module.

[0081] In this embodiment of the application, since each first execution module is the same execution module 10, the same execution module 10 is determined as the target execution module, thereby realizing that each input data required for instruction execution and the result of instruction execution output are stored in the same execution module 10.

[0082] For example, in the instruction "ADD R1, R2, R2", the first source operand includes two "R2"s, and the first logical register pointed to by the first source operand "R2" is logical register R2; the destination operand of this instruction is "R1", and the second logical register is logical register R1; Based on the processor's register renaming table, the first physical register mapped by logical register R2 is physical register P2; Since the first logical registers pointed to by the two first source operands "R2" are both logical register R2, and the first physical register mapped by logical register R2 is physical register P2, that is, the first execution module to which the first physical register corresponding to each first source operand "R2" belongs is the same execution module 10 (i.e. the first execution module to which physical register P2 belongs). Therefore, the first execution module to which physical register P2 belongs is determined as the target execution module. In the register renaming table, a mapping relationship between logical register R1 and physical register P1 is created, so as to obtain the value pointed to by logical register R2 from physical register P2. The instruction is executed by the first execution module to which physical register P2 belongs, the values ​​pointed to by the two logical registers R2 are added together, and the result of the addition is stored in physical register P1. Here, physical register P2 and physical register P1 are in the same first execution module.

[0083] This can be achieved by executing sub-steps 2043 to 2044, which allows the target execution module to be determined from the first execution module.

[0084] Optionally, in some embodiments, the method further includes the following steps: Step 208: When each of the source operands is a second source operand, obtain the second execution module 10 that has the most free physical registers.

[0085] The type of the second source operand is different from the type of the first source operand.

[0086] In some embodiments, the type of the second source operand includes memory address, immediate value, etc.

[0087] In this embodiment, since the type of the second source operand is different from that of the first source operand, i.e., the second source operand does not point to a logical register, the value pointed to by the second source operand is not stored in a physical register, and the value pointed to by the second source operand is stored in memory or the second source operand is an immediate value that can be directly read, then when each source operand is the second source operand, the instruction input data can be directly obtained or stored in memory, while the result of instruction execution is stored in a physical register. By obtaining the second execution module 10 with the most free physical registers, and after obtaining the second logical register, a mapping relationship between the second logical register and the third physical register of the second execution module is created in the register renaming table to balance the use of physical register resources.

[0088] Step 209: Obtain the second logic register.

[0089] In this embodiment, since the second execution module in the execution module 10 has the most free physical registers, it obtains the second logical register pointed to by the destination operand of the instruction, and then creates a mapping relationship between the second logical register and the third physical register of the second execution module in the register renaming table to balance the use of physical register resources.

[0090] Step 210: In the register renaming table, create a mapping relationship between the second logical register and the third physical register of the second execution module.

[0091] In this embodiment of the application, by creating a mapping relationship between the second logical register and the third physical register of the second execution module in the register renaming table, the result of the instruction execution is stored in the third physical register of the second execution module when the second execution module executes an instruction.

[0092] Taking steps 208 to 210 as an example, the instruction "ADD R1, [R3], #5" is used to add the value in the memory pointed to by the memory address in the logical register R3 to the immediate value "5", and store the result of the addition in the physical register mapped by the logical register R1. Here, "[R3]" is the source operand of type memory address, and "#5" is the source operand of type immediate value. That is, both "[R3]" and "#5" are second source operands. Therefore, each source operand of the instruction is a second source operand. When each source operand is a second source operand, the second execution module with the most free physical registers in the execution module 10 is obtained, and the second logical register is obtained. In the register renaming table, the mapping relationship between the second logical register and the third physical register of the second execution module is created.

[0093] This can be achieved by executing steps 208 to 210, where each source operand is the second source operand.

[0094] Optionally, in some embodiments, the method further includes the following steps: Step 211: When each of the source operands is the second source operand, select the third execution module from the execution modules 10 using the ping-pong algorithm.

[0095] In this embodiment, since the type of the second source operand is different from that of the first source operand (i.e., the second source operand does not point to a logical register, the value pointed to by the second source operand is not stored in a physical register, but the value pointed to by the second source operand is stored in memory or the second source operand is an immediate value that can be directly read), when each source operand is the second source operand, the instruction input data can be directly obtained or stored in memory, while the result of instruction execution is stored in a physical register. From the execution module 10, the third execution module is selected using the ping-pong algorithm, and after obtaining the second logical register, a mapping relationship is created between the second logical register and the fourth physical register of the third execution module in the register renaming table to balance the use of physical register resources.

[0096] Step 212: Obtain the second logic register.

[0097] In this embodiment of the application, by obtaining the second logical register, a mapping relationship between the second logical register and the fourth physical register of the third execution module is created in the register renaming table, so as to balance the use of physical register resources.

[0098] Step 213: In the register renaming table, create a mapping relationship between the second logical register and the fourth physical register of the third execution module.

[0099] In this embodiment of the application, by creating a mapping relationship between the second logical register and the fourth physical register of the third execution module in the register renaming table, the result of the instruction execution is stored in the fourth physical register of the third execution module when the third execution module executes an instruction.

[0100] Taking steps 208 to 210 as an example, the instruction "ADD R1, [R3], #5" is used to add the value in the memory pointed to by the memory address in the logical register R3 to the immediate value "5", and store the result of the addition in the physical register mapped by the logical register R1. Here, "[R3]" is the source operand of type memory address, and "#5" is the source operand of type immediate value. That is, both "[R3]" and "#5" are second source operands. Therefore, each source operand of the instruction is a second source operand. When each source operand is a second source operand, the third execution module is selected from the execution module 10 using the ping-pong algorithm, and the second logical register is obtained. In the register renaming table, a mapping relationship is created between the second logical register and the fourth physical register of the third execution module.

[0101] This can be achieved by executing steps 211 to 213, where each source operand is the second source operand, thus enabling register renaming.

[0102] Optionally, in some embodiments, after step 205, the method further includes the following steps: Step 214: Execute the instructions through the target execution module.

[0103] In some embodiments, instructions are executed by functional unit 13 in the target execution module.

[0104] In some embodiments, instructions are dispatched to the target execution module where the second physical register is located via a dispatch queue, and dispatched to the functional unit 13 by the issue queue 14 in the target execution module, so that the instructions can be executed by the functional unit 13; wherein, the second physical register is the physical register mapped to the second logical register pointed to by the destination operand of the instruction.

[0105] For example, the processor includes two execution modules 10. The identifiers of each physical register in the processor are arranged sequentially as an identifier set. The identifiers of the physical registers in the identifier set are from 0 to 183, that is, the identifier set includes 0, 1, 2, ..., 182, 183. The register file 11 of the first execution module 10 includes 92 physical registers. In the register file 11 of the first execution module 10, the identifiers of the physical registers are from 0 to 91, that is, the identifiers of the physical registers include 0, 1, 2, ..., 90, 91. Therefore, the 92 physical registers in the register file 11 of the first execution module 10 include... Physical register 0, physical register 1, physical register 2, ..., physical register 90, physical register 91; the register file 11 of the second execution module 10 includes 92 physical registers. In the register file 11 of the second execution module 10, the physical registers are identified as 92 to 183, that is, the physical registers are identified as 92, 93, 94, ..., 182, 183. Therefore, the 92 physical registers in the register file 11 of the second execution module 10 include physical register 92, physical register 93, physical register 94, ..., physical register 182, physical register 183; If the second logical register pointed to by the destination operand of the instruction is mapped to the second physical register 94, then the dispatch queue will dispatch the instruction to the second execution module 10, and the issue queue 14 in the second execution module 10 will dispatch the instruction to the functional unit 13 so that the instruction can be executed by the functional unit 13.

[0106] In this embodiment of the application, the instruction is executed by the target execution module, that is, the input data required for instruction execution is obtained by the functional unit 13 in the target execution module to execute the instruction, and the result of the instruction execution is stored in the register file 11 of the target execution module.

[0107] In some embodiments, refer to Figure 7The instruction processing flow includes: X1, instruction processing unit processing, i.e., instruction processing unit 20 retrieves the instruction from the instruction cache and decodes the instruction; X2, register renaming, the specific implementation process is similar to the aforementioned register renaming specific implementation process, and will not be repeated here; X3, dispatch queue dispatch, i.e., the dispatch queue dispatches the instruction to the issue queue 14 in the target execution module through the allocator; X4, allocator processing, i.e., the allocator dispatches the instruction to the issue queue 14 in the target execution module; X5, issue queue dispatch, i.e., the issue queue 14 dispatches the instruction to the functional unit 13 corresponding to the issue queue 14; X6, arithmetic logic operation, i.e., the functional unit 13 performs arithmetic logic operation. The following operations are performed: X7, multiplication (i.e., multiplication is performed by functional unit 13); X8, launch queue dispatch (similar to X5, not described further); X9, arithmetic-logical operation (similar to X6, not described further); X10, division (i.e., division is performed by functional unit 13); X11, launch queue dispatch (similar to X5, not described further); X12, arithmetic-logical operation (similar to X6, not described further); X13, multiplication (similar to X7, not described further); X14, launch queue dispatch (similar to X5, not described further); X15, arithmetic-logical operation (similar to X6, not described further); X16, division (similar to X10, not described further).

[0108] In summary, in this embodiment, by obtaining the first logical register pointed to by each first source operand of the instruction, and then obtaining the first physical register mapped to each first logical register based on the processor's register renaming table, and then obtaining the first execution module to which each first physical register belongs, and determining the target execution module from the first execution module according to a preset strategy, and then obtaining the second logical register pointed to by the destination operand of the instruction, and creating a mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table, register renaming is achieved. In the register renaming stage, at least one input data required for instruction execution and the result of instruction execution are stored in the same execution module 10. Compared with storing the result of instruction execution output of the functional unit 13 in one execution module 10 in the register file 11 of another execution module 10, the transmission distance is shorter, and therefore, the efficiency of instruction execution is higher. That is, storing at least one input data required for instruction execution and the result of instruction execution output in the same execution module 10 is more efficient than storing each input data required for instruction execution and the result of instruction execution output in different execution modules 10.

[0109] This application also provides a chip, including the processor as described above.

[0110] The specific implementation process of the processor in the chip and the specific implementation process of the register renaming method are similar to those described above, and will not be repeated here.

[0111] This application also provides an electronic device, including the chip described above.

[0112] The specific implementation process of processors and register renaming methods in electronic devices is similar to that described above, and will not be repeated here.

[0113] In related technologies, as the processor core launch width increases and the number of functional units increases, the number of ports in a fully bypassed network that is connected in pairs grows exponentially. This leads to a sharp increase in connection latency. Furthermore, as the number of ports in the fully bypassed network increases, the chip area occupied by the fully bypassed network also increases significantly. The dramatic increase in connection length also brings additional power loss.

[0114] In this embodiment, the processor includes an instruction processing unit and multiple execution modules 10. Each execution module 10 includes a register file 11, a bypass network 12, multiple functional units 13, and multiple issue queues 14. Since the different execution modules 10 are independent of each other, the connection lines between the functional units 13 of the different execution modules 10 are reduced, thereby reducing connection delay, number of ports, and chip area occupied by the bypass network 12, and reducing power loss.

[0115] The embodiments of this application can achieve the following: while maintaining the same number of instructions per cycle (IPC) during program execution, the complexity of the processor's physical design can be reduced, the processor's clock frequency can be increased, and the processor's power consumption and implementation area can be reduced, thereby improving processor performance. Furthermore, while ensuring that the actual number of physical registers remains unchanged, the register file 11 can be optimized, reducing the number of ports in the register file 11, thereby reducing the latency and area of ​​the register file 11. During the register renaming stage, the dependencies between instructions can be identified to minimize the possibility of cross-execution module 10 accessing the register file 11 during instruction execution. In addition, the embodiments of this application can dispatch instructions to the execution module 10 corresponding to the destination operand based on the identifier of the logical register pointed to by the instruction's destination operand. The embodiments of this application can reduce the pressure on the physical design process while maintaining the basic degree of instruction-level parallelism during program execution, based on existing general-purpose processor core design methods.

[0116] In summary, in this embodiment, the processor includes an instruction processing unit 20 and multiple execution modules 10. Each execution module 10 includes a register file 11, a bypass network 12, multiple functional units 13, and multiple issue queues 14. In each execution module 10, the functional units 13 and issue queues 14 correspond to each other. The issue queues 14 are connected to the instruction processing unit 20 and the corresponding functional units 13, respectively. The bypass network 12 is connected to each functional unit 13 and the register file 11. The issue queues 14 buffer the instructions output by the instruction processing unit 20, and then the functional units 13 execute the instructions. The instructions are stored in the register file 11. The system stores instruction data and transmits data stored in register file 11 to the input of functional unit 13 via bypass network 12, transmits data output from functional unit 13 to the input of functional unit 13, transmits data output from one functional unit 13 to the input of another functional unit 13, and transmits data output from the output of functional unit 13 to register file 11 for storage, thereby realizing the functions of the processor backend. Since the different execution modules 10 are independent of each other, the connection lines between the functional units 13 of the different execution modules 10 are reduced, thereby reducing the design difficulty of bypass network 12.

[0117] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A processor, characterized in that, It includes an instruction processing unit (20) and multiple execution modules (10), each execution module (10) including a register file (11), a bypass network (12), multiple functional units (13) and multiple launch queues (14); in the execution module (10), the functional units (13) and the launch queues (14) correspond to each other; In the execution module (10), the launch queue (14) is connected to the instruction processing unit (20) and the corresponding functional unit (13) of the launch queue (14), respectively. The launch queue (14) is used to buffer the instructions output by the instruction processing unit (20). The bypass network (12) is connected to each functional unit (13) and the register file (11), respectively. The bypass network (12) is used to transfer the data stored in the register file (11) to the input terminal of the functional unit (13), and to transfer the data output by the output terminal of the functional unit (13) to the input terminal of the functional unit (13), and to transfer the data output by the output terminal of one functional unit (13) to the input terminal of another functional unit (13), and to transfer the data output by the output terminal of the functional unit (13) to the register file (11) for storage. The functional unit (13) is used to execute the instruction. The register file (11) is used to store the data of the instruction.

2. The processor according to claim 1, characterized in that, The bypass network (12) includes a plurality of first multiplexers (121) and at least one second multiplexer (122). In the execution module (10), each functional unit (13) has a corresponding first multiplexer (121) and a second multiplexer (122); the output of the first multiplexer (121) corresponding to the functional unit (13) is connected to one input of the functional unit (13), the output of the functional unit (13) is connected to one input of each of the first multiplexers (121), the output of the functional unit (13) is also connected to one input of the second multiplexer (122) corresponding to the functional unit (13); the output of the second multiplexer (122) is connected to one input of the register file (11); the other input of the first multiplexer (121) is connected to one output of the register file (11).

3. The processor according to claim 1, characterized in that, The register files (11) of each of the execution modules (10) are interconnected.

4. The processor according to claim 1, characterized in that, Each execution module (10) corresponds to the same register renaming table, which is used to store the mapping relationship between logical registers and physical registers; each execution module (10) has a corresponding free list, which is used to store the identifiers of the free physical registers available for allocation of the execution module (10).

5. A register renaming method, characterized in that, Applied to a processor as described in any one of claims 1 to 4, wherein the register file (11) of the execution module (10) includes a plurality of physical registers, the method comprising: Get the first logical register pointed to by each first source operand of the instruction; Based on the processor's register renaming table, obtain the first physical register mapped to each of the first logical registers; the register renaming table is used to record the mapping relationship between logical registers and physical registers; Obtain the first execution module to which each of the first physical registers belongs, and determine the target execution module from the first execution modules according to a preset strategy; Obtain the second logical register pointed to by the destination operand of the instruction, and in the register renaming table, create a mapping relationship between the second logical register and the second physical register of the target execution module.

6. The method according to claim 5, characterized in that, Each of the physical registers has a corresponding status bit, which is preset to a first value; determining the target execution module from the first execution module according to a preset strategy includes: If at least a portion of the first physical registers belong to different first execution modules, and the status bit of each first physical register is the first value, the first execution module with the most free physical registers among the first execution modules is determined as the target execution module, or the first execution module selected from the first execution modules using the ping-pong algorithm is determined as the target execution module. If at least a portion of the first physical registers belong to different first execution modules, and among the first physical registers there is a target physical register whose status bit is the second value, then the first execution module to which the target physical register belongs is determined to be the target execution module. The idle physical register is a physical register that has not been mapped to a logical register; the second value is used to characterize the mapping relationship between the physical register and the logical register pointed to by the destination operand of other instructions, and is created in the previous instruction cycle.

7. The method according to claim 6, characterized in that, In the current instruction cycle, after creating the mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table, the method further includes: Set the status bit of the second physical register to the second value; At the end of the next instruction cycle, the method further includes: If the second physical register does not have a mapping relationship with other logical registers, the status bit of the second physical register is set to the first value.

8. The method according to claim 5, characterized in that, The step of determining the target execution module from the first execution module according to a preset strategy includes: When the number of the first source operands is one, the first execution module is determined as the target execution module; In the case where each of the first execution modules is the same execution module (10), the same execution module (10) is determined as the target execution module.

9. The method according to claim 5, characterized in that, The first source operand is an identifier of a logical register; the first logical register pointed to by each first source operand of the fetch instruction includes: Obtain each source operand of the instruction; If the first source operand exists among the source operands, the first logical register pointed to by each of the first source operands is obtained.

10. The method according to claim 9, characterized in that, The method further includes: When each of the source operands is the second source operand, obtain the second execution module (10) that has the most free physical registers, and obtain the second logical register. In the register renaming table, create a mapping relationship between the second logical register and the third physical register of the second execution module, or: From the execution module (10), the third execution module is selected using the ping-pong algorithm, and the second logical register is obtained. In the register renaming table, a mapping relationship is created between the second logical register and the fourth physical register of the third execution module. The type of the second source operand is different from the type of the first source operand.

11. The method according to claim 5, characterized in that, After creating the mapping relationship between the second logical register and the second physical register of the target execution module in the register renaming table, the method further includes: The instructions are executed by the target execution module.

12. A chip, characterized in that, The chip includes a processor as described in any one of claims 1 to 4.

13. An electronic device, characterized in that, Including the chip as described in claim 12.

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