Multi-alu array out-of-order scheduling circuitry and dual-mode data forwarding method

Abstract

The application discloses a multi-path ALU array disorder scheduling circuit system and a dual-mode hardwired data forwarding circuit, and belongs to the field of digital integrated circuits. The existing sequential emission architecture is restricted by chain data dependency, the ALU utilization rate is about 60%, and the pipeline bubble and data hazard problem is significant. The application is configured with M>=N+2 multi-entry reservation stations, a hardwired priority arbitration circuit, dynamic mapping renaming logic and a single result broadcast public data bus, and a bypass and straight-through dual-mode hardwired forwarding network independent of the bus is constructed, and three types of data hazards of read-after-write, write-after-read and write-after-write are eliminated in hardware. The total delay of chain dependency is compressed from 17 cycles to 10 cycles, the ALU utilization rate is increased from 60% to close to 100%, the control is fully hardwired, the forwarding switching delay is less than 1 clock cycle, and the application can be adapted to various high-density numerical calculation chips.

Description

Technical Field

[0001] This invention belongs to the interdisciplinary field of digital integrated circuit design and computer architecture, specifically relating to an out-of-order scheduling circuit system for multi-path arithmetic logic unit arrays, and a dual-mode hard-wired data forwarding method integrating bypass and pass-through data hazard detection. This invention is applicable to high-density computing scenarios with fixed-sequence chained data dependencies, such as tensor chained computation, numerical physics simulation, and deep learning inference. It can be integrated into various high-density numerical computing chips, AI accelerators, and digital signal processors, providing hardware-level out-of-order scheduling and low-latency data forwarding capabilities for high-speed numerical computation. Background Technology

[0002] In a numerical computation pipeline composed of a multi-channel ALU (Arithmetic Logic Unit) array, the ALUs are cascaded sequentially to form a closed-loop chain computation pipeline, used to perform chain-dependent operations such as metric tensor solving, connection symbol computation, covariant gradient difference, numerical integration, and trace purity determination. Taking a typical computation with five ALUs as an example, each iteration generates a fixed sequence of six instructions: absolute value, exponentiation, reciprocal, conformal mapping, multiplication, and addition. This sequence exhibits two data dependency characteristics:

[0003] (i) Chained write-after-read dependency. Each instruction depends on the result of the preceding instruction in sequence (absolute value operation, exponentiation operation, reciprocal operation, conformal mapping operation, multiplication operation, addition operation). Subsequent instructions must wait for the result of the preceding instruction to be ready before they can be executed. In the sequential issue architecture, the delays of 6 instructions are serially superimposed, totaling 17 cycles. When any instruction occupies the ALU, the other multiple paths are idle and waiting, and the average ALU utilization is only about 60%.

[0004] (ii) Parallel opportunities for irrelevant instructions. Different data points can be processed in parallel—the absolute value of data point i+1 has no data dependency on the exponent of data point i. When out-of-order scheduling capability is available, scheduling resources can be released immediately after the preceding instruction is issued, and subsequent irrelevant instructions can be immediately issued to an idle ALU for execution.

[0005] The existing technology has the following drawbacks:

[0006] Defect 1: Sequential execution leads to severe ALU resource idleness. Taking a typical six-instruction chain of a five-way ALU as an example, the execution cycles of each instruction are 2 cycles for absolute value, 4 cycles for exponentiation, 4 cycles for reciprocal, 3 cycles for conformal mapping, 2 cycles for multiplication, and 2 cycles for addition. Executing them sequentially takes a total of 17 cycles to complete all 6 instructions. Of these, approximately 10 clock cycles are used for effective computation, while the remaining 7 clock cycles are spent with multiple ALUs in an idle waiting state. The average hardware utilization rate is only about 60% (10 / 17≈60%), resulting in a serious waste of computing resources.

[0007] Defect 2: The general out-of-order scheduling architecture cannot adapt to high-density numerical computing hardware. Existing out-of-order scheduling mechanisms are designed for general-purpose processors with 16-32 scalar registers, resulting in huge overhead in broadcast network area and power consumption. High-density numerical computing chips are usually configured with only a few dedicated architecture registers, and the existing architecture does not prune reserved stations, arbitration and broadcast logic for fixed-chain instruction sequences, resulting in serious redundancy and loss.

[0008] Defect 3: Lack of a dedicated forwarding path adapted to chained dependencies. Existing forwarding schemes only have one effective method: global broadcast after register write-back. In short chained dependency scenarios, there is a lack of hard-wired bypass and pass-through forwarding architectures that allow ALU outputs to directly connect to lower-level arithmetic units, which cannot eliminate pipeline bubbles.

[0009] In summary, current high-density numerical computing hardware architectures for chain-dependent operations suffer from four major bottlenecks: low sequential launch utilization, large redundancy in general scheduling architecture, lack of dedicated forwarding paths, and difficulty in coordinating with mixed-precision adaptive pipelines. As a result, it is difficult to simultaneously achieve the numerical computing requirements of high throughput, low latency, and low power consumption. Summary of the Invention

[0010] Inventive concept

[0011] The concept of this invention is to reconstruct the general out-of-order scheduling mechanism in a hardware-specific manner to adapt to high-density numerical computation instruction scenarios with fixed chain dependencies under N≥3-channel ALU arrays (including but not limited to tensor chain numerical operations).

[0012] Specifically, it includes two major innovation directions:

[0013] First, customized out-of-order scheduling hardware modifications. A dedicated reserved station register file with a storage capacity of M≥N+2 is configured to ensure the number of entry points covers the peak issuance volume of chained instructions; a hard-wired priority arbitration tree is provided to achieve low-latency out-of-order issuance in a single cycle; and dynamic matching logic for renaming physical registers is added to uniformly eliminate the three types of data hazards—write-after-read, read-after-write, and write-after-write—at the hardware level.

[0014] Secondly, it features a unique hierarchical dual-mode inter-level forwarding hardware. Independent of the global broadcast path of the common data bus, it adds a bypass (0-cycle delay) and pass-through (1-cycle delay) dual-mode hard-wired forwarding network; relying on dedicated metal feedback traces between ALU array levels, intermediate results do not need to wait for register write-back and bus arbitration, and can be directly fed to the input of the next-level ALU, eliminating pipeline bubbles caused by chain dependencies at the physical circuit level.

[0015] The two directions mentioned above work together—customized scheduling hardware ensures the out-of-order parallel issuance of irrelevant instructions, and the dual-mode forwarding network ensures zero-bubble data transmission of chain-dependent instructions—to complement each other and enable the computing pipeline to operate stably in the theoretically optimal throughput range in chain-write-read-dependent scenarios.

[0016] Technical problems to be solved

[0017] This invention aims to address the multiple adaptation bottlenecks existing in chain-dependent high-density numerical computing hardware architectures. Specific technical problems are as follows:

[0018] First, the general out-of-order scheduling architecture has poor adaptability and low ALU computing power utilization. The existing general out-of-order scheduling mechanism is designed for scalar operation scenarios and has not made hardware tailoring and customized adaptation for the fixed chain instruction characteristics of N≥3-way ALU arrays. Under the sequential issue architecture, instruction serial waiting is serious, and the ALU hardware utilization is only about 60% (estimated value), and the advantages of multi-way parallel throughput cannot be brought into play.

[0019] Secondly, the general scheduling and broadcast network has significant redundancy and lacks multi-precision coordination capabilities. The common data bus, reserved stations, and broadcast logic of the general Tomasulo architecture are adapted to 16-32 scalar registers, resulting in huge area and power consumption overhead. This is incompatible with the hardware configuration of high-density numerical computing chips with a small number of dedicated architecture registers. Furthermore, there is no collaborative optimization for mixed-precision adaptive pipelines, leading to high data interaction latency and poor adaptability in multi-precision computing scenarios.

[0020] Third, the lack of a dedicated dual-mode inter-stage forwarding path means that pipeline bubbles cannot be eliminated. Existing forwarding schemes only support global broadcasting after register write-back or blank instruction filling without hardware forwarding. They lack bypass and pass-through dual-mode hard-wired inter-stage forwarding routing for chained short-distance write-after-read dependencies. They cannot transmit intermediate results that have not been written back to registers inside the ALU in advance. The instruction stalling and pipeline bubble problems caused by chained dependencies cannot be completely eliminated, thus limiting throughput performance.

[0021] Overall technical solution

[0022] This invention discloses a multi-channel ALU array out-of-order scheduling circuit system for chain-dependent high-density numerical computation, adaptable to N≥3 homogeneous or heterogeneous ALU array architectures, and particularly suitable for tensor chain-based iterative computation scenarios. This invention addresses the technical bottlenecks of low computational efficiency in traditional sequential scheduling, large redundancy overhead in general out-of-order architectures, difficulty in eliminating pipeline bubbles in chain-based write-after-read dependencies, and poor adaptability to multi-precision computations through a customized hard-wired out-of-order scheduling architecture, register renaming to eliminate data hazards, and a collaborative design of bypass and pass-through dual-mode hard-wired forwarding networks. The specific technical solution is as follows:

[0023] (I) Reserved Station Physical Register Array. M parallel instruction entries are configured, M≥N+2, ensuring the entry capacity covers the peak issuance of chained instructions. Each entry is an independent register file with a built-in dual-input numerical comparator. Hardware fields include a busy flag, hard-wired decoding logic for the instruction opcode, two sets of source operand value registers and corresponding common data bus waiting source number registers, target register number registers, issue cycle counter, and execution delay counter. The execution delay of each instruction is fixedly configured by the hard-wired logic. During the instruction issuance phase, the hard-wired parallel scanning logic synchronously detects the busy flags of all entries and prioritizes allocating idle entries. Based on the physical register renaming dynamic matching logic, it determines whether there are incomplete dependencies on the source operands—if dependencies exist, the corresponding waiting source number is set, and the instruction enters the data waiting state; if there are no dependencies, the register file value is directly read, and the instruction enters the ready state. When all M entries are full, the hard-wired combinational logic generates a reserved station full backpressure signal, blocking subsequent instruction issuance in real time.

[0024] (ii) Hard-wired priority arbitration tree. It consists of cascaded multi-stage 2-to-1 comparators, a pure combinational logic circuit. The inputs are coupled to the ready status signals of all reserved station entrances. Physical priority is determined based on the instruction transmission sequence number. The outputs are directly connected to the enable and operand inputs of each ALU via dedicated metal traces. The arbitration propagation delay is less than 0.5 clock cycles.

[0025] (III) Dynamic Matching Logic Circuit for Physical Register Renaming. This circuit bridges the reserved station array and the physical register file, implementing dynamic mapping between dedicated architecture registers and active reserved station entry numbers, executing the following mapping rules: Dynamic Binding—When an instruction is allocated to a reserved station entry, the target architecture register is bound to the current entry number; Issue Update and Write-back Clear—After an instruction is issued, the mapping logic updates the target register to point to the current entry, and the corresponding binding is automatically cleared after the result is written back; Latest Mapping Overwrites Old Mapping (Eliminating Write-After-Write Hazards)—When multiple instructions are written sequentially to the same architecture register, only the mapping binding of the last issued instruction is retained, and the overwritten preceding write instructions can still be executed normally and complete the physical write-back; Read Instruction Dependency Lookup—When subsequent instructions read the source architecture register, if a valid binding exists, they enter a waiting state; otherwise, they directly read the physical register file. Based on the above dynamic mapping logic, write-after-read, read-after-write, and write-after-write data hazards are eliminated simultaneously.

[0026] (iv) Public Data Bus Physical Broadcast Network. It consists of global unidirectional metal traces and multi-level fan-out buffers, covering all reserved station numerical comparators and ALU write-back ports. Each clock cycle broadcasts the result value of a single completed operation and its corresponding target number. Each reserved station uses its built-in dual comparators to match and wait for the source number in parallel. After a successful match, it automatically loads the valid operand and releases the waiting state.

[0027] (v) Three-stage hard-wired pipeline. A three-stage rigid pipeline timing architecture of transmit-execute-write-back is constructed to work in conjunction with a dual-mode forwarding network. The transmit stage selects and transmits ready instructions by arbitration tree; the execute stage performs ALU calculations based on the computational delay configured by hard-wired, and the results are latched into the inter-stage pipeline registers; the write-back stage drives the results to the common data bus to complete global broadcast.

[0028] (vi) Bypass and Straight-through Dual-Mode Hard-Connect Data Forwarding Network (Dual-Mode Hard-Connect Data Forwarding Network). Independent of the global broadcast path of the common data bus, a dedicated metal feedback trace is added between ALU stages. A zero-bubble dual-mode hardware forwarding mechanism is designed for chain-like short-distance write-after-read dependencies. The path selection is determined in real time by the hard-connect comparator, and the total switching delay is less than 1 clock cycle. Bypass mode (0-cycle delay): The station transmit output is hard-connected to the ALU input multiplexer, and ready operands are directly forwarded for write-after-read dependencies of adjacent instructions. Straight-through mode (1-cycle delay): A dedicated feedback trace is led out from the front end of the pipeline register between ALU stages. For intermediate results that have entered ALU execution but have not yet completed bus broadcasting, they are fed into the input of the next-level ALU in advance.

[0029] (vii) Hardware Data Hazard Detector. Monitors data dependencies across the entire pipeline instruction set: write-after-read hazard is eliminated through a reserved station source wait mechanism and dual-mode forwarding path; read-after-write and write-after-write hazard are eliminated through a register renaming dynamic mapping overwrite mechanism. No pipeline flushing or null instruction insertion is required throughout the entire process.

[0030] (viii) Hardwired backpressure signal generator. Based on the combinational logic of the reserved station full state, hardware backpressure is generated in real time to immediately block subsequent instruction decoding and transmission when the ingress resources are exhausted, thereby avoiding instruction overflow and scheduling disorder from the source.

[0031] Beneficial effects

[0032] Compared with traditional sequential launch pipeline architecture and the general-purpose Tomasulo out-of-order scheduler, this invention has the following outstanding technical advantages:

[0033] (i) Based on the out-of-order launch mechanism of the multi-entry reserve station, the average ALU utilization rate is increased from about 60% in the traditional sequential launch architecture to nearly 100%. The present invention configures a multi-entry reserve station array that satisfies the constraint M≥N+2, and the total entry capacity covers the peak launch volume of instructions in a single round of iteration; instructions that are independent between different data points can be directly scheduled to idle ALUs for parallel execution when the preceding chained instructions are still occupying ALU operations.

[0034] (II) Hardware native elimination of three types of data hazards by renaming dedicated physical registers, without the need for padding instructions. This invention configures a dynamic mapping logic circuit adapted to dedicated architecture registers to achieve dynamic binding of architecture registers to active reserved station entry numbers; the three types of data hazards—write-after-read, read-after-write, and write-after-write—are automatically resolved through dynamic resource allocation and overlay mapping mechanism via register renaming, without pipeline interruption or compiler insertion of blank wait instructions. For six-instruction chain operation sequences, the number of blank instructions required to be inserted due to data hazards is reduced from 5 in the traditional architecture to 0.

[0035] (III) A unique dual-mode hard-wired forwarding network with both bypass and direct forwarding modes fully covers chained write-after-read forwarding scenarios, reducing dependency waiting latency by approximately 77% and eliminating pipeline bubbles at their source. The bypass mode (0-cycle latency) adapts to short-distance write-after-read dependencies between adjacent instructions in the transmit queue; the direct mode (1-cycle latency) adapts to forwarding scenarios where intermediate results are being processed internally by the ALU but have not yet completed global broadcast. Simulation statistics show that approximately 30% of data forwarding is completed through the bypass path, while the remaining 70% relies on the direct path, resulting in an average system forwarding latency of only 0.7 clock cycles. In contrast, traditional chained write-after-read architectures without dedicated forwarding architectures cause an average pipeline pause of 3 clock cycles.

[0036] (iv) Clearly define the system throughput bandwidth bottleneck, providing greater flexibility for chip physical design optimization. Under various ALU operation latency configurations, the system IPC remains consistently above 0.998. The maximum system throughput is limited only by the single-cycle, single-result broadcast bandwidth of the common data bus, and is not bound to the single-level execution latency of the ALU array. Chip design can deepen the pipeline segmentation within each ALU level without sacrificing overall throughput performance, effectively reducing signal propagation delay and increasing the operating frequency.

[0037] (v) Achieving the optimal balance between the hardware area and performance of the reserve station through the mathematical constraint M≥N+2. Through simulation and iterative verification, M≥N+2 is the minimum hardware configuration that guarantees no full back pressure triggering of the reserve station throughout the process. It can minimize the hardware size of the reserve station register array while meeting the peak scheduling requirements of chained instructions, thus achieving the optimal trade-off between performance, area, and power consumption.

[0038] (vi) The dual-mode forwarding network and the hybrid precision adaptive pipeline physical layer are deeply coupled, reserving timing margins for high-precision switching. The dedicated metal feedback trace bypasses the long global trace of the common data bus. When the array front-end ALU switches from low precision to high precision floating-point operation, it provides an additional timing leeway for the establishment and maintenance of signals between ALU levels, ensuring that there are no conflicts between out-of-order scheduling and multi-precision dynamic switching at the hardware timing level.

[0039] (vii) All scheduling and control logic is implemented using pure hardwired connections, with no software or microcode scheduling delays. Command issuance arbitration, forwarding path selection, and reserved station full backpressure generation are all completed in real time by hardwired combinational logic. The overall path switching delay is less than 1 clock cycle (approximately 1ns at a 1GHz main frequency), making it suitable for high-speed, high-density numerical computing scenarios.

[0040] Terminology Definition

[0041] Multi-channel ALU array: A reconfigurable computing array containing N ALUs, where N≥3. A single ALU can handle one or more types of computing tasks. Those skilled in the art can merge or split computing tasks according to computing power requirements to form pipelines with different granularities, such as N=3, N=5, and N=7. The ALU array can be a homogeneous array (each ALU has the same computing power) or a heterogeneous array (each ALU has different bit widths, precision configurations, and supported instruction types).

[0042] Chained data dependency: In chained computation, subsequent instructions depend on the output of the previous instruction in turn, forming a write-after-read dependency chain. Typical examples include a fixed sequence of six instructions, such as absolute value operation, exponentiation operation, reciprocal operation, conformal mapping operation, multiplication operation, and addition operation, which depend on the results of their predecessors in turn.

[0043] Reserved station: An additional physical register array located at the ALU input port, used to store issued but not yet executed instructions and their operands. Each entry contains instruction information, operands, and a wait source number register. Multiple entries work in parallel to achieve out-of-order waiting and issuance of instructions.

[0044] Common Data Bus: A shared physical bus used to broadcast calculated results to all reserved stations that require that value as a source operand. This invention implements it as a physical broadcast network consisting of global unidirectional metal traces and multi-level fan-out buffers, providing a purely hardwired signal drive path.

[0045] Hardwired connections: Physical metal wires directly connect the circuits, without bus arbitration, microcode, or software scheduling logic; only registers and caches are configured as writable storage elements. In this invention, all scheduling decisions (transmission selection, forwarding path selection, and backpressure generation) are completed by hardwired combinational logic, without the need for processor software involvement.

[0046] Bypass mode: A working mode of the data forwarding network - when the source register of the current instruction is the same as the target register of the previously issued instruction, the operation value is directly transmitted from the output of the transmitter reserved station to the ALU input through a dedicated physical line, with a delay of 0 cycles.

[0047] Straight-through mode: A working mode of the data forwarding network - when the source register of the current instruction is the same as the target register of an instruction that has been executed in the ALU but has not yet been written to the common data bus, it is directly fed into the input of the next-level ALU from the pipeline register input of the ALU stage through a dedicated physical metal feedback line, with a delay of 1 cycle.

[0048] Issue stage, execution stage, and write-back stage: The three timing stages of the three-level hard-wired pipeline of this invention are: the issue stage, driven by the hard-wired priority arbitration tree, is responsible for arbitrarily selecting one instruction from the ready instructions to issue to the ALU; the execution stage is responsible for ALU operations and latching the results into the inter-stage pipeline registers; and the write-back stage is responsible for driving the inter-stage register values ​​to the common data bus and writing them back to the register file.

[0049] Arbitration Tree: A pure combinational logic priority arbitration circuit composed of multiple cascaded 2-to-1 comparators. Its input is connected to the ready flag of all reserved station entrances, and its output is directly coupled to the enable terminal of each ALU through hardwire. It is used to select the highest priority instruction in a single cycle according to the issue sequence number among multiple ready instructions. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the overall system architecture of the present invention, showing the connection relationship of each functional module; solid arrows represent the positive mainstream waterline data flow; dashed arrows represent the global broadcast and direct feedback lines of the common data bus; and dotted-dash arrows represent the back pressure output of the reserved station.

[0051] Figure 2 This is a schematic diagram of the reserved station array structure of the present invention, showing the internal register and comparator structure of a single entry point; the left side is a complete overall diagram of the reserved station array, which contains multiple parallel single instruction entries, and the bottom arrow indicates the array summary signal output; the right side is a detailed enlarged view of a single instruction entry point, in which the busy flag, opcode, source operand register, wait number register, target register and cycle counter are set from top to bottom in the single entry point. All register data are uniformly sent down to the bottom numerical comparator to complete the matching judgment.

[0052] Figure 3 This diagram illustrates the comparison of the dual-mode hardwired data forwarding network paths of the present invention, showing the comparison between bypass and direct forwarding paths. The diagram is divided into upper and lower regions by a horizontal dividing line: the upper region is the bypass mode, where the output of the reserved station is directly connected to the ALU input multiplexer via a hardwire, and the path has no buffer register, marked "Bypass mode, 0 cycle delay"; the lower region is the direct mode, where the input of the interstage pipeline register is connected to the lower-level ALU input multiplexer via a dedicated metal feedback line, marked "Direct mode, 1 cycle delay"; the solid arrows in the diagram represent the main data flow path, and the dashed arrows represent the feedback data flow path. Detailed Implementation

[0053] Example 1: General Architecture of Multi-Channel ALU Array and Chained Write-After-Read Hazard Elimination

[0054] like Figure 1 The system architecture shown in this invention comprises N ALUs, where N≥3, and can be configured as homogeneous or heterogeneous arrays. Each ALU performs chain-dependent operations such as metric tensor solving, connection symbol calculation, covariant gradient difference, numerical integration, and trace purity determination. This embodiment uses a five-ALU configuration (N=5) as the preferred configuration, with a reserved station entry point M=8 (satisfying M≥N+2). Taking a 6-instruction chain—absolute value r0, exponentiation r1, reciprocal r2, conformal mapping r3, multiplication r4, and addition r5—as an example, the complete execution trajectory is demonstrated.

[0055] like Figure 2 As shown in the reserved station array structure, each reserved station instruction entry is configured with two sets of waiting number registers qj and qk. A value of -1 indicates that the data is ready, and a value of a non-negative integer N indicates that the operation result depends on the Nth entry of the reserved station.

[0056] Period T1: Absolute value instruction is issued, hard-wired scan logic locks reserved station entry 0, and mapping logic binds r0 to entry 0.

[0057] Period T2: Absolute value is executed by ALU (2 cycles). Exponentiation instruction (dependent on r0) and reciprocal instruction (dependent on r0) enter entry 1 and entry 2 simultaneously, qj are both set to 0, and the program enters a waiting state.

[0058] Period T3: Conformal mapping instructions (dependent on r1) enter entry 3; multiplication instructions (dependent on r1 and r2) enter entry 4.

[0059] Cycle T4: After the absolute value operation is completed, the result is passed to the exponential / reciprocal ALU with a 1-cycle delay in pass-through mode; simultaneously, the result is broadcast on the common data bus—entry 1 and entry 2 simultaneously become ready. The addition instruction (dependent on r4 and r3) enters entry 5.

[0060] Cycle T5: The arbitration tree selection index instruction is sent to the idle ALU, and the bypass mode completes data preparation in cycle 0.

[0061] Periods T6 to T10: Conformal mapping, multiplication, and addition are issued out of order through the arbitration tree. Each instruction occupies the ALU independently according to its own execution delay (3 cycles for conformal mapping, 2 cycles for multiplication, and 2 cycles for addition), without blocking each other.

[0062] Technical effects: Total latency was reduced from approximately 17 cycles in sequential transmission to approximately 10 cycles (a reduction of approximately 41%), the peak occupancy rate of reserved stations was only 5 / 8, and backpressure was never triggered.

[0063] Example 2: Mathematical constraint relationship between the number of station entrances M and the number of ALUs N

[0064] like Figure 1 and Figure 2 As shown, this embodiment demonstrates the design basis and verification results for M≥N+2.

[0065] Design principle: For a pipeline consisting of N ALUs, a single iteration generates N+1 instructions (taking a five-ALU as an example, it generates 6 instructions), which must satisfy M≥N+2 to ensure at least one idle entry point.

[0066] Comparative verification:

[0067] Configuration 1: M=N+1 (6 entries). During the execution of long-delay instructions, all reserved stations are fully occupied, and the backpressure trigger rate is approximately 15%.

[0068] Configuration 2: M=N+2 (8 inlets, preferred in this invention). Peak occupancy rate of reserved stations is 5 / 8, and backpressure trigger rate is 0%.

[0069] Configuration 3: M=N+3 (9 entry points). The peak occupancy rate of the reserved stations remains at 5 / 8, the backpressure trigger rate is 0%, the hardware area increases by 12.5% ​​and there is no performance improvement.

[0070] Technical effect: M≥N+2 is the minimum number of inlets configured under the premise of ensuring zero back pressure triggering, which balances performance and area optimization.

[0072] Example 3: Performance Comparison and Scenarios of Dual-Mode Forwarding Networks

[0073] like Figure 3 As shown, the forwarding network of the present invention includes two modes: bypass and direct. This embodiment verifies the effect of the dual-mode forwarding network and the usage ratio of the two modes.

[0074] Comparison of forwarding enabled vs. forwarding disabled (2000 data points, 12000 commands):

[0075] No forwarding: Total running cycle approximately 14406, IPC≈0.833, with an average of 1 pause cycle every 5 cycles.

[0076] Enabling forwarding: Total runtime approximately 12010, IPC ≈ 0.999, with no interruptions throughout.

[0077] Large-scale test (5000 data points): IPC≈1.000 when forwarding is enabled, IPC≈0.833 when forwarding is disabled, with a speed improvement of about 20%.

[0078] Forwarding scenario distribution (actual measurement of 5000 data points):

[0079] Bypass mode (0 cycles): Approximately 30%, adapts to short-distance write-after-read dependencies between adjacent instructions.

[0080] Straight-through mode (1 cycle): Approximately 70%, adapted for forwarding intermediate results being processed within the ALU.

[0081] Average forwarding delay: 0.3×0 + 0.7×1 = approximately 0.7 cycles.

[0082] Compared to the average 3-cycle pause after a write-to-read sequence without forwarding, latency is reduced by approximately 77%.

[0083] Example 4: Verification of full back pressure at the retention station

[0084] like Figure 1 reverse pressure signal path and Figure 2 As shown in the station structure, this embodiment verifies that the back pressure was never triggered under the M=8 configuration.

[0085] Benchmarking with 100,000 data points: 5 / 8 of the inputs were occupied during the 6-instruction chain launch. The CDB broadcast one completion result per cycle. Reserved stations decreased at a rate of approximately one input released per cycle. The average occupancy rate was 3.5 / 8 (approximately 44%). Back pressure with all 8 inputs full was never triggered.

[0086] Technical effect: M=8 (i.e. M=N+2 for N=5) is the minimum inlet configuration that guarantees zero back pressure.

Claims

1. A circuit system for out-of-order scheduling of a multi-channel ALU array, wherein the multi-channel ALU array comprises N ALUs and N≥3, characterized in that, include: A reserved station physical register array is configured with M parallel instruction entries, wherein the number of reserved station entries M and the number of ALUs N satisfy the relationship M≥N+2; each entry is configured with an instruction opcode storage field, a source operand storage field, a waiting source number storage field, a target register number storage field, and an operation delay count field; the reserved station array embeds parallel numerical comparison logic, which is used to match the waiting source number and update the operand status in real time during the public data bus broadcast phase; when all entries are in an occupied state, a reserved station full reverse voltage signal is generated through hard-wired combinational logic to block subsequent instruction transmission. The hard-wired priority arbitration circuit is composed of multiple levels of comparators and pure combinational logic cascaded together. It has full access to the instruction ready state of all reserved station entry points and selects the best output transmission enable signal from multiple ready instructions in a single cycle. The physical register renaming mapping logic circuit bridges the reserved station array and the physical register file. It is used to realize the dynamic mapping between the architecture registers and the currently active reserved station entry number. By dynamically overwriting the latest mapping relationship, it eliminates write-after-write data hazards and, together with the reserved station wait mechanism, eliminates read-after-write and read-after-write data hazards. The public data bus physical broadcast network consists of global unidirectional metal traces and multi-level fan-out buffers, covering all reserved station entrances and ALU write-back ports. Each clock cycle broadcasts a single set of operation results and the corresponding target number. The three-stage hardwired pipeline is divided into the transmit stage, the execute stage, and the write-back stage. The dual-mode hardwired data forwarding network is independent of the public data bus physical broadcast network and includes two forwarding mechanisms: bypass mode and pass-through mode. In the bypass mode, the output of the transmitter-reserved station is directly connected to the input of the ALU in a zero-cycle hardwired path, while in the pass-through mode, the input of the pipeline register between ALU stages is led to the input of the next-level ALU in a single-cycle dedicated feedback path.

2. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The multi-channel ALU array is a five-channel ALU array (N=5), with each level of ALU cascaded to form a closed-loop pipeline for chain-dependent operations.

3. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The reserved station physical register array is configured with 8 parallel instruction entries (M=8), satisfying the minimum zero backpressure hardware constraint of M≥N+2.

4. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The execution latency of each type of arithmetic instruction is fixed by hard-wired logic: exponentiation and reciprocal operations are configured to 4 clock cycles, conformal mapping operations are configured to 3 clock cycles, and absolute value operations, multiplication operations, and addition operations are all configured to 2 clock cycles.

5. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The hardwired priority arbitration circuit is composed of multiple cascaded 2-to-1 comparators, and the overall signal propagation delay is less than 0.5 clock cycles.

6. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The public data bus physical broadcast network is only allowed to broadcast a single set of computation results per clock cycle, and the maximum throughput of the system is limited by the public data bus broadcast bandwidth.

7. A dual-mode hardwired data forwarding method for a multi-channel ALU array, wherein the multi-channel ALU array comprises N ALUs and N≥3, characterized in that, include: By bypassing the physical hard-wired path, when the current instruction source register matches the target register of the immediately preceding issued instruction and the operand has been loaded into the reservation station, the data at the output of the issue-level reservation station is directly forwarded to the input of the execution-level ALU with a delay of 0 cycles. By using a direct physical metal feedback path, for intermediate results that have entered ALU execution but have not yet completed the write-back of the common data bus, the data at the input end of the inter-ALU pipeline register is fed into the input end of the next-level ALU in advance, with a delay of 1 cycle. Through hard-wired mode selection and comparison logic, pure combinational logic matched by pipeline register numbers makes a real-time decision on whether to use bypass mode or pass-through mode, thus completing the automatic switching of forwarding mode.

8. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The physical register renaming dynamic matching logic circuit adapts to the dedicated architecture register configuration, and automatically shields the conflict of multiple write operations to the same architecture register through the dynamic binding overwrite mechanism, and the hardware natively eliminates the write-after-write data risk.

9. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, The overall switching delay of the dual-mode hardwired data forwarding network is less than one clock cycle.

10. The out-of-order scheduling circuit system for a multi-channel ALU array according to claim 1, characterized in that, Each entry of the reserved station physical register array has a built-in dual-input numerical comparator, which is used to perform parallel matching of the broadcast target number and the entry waiting source number during the public data bus broadcast phase.

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