Consistency transaction pipeline bypass method and apparatus in an interchip interconnect system

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a consistency transaction pipeline bypass method and device in an inter-chip interconnection system, comprising: obtaining a to-be-processed consistency transaction and related running state information, determining bypass judgment items according to a transaction type and executing judgment; when each item meets a bypass condition, taking the transaction as a bypass candidate transaction, and uniformly scheduling and arbitrating the to-be-sent transaction in a standard pipeline; after obtaining a sending authorization, rechecking a bypass qualification according to updated running state information at a sending submission moment. When the rechecking passes, executing bypass sending submission and updating transaction tracking state and resource state, so that the transaction bypasses at least part of a pipeline stage; otherwise, entering a standard pipeline for processing. The embodiment of the present application can maintain transaction order, scheduling relationship and resource state correctness, shorten processing delay, reduce pipeline resource occupation, and improve transaction processing efficiency and effective throughput.

Description

Technical Field

[0001] This application relates to the field of chip design, and more specifically to a method and apparatus for bypassing a consistent transaction pipeline in an inter-chip interconnect system. Background Technology

[0002] In multi-core system-on-a-chip (SoC), chiplet, and multi-chip architectures, different chip nodes typically transmit requests, data, and cache consistency messages via chip-to-chip (C2C) interconnects. Chip nodes can be either dies or individual chips. To maintain cache consistency between different chip nodes, the C2C interface usually works in conjunction with a network-on-chip (NoC) interface to forward request and listener transactions.

[0003] When existing inter-chip interconnect devices receive a consistent transaction, it typically requires multiple pipeline stages, including transaction registration, dependency checking, resource allocation, scheduling arbitration, and message sending. Even if there is no actual conflict between the current transaction and transactions in transit, it still needs to be processed according to the complete pipeline. In addition, the processing latency of cross-chip snooping transactions can also affect the completion time of related consistent transactions.

[0004] Therefore, the existing consistency transaction processing methods in inter-chip interconnect systems suffer from long processing latency and excessive pipeline resource consumption time, necessitating the development of a new solution. Summary of the Invention

[0005] This application provides a method and apparatus for bypassing the pipeline of consistent transactions in an inter-chip interconnect system, which solves the technical problems of long processing latency and long pipeline resource occupation time in the existing consistent transaction processing methods of inter-chip interconnect systems.

[0006] In a first aspect, embodiments of this application provide a consistent transaction pipeline bypass method in an inter-chip interconnect system, applied to an interconnect proxy node between an on-chip network interface and an inter-chip interconnect interface, the method comprising: Obtain the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node; The corresponding set of bypass decision items is determined according to the transaction type of the consistency transaction to be processed, and each bypass decision item in the set of bypass decision items is executed according to the running status information to obtain the corresponding decision result. If the project judgment results all meet the corresponding bypass conditions, the pending consistency transaction is regarded as a bypass candidate transaction, and the bypass candidate transaction and the pending transaction in the standard pipeline are uniformly scheduled and arbitrated to determine the sending authorization of the bypass candidate transaction. In response to the transmission authorization, at the time of transmission submission of the bypass candidate transaction, the bypass qualification of the bypass candidate transaction is reviewed according to the updated running status information; After the bypass qualification review is passed, the bypass candidate transaction is sent and committed according to the sending authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass sending and commit, so that the bypass candidate transaction bypasses at least part of the pipeline stages in the standard pipeline; If any of the project judgment results does not meet the corresponding bypass conditions, the bypass candidate transaction does not obtain the sending authorization, or the bypass qualification review fails, the pending consistency transaction will be transferred to the standard pipeline for processing.

[0007] Secondly, embodiments of this application provide a consistency transaction pipeline bypass device in an inter-chip interconnect system. The device is disposed at an interconnect proxy node between the on-chip network interface and the inter-chip interconnect interface, and the device includes: The input / output module is configured to acquire the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node; The processing module is configured to determine a corresponding set of bypass decision items based on the transaction type of the consistency transaction to be processed, and execute each bypass decision item in the set of bypass decision items according to the running status information to obtain the corresponding decision result; if all the decision results of the items meet the corresponding bypass conditions, the consistency transaction to be processed is regarded as a bypass candidate transaction, and the bypass candidate transaction is uniformly scheduled and arbitrated with the transactions to be sent in the standard pipeline to determine the sending authorization of the bypass candidate transaction; in response to the sending authorization, at the time of sending submission of the bypass candidate transaction... The bypass eligibility of the candidate bypass transaction is verified based on the updated runtime status information. After the bypass eligibility verification is passed, a bypass send commit is performed on the candidate bypass transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit, so that the candidate bypass transaction bypasses at least some pipeline stages in the standard pipeline. If any of the project judgment results does not meet the corresponding bypass conditions, the candidate bypass transaction does not obtain the send authorization, or the bypass eligibility verification fails, the pending consistency transaction is transferred to the standard pipeline for processing. The input / output module is further configured to output the bypass candidate transaction via the on-chip network interface or the inter-chip interconnect interface according to the bypass send submission executed by the processing module.

[0008] It is worth noting that the consistency transaction pipeline bypass device in the inter-chip interconnect system has the function of implementing the consistency transaction pipeline bypass method in the inter-chip interconnect system corresponding to the first aspect provided above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function, and the modules can be software and / or hardware.

[0009] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the consistent transaction pipeline bypass method in an inter-chip interconnect system as described in the first aspect.

[0010] Fourthly, embodiments of this application provide a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the consistent transaction pipeline bypass method in the inter-chip interconnect system described in the first aspect.

[0011] Fifthly, embodiments of this application provide a chip including a processor coupled to a transceiver for executing the technical solution provided in the first aspect of this application. In one possible design, the chip can also be a dedicated hardware structure for implementing the technical solution provided in the first aspect.

[0012] In a sixth aspect, embodiments of this application provide a chip system including a processor for implementing the functions involved in the first aspect above, such as generating or processing information involved in the consistent transaction pipeline bypass method in the inter-chip interconnect system provided in the first aspect above.

[0013] In one possible design, the aforementioned chip system further includes a memory connected to the processor via a circuit structure. This memory stores program instructions and data necessary for the terminal. The chip system can be composed of a single chip or may include chips and other discrete devices. Further optionally, the chip also includes a communication interface to which the processor connects. The communication interface receives data and / or information that needs to be processed. The processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing result through the communication interface. This communication interface can be an input / output interface.

[0014] In a seventh aspect, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on a computer, cause the computer to execute the consistency transaction pipeline bypass method in the inter-chip interconnect system provided in the first aspect.

[0015] Compared to existing technologies, in this embodiment, the interconnecting proxy node acquires the pending consistency transactions and their related operational status information, enabling bypass judgment to be based on the current status of in-transit transactions, pending transactions, and transaction processing resources, rather than statically determining the transaction transmission path solely based on transaction type or fixed channels. The interconnecting proxy node determines a corresponding set of bypass judgment items based on the transaction type of the pending consistency transaction. This allows for the separate examination of potential transaction dependencies, order constraints, scheduling status, and resource availability for different transactions such as request transactions and listening transactions. The results of each item's judgment collectively determine whether the pending consistency transaction meets the conditions for bypassing certain pipeline stages, thereby preventing transactions that do not meet consistency, order, or resource requirements from entering the bypass transmission path.

[0016] When all project judgment results meet the corresponding bypass conditions, the interconnect agent node will treat the pending consistency transaction as a bypass candidate transaction and perform unified scheduling arbitration with the pending transactions in the standard pipeline. This ensures that the bypass candidate transaction remains bound by the current scheduling relationship, preventing high-priority transactions from being delayed or the predetermined sending order from being altered due to bypass sending. After the bypass candidate transaction is authorized to send, the interconnect agent node will re-verify the bypass qualification based on the updated runtime status information at the time of sending and committing. This is to identify changes in the status of in-transit transactions, resource consumption, or scheduling status that have occurred between the initial bypass judgment and the actual sending and committing, avoiding the use of invalid judgment results to execute bypass sending.

[0017] After the bypass qualification review is passed, the interconnected agent node executes a bypass send commit based on the send authorization, and updates the corresponding transaction tracking status and resource status with the bypass send commit, ensuring that transaction send, transaction tracking, and related resource occupancy correspond to each other, and guaranteeing that transaction response and resource release can still be continuously managed after the bypass send. Thus, bypass candidate transactions can skip at least some pipeline stages in the standard pipeline, such as transaction queuing, duplicate dependency checks, resource allocation, or scheduling waits. For any transaction whose project judgment result does not meet the bypass conditions, does not obtain send authorization, or fails the bypass qualification review at the time of send commit, the interconnected agent node transfers it to the standard pipeline for processing, to utilize the standard pipeline's transaction checking and processing mechanisms.

[0018] Therefore, the embodiments of this application can identify transactions that meet the conditions for early transmission based on the real-time running status of consistent transactions. While maintaining cache consistency, transaction order, scheduling relationships, and correct resource usage, it reduces the number of pipeline stages and waiting periods traversed by transactions without actual conflicts, thus shortening the processing latency of consistent transactions. Simultaneously, by unifying scheduling arbitration and bypass qualification verification during transmission and submission, it reduces priority inversion, state mismatch, and resource allocation errors that may be caused by static bypassing or single-step determination, and reduces the time occupied by resources such as trace entries and scheduling bandwidth in the standard pipeline, thereby improving the efficiency and effective throughput of consistent transaction processing between the on-chip network interface and the inter-chip interconnect interface. Attached Figure Description

[0019] The objectives, features, and advantages of the embodiments of this application will become readily understood by referring to the accompanying drawings and the detailed description of the embodiments. Wherein: Figure 1 A flowchart illustrating a consistent transaction pipeline bypass method in an inter-chip interconnect system provided in this application embodiment; Figure 2 A schematic diagram of a consistent transaction pipeline bypass device in an inter-chip interconnect system provided in this application embodiment; Figure 3 A schematic diagram of a request transaction bypass processing flow provided in an embodiment of this application; Figure 4 A schematic diagram of a bypass processing flow for eavesdropping transactions is provided for an embodiment of this application; Figure 5 A timing comparison diagram of a bypass path and a standard pipeline is provided for an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a consistency transaction pipeline bypass device in an inter-chip interconnect system according to an embodiment of this application. Figure 7 This is a schematic diagram of the structure of a computing device according to an embodiment of this application; Figure 8 This is a schematic diagram of a server structure in one embodiment of this application.

[0020] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0023] It should be understood that, in order to clearly describe the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0024] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] This application provides a method and apparatus for pipelined bypassing consistent transactions in an inter-chip interconnect system. It is applied to cache-consistent interconnect scenarios in multi-core on-chip systems, chiplet systems, multi-die systems, or multi-chip systems, and is used to forward consistent transactions between on-chip network interfaces and inter-chip interconnect interfaces. The chip nodes include dies or chips. This method can be implemented using digital circuit logic and can be described and synthesized into a corresponding circuit structure using a hardware description language, and deployed in interconnect proxy nodes, protocol bridging nodes, or other hardware nodes with consistent transaction forwarding capabilities.

[0027] Figure 1 This is a flowchart illustrating a consistent transaction pipeline bypass method in an inter-chip interconnect system, as provided in an embodiment of this application. This method can be executed by a consistent transaction pipeline bypass device in an inter-chip interconnect system.

[0028] Figure 2 This is a schematic diagram of a consistent transaction pipeline bypass device in an inter-chip interconnect system provided in an embodiment of this application. (Refer to...) Figure 2This device can be deployed in the interconnect agent node of a cache coherence interconnect, positioned between the chip-to-chip coherence bus protocol interface C2C-CHI and the on-chip network coherence bus protocol interface NOC-CHI. It includes a Request Handling Unit (RHU), a Snoop Handling Unit (SHU), and a data buffer layer located between the RHU and SHU. The device can also connect to the Advanced Peripheral Bus (APB) to access configuration parameters and operational status within the device.

[0029] In this embodiment of the application, C2C-CHI and NOC-CHI can use the Coherent Hub Interface (CHI) protocol to transmit consistent transactions. Based on Figure 2 The illustrated architecture uses a 512-bit data width for both C2C-CHI and NOC-CHI, and a 32-bit data width for APB, as an example. In practical applications, the data width of each interface can be determined based on protocol configuration, link bandwidth between chip nodes, and on-chip network structure, and does not constitute a limitation on the embodiments of this application. C2C-CHI includes a request inlet and a listening outlet. The request inlet is used to receive request transactions entering the interconnect proxy node from the C2C side, and the listening outlet is used to send the listening transactions processed by the interconnect proxy node back to the C2C side. NOC-CHI includes a request outlet and a listening inlet. The request outlet is used to send request transactions to the NoC side, and the listening inlet is used to receive listening transactions entering the interconnect proxy node from the NoC side. Thus, request transactions form a request transmission direction from C2C-CHI to NOC-CHI, and listening transactions form a listening transmission direction from NOC-CHI to C2C-CHI. The RHU is used to process request transactions received by C2C-CHI and sent to NOC-CHI. RHU may include an hazard and sequence check unit, a dependency check unit, an RHU transaction entry unit, and an RHU scheduling and distribution unit.

[0030] The hazard and sequence check unit is used to check for hazard between a listening transaction and a completion acknowledgment, as well as between a listening transaction and a write-back transaction, based on the address, transaction type, and processing status of the pending request transaction and the transactions in transit. The dependency check unit is used to check for device type non-mergeable access dependencies, ordered write observation dependencies, and non-device type non-mergeable access dependencies. The specific types of the above check items can be determined based on the CHI protocol version, transaction ordering rules, and storage attribute configuration used by the interconnect agent node.

[0031] RHU transaction table entries can form a request transaction tracker to record in-transit request transactions in interconnected agent nodes. Figure 2 In this example, taking an RHU transaction entry unit comprising four partitions, each partition can have multiple request transaction tracing entries. Request transaction tracing entries can maintain the transaction state (state), data buffer state (dbstate), and request attribute (reqattr).

[0032] Transaction status can be used to indicate whether the corresponding request transaction is valid, has been sent, is waiting for a response, or has been completed. Data buffer status can be used to indicate the read or write data buffer resources occupied by the request transaction. Request attributes can include at least one of the following: source node identifier, target node identifier, transaction identifier, address, transaction type, storage attributes, order attributes, and quality of service information. In practical applications, the number of partitions in the request transaction tracker, the number of entries in each partition, and the fields in each entry can be configured according to the number of transactions in transit that can be supported and circuit timing requirements.

[0033] The RHU transaction entry unit provides the transaction attributes and states from each valid request transaction trace entry to the hazard and order checking unit and the dependency checking unit. Each checking unit compares the pending request transaction with each valid request transaction trace entry, generating corresponding hazard hit results and dependency hit results. The comparisons of each entry can be performed in parallel using a comparator array, and the comparison results are then summarized to form a dependency state snapshot used for request transaction bypass determination.

[0034] The RHU scheduling and distribution unit may include a Quality of Service (QoS) arbitrator, a partition arbitrator, a flow control unit (FCU) packetizing unit, a receive buffer, and a distribution multiplexer. The QoS arbitrator selects the transaction to be sent based on the QoS level or scheduling priority of the requesting transaction; the partition arbitrator selects among transactions output from multiple RHU partitions; the FCU packetizing unit generates flow control units to be sent according to the protocol format of the target interface; the receive buffer temporarily stores transactions participating in the distribution; and the distribution multiplexer selects the transaction to be sent in the current processing cycle from the transactions to be sent output from the standard pipeline and the request bypass candidate transactions.

[0035] The request-bypass candidate transaction and the pending transactions in the standard pipeline are sent to the same arbitration domain of the RHU scheduling and distribution unit. If there is a pending transaction in the standard pipeline with a higher scheduling priority than the request-bypass candidate transaction, the RHU scheduling and distribution unit will prioritize that pending transaction. If there is no pending transaction with a higher scheduling priority, the request-bypass candidate transaction can obtain transmission authorization and be sent to NOC-CHI via the request-bypass path. This avoids the request-bypass candidate transaction independently occupying the transmission interface, which could delay high-priority transactions.

[0036] The data buffer layer can include a Write Data Buffer (WDB), a Snoop Response Data Buffer (SRDB), and a Read Data Buffer (RDB). The WDB is used to cache write data transmitted from the C2C side to the NoC side, the SRDB is used to cache snoop response data transmitted from the NoC side to the C2C side, and the RDB is used to cache read data returned from the NoC side to the C2C side and corresponding to the request transaction.

[0037] RDBs can be managed by the read data buffer management unit. The read data buffer management unit maintains the occupancy status of each RDB entry and determines available RDB entries for a requesting transaction when that transaction has read return semantics. If multiple requesting transactions request RDBs within the same processing cycle, the read data buffer management unit can perform resource allocation arbitration and generate exclusive allocation grants to prevent the same RDB entry from being allocated repeatedly within the same processing cycle. Figure 2 Only the module locations of WDB, SRDB, and RDB are shown. The specific data input ports, output ports, and internal connections can be configured according to the data path of the interconnected agent nodes.

[0038] The SHU is used to process listening transactions received by NOC-CHI and sent to C2C-CHI. The SHU may include an SHU scheduling and distribution unit, an SHU transaction entry unit, a listening and receiving buffer, configuration registers, and a performance monitoring unit (PMU).

[0039] The SHU scheduling and distribution unit may include a Quality of Service (QoS) arbitrator, a partition arbitrator, a flow control unit packaging unit, and a message credit management unit (msgcrdmgr). The QoS arbitrator and partition arbitrator are used to determine the transaction to be sent among multiple listening transactions; the flow control unit packaging unit is used to generate listening flow control units according to the protocol format corresponding to C2C-CHI; the message credit management unit is used to maintain available message credits for each message channel and update the corresponding credit count based on the sending of listening transactions and the return of message credits.

[0040] SHU transaction table entries can be used to construct a listener transaction tracker, or as a listener hold table or a listener risk table. Figure 2Taking the SHU transaction entry unit, which includes four partitions, as an example, the listening transaction tracking entries in each partition can maintain the transaction state (state), request attribute (reqattr), and response attribute (respattr). The transaction state indicates whether the listening transaction is valid, whether it has been sent, and whether the corresponding response has been received; the request attribute can include the transaction identifier, destination address, source node identifier, and destination node identifier; the response attribute can include at least one of the response opcode, response status, and response data status.

[0041] The SHU transaction entry unit determines whether there are any allocable idle listening transaction entries based on the occupancy status of each listening transaction tracking entry, and determines whether there are any sequence hazards between the completion confirmation and the listening transaction based on the in-transit request transaction status in the request transaction tracker. The message credit management unit simultaneously determines whether the message channel corresponding to the listening transaction has available message credit. When an idle listening transaction entry exists, no corresponding sequence hazard exists, and available message credit exists, the listening transaction can be identified as a listening bypass candidate transaction.

[0042] When a listening bypass candidate transaction is granted transmission authorization and still meets the bypass conditions at the time of transmission commit, the SHU scheduling and distribution unit can directly send the listening transaction to C2C-CHI through the listening bypass path. The valid transmission of a listening transaction, the occupancy of idle listening transaction entries, and the deduction of message credit can be controlled by the same bypass transmission commit, to avoid a partially committed state where the listening transaction entry is already occupied or the message credit has been deducted before the listening transaction has been validly transmitted.

[0043] The listener receive buffer is used to temporarily store listener transactions received by NOC-CHI. The configuration register can be used to store at least one of the following: request bypass enable flag, listener bypass enable flag, scheduling priority threshold, and performance monitoring control parameters. The PMU can record the number of bypass requests, listener bypass counts, number of bypass eligibility verification failures, and the number of times different bypass criteria are not met, providing operational data for bypass policy configuration and performance analysis.

[0044] The APB can serve as an access interface for configuration registers and a status read interface for the PMU. Processors or other control nodes can write bypass enable parameters and scheduling configuration parameters through the APB, and can also read bypass hit rates, failure reasons, and resource usage status recorded by the PMU. Figure 2 The corresponding locations of APB, configuration register, and PMU are shown. The specific read / write channels and internal connection methods of APB can be implemented using existing bus interface structures.

[0045] In this embodiment, the Bypass Eligibility Checker (BEC) can be configured in both the RHU and SHU. The request bypass eligibility checker in the RHU receives status information from the hazard and sequence checking unit, dependency checking unit, RHU transaction entry unit, RHU scheduling and distribution unit, and read data buffer management unit, and determines whether the request transaction satisfies the bypass conditions corresponding to transaction dependencies, scheduling status, and read return resources. The listener bypass eligibility checker in the SHU receives status information from the SHU transaction entry unit and message credit management unit, and determines whether the listener transaction satisfies the bypass conditions corresponding to the listener transaction entry, sequence hazard, and message credit.

[0046] Each state-providing unit can output a corresponding state snapshot within the same processing cycle, enabling BEC to execute the corresponding bypass decision items in parallel. The bypass eligibility result generated by BEC is sent to the corresponding scheduling and distribution unit, which performs unified scheduling arbitration on bypass candidate transactions and pending transactions in the standard pipeline. After a bypass candidate transaction is granted transmission authorization, BEC can review the bypass eligibility based on the updated state snapshot at the time of transmission commit.

[0047] If the bypass eligibility verification is successful, the corresponding scheduling and distribution unit executes the bypass send commit and updates the transaction tracking status and resource status. Requesting transactions are sent to NOC-CHI via the RHU's request bypass path, and listening transactions are sent to C2C-CHI via the SHU's listening bypass path. Transactions that meet the bypass conditions can skip at least one pipeline stage in the standard pipeline, including queuing, duplicate hazard checks, resource allocation, or scheduling waits.

[0048] If any bypass decision item does not meet the corresponding bypass conditions, the bypass candidate transaction does not obtain send authorization, or the bypass qualification review at the time of send submission fails, the pending consistency transaction will be transferred to the Full Pipeline (FPL) for regular processing. FPL can sequentially execute transaction queuing, hazard or dependency checks, transaction processing resource allocation, scheduling arbitration, and transaction send.

[0049] In one alternative implementation, Figure 2Based on the illustrated architecture, interconnect agent nodes can also be configured with a Rollback and Re-inject Controller (RRC). For bypass candidate transactions that have been authorized to send but have not yet been accepted by the target interface, the RRC monitors for late transaction dependencies, message credit expiration, and order hazard state changes. If the above state changes invalidate the bypass qualification, the RRC revoks the bypass send, first releasing or returning the reserved RDB, listening transaction entries, or message credits, and then re-injecting the corresponding transaction into the FPL. If the target interface has already accepted the transaction, local revocation is not performed; instead, the transaction processing continues according to the corresponding consistency protocol.

[0050] Through the above structure, RHU and SHU perform bypass eligibility determinations for the request path and listener path respectively, based on the transaction type, and complete unified arbitration between bypass candidate transactions and standard pipeline transactions in their respective scheduling and distribution units. Transactions that meet the requirements of transaction dependency, sequence relationship, scheduling priority, transaction tracing resources, and message flow control can bypass at least some pipeline stages in the standard pipeline, thereby reducing the processing wait cycle of request transactions and listener transactions, shortening the processing latency of cross-chip consistency transactions, and reducing the occupation time of standard pipeline and transaction tracing resources.

[0051] Reference Figure 1 A method for pipelined bypassing of consistent transactions in an inter-chip interconnect system includes the following steps 101-106: Step 101: Obtain the consistency transaction to be processed and the running status information related to the consistency transaction in the interconnected proxy node.

[0052] In this embodiment of the application, the running status information includes the transaction status of transactions in transit, the scheduling status of transactions to be sent, and the availability status of transaction processing resources.

[0053] Specifically, the interconnect proxy node is positioned between the Network-on-Chip (NoC) interface and the Chip-to-Chip (C2C) interface to receive, process, and forward consistency transactions between the two interfaces. Consistency transactions awaiting processing can be transactions that arrive at the interconnect proxy node in the current processing cycle but have not yet entered the standard pipeline or are waiting to be processed at the entry point of the standard pipeline. These include request transactions and listener transactions. Request transactions can include read requests, write requests, and atomic operation transactions. Listener transactions can include consistency listener transactions received by the Network-on-Chip side and that need to be sent to the C2C interface side.

[0054] The operational status information reflects whether the interconnected broker node has the conditions to safely send pending consistent transactions within the current processing cycle. Specifically, the transaction status of in-transit transactions characterizes transactions that have been received by the interconnected broker node but not yet completed, and their current processing stage. The scheduling status of transactions to be sent characterizes transactions waiting to be sent in the standard pipeline, their corresponding scheduling priorities, and send request status. The availability status of transaction processing resources characterizes whether the trace entries, data buffer resources, and message credit resources required for transaction sending and subsequent response processing can be allocated.

[0055] The interconnected agent nodes form a snapshot of the running status based on the information obtained within the same processing cycle, so that the transaction status, scheduling status and resource status used for subsequent bypass decisions have a corresponding time base, reducing the possibility of erroneous bypass decisions due to inconsistent collection times of different status information.

[0056] As an optional embodiment, in step 101, obtaining the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node includes: obtaining the transaction attributes and transaction status of the in-transit transaction from the request transaction tracker and the listener transaction tracker; obtaining the pending transaction and its scheduling status in the standard pipeline from the scheduling and distribution unit; and obtaining the resource availability status from the resource management unit corresponding to the transaction processing resource; taking the transaction attributes, the transaction status, the scheduling status, and the resource availability status as a status snapshot corresponding to the same processing cycle; executing each of the bypass judgment items in parallel according to the status snapshot; and summarizing the judgment results of each item to determine whether the pending consistency transaction meets the corresponding bypass conditions.

[0057] Specifically, the request transaction tracker is used to record in-transit request transactions. Valid transaction tracking entries can record at least one of the following: transaction validity status, source node identifier, target node identifier, transaction identifier, address, transaction type, storage attribute, order attribute, data buffer resource occupancy status, and response reception status. The listener transaction tracker is used to record in-transit listener transactions. Its valid transaction tracking entries can record at least one of the following: listener transaction address, transaction identifier, sending status, response status, and hazard status between the listener and the request transaction.

[0058] The scheduling and distribution unit collects the sending requests and scheduling information of transactions to be sent in the standard pipeline. The scheduling information may include at least one of the following: service quality level, transaction priority, transaction arrival order, partition to which it belongs, and polling status. The resource management unit may include a read data buffer management unit, a listening transaction entry management unit, and a message credit management unit, which respectively output the idle status of the read data buffer resources, the occupancy status of the listening transaction entries, and the number of available message credits for the message channel.

[0059] In one circuit implementation, the requesting transaction tracker, the listening transaction tracker, the scheduling and distribution unit, and each resource management unit provide corresponding status signals to the bypass eligibility determination logic within the same processing cycle. The bypass eligibility determination logic can utilize parallel comparison circuits to execute multiple bypass determination items, and then obtain the bypass eligibility signal through logical aggregation. This implementation eliminates the need to sequentially query various status information, which helps to shorten the processing cycle occupied by bypass eligibility determination.

[0060] Step 102: Determine the corresponding bypass decision item set according to the transaction type of the consistency transaction to be processed, and execute each bypass decision item in the bypass decision item set according to the running status information to obtain the corresponding item decision result.

[0061] The bypass decision item set includes transaction dependency or sequence status decision items and transaction processing resource availability decision items.

[0062] Specifically, different types of consistency transactions have different transmission security requirements. Requesting transactions need to check for address dependencies or order constraints between themselves and in-transit transactions, and, when they have read-return semantics, check the buffer resources required for the returned data. Listening transactions need to check for the existence of a trace entry available to record the listening transaction, whether it forms a sequence hazard with a requesting transaction waiting for completion confirmation, and whether the corresponding message channel has available message credit. Therefore, interconnect broker nodes first identify the transaction type of the consistency transaction to be processed, and then call the bypass decision item set corresponding to that transaction type, avoiding the application of the same static bypass rules to all transactions.

[0063] Each bypass decision item outputs a corresponding decision result. For example, the decision result can use a single valid signal to indicate whether the corresponding bypass condition is met or not, or it can simultaneously output a failure reason identifier to distinguish between situations such as transaction dependency hit, insufficient scheduling priority, unavailable buffer resources, insufficient listening transaction entries, sequence hazard hit, or insufficient message credit. Only when all decision results of each item meet the corresponding bypass condition will the pending consistency transaction enter the scheduling process of subsequent bypass candidate transactions.

[0064] As an optional embodiment, if the consistency transaction to be processed is a request transaction, the bypass decision item set includes transaction dependency decision items, scheduling status decision items, and read return resource decision items. Specifically, the transaction dependency decision items are used to determine whether sending the request transaction early will disrupt its address dependency or order relationship with in-transit transactions; the scheduling status decision items are used to determine whether sending the request transaction early will delay standard pipeline transactions with higher scheduling priority; and the read return resource decision items are used to determine whether the request transaction with read return semantics already has the buffer conditions to receive the returned data before it is sent.

[0065] For write requests that do not have read-return semantics, the outcome of the read-return resource determination item can be set to meet the bypass condition, so that the bypass qualification of such requests is mainly determined by the transaction dependency determination result and the scheduling status determination result. For read requests and atomic operations such as atomic load, atomic comparison, or atomic swap that have read-return semantics, it is necessary to further obtain the qualification for allocation of read data buffer resources.

[0066] Based on the above optional embodiments, in step 102, the step of executing each bypass decision item in the bypass decision item set according to the running status information to obtain the corresponding item decision result includes: The transaction information of the requested transaction is compared with each valid transaction tracking entry in the requested transaction tracker and the listening transaction tracker to determine whether the requested transaction has a preset transaction dependency with any in-transit transaction; based on the scheduling information of the requested transaction and the scheduling status of the transactions to be sent in the standard pipeline, it is determined whether the requested transaction meets the early sending condition; if the requested transaction has read return semantics, based on the availability and allocation status of the read data buffer resource, it is determined whether read data buffer resource can be allocated to the requested transaction; based on the item judgment results of the transaction dependency judgment item, the scheduling status judgment item, and the read return resource judgment item, it is determined whether the requested transaction meets the corresponding bypass condition.

[0067] Specifically, interconnected agent nodes can be configured with combined logic for performing transaction dependency determination, scheduling status determination, and read return resource determination. The transaction dependency determination logic uses transaction information such as the address, transaction type, storage attributes, and order attributes of the requested transaction as one set of comparison inputs, and the corresponding information recorded in each valid transaction tracking table as another set of comparison inputs, performing parallel comparisons on each valid transaction tracking table entry. The scheduling status determination logic compares the scheduling priority of the requested transaction with that of standard pipeline transactions awaiting transmission. The read return resource determination logic determines whether the requested transaction can occupy the corresponding resource based on the idle status of the read data buffer resource and the resource allocation authorization.

[0068] When a request transaction has no pre-defined transaction dependencies, meets the early send condition, and can obtain read data buffer resources when it has read return semantics, the interconnected agent node determines that the decision results of each item of the request transaction meet the corresponding bypass condition. If any item decision result does not meet the corresponding bypass condition, the request transaction is not directly determined as a sendable transaction, but is handed over to the standard pipeline for continued queuing, hazard checking, resource allocation, and scheduling processing.

[0069] Further optionally, in the above optional embodiments, the preset transaction dependencies include transaction hazards between listening transactions and write-back transactions, transaction dependencies corresponding to non-mergeable access of device types, transaction dependencies corresponding to non-mergeable access of non-device types, and transaction dependencies corresponding to ordered write observations.

[0070] Specifically, a transaction hazard between a listening transaction and a write-back transaction refers to a situation where the current request and an in-transit listening transaction or write-back transaction involve the same cache line or satisfy other preset address associations, and sending the current request early may change the processing order of the listening transaction and the write-back transaction. Write-back transactions can include transactions used to write cache line data back to their home node.

[0071] Transaction dependencies corresponding to non-mergeable device types refer to access relationships between a requesting transaction with device storage attributes and non-mergeable attributes, where the requesting transaction and the in-transit transaction need to be processed according to the protocol order. Transaction dependencies corresponding to non-mergeable non-device types refer to requesting transactions that do not belong to the aforementioned non-mergeable device types, where there are read-write dependencies, write-write dependencies, or other dependencies that prohibit early transmission between them and incomplete transactions at the same address or associated address. Transaction dependencies corresponding to ordered write observations refer to the requirement that the current write request and the in-transit write transaction have ordered observation requirements, and early transmission of the current write request may change the prescribed observable order of write transactions.

[0072] The above dependency types can be configured based on the consistency protocol version, storage attribute definitions, and transaction ordering rules adopted by the interconnected proxy nodes. All types of dependencies together constitute the dependency-free condition that must be met for a requested transaction to be bypassed; if any dependency is hit, the requested transaction will be prevented from being bypassed.

[0073] Based on the above optional embodiments, in step 102, comparing the transaction information of the requested transaction with each valid transaction tracking entry in the requested transaction tracker and the listening transaction tracker to determine whether the requested transaction has a preset transaction dependency with any in-transit transaction includes: From the transaction information of the requesting transaction and each of the valid transaction tracking entries, comparison information corresponding to various preset transaction dependencies is obtained. The comparison information includes at least one of address information, transaction type, storage attribute, order attribute, and transaction status. For each of the valid transaction tracking entries, matching judgments of various preset transaction dependencies are performed according to the corresponding comparison information to obtain dependency judgment results corresponding to each of the valid transaction tracking entries. The dependency judgment results are summarized. If any of the valid transaction tracking entries matches any of the preset transaction dependencies, it is determined that there is a preset transaction dependency between the requesting transaction and the in-transit transactions, and it is determined that the item judgment result of the transaction dependency judgment item does not meet the corresponding bypass condition. If none of the valid transaction tracking entries match any of the preset transaction dependencies, it is determined that there is no preset transaction dependency between the requesting transaction and each of the in-transit transactions, and it is determined that the item judgment result of the transaction dependency judgment item meets the corresponding bypass condition.

[0074] Specifically, comparison logic can be set for each valid transaction tracking entry in both the requesting and listening transaction trackers. The comparison logic first determines whether the transaction tracking entry records any incomplete transactions based on the valid bits; invalid transaction tracking entries are not included in the dependency judgment. For valid transaction tracking entries, the comparison logic determines whether the address of the currently requested transaction and the address recorded in the entry point to the same cache line. The cache line address can be obtained by removing the cache line offset bits from the address, and the cache line size can be configured according to the cache structure adopted by the interconnect system.

[0075] After the addresses satisfy the preset matching relationship, the comparison logic further combines the transaction type, storage attributes, order attributes, and transaction status to determine whether a corresponding type of transaction dependency has been formed. For example, for device types that cannot be merged, it is necessary to combine the device storage attributes and the non-mergeable attribute for judgment; for ordered write observation dependencies, it is necessary to combine the write transaction type and the ordered observation attribute for judgment; for transaction hazards between listening transactions and write-back transactions, it is also necessary to combine whether the in-transit transaction is currently in the listening or write-back processing stage for judgment.

[0076] Each comparison logic outputs a corresponding dependency hit signal, and then the dependency hit signals of all valid transaction trace entries are summarized. In one hardware implementation, the dependency hit signals can be generated in parallel using a comparator array, and then a global dependency hit result is obtained through reduction OR logic. If any valid transaction trace entry hits any type of preset transaction dependency, the bypassing of that request transaction is prohibited; only when none of the valid transaction trace entries hit any type of preset transaction dependency is the bypass condition determined. Therefore, it is possible to determine whether a request transaction can be sent ahead of schedule based on the current state of all in-transit transactions.

[0077] Further optionally, in the above optional embodiments, determining whether the request transaction meets the early sending condition based on the scheduling information of the request transaction and the scheduling status of the pending transactions in the standard pipeline includes: determining whether there are any transactions in the pending state in the standard pipeline; if there are no transactions in the pending state, determining that the request transaction meets the early sending condition; if there are transactions in the pending state, comparing the scheduling priority of the request transaction with the scheduling priority of the transactions in the pending state, and determining that the request transaction meets the early sending condition if there are no pending transactions with a higher scheduling priority than the request transaction.

[0078] Specifically, the scheduling and distribution unit can receive send requests from one or more pending transactions in the standard pipeline and read the quality of service level or transaction priority of each pending transaction. If there are no valid send requests in the standard pipeline, the early send of the requesting transaction will not occupy the send opportunities already allocated to other transactions, and thus it can be determined that it meets the early send condition.

[0079] If there are pending transactions in the standard pipeline, the scheduling priority of the current requesting transaction is compared with that of each pending transaction. If a pending transaction with a higher scheduling priority exists, the current requesting transaction is prevented from bypassing, and its sending opportunity is reserved. If no pending transaction with a higher scheduling priority exists, the current requesting transaction can be submitted to the subsequent unified scheduling arbitration.

[0080] When a requesting transaction and a pending transaction have the same scheduling priority, the sending order can be determined based on arrival order, polling status, partition affiliation, or a preset quality of service policy. This same-priority rule can be uniformly executed by the scheduling and distribution unit without changing the processing principle that higher-priority standard pipeline transactions can prevent lower-priority bypass transactions from being sent prematurely. Therefore, bypass paths will not preempt the sending interface independently of the standard pipeline, thus avoiding priority inversion caused by bypass transactions.

[0081] Further optionally, in the above optional embodiments, if the request transaction has read return semantics, determining whether read data buffer resources can be allocated to the request transaction based on the availability and allocation status of the read data buffer resources includes: determining whether the read data buffer resources corresponding to the request transaction are in an idle state, and performing resource allocation arbitration on request transactions with read return semantics within the same processing cycle; if the read data buffer resources are in an idle state and the request transaction obtains exclusive allocation authorization generated by the resource allocation arbitration, determining that the read data buffer resources can be allocated to the request transaction; if the read data buffer resources are not in an idle state or the request transaction does not obtain the exclusive allocation authorization, determining that the item determination result of the read return resource determination item does not meet the corresponding bypass condition; wherein, providing the exclusive allocation authorization to a request transaction within the same processing cycle, the request transaction with read return semantics includes read request transactions and atomic operation transactions.

[0082] Specifically, the read data buffer resource is used to receive and temporarily store the return data of requesting transactions. The read data buffer management unit maintains the occupancy status of each read data buffer entry and generates a resource availability indication based on the free entries. When multiple requesting transactions with read return semantics apply for read data buffer resources within the same processing cycle, the read data buffer management unit performs resource allocation arbitration on each requesting transaction and generates an exclusive allocation authorization pointing to one of the requesting transactions.

[0083] For example, the exclusive allocation authorization can employ one-hot encoding, ensuring that the same read data buffer resource or the same read data buffer partition is allocated to at most one request transaction within a processing cycle. The read data buffer resource can also be divided into multiple independent partitions, with each partition generating an exclusive allocation authorization for its corresponding request transaction, thereby improving parallel processing capabilities while avoiding duplicate allocation of the same buffer entry.

[0084] A requesting transaction is only deemed eligible to receive returned data if the read data buffer resource is idle and has been exclusively allocated. If the resource is already occupied or the requesting transaction is not granted permission in resource contention, the requesting transaction will not pass the read return resource determination and will proceed to the standard pipeline or wait for a subsequent processing cycle to participate in the determination again. Therefore, the storage location of the returned data can be determined before the requesting transaction is issued, preventing the inability to receive returned data due to a lack of buffer resources after a bypass read request is issued.

[0085] As an optional embodiment, if the consistency transaction to be processed is a listening transaction, the bypass decision item set includes listening transaction entry decision items, sequence hazard decision items, and message credit decision items.

[0086] Specifically, the Listen Transaction Entry Determination item is used to determine whether there is an idle entry in the Listen Transaction Tracker that can record the processing status of a bypassed Listen Transaction. The Sequence Hazard Determination item is used to determine whether sending a Listen Transaction prematurely would change the protocol processing order between it and the completion confirmation of an in-transit request transaction. The Message Credit Determination item is used to determine whether the receiving side of the target message channel has the buffering capacity to receive the Listen Transaction.

[0087] The three criteria mentioned above correspond to transaction tracking, order safety, and link flow control, respectively. Only when all three criteria meet the corresponding bypass conditions can a listening transaction be considered as a bypass candidate transaction, thus avoiding transaction loss, duplicate processing, or flow control anomalies caused by the inability to track the listening status, disruption of the completion confirmation order, or exceeding the target channel's receiving capacity.

[0088] Based on the above optional embodiments, in step 102, each bypass determination item in the bypass determination item set is executed according to the running status information, including: determining whether there is an idle listening transaction entry that can be allocated to the listening transaction based on the entry occupancy status of the listening transaction tracker; comparing the transaction information of the listening transaction with the transaction information of each in-transit request transaction in the request transaction tracker to determine whether there is a sequence hazard between the listening transaction and any of the in-transit request transactions; determining whether the message channel has available message credit based on the message credit status of the message channel corresponding to the listening transaction; if there is an idle listening transaction entry, no sequence hazard, and the message channel has available message credit, determining that the determination results of each item satisfy the corresponding bypass conditions.

[0089] Specifically, the transaction tracker can set up transaction tracking entries for multiple in-transit transactions and indicate whether the corresponding entry is occupied through an entry validity bit or status field. The transaction entry management logic summarizes the occupancy status of each entry, outputs an entry availability indicator when at least one entry is in an idle state, and can also output the index of the entry to be allocated at the same time.

[0090] The message credit management unit maintains available message credit counts separately for message channels or virtual channels. For each successful transmission of a listening transaction that requires buffer space on the target channel, the corresponding message credit is deducted. Upon receiving credit returned from the target side, the corresponding message credit is added. The message credit determination item only meets the bypass condition when the available message credits of the message channel corresponding to the listening transaction are greater than zero.

[0091] Interconnect agent nodes can obtain idle listener transaction entries, sequence hazard judgment results, and message credit status in parallel within the same processing cycle, and then perform logical aggregation on the three results. If any condition is not met, the listener transaction is transferred to the standard pipeline. If all three conditions are met, it is identified as a listener bypass candidate transaction to shorten the waiting time from receiving the listener transaction from the on-chip network interface to issuing the listener transaction through the inter-chip interconnect interface.

[0092] Further optionally, the step of comparing the transaction information of the listening transaction with the transaction information of each in-transit request transaction in the request transaction tracker to determine whether there is a sequence hazard between the listening transaction and any of the in-transit request transactions in terms of completion confirmation and listening transaction includes: Based on the transaction status in the request transaction tracker, a target in-transit request transaction in the waiting-for-completion confirmation state is determined from each of the in-transit request transactions; the target address corresponding to the listening transaction is compared with the transaction address corresponding to the target in-transit request transaction; if the target address and the transaction address of any target in-transit request transaction satisfy a preset address matching relationship, and the early sending of the listening transaction would change the processing order between the completion confirmation of the target in-transit request transaction and the listening transaction, it is determined that the order hazard exists; if there is no target in-transit request transaction that satisfies the preset address matching relationship, or the early sending of the listening transaction would not change the processing order, it is determined that the order hazard does not exist.

[0093] Specifically, the transaction status in the request transaction tracker can indicate whether the corresponding in-transit request transaction has received a completion response, whether a completion acknowledgment needs to be sent, and whether the completion acknowledgment has been sent. The interconnected agent node first filters transactions that have not yet sent completion acknowledgments from each valid request transaction tracker entry, and then compares the target address of the listening transaction with the transaction address of the filtered transactions.

[0094] The default address matching relationship can be that both points to the same cache line, or it can be other address associations determined by the adopted consistency protocol. If the addresses do not match, the listening transaction usually will not affect the completion confirmation order of the target in-transit request transaction. If the addresses match, the current state of the target in-transit request transaction, the type of the listening transaction, and the order requirements specified by the protocol are further considered to determine whether sending the listening transaction early will skip the completion confirmation that should be processed first.

[0095] When any in-transit request simultaneously satisfies both the address association condition and the order conflict condition, an order hazard hit result is output, preventing the listening transaction from bypassing. Only when there are no such in-transit requests is an order hazard elimination result output. This ensures that bypassed listening transactions still follow the protocol order between completion confirmation and listening transactions.

[0096] Figure 3 This is a schematic diagram of a request transaction bypass processing flow provided in an embodiment of this application. (Refer to...) Figure 3 After receiving the pending request transaction R, the interconnected agent node can execute the transaction dependency judgment item A1, the scheduling status judgment item A2, and the read return resource judgment item A3 in parallel within the same processing cycle, and obtain the corresponding judgment results for each item.

[0097] exist Figure 3 In the process, transaction dependency determination item A1 is used to determine whether there is a preset transaction dependency between the requesting transaction R and the in-transit transactions in the interconnection agent node that prohibits the early sending of the requesting transaction R. The interconnection agent node performs parallel comparisons of the transaction information of the requesting transaction R with each valid transaction tracking entry in the requesting transaction tracker and the listening transaction tracker, and checks the transaction hazards between the listening transaction and the write-back transaction, the transaction dependencies corresponding to non-mergeable access of device type, the transaction dependencies corresponding to non-mergeable access of non-device type, and the transaction dependencies corresponding to ordered write observations.

[0098] exist Figure 3 In the process, if any valid transaction tracking entry matches any type of preset transaction dependency, it is determined that transaction dependency determination item A1 does not meet the bypass condition. If none of the valid transaction tracking entries match any type of preset transaction dependency, it is determined that there is no preset transaction dependency between the requesting transaction R and any in-transit transactions, and transaction dependency determination item A1 meets the bypass condition.

[0099] In one circuit implementation, comparison logic can be set for each valid transaction trace entry to generate corresponding dependency hit signals in parallel. Then, reduction or processing is performed on each dependency hit signal. When the reduction result indicates that at least one dependency hit signal is valid, A1 is set to the first logic value. When all dependency hit signals are invalid, A1 is set to the second logic value. For example, A1=0 can be used to indicate that the bypass condition is not met, and A1=1 can be used to indicate that the bypass condition is met. The above logic values ​​are for illustrative purposes only and do not constitute a limitation on the signal encoding method.

[0100] exist Figure 3 In the process, scheduling status determination item A2 is used to determine whether sending the request transaction R early will change the scheduling relationship with the pending transactions in the standard pipeline. The interconnect agent node obtains the pending transactions and their scheduling priorities in the standard pipeline from the scheduling and distribution unit. When there are no pending transactions in the standard pipeline, scheduling status determination item A2 is determined to meet the bypass condition.

[0101] When there are transactions in the pending-send state in the standard pipeline, the scheduling priority of the requesting transaction R is compared with the scheduling priority of each pending-send transaction. If there is a pending-send transaction with a higher scheduling priority than the requesting transaction R, the requesting transaction R is not allowed to bypass and send before that pending-send transaction, and A2 is determined not to meet the bypass condition. If there is no pending-send transaction with a higher scheduling priority than the requesting transaction R, then A2 is determined to meet the bypass condition. This judgment prevents low-priority requesting transactions from using bypass paths to preemptively occupy the sending interface and delay high-priority transactions.

[0102] For request transactions R and pending transactions with the same scheduling priority, their sending order can be determined based on arrival order, partition affiliation, polling status, or preset quality of service rules. This same-priority processing rule can be uniformly executed by the scheduling and distribution unit.

[0103] The read return resource determination item A3 is used to determine whether a request transaction R with read return semantics has the read data buffer conditions required to receive the returned data. Request transactions with read return semantics can include read request transactions as well as atomic operation transactions such as atomic loads, atomic comparisons, and atomic swaps.

[0104] When a requesting transaction R has read-return semantics, the read data buffer management unit checks whether there is an idle read data buffer (RDB) entry and arbitrates resource allocation for requesting transactions that request RDB within the same processing cycle. Only when an idle RDB entry exists and the requesting transaction R obtains exclusive allocation authorization for the current processing cycle is A3 determined to meet the bypass condition.

[0105] In one optional embodiment, exclusive allocation authorization employs one-hot encoding. At most one requesting transaction is granted an exclusive allocation authorization to the same RDB or the same RDB partition within the same processing cycle. When multiple requesting transactions with read-return semantics compete for the same RDB resource within the same processing cycle, the read data buffer management unit selects one requesting transaction according to a preset resource allocation rule and grants it an exclusive allocation authorization. Other requesting transactions that do not obtain an exclusive allocation authorization do not pass the A3 decision and can either wait for the next processing cycle to participate in the decision again or be transferred to standard pipeline processing.

[0106] When a requesting transaction R does not have read-return semantics, there is no need to pre-allocate an RDB for receiving the returned data. Therefore, A3 corresponding to this requesting transaction can be directly set to satisfy the bypass condition, so that the requesting transaction without read-return semantics can mainly determine whether it can become a bypass candidate transaction based on A1 and A2.

[0107] Transaction dependency determination item A1, scheduling status determination item A2, and read return resource determination item A3 can be executed in parallel by the bypass eligibility determiner within the same processing cycle. The bypass eligibility determiner summarizes the determination results of the three items to determine the bypass determination result Bypass_Req.

[0108] In one optional embodiment, the request bypass determination result can be expressed as: Bypass_Req=A1∧A2∧A3. Where A1 represents the determination result of the transaction dependency determination item, A2 represents the determination result of the scheduling status determination item, A3 represents the determination result of the read return resource determination item, and ∧ represents a logical AND relation. This expression indicates that the requesting transaction R is eligible for bypassing only when all three determination results satisfy the corresponding bypass conditions, without limiting the specific signal names and encoding forms of each determination result.

[0109] When A1, A2, and A3 all meet their respective bypass conditions, the interconnecting agent node designates request transaction R as a request bypass candidate transaction. This request bypass candidate transaction continues to undergo unified scheduling arbitration with pending transactions in the standard pipeline, rather than independently occupying the request sending interface immediately after forming Bypass_Req. After the request bypass candidate transaction obtains sending authorization, the interconnecting agent node verifies the bypass eligibility of request transaction R at the time of sending commit based on the updated transaction dependency state, scheduling state, and RDB resource state.

[0110] If the request transaction R still satisfies the bypass conditions corresponding to A1, A2, and A3 at the time of sending and committing, the interconnected proxy node performs a bypass send and commit for the request transaction R, so that the request transaction R bypasses at least one pipeline stage in the standard pipeline, such as queuing, repeated hazard checks, resource allocation, or scheduling wait, and is sent through the target interface of the request path.

[0111] For a request transaction R with read-return semantics, the interconnecting agent node locks and allocates the corresponding RDB entry according to the exclusive allocation authorization, and establishes or updates a bypass transaction tracking entry in the request transaction tracker to track the request transaction. The bypass transaction tracking entry can record at least one of the following: transaction identifier, target node identifier, address, RDB entry index, sending status, and response receiving status.

[0112] The allocation of RDB entries, the creation or updating of bypass transaction tracking entries, and the valid sending of request transaction R can be associated with the same bypass send commit. After request transaction R is accepted by the target interface, the bypass transaction tracking entry is updated to either sent or awaiting response status. When the interconnect agent node receives the completion response Comp or the completion response CompData carrying return data corresponding to request transaction R, it queries the bypass transaction tracking entry based on the transaction identifier carried in the response and uses the RDB entry index recorded therein to receive or read the corresponding return data. After completing the expected response processing, the corresponding RDB entries and transaction tracking resources are released.

[0113] For request transactions that do not have read-return semantics, bypass transaction trace entries required for subsequent transaction management can still be created or updated in the request transaction tracer, but without allocating RDB. These bypass transaction trace entries can use fewer fields than standard pipelined transaction trace entries, retaining only the necessary information for transaction response matching, sending status records, and related resource release. Minimization here means omitting intermediate pipeline states unnecessary for bypass processing, not that transaction trace entries must have a fixed number or type of fields.

[0114] If the decision result of any of the items A1, A2, and A3 does not meet the corresponding bypass condition, the requesting transaction R is not determined as a request bypass candidate transaction and is transferred to the Full Pipeline (FPL) for normal processing. The FPL can sequentially perform transaction queuing, hazard or dependency checks, transaction processing resource allocation, scheduling arbitration, and transaction sending on the requesting transaction R. Figure 3 The sequence from Q to Hazard to Alloc and finally to Sched is used to illustrate the pipeline stages mentioned above. The specific number and arrangement of pipeline stages in FPL can be determined based on the hardware structure of the interconnected agent nodes.

[0115] If a requesting transaction R has been identified as a candidate for bypassing but has not obtained send authorization in the unified scheduling arbitration, it can retain its bypass candidate status and re-participate in arbitration in a subsequent processing cycle. Alternatively, it can be transferred to FPL based on the waiting period, resource status, or scheduling policy. If a requesting transaction R obtains send authorization but fails to pass the bypass qualification review at the send commit time, its bypass send commit is canceled and it is transferred to FPL.

[0116] In one optional implementation, the interconnecting agent node is further equipped with a rollback and re-inject controller (RRC). After the requesting transaction R is granted a send authorization but before it is acknowledged and accepted by the target interface, the RRC can continue to monitor the running status information of the requesting transaction R. When a late transaction dependency occurs, the reserved resources fail, or other state changes cause the requesting transaction R to no longer meet the bypass conditions, the RRC cancels the bypass valid send indication for the requesting transaction R, releases or returns the RDB and transaction tracking resources reserved for the requesting transaction, and then re-injects the requesting transaction R into the FPL.

[0117] Resource release and re-injection are performed in the order of releasing resources first and then re-injecting them, to avoid bypass paths and FPL simultaneously recording the same request transaction or occupying the same transaction processing resources. After re-injecting the FPL, the request transaction R re-executes dependency checks, resource allocation, and scheduling processing according to the standard pipeline transaction order.

[0118] The above rollback process applies to interface implementations where there is a revocable phase between the sending authorization and the target interface's acceptance confirmation. If the target interface has already accepted the request transaction R, local rollback will not be performed via RRC; instead, the request transaction and its response processing will continue to be completed according to the corresponding consistency protocol. Figure 3 The rewind path between RRC and FPL in the abnormal rollback is used to represent the resource release and re-injection relationship within the revocable phase.

[0119] In this embodiment, interconnected proxy nodes perform three types of judgments in parallel within the same processing cycle: transaction dependency, scheduling priority, and read return resources. Only request transactions that do not have preset transaction dependencies, do not affect the sending of high-priority transactions, and already have the necessary data return buffer conditions are identified as bypass candidate transactions. Therefore, eligible request transactions can skip at least some pipeline stages in the FPL, while maintaining the correctness of transaction order, resource status, and subsequent response processing through unified scheduling arbitration, on-commit verification, necessary transaction tracking, and anomaly rollback.

[0120] Figure 4 This is a schematic diagram of a bypass processing flow for eavesdropping transactions, provided as an embodiment of this application. (Refer to...) Figure 4 After receiving the listening transaction S to be processed through the on-chip network interface, the interconnected agent node can execute the listening transaction entry judgment item B1, the sequence hazard judgment item B2, and the message credit judgment item B3 in parallel within the same processing cycle, and obtain the corresponding judgment results.

[0121] The Listening Transaction Entry Decision Item B1 is used to determine whether there is a free Listening Transaction Entry in the Listening Transaction Tracker that can be allocated to Listening Transaction S. The Listening Transaction Tracker can set up separate Listening Transaction Entries for each in-transit Listening Transaction, and indicate whether the corresponding entry is occupied through the entry validity bit or the transaction status field. Listening Transaction Entries are used to record the transaction attributes, send status, response status, and hazard states between the Listening Transaction and other consistent transactions.

[0122] Figure 4 In this system, the listening transaction entry management logic reads the occupancy status of each listening transaction entry to determine if there are any idle listening transaction entries, and can simultaneously generate an index for entries to be allocated. When at least one idle listening transaction entry exists, it is determined that B1 meets the corresponding bypass condition. When all listening transaction entries are occupied, it is determined that B1 does not meet the corresponding bypass condition. In one circuit implementation, B1=1 can be used to indicate the existence of an idle listening transaction entry, and B1=0 can be used to indicate the absence of an idle listening transaction entry. The above logical values ​​are for illustrative purposes only and do not constitute a limitation on the signal encoding method for the project determination result.

[0123] Sequence Hazard Detection Item B2 is used to determine whether there is a sequence hazard between the listening transaction S and the in-transit request transaction, where the completion acknowledgment is pending. The transaction status in the request transaction tracker indicates whether the corresponding in-transit request transaction is waiting to send a completion acknowledgment (CompAck). The interconnecting agent node first filters the target in-transit request transactions that are waiting for completion acknowledgment from among the in-transit request transactions based on the valid status and transaction status of each request transaction tracker entry, and then compares the target address of the listening transaction S with the transaction address of the target in-transit request transaction.

[0124] For example, the cache line addresses of the listening transaction S and the target in-transit request transaction can be extracted separately, and it can be determined whether they point to the same cache line. The cache line address can be obtained by removing the offset bits within the cache line from the transaction address; the specific number of offset bits can be determined based on the cache line size. If the two do not satisfy the preset address matching relationship, the target in-transit request transaction will generally not form a corresponding ordering hazard with the listening transaction S.

[0125] If the listening transaction S and the target in-transit request transaction satisfy a preset address matching relationship, then further, based on the current state of the target in-transit request transaction, the type of the listening transaction, and the order requirements stipulated in the protocol, it is determined whether sending the listening transaction S early will change the processing order between CompAck and the listening transaction. If sending the listening transaction S early would skip the CompAck that should be processed first, then a CompAck-Snoop order hazard is determined to exist. If the above situation does not exist, then the order hazard is determined to have been eliminated.

[0126] When any in-transit request transaction and the listening transaction S form a CompAck-Snoop sequence hazard, it is determined that B2 does not satisfy the corresponding bypass condition. When there is no in-transit request transaction forming the sequence hazard, it is determined that B2 satisfies the corresponding bypass condition. For example, B2=1 can be used to indicate that the sequence hazard has been eliminated, and B2=0 can be used to indicate that the sequence hazard still exists.

[0127] Message credit determination item B3 is used to determine whether the target message channel corresponding to the listening transaction S has available message credit MsgCrd. Message credit is used to indicate the number of transactions that the target-side message channel can currently receive or the number of available receive buffers. The message credit management unit can maintain corresponding available message credit counts according to message channel, virtual channel, or message type.

[0128] The interconnected proxy node determines the corresponding target message channel based on the target information and message type carried by the listening transaction S, and reads the available message credit count of that target message channel. When the available message credit count is greater than zero, it indicates that the target side has buffer capacity available to receive the listening transaction S, and it is determined that B3 meets the corresponding bypass condition. When the available message credit count is zero, it is determined that B3 does not meet the corresponding bypass condition.

[0129] After a listening transaction S successfully secures a transmission opportunity on the target message channel, the message credit management unit deducts the corresponding available message credit; upon receiving message credit returned from the target side, it adds the corresponding available message credit. By checking message credit before sending a listening transaction, it is possible to avoid sending transactions to a target message channel with insufficient receiving capacity.

[0130] B1, B2, and B3 can be calculated in parallel within the same processing cycle by a bypass eligibility determiner located in the listening processing unit. The bypass eligibility determiner summarizes the determination results of the three items to determine the listening bypass determination result Bypass_Snp. For example, the listening bypass determination result can be expressed as: Bypass_Snp = B1∧B2∧B3; where B1 represents the determination result of the listening transaction entry, B2 represents the determination result of the sequence hazard determination, B3 represents the determination result of the message credit determination, and ∧ represents a logical AND relation. The above expression is only used to illustrate the combination relationship between the three item determination results and does not limit the name, bit width, or specific encoding method of the corresponding signal.

[0131] When B1, B2, and B3 all meet their respective bypass conditions, the interconnected agent node identifies the listening transaction S as a listening bypass candidate transaction. This listening bypass candidate transaction participates in unified scheduling arbitration along with the pending transactions in the standard pipeline, and after obtaining transmission authorization, its bypass eligibility is verified at the transmission submission time based on the updated runtime status information.

[0132] During the review, the interconnected broker node re-determines whether the idle listening transaction entry still exists, whether the CompAck-Snoop sequence hazard is still cleared, and whether the target message channel still has available message credit. If the above conditions are still met at the send commit time, a bypass send commit is performed on the listening transaction S.

[0133] When performing a bypass send submission, the interconnect agent node occupies the corresponding listening transaction entry according to the idle entry index, and records at least one of the transaction identifier, target address, target chip node identifier, sending status, and response status of the listening transaction S; the message credit management unit deducts the available message credit of the target message channel corresponding to the listening transaction S; the listening processing unit sends the listening transaction S to the C2C side through the chip interconnect interface, so that the listening transaction bypasses at least part of the pipeline stage in the standard pipeline.

[0134] The occupancy of a listener transaction entry, the deduction of message credit, and the valid transmission of a listener transaction S can be associated with the same bypass commit. In one hardware implementation, these actions are controlled by the same commit validity signal and the status confirmation is completed within the same processing cycle. The occupancy of the corresponding listener transaction entry and the deduction of message credit are only confirmed when the inter-chip interconnect interface accepts a listener transaction S; if the inter-chip interconnect interface does not accept a listener transaction S, the above resource status update is not confirmed, or the reserved resources are restored to their pre-commit state.

[0135] By associating message credit deduction with the effective sending of a listening transaction, we can avoid prematurely consuming message credit before the transaction is accepted by the interface, and also avoid over-sending caused by the transaction being accepted but message credit not being deducted. By associating the occupancy of a listening transaction entry with effective sending, we can ensure that each sent bypass listening transaction has a corresponding tracking entry.

[0136] If the decision result of any of B1, B2, and B3 does not meet the corresponding bypass condition, the listening transaction S is not identified as a listening bypass candidate transaction, but is instead transferred to the full pipeline FPL for normal processing. The FPL can sequentially perform transaction queuing, hazard checking, transaction processing resource allocation, scheduling arbitration, and transaction sending on the listening transaction S. Figure 4 The sequence from Q to Hazard to Alloc and finally to Sched is used to illustrate the pipeline stages mentioned above. The specific pipeline stages and their order can be determined based on the hardware structure of the interconnected agent nodes.

[0137] If a listening transaction S has been identified as a candidate for listening bypass but has not obtained a transmission authorization in the unified scheduling arbitration, it can be allowed to re-participate in the arbitration in a subsequent processing cycle, or it can be transferred to FPL based on its waiting status. If a listening transaction S obtains a transmission authorization, but B1, B2, or B3 no longer meets the corresponding bypass conditions at the time of transmission submission, then it is prohibited from occupying the listening transaction entry, deducting message credits, and sending listening transaction S through the chip interconnect interface, and it is transferred to FPL.

[0138] In one alternative implementation, the interconnect agent node is further provided with a rollback and re-injection controller (RRC). After the listening transaction S is authorized to send and before it is acknowledged and accepted by the inter-chip interconnect interface, the RRC continues to monitor the operational status information related to the listening transaction S to form a revocable bypass processing phase.

[0139] During this phase, RRC can monitor whether the CompAck-Snoop sequence hazard changes from an eliminated state to a hit state, whether reserved message credits become invalid, and whether listener transaction entries are still available for the current listener transaction. If a new arrival or en route request transaction's state change causes a new address and order conflict between the listener transaction S and a request transaction waiting for completion confirmation, then a sequence hazard state change is determined to have occurred.

[0140] When RRC detects a bypass eligibility failure before accepting listener transaction S at the inter-chip interconnect interface, it cancels the bypass valid transmission indication for listener transaction S, releases the reserved listener transaction entry, and returns the reserved or pre-deducted message credits. After confirming that the relevant resources have been restored, listener transaction S is re-injected into the FPL entry point, causing it to re-execute hazard checks, resource allocation, and scheduling processing in the standard pipeline sequence.

[0141] Resource return and transaction re-injection are performed in the order of resource return first, followed by re-injection. This order avoids listening transactions from simultaneously occupying transaction tracking resources in the bypass path and FPL, and reduces the risk of message credits being repeatedly occupied or missed.

[0142] The aforementioned local cancellation applies only if the inter-chip interconnect interface has not yet acknowledged acceptance of the listening transaction S. If the inter-chip interconnect interface has already accepted the listening transaction S, local cancellation is not performed; instead, the listening transaction and its response continue to be processed according to the corresponding consistency protocol. In implementations where the protocol supports retries, the corresponding retry processing can also be performed according to the protocol specifications.

[0143] In this embodiment, interconnected proxy nodes check the listener transaction entries, CompAck-Snoop sequence hazards, and message credit of the target message channel in parallel within the same processing cycle. Only when all three conditions are met is a listener bypass candidate transaction formed, and bypass transmission is completed through unified scheduling, on-commit verification, and associated resource commit. This shortens the processing path of NoC-side listener transactions forwarded to the C2C side via interconnected proxy nodes, while maintaining the correctness of listener transaction tracking, confirmation order, and message credit flow control.

[0144] Step 103: If all the project judgment results meet the corresponding bypass conditions, the pending consistency transaction is taken as a bypass candidate transaction, and the bypass candidate transaction and the pending transaction in the standard pipeline are uniformly scheduled and arbitrated to determine the sending authorization of the bypass candidate transaction.

[0145] Specifically, bypass candidate transactions do not directly bypass the scheduling and distribution unit to occupy the sending interface. Instead, they are used as input for unified scheduling arbitration along with the transactions to be sent in the standard pipeline. Unified scheduling arbitration can first compare the scheduling priorities of each transaction, and then select transactions with the same scheduling priority based on the transaction arrival order, the partition to which they belong, or the polling status.

[0146] If a transaction with a higher scheduling priority than a bypass candidate transaction exists in the standard pipeline, then the transaction with the higher scheduling priority is granted a send authorization, and the bypass candidate transaction is prevented from sending in the current processing cycle. If the bypass candidate transaction has a higher scheduling priority, or if there is no transaction in the standard pipeline that can participate in the current send, then the bypass candidate transaction can be granted a send authorization.

[0147] When multiple bypass candidate transactions exist within the same processing cycle, transactions can be selected in descending order of scheduling priority. Round-robin arbitration is then performed on bypass candidate transactions with the same scheduling priority to generate an exclusive authorization signal indicating the authorized transaction. By including bypass paths and standard pipeline paths in the same arbitration domain, the established quality of service and transaction scheduling relationships can be maintained while achieving the benefits of bypass latency.

[0148] Step 104: In response to the sending authorization, at the time of sending and submitting the bypass candidate transaction, the bypass qualification of the bypass candidate transaction is reviewed according to the updated running status information.

[0149] Specifically, one or more processing cycles may occur between the initial determination of a project and the granting of a send authorization to a bypass candidate transaction. During this period, the transaction status in the requesting transaction tracker or listening transaction tracker, the pending send status of the standard pipeline, the occupancy status of read data buffer resources, the occupancy status of listening transaction entries, or the number of message credits may change. Therefore, the initial bypass determination result is only used to form bypass candidate transactions, and the interconnected broker node needs to review it based on the latest status before actually sending and committing.

[0150] For requesting bypass candidate transactions, the review can include whether new pre-defined transaction dependencies have emerged, whether transactions with higher scheduling priority are pending, and whether the already acquired read data buffer resource allocation eligibility remains valid. For listening bypass candidate transactions, the review can include whether idle listening transaction entries are still available for allocation, whether the ordering hazard between completion acknowledgments and listening transactions is still eliminated, and whether the target message channel still has available message credits.

[0151] If all conditions required for review are still met, the bypass qualification remains valid and step 105 is allowed. If any condition has changed and the bypass condition is no longer met, the current transmission authorization is revoked or the bypass transmission submission is blocked, and step 106 is executed. The review upon submission ensures that bypass transmission is based on the actual operational state at the time of transmission, rather than relying on an expired state snapshot.

[0152] Step 105: After the bypass qualification review is passed, the bypass candidate transaction is sent and committed according to the sending authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass sending and commit, so that the bypass candidate transaction bypasses at least part of the pipeline stages in the standard pipeline.

[0153] Specifically, bypass send submission indicates that the bypass candidate transaction is delivered to the corresponding send interface, and the required tracking information and transaction processing resource occupancy are simultaneously confirmed. Request bypass candidate transactions can be received from the chip interconnect interface side and sent to the on-chip network interface side via the request processing unit; listen bypass candidate transactions can be received from the on-chip network interface side and sent to the chip interconnect interface side via the listen processing unit.

[0154] A bypass path can skip at least one pipeline stage in a standard pipeline, including queuing, duplicate transaction registration, dependency checking, resource allocation, or scheduling waits, while still retaining the trace information and resource status necessary to complete the subsequent response processing of the transaction. The specific pipeline stages skipped can be determined based on the pipeline structure of the interconnected agent nodes.

[0155] The updates to transaction tracking status and resource status are correlated with the effective sending of bypass transactions. If the sending interface does not accept the transaction, the corresponding resource is not permanently confirmed as occupied; if the transaction is accepted by the sending interface, it is recorded that the transaction has been sent, and the tracking relationship required for subsequent receipt of completion response, data response, or listen response is retained to avoid duplicate transaction sending, duplicate resource allocation, or mismatched responses.

[0156] As an optional embodiment, it is assumed that the bypass candidate transaction is a request transaction with read-return semantics. Specifically, a request transaction with read-return semantics needs to receive a corresponding completion response or data response after being sent. In order for such requests to bypass the regular resource allocation phase in the standard pipeline, the interconnect agent node needs to determine the read data buffer resource and the request transaction tracking entry when submitting the bypass request, and establish the correspondence between the request transaction, the returned data, and the read data buffer resource.

[0157] Based on the above assumptions, in step 105, a bypass send commit is performed on the bypass candidate transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit. This includes: allocating the read data buffer resource to the requesting transaction according to the exclusive allocation authorization, and establishing or updating a bypass transaction tracking entry for tracking the requesting transaction in the requesting transaction tracker; associating the allocation of the read data buffer resource, the establishment or update of the bypass transaction tracking entry, and the sending of the requesting transaction with the same bypass send commit; updating the bypass transaction tracking entry according to the received completion response or data response of the requesting transaction, and releasing the read data buffer resource allocated to the requesting transaction.

[0158] Specifically, the read data buffer management unit locks the corresponding read data buffer table entry based on exclusive allocation authorization and provides its index to the request transaction tracker. The request transaction tracker establishes or updates the bypass transaction tracking table entry, recording at least one of the following: request transaction identifier, target node identifier, address information, read data buffer index, sending status, and response receiving status.

[0159] During the valid processing cycle of send-commit, the request transaction is sent via the on-chip network interface, simultaneously updating the read data buffer entry to the occupied state and updating the bypass transaction tracking entry to the sent or waiting-for-response state. These actions are controlled by the same bypass send-commit mechanism; if the request transaction is not successfully sent, an inconsistent state of resource allocation without transaction issuance will not simultaneously occur.

[0160] After a request transaction is sent, the interconnected agent node queries the bypass transaction tracking entry based on the transaction identifier carried in the completion response or data response, and writes the returned data to the corresponding read data buffer resource. Once the expected response is received, the bypass transaction tracking entry is updated to a completed state, and the read data buffer resource is released for reallocation by subsequent request transactions. This ensures that request transactions with read return semantics have a definite return data storage location before bypass transmission.

[0161] As an optional embodiment, it is assumed that the bypass candidate transaction is the listening transaction.

[0162] Specifically, the listening transaction bypass is used to shorten the processing path of listening transactions received on the on-chip network side, which is forwarded to the inter-chip interconnect interface side via the interconnect proxy node. After a listening transaction is sent, its sending status and subsequent response status still need to be recorded through the listening transaction table, and the receiving buffer capacity of the corresponding message channel is occupied according to the message credit flow control rules.

[0163] Based on the above assumptions, in step 105, a bypass send commit is performed on the bypass candidate transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit, including: in response to the same bypass send commit, the listening transaction occupies the idle listening transaction entry, deducts the message credit of the message channel corresponding to the listening transaction, and sends the listening transaction through the chip interconnect interface; if any one of the idle listening transaction entry, the sequence hazard, and the message credit does not meet the corresponding bypass condition at the time of the send commit, the occupation of the idle listening transaction entry is prohibited, the deduction of the message credit is prohibited, and the sending of the listening transaction is prohibited.

[0164] Specifically, the monitoring transaction entry management logic updates the corresponding entry to an occupied state based on the idle entry index, and records at least one of the following: transaction identifier, target address, target chip node identifier, sending status, and response status of the monitoring transaction. The message credit management unit determines the message channel to which the monitoring transaction belongs and deducts the available message credit count of that message channel when the monitoring transaction completes a valid transmission.

[0165] The occupancy of a listener's entry, the deduction of message credit, and the sending of the listener's transaction can all be controlled by the same commit confirmation signal, and status confirmation can be completed within the same processing cycle. Entry occupancy and message credit deduction are only confirmed when the inter-chip interconnect interface accepts the listener's transaction. If the interface does not accept the transaction, the corresponding resource status is maintained or restored to prevent message credit leakage.

[0166] At the time of commit, if an idle listener entry is already occupied by another transaction, a new completion acknowledgment and listener order hazard occurs, or the message credit is already occupied by another sending transaction, then all three commit actions are prohibited simultaneously, and the listener transaction is handed over to the standard pipeline for processing. This associated commit method can avoid the partial commit state formed by only updating part of the resource state without actually sending the listener transaction.

[0167] Step 106: If any of the project judgment results does not meet the corresponding bypass conditions, the bypass candidate transaction does not obtain the sending authorization, or the bypass qualification review fails, the pending consistency transaction is transferred to the standard pipeline for processing.

[0168] Specifically, a standard pipeline can include pipeline stages such as transaction queuing, transaction tracking entry allocation, transaction dependency or hazard checks, transaction processing resource allocation, scheduling arbitration, and transaction sending. When entering a standard pipeline, the consistent transactions to be processed and their transaction attributes are written to the standard pipeline's ingress buffer or transaction queue, and the standard pipeline completes subsequent processing in the usual order.

[0169] Transactions that fail the initial bypass determination can be directly sent to the standard pipeline entry point. Transactions that have become bypass candidate transactions but have not yet obtained send authorization can be retained until the next processing cycle to re-participate in unified scheduling arbitration, or they can be transferred to the standard pipeline according to preset waiting conditions. Transactions that fail the bypass qualification review during send submission will have their bypass candidate status canceled and will be transferred to the standard pipeline.

[0170] The reasons for bypass failures can be logged to the performance monitoring unit. For example, the number of times transaction dependency hits, insufficient scheduling priority, insufficient read data buffer resources, insufficient listening transaction entries, sequence hazard hits, insufficient message credit, and commit review failures can be counted separately to analyze the bypass hit rate and adjust bypass enabling strategies, priority strategies, or resource configurations.

[0171] As an optional embodiment, after the bypass candidate transaction obtains the send authorization and before it is accepted by the target interface, the system monitors whether the running status information corresponding to the bypass candidate transaction undergoes a state change that would invalidate the bypass qualification. If the state change is detected, the bypass send commit of the bypass candidate transaction is revoked, and the transaction processing resources allocated or reserved for the bypass candidate transaction are released or returned. After the transaction processing resources are released or returned, the bypass candidate transaction is re-injected into the standard pipeline for processing.

[0172] Specifically, this embodiment is applicable to interface implementations where there is a revocable phase between the sending authorization and the target interface's acceptance confirmation. The interconnect proxy node can be configured with rollback and re-injection control logic. After a bypass candidate transaction obtains sending authorization, it updates the transaction status to a pending commit or trial send state, and continuously monitors late-arriving transaction dependencies, message credit failures, and sequence hazard status changes before the target interface generates an acceptance indication.

[0173] Late transaction dependency can be a pre-defined transaction dependency formed between a transaction newly entering the interconnected agent node after the initial bypass determination and a bypass candidate transaction. Message credit failure can be caused by the original available message credit being occupied by a higher priority transaction, making the current transaction no longer able to send. Sequence hazard state change can be caused by a new in-transit transaction state that makes the previously eliminated sequence hazard between the completion confirmation and the listening transaction re-established.

[0174] If the aforementioned state change is detected before the target interface accepts the transaction, the rollback and re-injection control logic cancels the valid send instruction for the transaction and releases or returns the reserved read data buffer resources, listening transaction entries, or message credits according to the transaction type. After the resources are released or returned, a re-injection request is submitted to the standard pipeline entry point, carrying the transaction information of the original pending consistency transaction, so that the standard pipeline re-executes dependency checks, resource allocation, and scheduling in the normal manner.

[0175] Resource release and transaction re-injection are performed sequentially to prevent bypass paths and standard pipelines from simultaneously occupying the same resources or recording the same transaction. If the target interface has already confirmed acceptance of the bypass transaction, the aforementioned local rollback is not performed; instead, the transaction should continue to be completed according to the corresponding consistency protocol, or, if supported by the protocol, a protocol-level retry mechanism should be used. Therefore, the revocable phase is defined as the point at which the target interface has not yet confirmed acceptance of the transaction.

[0176] Figure 5 This is a timing comparison diagram of a bypass path and a standard pipeline provided in an embodiment of this application. (Refer to...) Figure 5 In the diagram, C0 to C6 represent the sequentially arriving processing cycles. The complete pipeline (FPL) and the bypass path (BXP) represent the processing stages that the same consistent transaction undergoes under different processing methods. The correspondence between processing cycles and processing stages shown in the diagram is only used to illustrate the timing differences between the two paths and does not constitute a limitation on the number of pipeline stages, fixed processing cycles, or the actual duration of each stage.

[0177] In the complete pipeline FPL, a consistent transaction can sequentially pass through the transaction reception phase, transaction tracking phase, hazard or dependency check phase, transaction processing resource allocation phase, scheduling arbitration phase, and transaction sending phase. The transaction processing latency of the complete pipeline can be expressed as: TFPL = Trecv + Ttrack + Thazard + Talloc + Tsched + Tsend. Where TFPL represents the processing latency required for a consistent transaction to pass through the complete pipeline; Trecv represents the processing latency required to receive and parse the consistent transaction; Ttrack represents the processing latency required to establish or update transaction track entries; Thazard represents the processing latency required to perform transaction dependency, sequence relation, or hazard checks; Talloc represents the processing latency required to allocate transaction track entries, data buffer resources, or message credit resources; Tsched represents the processing latency required to perform scheduling arbitration and determine the transaction to send; and Tsend represents the processing latency required to commit the transaction to the target interface.

[0178] Figure 5 Taking a complete pipeline that sequentially executes the above processing stages and completes transaction transmission in approximately six or more processing cycles as an example. In other implementations, one or more stages of transaction reception, transaction tracking, hazard checking, resource allocation, scheduling arbitration, and transaction transmission can be further split, merged, or executed in parallel. Therefore, the actual number of stages and transaction processing latency of the complete pipeline can be determined based on the circuit structure and operating frequency of the interconnected agent nodes.

[0179] In the Bypass Path (BXP), after receiving a pending consistency transaction, the interconnecting agent node selects the corresponding set of bypass decision items based on the transaction type and executes each bypass decision item in parallel according to the runtime state snapshot of the same processing cycle. When the pending consistency transaction is a request transaction, the bypass decision may include transaction dependency decision item A1, scheduling status decision item A2, and read return resource decision item A3. When the pending consistency transaction is a listening transaction, the bypass decision may include listening transaction entry decision item B1, sequence hazard decision item B2, and message credit decision item B3. For example, the transaction processing latency of the bypass path can be expressed as: TBXP = Trecv + Tbypass_decide + Tsend. Wherein, TBXP represents the processing latency required for the pending consistency transaction to pass through the bypass path. Tbypass_decide represents the processing latency required to execute each bypass decision item according to the runtime state information, summarize the decision results, and form bypass eligibility.

[0180] In one hardware implementation, the request transaction tracker, the listener transaction tracker, the scheduling and distribution unit, and each resource management unit output corresponding runtime status snapshots to the bypass eligibility determiner within the same processing cycle. The bypass eligibility determiner uses combinational logic to execute each bypass determination item in parallel, so that Tbypass_decide corresponds to one processing cycle.

[0181] Furthermore, some of the processing required for bypass determination can be performed in parallel with the transaction reception phase. For example, when receiving information such as the transaction type, address, scheduling priority, and storage attributes of a pending consistent transaction, the requesting transaction tracker and the listening transaction tracker can simultaneously output the transaction attributes and transaction status of each valid transaction tracking entry, and the resource management unit can simultaneously output the availability status of transaction processing resources. Once the transaction information required for bypass determination is formed, the bypass eligibility determiner completes the item determination based on the already obtained runtime state snapshot, thereby reducing the serial waiting between transaction reception and bypass determination.

[0182] When the results of each project meet the corresponding bypass conditions, the pending consistency transaction is identified as a bypass candidate transaction. After obtaining send authorization and passing the bypass eligibility review at the commit time, the bypass candidate transaction can bypass at least one stage in the complete pipeline, including transaction queuing, duplicate hazard or dependency checks, regular resource allocation, and scheduling wait, and directly enter the bypass send and commit stage.

[0183] It should be noted that bypass candidate transactions still participate in the unified scheduling and arbitration between themselves and standard pipeline transactions awaiting transmission, and their bypass eligibility is verified based on the updated runtime status information during actual transmission and submission. Therefore, Figure 5 The bypass path skipping the scheduling phase means that the transaction does not need to go through the regular scheduling pipeline stages and its preceding waiting processes in the complete pipeline. It does not mean that the bypass candidate transaction can directly occupy the sending interface without going through the unified scheduling arbitration.

[0184] For request transactions with read-return semantics, RDB availability determination and exclusive allocation authorization can be completed in the bypass determination and send-commit phase. Therefore, the request transaction does not need to go through the regular read data buffer resource allocation phase in the full pipeline. When the request transaction completes the bypass send-commit, the RDB allocation, bypass transaction tracking entry update, and valid send of the request transaction are interconnected.

[0185] For listener transactions, the determination of idle listener transaction entries, CompAck-Snoop sequence hazard checks, and message credit availability determination can be completed in parallel during the bypass decision phase. When a listener transaction completes bypass send commit, the listener transaction entry occupancy, message credit deduction, and valid send of the listener transaction are interrelated. Therefore, a listener transaction can skip at least one of the regular entry allocation, hazard checks, and message credit waiting phases in the full pipeline.

[0186] Figure 5 For example, a bypass path completes early transmission in approximately two processing cycles, reducing the pipeline by about four processing cycles compared to a full pipeline of approximately six or more processing cycles. This number of processing cycles is an example obtained under the condition that the bypass decision can be completed in a single cycle, the sending interface has the receiving conditions, and there is no additional waiting. The actual number of processing cycles saved can also be affected by factors such as transaction type, unified scheduling arbitration result, target interface backpressure state, resource availability, pipeline stage number, and operating frequency.

[0187] For listening transactions received by the NoC side and needing to be sent to the C2C side, reducing the processing latency within the interconnect proxy node can correspondingly reduce the time it takes for the listening transaction to reach the target chip node and shorten the completion time of consistency transactions that depend on the response of the listening transaction. For request transactions received by the C2C side and sent to the NoC side, using a bypass path can reduce the queuing and processing waiting time of requests without actual transaction dependencies within the interconnect proxy node.

[0188] Through the aforementioned timing relationships, interconnected proxy nodes enable consistent transactions that meet the bypass conditions to bypass at least some pipeline stages in the standard pipeline, reducing the processing cycle between transaction reception and transmission; at the same time, they retain unified scheduling arbitration, bypass qualification verification at commit time, and transaction tracking status and resource status updates to maintain the correctness of transaction order, scheduling relationships, and resource usage status.

[0189] In this embodiment, transactions eligible for bypassing can be dynamically determined based on the transaction type and real-time running status of consistent transactions. By performing unified scheduling arbitration with transactions to be sent in the standard pipeline and verifying bypass eligibility at the time of sending and committing, bypassing can prevent transactions from disrupting the order of transactions, scheduling relationships, or resource usage status. This allows consistent transactions that meet the bypass conditions to bypass at least some pipeline stages in the standard pipeline, thereby shortening the processing latency of consistent transactions, reducing the time occupied by transaction tracking resources and pipeline resources, and improving the efficiency and effective throughput of consistent transaction processing in the inter-chip interconnect system.

[0190] In some embodiments, after receiving a consistent transaction, the interconnected agent node first identifies the transaction as a request transaction or a listening transaction, and obtains a snapshot of the running status of the same processing cycle from the request transaction tracker, the listening transaction tracker, the scheduling and distribution unit, and the resource management unit.

[0191] When a consistency transaction is a request transaction, the interconnect agent node compares the request transaction with each valid transaction trace entry to determine if there are transaction hazards between listening transactions and write-back transactions, non-mergeable access dependencies of device types, non-mergeable access dependencies of non-device types, or ordered write observation dependencies. Simultaneously, it checks if there are any higher-priority pending transactions in the standard pipeline. If the request transaction has read-return semantics, it also performs availability checks and exclusive allocation arbitration on read data buffer resources. After all items pass, the request transaction is designated as a bypass candidate transaction.

[0192] When a consistency transaction is a listening transaction, the interconnecting agent node checks if there are any idle entries in the listening transaction tracker, compares the address and order of the listening transaction with the in-transit request transactions waiting for completion confirmation, and checks the available message credits of the target message channel. If all three criteria are met, the listening transaction is designated as a bypass candidate transaction.

[0193] Bypass candidate transactions and pending transactions in the standard pipeline participate in unified scheduling and arbitration. After a bypass candidate transaction is granted send authorization, the interconnected agent node verifies its bypass eligibility based on the latest operational status at the send commit time. If the verification passes, the requesting transaction's read data buffer allocation, bypass transaction tracking entry update, and request send are interconnected; the listening transaction's listening transaction entry occupancy, message credit deduction, and listening transaction send are interconnected. If the verification fails or the transaction is not granted send authorization, the transaction is transferred to the standard pipeline for processing.

[0194] Through the above process, the interconnected proxy node only allows transactions that currently have no transaction dependencies or sequence hazards, whose scheduling relationships allow for early sending, and whose required transaction processing resources are ready to enter the bypass path, and verifies the status using the updated state before actual sending and commit. Therefore, it can reduce the pipeline stages and waiting periods traversed by conflict-free transactions, while maintaining the correctness of transaction order, scheduling priority, return data reception capacity, and message channel flow control status.

[0195] The above describes a consistent transaction pipeline bypass method in an inter-chip interconnect system according to an embodiment of this application. The following describes the consistent transaction pipeline bypass device in an inter-chip interconnect system that performs the above-described consistent transaction pipeline bypass method in an inter-chip interconnect system.

[0196] See Figure 6 ,like Figure 6 The diagram illustrates the structure of a consistent transaction pipeline bypass device in an inter-chip interconnect system. The consistent transaction pipeline bypass device in the inter-chip interconnect system of this application embodiment can achieve the above-described... Figure 1The steps of the consistent transaction pipeline bypass method in the inter-chip interconnect system executed in the corresponding embodiment are described. The function of the consistent transaction pipeline bypass device in the inter-chip interconnect system can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions, and the modules can be software and / or hardware. The consistent transaction pipeline bypass device in the inter-chip interconnect system may include an input / output module 601 and a processing module 602. The functional implementation of the processing module 602 and the input / output module 601 can be referred to Figure 1 The operations performed in the corresponding embodiments will not be described in detail here.

[0197] The input / output module 601 is configured to acquire the consistency transaction to be processed and the running status information related to the consistency transaction in the interconnected proxy node. The processing module 602 is configured to determine a corresponding set of bypass decision items based on the transaction type of the consistency transaction to be processed, and execute each bypass decision item in the set of bypass decision items according to the running status information to obtain the corresponding item decision result; if all item decision results meet the corresponding bypass conditions, the consistency transaction to be processed is taken as a bypass candidate transaction, and the bypass candidate transaction is uniformly scheduled and arbitrated with the transaction to be sent in the standard pipeline to determine the sending authorization of the bypass candidate transaction; in response to the sending authorization, when the sending of the bypass candidate transaction is submitted. At any given moment, the bypass eligibility of the candidate bypass transaction is reviewed based on the updated runtime status information; after the bypass eligibility review is passed, a bypass send commit is performed on the candidate bypass transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit, so that the candidate bypass transaction bypasses at least some pipeline stages in the standard pipeline; if any of the project judgment results does not meet the corresponding bypass conditions, the candidate bypass transaction does not obtain the send authorization, or the bypass eligibility review fails, the pending consistency transaction is transferred to the standard pipeline for processing; The input / output module 601 is further configured to output the bypass candidate transaction through the on-chip network interface or the inter-chip interconnect interface according to the bypass send submission executed by the processing module.

[0198] In some implementations, the input / output module 601 acquires the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node, specifically configured as follows: The system obtains the transaction attributes and transaction status of transactions in transit from the request transaction tracker and the listener transaction tracker, obtains the transactions to be sent in the standard pipeline and their scheduling status from the scheduling and distribution unit, and obtains the resource availability status from the resource management unit corresponding to the transaction processing resource. The transaction attributes, transaction status, scheduling status, and resource availability status are taken as state snapshots corresponding to the same processing cycle. Based on the state snapshot, each of the bypass decision items is executed in parallel, and the decision results of each item are summarized to determine whether the pending consistency transaction meets the corresponding bypass condition.

[0199] In some implementations, if the pending consistency transaction is a request transaction, the bypass decision item set includes transaction dependency decision items, scheduling status decision items, and read return resource decision items.

[0200] The processing module 602 executes each bypass decision item in the bypass decision item set according to the running status information to obtain the corresponding item decision result, specifically configured as follows: The transaction information of the requested transaction is compared with each valid transaction tracking entry in the requested transaction tracker and the listening transaction tracker to determine whether the requested transaction has a preset transaction dependency with any in-transit transaction. Based on the scheduling information of the requested transaction and the scheduling status of the transactions to be sent in the standard pipeline, determine whether the requested transaction meets the conditions for early sending. If the requested transaction has read return semantics, determine whether read data buffer resources can be allocated to the requested transaction based on the availability and allocation status of the read data buffer resources; Based on the results of the transaction dependency determination items, the scheduling status determination items, and the read return resource determination items, it is determined whether the request transaction meets the corresponding bypass conditions.

[0201] In some implementations, the preset transaction dependencies include transaction hazards between listening transactions and write-back transactions, transaction dependencies corresponding to non-mergeable access of device types, transaction dependencies corresponding to non-mergeable access of non-device types, and transaction dependencies corresponding to ordered write observations.

[0202] The processing module 602 compares the transaction information of the requested transaction with each valid transaction tracking entry in the requested transaction tracker and the listening transaction tracker to determine whether the requested transaction has a preset transaction dependency with any in-transit transaction. Specifically, it is configured as follows: From the transaction information of the requested transaction and each of the valid transaction tracking entries, obtain comparison information corresponding to the various preset transaction dependencies. The comparison information includes at least one of address information, transaction type, storage attribute, order attribute, and transaction status. For each valid transaction tracking entry, a matching judgment of various preset transaction dependencies is performed according to the corresponding comparison information to obtain the dependency judgment result corresponding to each valid transaction tracking entry; Summarize the dependency judgment results. If any valid transaction tracking entry hits any of the preset transaction dependencies, it is determined that there is a preset transaction dependency between the request transaction and the transaction in transit, and it is determined that the project judgment result of the transaction dependency judgment item does not meet the corresponding bypass condition. If none of the valid transaction tracking entries match any of the preset transaction dependencies, it is determined that there is no preset transaction dependency between the request transaction and each of the in-transit transactions, and the item determination result of the transaction dependency determination item satisfies the corresponding bypass condition.

[0203] In some implementations, the processing module 602 determines whether the request transaction meets the early sending condition based on the scheduling information of the request transaction and the scheduling status of the pending transactions in the standard pipeline. Specifically, it is configured as follows: Determine whether there are any transactions in the standard pipeline that are in a pending state; If there is no transaction in the pending-send state, determine that the requesting transaction meets the early send condition; If there are transactions in the pending-send state, the scheduling priority of the requesting transaction is compared with the scheduling priority of the transactions in the pending-send state. If there are no pending-send transactions with a higher scheduling priority than the requesting transaction, it is determined that the requesting transaction meets the early sending condition.

[0204] In some implementations, the processing module 602, if the request transaction has read return semantics, determines whether read data buffer resources can be allocated to the request transaction based on the availability and allocation status of the read data buffer resources. Specifically, this is configured as follows: Determine whether the read data buffer resource corresponding to the request transaction is in an idle state, and arbitrate the resource allocation for request transactions with read return semantics within the same processing cycle; If the read data buffer resource is idle and the requesting transaction obtains an exclusive allocation authorization generated by the resource allocation arbitration, it is determined that the read data buffer resource can be allocated to the requesting transaction. If the read data buffer resource is not in an idle state or the request transaction has not obtained the exclusive allocation authorization, the project determination result of the read return resource determination item does not meet the corresponding bypass condition. Within the same processing cycle, the exclusive allocation authorization is granted to a request transaction, and the request transaction with the read return semantics includes read request transactions and atomic operation transactions.

[0205] In some implementations, the bypass candidate transaction is a request transaction with read return semantics; the processing module 602 performs a bypass send commit on the bypass candidate transaction according to the send authorization, and updates the corresponding transaction tracking status and resource status according to the bypass send commit, specifically configured as follows: The exclusive allocation authorization is used to allocate the read data buffer resource to the requesting transaction, and a bypass transaction tracking entry is created or updated in the requesting transaction tracker to track the requesting transaction. The allocation of the read data buffer resources, the creation or update of the bypass transaction tracking entry, and the sending of the request transaction are associated with the same bypass send commit. Based on the received completion response or data response of the requested transaction, update the bypass transaction tracking entry and release the read data buffer resources allocated to the requested transaction.

[0206] In some implementations, if the consistency transaction to be processed is a snooping transaction, the bypass decision item set includes snooping transaction entry decision items, sequence hazard decision items, and message credit decision items. The processing module 602 executes each bypass decision item in the bypass decision item set according to the running status information, specifically configured as follows: Based on the entry occupancy status of the listening transaction tracker, determine whether there are any idle listening transaction entries that can be allocated to the listening transaction; The transaction information of the listening transaction is compared with the transaction information of each in-transit request transaction in the request transaction tracker to determine whether there is a sequence hazard between the listening transaction and any of the in-transit request transactions in terms of completion confirmation and listening transaction. Based on the message credit status of the message channel corresponding to the listening transaction, determine whether the message channel has available message credit; If the idle listening transaction entry exists, the sequence hazard does not exist, and the message channel has the available message credit, then it is determined that the judgment results of each item satisfy the corresponding bypass condition.

[0207] In some implementations, the processing module 602 compares the transaction information of the listening transaction with the transaction information of each in-transit request transaction in the request transaction tracker to determine whether there is a sequence hazard between the listening transaction and any of the in-transit request transactions, specifically configured as follows: Based on the transaction status in the request transaction tracker, determine the target in-transit request transaction that is in a waiting-for-completion confirmation state from each of the in-transit request transactions; Compare the target address corresponding to the listening transaction with the transaction address corresponding to the target in-transit request transaction; If the target address and the transaction address of any of the target in-transit request transactions satisfy a preset address matching relationship, and the early sending of the listening transaction will change the processing order between the completion confirmation of the target in-transit request transaction and the listening transaction, it is determined that the order hazard exists; If there are no target in-transit request transactions that satisfy the preset address matching relationship, or if the early sending of the listening transaction will not change the processing order, it is determined that there is no ordering hazard.

[0208] The embodiments of this application, through the aforementioned apparatus, can dynamically determine transactions eligible for bypassing based on the transaction type and real-time operating status of consistent transactions. By performing unified scheduling arbitration with transactions to be sent in the standard pipeline and verifying bypass eligibility at the time of sending and submission, bypassing is prevented from disrupting transaction order, scheduling relationships, or resource usage status. This allows consistent transactions that meet the bypass conditions to bypass at least some pipeline stages in the standard pipeline, thereby shortening the processing latency of consistent transactions, reducing the occupation time of transaction tracking resources and pipeline resources, and improving the efficiency and effective throughput of consistent transaction processing in the inter-chip interconnect system.

[0209] The consistency transaction pipeline bypass device 60 in the inter-chip interconnect system of this application embodiment has been described above from the perspective of modular functional entities. The consistency transaction pipeline bypass device in the inter-chip interconnect system of this application embodiment will be described below from the perspective of hardware processing.

[0210] It should be noted that, Figure 6 The physical device corresponding to the input / output module 601 shown can be a transceiver, radio frequency circuit, communication module, and input / output (I / O) interface, etc., and the physical device corresponding to the processing module 602 can be a processor.

[0211] Figure 6 The devices shown can all have the following characteristics: Figure 7 The structure shown, when Figure 6 The consistency transaction pipeline bypass device 60 in the inter-chip interconnect system shown has, for example: Figure 7 When the structure shown is used, Figure 7 The processor and transceiver in the device can perform the same or similar functions as the processing module 602 and input / output module 601 provided in the aforementioned device embodiments. Figure 7 The computer program that the memory storage processor in the above-mentioned inter-chip interconnect system needs to call when executing the consistent transaction pipeline bypass method.

[0212] This application also relates to a chip system including at least one processor and an interface circuit. The processor includes a plurality of vector storage units. The processor is used to perform instruction and / or data interaction through the interface circuit, causing the chip system to perform the methods of any of the above embodiments.

[0213] In one possible implementation, the chip system may also directly include a memory in which computer programs or computer instructions are stored.

[0214] For example, the memory can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM).

[0215] This application also relates to a processor, which includes a plurality of storage units for calling computer programs or computer instructions stored in the memory to cause the processor to execute the methods described in any of the above embodiments.

[0216] For example, in the embodiments of this application, the processor is an integrated circuit chip with signal processing capabilities. For instance, the processor may be an FPGA, a general-purpose processor, a DSP, an ASIC, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, a SoC, a CPU, a network processor (NP), a microcontroller unit (MCU), a PLD, or other integrated chips, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. In one possible implementation, the embodiments of this application also provide a computer-readable storage medium storing program code, which, when executed on the computer, causes the computer to perform the above-described method embodiments.

[0217] This application also provides a computing device; please refer to [link / reference]. Figure 8 , Figure 8 This is a schematic diagram of a computing device 1100 provided in an embodiment of this application. The computing device 1100 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1122 (e.g., one or more processors) and a memory 1132, and one or more storage media 1130 (e.g., one or more mass storage devices) for storing application programs 1142 or data 1144. The memory 1132 and storage media 1130 may be temporary or persistent storage. The program stored in the storage media 1130 may include one or more modules (not shown in the figure), each module may include a series of instruction operations on a server. Furthermore, the CPU 1122 may be configured to communicate with the storage media 1130 and execute the series of instruction operations in the storage media 1130 on the computing device 1100. The computing device 1100 may also include one or more power supplies 1126, one or more wired or wireless network interfaces 1150, one or more input / output interfaces 1158, and / or one or more operating systems 1141, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc.

[0218] The steps performed by the server in the above embodiments can be based on this Figure 8 The structure of the computing device 1100 shown. For example, as in the above embodiment, by Figure 8 The steps performed by the data processing device 60 or the image processing device 70 shown can be based on this Figure 8The server structure is shown. For example, the central processing unit 1122 performs the following operations by calling instructions from memory 1132: The input / output interface 1158 is used to obtain the consistency transaction to be processed and the running status information related to the consistency transaction in the interconnected agent node. The central processing unit 1122 is configured to determine a corresponding set of bypass decision items based on the transaction type of the pending consistency transaction, and execute each bypass decision item in the set of bypass decision items according to the running status information to obtain the corresponding item decision result; if all item decision results meet the corresponding bypass conditions, the pending consistency transaction is designated as a bypass candidate transaction, and the bypass candidate transaction is uniformly scheduled and arbitrated with the pending transactions in the standard pipeline to determine the sending authorization of the bypass candidate transaction; in response to the sending authorization, the sending submission of the bypass candidate transaction is initiated. At any given time, the bypass eligibility of the candidate bypass transaction is reviewed based on the updated runtime status information; after the bypass eligibility review is passed, a bypass send commit is performed on the candidate bypass transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit, so that the candidate bypass transaction bypasses at least some pipeline stages in the standard pipeline; if any of the project judgment results does not meet the corresponding bypass conditions, the candidate bypass transaction does not obtain the send authorization, or the bypass eligibility review fails, the pending consistency transaction is transferred to the standard pipeline for processing; The bypass candidate transaction can also be output through the on-chip network interface or the chip interconnect interface according to the bypass submission executed by the processing module via the input / output interface 1158.

[0219] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0220] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0221] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or modules, and may be electrical, mechanical, or other forms.

[0222] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0223] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0224] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0225] The computer program product includes one or more computer instructions. When the computer program is loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0226] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this application to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. A method for pipelined bypassing of consistent transactions in an inter-chip interconnect system, characterized in that, The method, which applies to an interconnect proxy node between an on-chip network interface and an inter-chip interconnect interface, includes: Obtain the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node; The corresponding set of bypass decision items is determined according to the transaction type of the consistency transaction to be processed, and each bypass decision item in the set of bypass decision items is executed according to the running status information to obtain the corresponding decision result. If the project judgment results all meet the corresponding bypass conditions, the pending consistency transaction is regarded as a bypass candidate transaction, and the bypass candidate transaction and the pending transaction in the standard pipeline are uniformly scheduled and arbitrated to determine the sending authorization of the bypass candidate transaction. In response to the transmission authorization, at the time of transmission submission of the bypass candidate transaction, the bypass qualification of the bypass candidate transaction is reviewed according to the updated running status information; After the bypass qualification review is passed, the bypass send commit is performed on the bypass candidate transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit, so that the bypass candidate transaction bypasses at least part of the pipeline stages in the standard pipeline; If any of the project judgment results does not meet the corresponding bypass conditions, the bypass candidate transaction does not obtain the sending authorization, or the bypass qualification review fails, the pending consistency transaction will be transferred to the standard pipeline for processing.

2. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 1, characterized in that, The process of obtaining the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node includes: The system obtains the transaction attributes and transaction status of transactions in transit from the request transaction tracker and the listener transaction tracker, obtains the transactions to be sent in the standard pipeline and their scheduling status from the scheduling and distribution unit, and obtains the resource availability status from the resource management unit corresponding to the transaction processing resource. The transaction attributes, transaction status, scheduling status, and resource availability status are taken as state snapshots corresponding to the same processing cycle. Based on the state snapshot, each of the bypass decision items is executed in parallel, and the decision results of each item are summarized to determine whether the pending consistency transaction meets the corresponding bypass condition.

3. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 1, characterized in that, If the pending consistency transaction is a request transaction, the bypass decision item set includes transaction dependency decision items, scheduling status decision items, and read return resource decision items; The step of executing each bypass decision item in the bypass decision item set according to the running status information to obtain the corresponding item decision result includes: The transaction information of the requested transaction is compared with each valid transaction tracking entry in the requested transaction tracker and the listening transaction tracker to determine whether the requested transaction has a preset transaction dependency with any in-transit transaction. Based on the scheduling information of the requested transaction and the scheduling status of the transactions to be sent in the standard pipeline, determine whether the requested transaction meets the conditions for early sending. If the requested transaction has read return semantics, determine whether read data buffer resources can be allocated to the requested transaction based on the availability and allocation status of the read data buffer resources; Based on the results of the transaction dependency determination items, the scheduling status determination items, and the read return resource determination items, it is determined whether the request transaction meets the corresponding bypass conditions.

4. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 3, characterized in that, The preset transaction dependencies include transaction hazards between listening transactions and write-back transactions, transaction dependencies corresponding to non-mergeable access of device types, transaction dependencies corresponding to non-mergeable access of non-device types, and transaction dependencies corresponding to ordered write observations. The step of comparing the transaction information of the requested transaction with each valid transaction tracking entry in the requested transaction tracker and the listening transaction tracker to determine whether the requested transaction has a preset transaction dependency with any in-transit transaction includes: From the transaction information of the requested transaction and each of the valid transaction tracking entries, obtain comparison information corresponding to the various preset transaction dependencies. The comparison information includes at least one of address information, transaction type, storage attribute, order attribute, and transaction status. For each valid transaction tracking entry, a matching judgment of various preset transaction dependencies is performed according to the corresponding comparison information to obtain the dependency judgment result corresponding to each valid transaction tracking entry; Summarize the dependency judgment results. If any valid transaction tracking entry hits any of the preset transaction dependencies, it is determined that there is a preset transaction dependency between the request transaction and the transaction in transit, and it is determined that the project judgment result of the transaction dependency judgment item does not meet the corresponding bypass condition. If none of the valid transaction tracking entries match any of the preset transaction dependencies, it is determined that there is no preset transaction dependency between the request transaction and each of the in-transit transactions, and the item determination result of the transaction dependency determination item satisfies the corresponding bypass condition.

5. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 3, characterized in that, The step of determining whether the requested transaction meets the early transmission condition based on the scheduling information of the requested transaction and the scheduling status of the pending transactions in the standard pipeline includes: Determine whether there are any transactions in the standard pipeline that are in a pending state; If there is no transaction in the pending-send state, determine that the requesting transaction meets the early send condition; If there are transactions in the pending-send state, the scheduling priority of the requesting transaction is compared with the scheduling priority of the transactions in the pending-send state. If there are no pending-send transactions with a higher scheduling priority than the requesting transaction, it is determined that the requesting transaction meets the early sending condition.

6. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 3, characterized in that, If the requested transaction has read return semantics, determining whether read data buffer resources can be allocated to the requested transaction based on the availability and allocation status of the read data buffer resources includes: Determine whether the read data buffer resource corresponding to the request transaction is in an idle state, and arbitrate the resource allocation for request transactions with read return semantics within the same processing cycle; If the read data buffer resource is idle and the requesting transaction obtains an exclusive allocation authorization generated by the resource allocation arbitration, it is determined that the read data buffer resource can be allocated to the requesting transaction. If the read data buffer resource is not in an idle state or the request transaction has not obtained the exclusive allocation authorization, the project determination result of the read return resource determination item does not meet the corresponding bypass condition. Within the same processing cycle, the exclusive allocation authorization is granted to a request transaction, and the request transaction with the read return semantics includes read request transactions and atomic operation transactions.

7. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 6, characterized in that, The bypass candidate transaction is a request transaction with read return semantics; The step of performing a bypass send commit on the bypass candidate transaction according to the send authorization, and updating the corresponding transaction tracking status and resource status according to the bypass send commit, includes: The exclusive allocation authorization is used to allocate the read data buffer resource to the requesting transaction, and a bypass transaction tracking entry is created or updated in the requesting transaction tracker to track the requesting transaction. The allocation of the read data buffer resources, the creation or update of the bypass transaction tracking entry, and the sending of the request transaction are associated with the same bypass send commit. Based on the received completion response or data response of the requested transaction, update the bypass transaction tracking entry and release the read data buffer resources allocated to the requested transaction.

8. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 1, characterized in that, If the pending consistency transaction is a listening transaction, the bypass decision item set includes listening transaction entry decision items, sequence hazard decision items, and message credit decision items; The step of executing each bypass decision item in the bypass decision item set according to the running status information includes: Based on the entry occupancy status of the listening transaction tracker, determine whether there are any idle listening transaction entries that can be allocated to the listening transaction; The transaction information of the listening transaction is compared with the transaction information of each in-transit request transaction in the request transaction tracker to determine whether there is a sequence hazard between the listening transaction and any of the in-transit request transactions in terms of completion confirmation and listening transaction. Based on the message credit status of the message channel corresponding to the listening transaction, determine whether the message channel has available message credit; If the idle listening transaction entry exists, the sequence hazard does not exist, and the message channel has the available message credit, then it is determined that the judgment results of each item satisfy the corresponding bypass condition.

9. The consistent transaction pipeline bypass method in an inter-chip interconnect system according to claim 8, characterized in that, The step of comparing the transaction information of the monitored transaction with the transaction information of each in-transit request transaction in the request transaction tracker to determine whether there is a sequence hazard between the monitored transaction and any of the in-transit request transactions, includes: Based on the transaction status in the request transaction tracker, determine the target in-transit request transaction that is in a waiting-for-completion confirmation state from each of the in-transit request transactions; Compare the target address corresponding to the listening transaction with the transaction address corresponding to the target in-transit request transaction; If the target address and the transaction address of any of the target in-transit request transactions satisfy a preset address matching relationship, and the early sending of the listening transaction will change the processing order between the completion confirmation of the target in-transit request transaction and the listening transaction, it is determined that the order hazard exists; If there are no target in-transit request transactions that satisfy the preset address matching relationship, or if the early sending of the listening transaction will not change the processing order, it is determined that there is no ordering hazard.

10. A consistency transaction pipeline bypass device in an inter-chip interconnect system, characterized in that, The device is an interconnect proxy node disposed between the on-chip network interface and the inter-chip interconnect interface, and the device includes: The input / output module is configured to acquire the pending consistency transaction and the running status information related to the pending consistency transaction in the interconnected proxy node; The processing module is configured to determine a corresponding set of bypass decision items based on the transaction type of the consistency transaction to be processed, and execute each bypass decision item in the set of bypass decision items according to the running status information to obtain the corresponding decision result; if all the decision results of the items meet the corresponding bypass conditions, the consistency transaction to be processed is regarded as a bypass candidate transaction, and the bypass candidate transaction is uniformly scheduled and arbitrated with the transactions to be sent in the standard pipeline to determine the sending authorization of the bypass candidate transaction; in response to the sending authorization, at the time of sending submission of the bypass candidate transaction... The bypass eligibility of the candidate bypass transaction is verified based on the updated runtime status information. After the bypass eligibility verification is passed, a bypass send commit is performed on the candidate bypass transaction according to the send authorization, and the corresponding transaction tracking status and resource status are updated according to the bypass send commit, so that the candidate bypass transaction bypasses at least some pipeline stages in the standard pipeline. If any of the project judgment results does not meet the corresponding bypass conditions, the candidate bypass transaction does not obtain the send authorization, or the bypass eligibility verification fails, the pending consistency transaction is transferred to the standard pipeline for processing. The input / output module is further configured to output the bypass candidate transaction via the on-chip network interface or the inter-chip interconnect interface according to the bypass send submission executed by the processing module.

Images