A heterogeneous computing chip for DICT computing room and a task scheduling method thereof

Abstract

The application relates to the technical field of computing chips, in particular to a heterogeneous computing chip for a DICT computing power machine room and a task scheduling method thereof, which comprises a chip base body, and a general-purpose computing core, a parallel computing core, a neural network acceleration core, a network protocol processing core, a storage access control core and a security encryption core are integrated on the chip base body. The chip realizes on-chip fusion execution of communication, AI reasoning, storage access and security encryption tasks through the cooperation of the general-purpose computing core, the parallel computing core, the neural network acceleration core, the network protocol processing core, the storage access control core and the security encryption core. Through the task image scheduling mechanism, the task matching, dynamic migration and strategy updating are carried out in combination with the resource state, power consumption temperature and tenant security information, so that the mixed business processing efficiency, energy consumption control ability and multi-tenant isolation security of the DICT computing power machine room are improved.

Description

Technical Field

[0001] This invention relates to the field of computing chip technology, and in particular to a heterogeneous computing chip for DICT computing power data centers and its task scheduling method. Background Technology

[0002] DICT computing power data centers are computing infrastructures that integrate digital, information, and communication technologies. They typically need to simultaneously handle multiple tasks such as communication signaling processing, network forwarding, AI inference, big data analysis, cloud computing services, storage access, and network security detection. Compared to traditional IDC data centers, the business loads in DICT computing power data centers are more complex, and different tasks have significant differences in latency, bandwidth, computing power, storage access, and security isolation. For example, communication signaling processing tasks usually have strong low latency requirements, AI inference tasks usually have high parallel computing requirements, storage access tasks are usually sensitive to data migration and cache hit rates, and security encryption tasks require high isolation and reliability.

[0003] Existing heterogeneous computing chips for DICT computing power rooms typically employ a separate deployment of different hardware such as CPUs, GPUs, NPUs, DPUs, or FPGAs, with task allocation handled by server hosts or upper-layer scheduling platforms. While this approach can improve the processing capacity of certain types of tasks, different computing devices need to exchange data through external buses, network switching devices, or server hosts, which can easily lead to long data migration paths, high communication latency, and duplicate cache usage. For DICT services where communication and computing tasks are highly coupled, the separate heterogeneous architecture makes it difficult to achieve rapid collaboration of communication, computing, and storage resources.

[0004] To address the aforementioned issues, a search revealed a patent with publication number CN112463709B that discloses a configurable heterogeneous AI processor. The patent proposes "including at least two different types of computing units, and setting up a corresponding task queue, storage unit, and controller for each computing unit. The controller includes a task scheduling module, a task synchronization module, and a memory access control module. The task scheduling module can decompose the neural network computation graph to be processed into multiple computational subtasks according to the task allocation options in the configuration file, and distribute the computational subtasks to the corresponding computing units for execution according to the type of computational subtask, the queuing status of the task queue, or a specified marker." While this solution can achieve flexible allocation of neural network tasks within the heterogeneous AI processor through configuration files and a task scheduling module, improving the collaborative utilization efficiency between different computing units, it primarily focuses on task decomposition and computational subtask scheduling of the AI ​​neural network computation graph, emphasizing the task allocation problem between different computing units within the AI ​​processor, and does not address DICT (Distributed Computing Technology). In traditional computing data centers, various mixed business tasks, such as communication signaling processing, network forwarding, AI inference, storage access, and security encryption, are modeled using a unified task profile. However, resource status awareness, power consumption and thermal control coordination, and tenant security isolation are not integrated into the chip-level scheduling closed loop. In contrast, this invention does not simply distribute subtasks to the neural network computation graph. Instead, it integrates a converged computing and storage execution mechanism, a task profile scheduling mechanism, an on-chip data exchange mechanism, a resource status awareness mechanism, a power consumption and thermal control coordination mechanism, and a tenant security isolation mechanism on the chip substrate. Through task feature extraction, business type identification, priority determination, resource status acquisition, task profile generation, target core matching, dynamic migration judgment, and security isolation verification, communication tasks, computing tasks, storage tasks, and security tasks can be uniformly scheduled within the same heterogeneous computing chip. This directly addresses the problems of high data migration overhead, low efficiency of computing and storage coordination, disconnect between thermal control and scheduling, and insufficient multi-tenant isolation in DICT computing data centers with discrete heterogeneous devices.

[0005] In light of this, in-depth research into the aforementioned issues led to the creation of this case. Summary of the Invention

[0006] The purpose of this invention is to provide a heterogeneous computing chip and its task scheduling method for DICT computing power data centers, in order to solve the problem mentioned in the background art of existing heterogeneous computing chips for DICT computing power data centers. Computing power data centers typically use different hardware such as CPU, GPU, NPU, DPU or FPGA to be deployed separately, and the task allocation is completed by the server host or upper-layer scheduling platform. Although the above methods can improve the processing capacity of a certain type of task, different computing devices need to exchange data through external buses, network switching equipment or server hosts, which can easily lead to long data migration paths, high communication latency and duplicate cache occupation. For DICT services with a high degree of coupling between communication tasks and computing tasks, the discrete heterogeneous architecture is difficult to achieve rapid coordination of communication, computing and storage resources.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a heterogeneous computing chip for DICT computing power data centers and its task scheduling method, comprising a chip substrate,

[0008] The integrated computing and storage fusion execution mechanism on the chip substrate includes a general computing core, a parallel computing core, a neural network acceleration core, a network protocol processing core, a storage access control core, a security encryption core, a shared cache unit, and a near data cache unit.

[0009] A task profiling and scheduling mechanism integrated on the chip substrate, which is communicatively connected to the computing-storage fusion execution mechanism, is used to generate task profiles and perform task allocation and dynamic migration.

[0010] An on-chip data exchange mechanism integrated on the chip substrate is communicatively connected to the computing-storage fusion execution mechanism and the task profiling and scheduling mechanism, respectively, for transmitting task tags and task data between different computing cores;

[0011] A data center interconnection interface mechanism integrated on the chip substrate is communicatively connected to the task profiling and scheduling mechanism and is used to interact with external devices of the DICT computing power data center.

[0012] A resource status sensing mechanism integrated on the chip substrate is communicatively connected to the computing-storage fusion execution mechanism and the task profiling and scheduling mechanism, respectively, and is used to collect the real-time operating status of each computing core.

[0013] A power consumption and thermal control coordination mechanism is integrated on the chip substrate. The power consumption and thermal control coordination mechanism is communicatively connected to the resource status sensing mechanism and the task profiling and scheduling mechanism, respectively, and is used to generate thermal control scheduling signals based on chip power consumption and temperature status.

[0014] A tenant security isolation mechanism is integrated on the chip substrate. The tenant security isolation mechanism is communicatively connected to the task profiling and scheduling mechanism and the computing and storage fusion execution mechanism, respectively, and is used to perform hardware-level isolation of tasks of different tenants.

[0015] Preferably, the general-purpose computing core, parallel computing core, neural network acceleration core, network protocol processing core, storage access control core, and security encryption core are all connected to the shared cache unit through an on-chip data exchange mechanism.

[0016] Preferably, the shared cache unit is a unified cache accessed by the general computing core, parallel computing core, neural network acceleration core, network protocol processing core, storage access control core, and security encryption core, and the near data cache unit is communicatively connected to the storage access control core.

[0017] Preferably, the task profiling and scheduling mechanism includes a task receiving unit, a task feature extraction unit, a business type identification unit, a priority determination unit, a resource matching decision unit, a task queue caching unit, a dynamic migration control unit, an execution feedback unit, and a scheduling strategy update unit. The task receiving unit, task feature extraction unit, business type identification unit, priority determination unit, and resource matching decision unit are sequentially and communicatively connected. The resource matching decision unit is communicatively connected to the task queue caching unit, the dynamic migration control unit, and the execution feedback unit, respectively. The execution feedback unit is communicatively connected to the scheduling strategy update unit.

[0018] Preferably, the task receiving unit is communicatively connected to the computer room interconnection interface mechanism, and the resource matching decision unit is communicatively connected to the resource status sensing mechanism, the power consumption and thermal control coordination mechanism, the task queue caching unit, the dynamic migration control unit, and the execution feedback unit, respectively.

[0019] Preferably, the on-chip data exchange mechanism includes an on-chip interconnect bus, the on-chip interconnect bus is connected to a task tag channel, the on-chip interconnect bus is connected to a data transfer channel, and the on-chip interconnect bus is connected to a cache consistency control unit, which is connected to a shared cache unit and a near data cache unit respectively.

[0020] Preferably, the resource status awareness mechanism includes a core load detection unit, a cache occupancy detection unit, a bandwidth congestion detection unit, a power consumption detection unit, a temperature detection unit, and a fault status detection unit. The core load detection unit, cache occupancy detection unit, bandwidth congestion detection unit, power consumption detection unit, temperature detection unit, and fault status detection unit are all communicatively connected to the task profiling and scheduling mechanism.

[0021] Preferably, the power consumption and thermal control coordination mechanism includes a power consumption threshold management unit, a temperature zone judgment unit, a frequency reduction control unit, a task current limiting unit, and a thermal migration control unit, wherein the thermal migration control unit is communicatively connected to the task profiling and scheduling mechanism.

[0022] Preferably, the tenant security isolation mechanism includes a tenant identifier storage unit, an access permission verification unit, an isolation address mapping unit, and a security execution zone, wherein the isolation address mapping unit is communicatively connected to the security execution zone.

[0023] A heterogeneous computing chip for DICT computing power data centers and its task scheduling method, comprising the following steps:

[0024] S1: Task reception, receiving tasks to be executed from the DICT computing power data center management platform, server operating system, virtualization platform or container orchestration platform through the data center interconnection interface mechanism;

[0025] S2: Task feature extraction. The task feature extraction unit extracts the business source, data scale, computation operator type, data packet format, storage access mode, latency constraints, tenant identifier and security level information of the task to be executed, forming a task feature set.

[0026] S3: Service type identification. The service type identification unit classifies the tasks to be executed into communication signaling tasks, network forwarding tasks, AI inference tasks, parallel computing tasks, storage access tasks, security encryption tasks, or mixed service tasks based on the task feature set.

[0027] S4: Priority determination. The priority determination unit determines the task execution priority based on the business type, service level agreement, latency requirements, tenant level, and reliability requirements of the task, and assigns a corresponding priority label to the task.

[0028] S5: Resource status acquisition, the resource status sensing mechanism collects the load rate, cache utilization, available bandwidth, current power consumption, core temperature and fault status information of each computing core in real time;

[0029] S6: Task profile generation. The task profile scheduling agency integrates task type, task priority, latency constraints, data migration volume, storage access frequency, tenant identifier, power consumption constraints, and temperature constraints to generate a task profile describing the task to be executed.

[0030] S7: Target Core Matching. The resource matching decision unit matches the task profile with the real-time resource status of each computing core and selects the target computing core.

[0031] S8: On-chip task distribution. The task profile scheduler sends task tags, task data and tenant identifiers to the target computing core through the on-chip data exchange mechanism, and maintains data consistency between the shared cache unit and the near data cache unit through the cache consistency control unit.

[0032] S9: Task execution and feedback. The target computing core executes tasks, and the execution feedback unit collects information on task execution latency, cache hit rate, bandwidth usage, power consumption changes, temperature changes, and abnormal status.

[0033] S10: Dynamic migration judgment. The task profiling and scheduling agency judges whether the target computing core is overloaded, temperature exceeds the threshold, bandwidth is congested, execution timeout or fault state based on the execution feedback information. If yes, then execute S11; otherwise, execute S12.

[0034] S11: Dynamic task migration. The dynamic migration control unit migrates unfinished tasks to standby computing cores, or splits unfinished tasks into multiple subtasks and distributes them to multiple computing cores for parallel execution.

[0035] S12: Security isolation verification. The tenant security isolation mechanism verifies the tenant identifier, access permissions, and isolation address mapping relationship during task execution and when the result is returned. S13: Scheduling policy update. The scheduling policy update unit updates the scheduling policy library based on task completion time, resource usage, energy consumption data, migration count, and exception records.

[0036] Compared with the prior art, the beneficial effects of the present invention are:

[0037] 1. This invention relates to a heterogeneous computing chip and its task scheduling method for DICT computing power data centers. It employs a general-purpose computing core, a parallel computing core, a neural network acceleration core, a network protocol processing core, a storage access control core, a security encryption core, a shared cache unit, and a near-data cache unit to form a unified computing and storage execution mechanism. This enables hybrid tasks such as communication signaling, network forwarding, AI inference, parallel computing, storage access, and security encryption in DICT computing power data centers to be processed collaboratively on-chip within the same chip substrate. Compared to the traditional approach that relies on separate deployments of CPU, GPU, DPU, NPU, and security acceleration cards, this invention reduces cross-device data movement and external bus interaction, shortens task scheduling paths, reduces cache duplication and bandwidth congestion, and improves multi-core data reuse efficiency through shared cache units and near-data cache units, thereby enhancing hybrid service processing capabilities and low-latency response capabilities.

[0038] 2. This paper presents a heterogeneous computing chip and its task scheduling method for DICT computing power data centers. It employs a task profiling and scheduling mechanism, a resource status awareness mechanism, a power consumption and thermal control coordination mechanism, and a tenant security isolation mechanism to form a closed-loop scheduling system. This system enables tasks to be executed to be matched with target cores based on service type, priority, latency constraints, tenant identifier, power consumption and temperature, and real-time resource status after entering the chip. During execution, if overload, temperature exceeding threshold, bandwidth congestion, execution timeout, or fault conditions occur, the dynamic migration control unit can migrate or split the task for execution. The power consumption and thermal control coordination mechanism can perform frequency reduction, rate limiting, and hot migration scheduling. The tenant security isolation mechanism can perform hardware-level isolation verification of tasks from different tenants, thereby improving the chip's reliability, energy consumption control capabilities, security isolation capabilities, and long-term operational stability in DICT computing power data centers. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the overall system framework of the present invention;

[0040] Figure 2 This is a schematic diagram of the structure of the universal computing and storage fusion execution mechanism of the present invention;

[0041] Figure 3 This is a schematic diagram of the task image scheduling mechanism of the present invention;

[0042] Figure 4 This is a schematic diagram of the on-chip data exchange mechanism of the present invention;

[0043] Figure 5 This is a schematic diagram of the resource status perception and power consumption thermal control collaborative scheduling of the present invention;

[0044] Figure 6 This is a schematic diagram of the hybrid service task scheduling of the present invention;

[0045] Figure 7 This is a schematic diagram of the tenant safety isolation mechanism of the present invention;

[0046] Figure 8 This is a flowchart of the task scheduling method of the present invention.

[0047] In the diagram: 1. Chip substrate; 2. General-purpose computing and storage fusion execution mechanism; 201. General-purpose computing core; 202. Parallel computing core; 203. Neural network acceleration core; 204. Network protocol processing core; 205. Storage access control core; 206. Security encryption core; 207. Shared cache unit; 208. Near data cache unit; 3. Task profiling and scheduling mechanism; 301. Task receiving unit; 302. Task feature extraction unit; 303. Business type identification unit; 304. Priority determination unit; 305. Resource matching decision unit; 306. Task queue cache unit; 307. Dynamic migration control unit; 308. Execution feedback unit; 309. Scheduling strategy update unit; 4. On-chip data exchange mechanism; 401. On-chip interconnect bus; 402. Task Tag Channel; 403. Data Migration Channel; 404. Cache Consistency Control Unit; 5. Data Center Interconnection Interface Mechanism; 6. Resource Status Awareness Mechanism; 601. Core Load Detection Unit; 602. Cache Occupancy Detection Unit; 603. Bandwidth Congestion Detection Unit; 604. Power Consumption Detection Unit; 605. Temperature Detection Unit; 606. Fault Status Detection Unit; 7. Power Consumption and Thermal Control Coordination Mechanism; 701. Power Consumption Threshold Management Unit; 702. Temperature Zone Judgment Unit; 703. Frequency Reduction Control Unit; 704. Task Rate Limiting Unit; 705. Hot Migration Control Unit; 8. Tenant Security Isolation Mechanism; 801. Tenant Identifier Registration Unit; 802. Access Permission Verification Unit; 803. Isolation Address Mapping Unit; 804. Secure Execution Zone. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Please see Figure 1-8 This invention provides a technical solution: a heterogeneous computing chip for DICT computing power data centers and its task scheduling method, comprising a chip substrate 1,

[0050] The general computing and storage fusion execution mechanism 2 is integrated on the chip substrate 1. The general computing and storage fusion execution mechanism 2 includes a general computing core 201, a parallel computing core 202, a neural network acceleration core 203, a network protocol processing core 204, a storage access control core 205, a security encryption core 206, a shared cache unit 207, and a near data cache unit 208.

[0051] The task profile scheduling mechanism 3 is integrated on the chip substrate 1. The task profile scheduling mechanism 3 is communicatively connected to the computing and storage fusion execution mechanism 2 and is used to generate task profiles and perform task allocation and dynamic migration.

[0052] The on-chip data exchange mechanism 4 is integrated on the chip substrate 1. The on-chip data exchange mechanism 4 is communicatively connected to the computing-storage fusion execution mechanism 2 and the task profiling and scheduling mechanism 3, respectively, and is used to transmit task tags and task data between different computing cores.

[0053] The data center interconnection interface mechanism 5 is integrated on the chip substrate 1. The data center interconnection interface mechanism 5 is communicatively connected to the task profile scheduling mechanism 3 and is used to interact with external devices of the DICT computing power data center.

[0054] The resource status sensing mechanism 6 is integrated on the chip substrate 1. The resource status sensing mechanism 6 is communicatively connected to the computing and storage fusion execution mechanism 2 and the task profiling and scheduling mechanism 3, respectively, and is used to collect the real-time operating status of each computing core.

[0055] The power consumption and thermal control coordination mechanism 7 is integrated on the chip substrate 1. The power consumption and thermal control coordination mechanism 7 is communicatively connected to the resource status sensing mechanism 6 and the task profiling and scheduling mechanism 3, respectively, and is used to generate thermal control scheduling signals based on chip power consumption and temperature status.

[0056] The tenant security isolation mechanism 8, integrated on the chip substrate 1, is communicatively connected to the task profiling and scheduling mechanism 3 and the converged computing and storage execution mechanism 2. It is used to perform hardware-level isolation of tasks from different tenants. Through the setup of the chip substrate 1, the converged computing and storage execution mechanism 2, the task profiling and scheduling mechanism 3, the on-chip data exchange mechanism 4, the data center interconnection interface mechanism 5, the resource status awareness mechanism 6, the power consumption and thermal control coordination mechanism 7, and the tenant security isolation mechanism 8, the mixed tasks in the DICT computing power data center can be received, identified, scheduled, executed, fed back, migrated, and securely isolated on the chip, reducing the scheduling overhead caused by external multi-device collaboration.

[0057] Furthermore, the general-purpose computing core 201, parallel computing core 202, neural network acceleration core 203, network protocol processing core 204, storage access control core 205, and security encryption core 206 are all connected to the shared cache unit 207 through the on-chip data exchange mechanism 4. By setting up multiple types of computing cores, the chip substrate 1 can select the appropriate core to execute tasks for different business types, avoiding the concentration of all tasks in a single general-purpose core and improving the parallel processing capability of mixed business.

[0058] Furthermore, the shared cache unit 207 is a unified cache accessed by the general computing core 201, parallel computing core 202, neural network acceleration core 203, network protocol processing core 204, storage access control core 205, and security encryption core 206. The near data cache unit 208 is communicatively connected to the storage access control core 205. Through the setting of the shared cache unit 207, task data can be reused among different computing cores, reducing repeated memory accesses. Through the setting of the near data cache unit 208, the storage access control core 205 can cache frequently accessed data nearby, improving the processing efficiency of storage-intensive tasks.

[0059] Furthermore, the task profiling and scheduling mechanism 3 includes a task receiving unit 301, a task feature extraction unit 302, a business type identification unit 303, a priority determination unit 304, a resource matching decision unit 305, a task queue caching unit 306, a dynamic migration control unit 307, an execution feedback unit 308, and a scheduling strategy update unit 309. The task receiving unit 301, the task feature extraction unit 302, the business type identification unit 303, the priority determination unit 304, and the resource matching decision unit 305 are sequentially connected in communication. The resource matching decision unit 305 is connected in communication with the task queue caching unit 306, the dynamic migration control unit 307, and the execution feedback unit 308, respectively. The execution feedback unit 308 is connected in communication with the scheduling strategy update unit 309. Through the configuration of the task profiling and scheduling mechanism 3, tasks can be identified and profiled before being allocated to the corresponding computing cores, avoiding a decrease in execution efficiency caused by a mismatch between task types and computing core capabilities.

[0060] Furthermore, the task receiving unit 301 is communicatively connected to the computer room interconnection interface mechanism 5, and the resource matching decision unit 305 is communicatively connected to the resource status sensing mechanism 6, the power consumption and thermal control coordination mechanism 7, the task queue cache unit 306, the dynamic migration control unit 307, and the execution feedback unit 308, respectively. Through the setting of the resource matching decision unit 305, the task distribution can simultaneously refer to the task profile, resource status, and thermal control strategy, thereby improving the real-time performance and accuracy of scheduling judgment.

[0061] Furthermore, the on-chip data exchange mechanism 4 includes an on-chip interconnect bus 401, which is connected to a task tag channel 402, a data transfer channel 403, and a cache consistency control unit 404. The cache consistency control unit 404 is connected to the shared cache unit 207 and the near data cache unit 208. The on-chip interconnect bus 401 enables on-chip data interaction between computing cores. The task tag channel 402 and the data transfer channel 403 enable the separate transmission of task control information and task data. The cache consistency control unit 404 makes the cache data state more stable during multi-core concurrent execution.

[0062] Furthermore, the resource status awareness mechanism 6 includes a core load detection unit 601, a cache occupancy detection unit 602, a bandwidth congestion detection unit 603, a power consumption detection unit 604, a temperature detection unit 605, and a fault status detection unit 606. All four units are communicatively connected to the task profiling and scheduling mechanism 3. Through the configuration of the resource status awareness mechanism 6, the task profiling and scheduling mechanism 3 can obtain real-time information on the load, cache, bandwidth, power consumption, temperature, and fault status of each computing core, providing a data foundation for target core matching and task migration.

[0063] Furthermore, the power consumption and thermal control coordination mechanism 7 includes a power consumption threshold management unit 701, a temperature zone judgment unit 702, a frequency reduction control unit 703, a task current limiting unit 704, and a thermal migration control unit 705. The thermal migration control unit 705 is communicatively connected to the task profile scheduling mechanism 3. Through the setting of the power consumption and thermal control coordination mechanism 7, the chip can generate frequency reduction, current limiting, and thermal migration strategies under high power consumption or high temperature conditions, thereby reducing the impact of continuous high load operation on chip stability.

[0064] Furthermore, the tenant security isolation mechanism 8 includes a tenant identifier registration unit 801, an access permission verification unit 802, an isolation address mapping unit 803, and a secure execution area 804. The isolation address mapping unit 803 is communicatively connected to the secure execution area 804. Through the setting of the tenant security isolation mechanism 8, different tenant tasks can be isolated in terms of tenant identifier, access permission, address space, and execution area, thereby reducing the risk of data out-of-bounds operation in multi-tenant mixed operation.

[0065] A heterogeneous computing chip for DICT computing power data centers and its task scheduling method, comprising the following steps:

[0066] S1: Task reception, receiving tasks to be executed from the DICT computing power data center management platform, server operating system, virtualization platform or container orchestration platform through the data center interconnection interface mechanism 5;

[0067] S2: Task feature extraction. The task feature extraction unit 302 extracts the business source, data scale, calculation operator type, data packet format, storage access mode, latency constraints, tenant identifier and security level information of the task to be executed, forming a task feature set.

[0068] S3: Service type identification. The service type identification unit 303 divides the tasks to be executed into communication signaling tasks, network forwarding tasks, AI inference tasks, parallel computing tasks, storage access tasks, security encryption tasks, or mixed service tasks according to the task feature set.

[0069] S4: Priority determination. Priority determination unit 304 determines the task execution priority based on the business type, service level agreement, latency requirements, tenant level, and reliability requirements of the task, and assigns a corresponding priority label to the task.

[0070] S5: Resource status acquisition, the resource status sensing mechanism 6 collects the load rate, cache utilization rate, available bandwidth, current power consumption, core temperature and fault status information of each computing core in real time;

[0071] S6: Task profile generation. The task profile scheduling mechanism 3 integrates task type, task priority, latency constraints, data migration amount, storage access frequency, tenant identifier, power consumption constraints, and temperature constraints to generate a task profile describing the task to be executed.

[0072] S7: Target core matching, resource matching decision unit 305 matches the task profile with the real-time resource status of each computing core and selects the target computing core;

[0073] S8: On-chip task distribution, the task profile scheduling mechanism 3 sends the task tag, task data and tenant identifier to the target computing core through the on-chip data exchange mechanism 4, and maintains the data consistency of the shared cache unit 207 and the near data cache unit 208 through the cache consistency control unit 404.

[0074] S9: Task execution and feedback. The target computing core executes tasks, and the execution feedback unit 308 collects information on task execution latency, cache hit rate, bandwidth usage, power consumption changes, temperature changes, and abnormal status.

[0075] S10: Dynamic migration judgment. The task profile scheduling mechanism 3 judges whether the target computing core is overloaded, temperature exceeds the threshold, bandwidth is congested, execution timeout or fault state based on the execution feedback information. If yes, execute S11; otherwise, execute S12.

[0076] S11: Dynamic task migration. The dynamic migration control unit 307 migrates unfinished tasks to standby computing cores, or splits unfinished tasks into multiple subtasks and assigns them to multiple computing cores for parallel execution.

[0077] S12: Security isolation verification, the tenant security isolation mechanism 8 verifies the tenant identifier, access permissions and isolation address mapping relationship during task execution and when the result is returned; S13: Scheduling policy update, the scheduling policy update unit 309 updates the scheduling policy library according to the task completion time, resource usage, energy consumption data, migration times and exception records.

[0078] Working principle: First, during use, the DICT computing power data center management platform, server operating system, virtualization platform, or container orchestration platform inputs communication signaling, network forwarding, AI inference, parallel computing, storage access, security encryption, or mixed business tasks to the chip substrate 1 through the data center interconnection interface mechanism 5. After the task receiving unit 301 receives the task to be executed, the task feature extraction unit 302 extracts the task's business source, data scale, computing operator type, data packet format, storage access mode, latency constraints, tenant identifier, and security level information, so that the task has clear business characteristics from the moment it enters the chip. Subsequently, the business type identification unit 303 determines whether the task belongs to a communication signaling task, network forwarding task, parallel computing task, storage access task, security encryption task, or mixed business task based on the task feature set. For network forwarding tasks, AI inference tasks, parallel computing tasks, storage access tasks, security encryption tasks, or mixed service tasks, the priority determination unit 304 determines the task execution priority based on service level agreements, latency requirements, tenant level, and reliability requirements, ensuring that high real-time and high reliability tasks receive priority scheduling opportunities. Simultaneously, the resource status awareness mechanism 6 continuously collects data on the load rate, cache utilization, available bandwidth, current power consumption, core temperature, and fault status of the general computing core 201, parallel computing core 202, neural network acceleration core 203, network protocol processing core 204, storage access control core 205, and security encryption core 206. The power consumption and thermal control coordination mechanism 7 generates data based on power consumption thresholds and temperature zoning status. Frequency reduction, rate limiting, or hot migration suggestions are provided. The task profiling scheduling mechanism 3 forms a task profile by comprehensively considering task type, priority, data migration amount, storage access frequency, tenant identifier, power consumption constraints, and temperature constraints. The resource matching decision unit 305 then matches the task profile with the real-time resource status of each computing core to select a more suitable target computing core. Once the target computing core is determined, the on-chip data exchange mechanism 4 transmits task tags and tenant identifiers through the task tag channel 402 and transmits task data through the data migration channel 403, separating control information from data content to reduce the possibility of mutual blocking. During task execution, the target computing core can access the shared cache unit 207. For storage access-intensive tasks, it can also utilize the near-data cache. The cache unit 208 shortens the data access path, and the cache consistency control unit 404 continuously maintains data consistency between the shared cache unit 207 and the near-data cache unit 208, reducing data conflicts caused by concurrent access from multiple cores. During task execution, the execution feedback unit 308 continuously collects information on task execution latency, cache hit rate, bandwidth usage, power consumption changes, temperature changes, and abnormal states. When the feedback results show that the target computing core is overloaded, exceeds the temperature threshold, experiences bandwidth congestion, execution timeout, or a fault state, the dynamic migration control unit 307 migrates the unfinished task to a backup computing core, or splits the unfinished task into multiple subtasks and allocates them to multiple computing cores for parallel execution. If the temperature or power consumption continues to rise...The power consumption and thermal control coordination mechanism 7 further coordinates with the frequency reduction control unit 703, task current limiting unit 704, and hot migration control unit 705 to adjust the task distribution. Throughout the task execution and result return process, the tenant security isolation mechanism 8 verifies the tenant identity, access permissions, and isolation address mapping relationship through the tenant identifier register unit 801, access permission verification unit 802, isolation address mapping unit 803, and secure execution area 804. This ensures that different tenant tasks remain isolated in the computing core, cache, and address space, preventing data out-of-bounds access and mixed permissions. After the task is completed, the scheduling policy update unit 309 updates the scheduling policy library based on the task completion time, resource usage, energy consumption data, migration count, and exception records, enabling subsequent tasks of the same type to be matched with suitable computing cores more quickly.

[0079] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A heterogeneous computing chip for DICT computing power data centers, comprising a chip substrate (1), characterized in that: The integrated computing and storage fusion execution mechanism (2) on the chip substrate (1) includes a general computing core (201), a parallel computing core (202), a neural network acceleration core (203), a network protocol processing core (204), a storage access control core (205), a security encryption core (206), a shared cache unit (207), and a near data cache unit (208); the integrated task profile scheduling mechanism (3) on the chip substrate (1) is communicatively connected to the integrated computing and storage fusion execution mechanism (2) and is used to generate task profiles and perform task allocation and dynamic migration; An on-chip data exchange mechanism (4) is integrated on the chip substrate (1). The on-chip data exchange mechanism (4) is communicatively connected to the computing-storage fusion execution mechanism (2) and the task profiling and scheduling mechanism (3) respectively, and is used to transmit task tags and task data between different computing cores. A data center interconnection interface mechanism (5) is integrated on the chip substrate (1). The data center interconnection interface mechanism (5) is communicatively connected to the task profiling and scheduling mechanism (3), and is used to interact with external devices of the DICT computing power data center. The resource status sensing mechanism (6) is integrated on the chip substrate (1). The resource status sensing mechanism (6) is connected to the computing and storage fusion execution mechanism (2) and the task profiling and scheduling mechanism (3) respectively, and is used to collect the real-time running status of each computing core. A power consumption and thermal control coordination mechanism (7) is integrated on the chip substrate (1). The power consumption and thermal control coordination mechanism (7) is communicatively connected to the resource status sensing mechanism (6) and the task profile scheduling mechanism (3) respectively, and is used to generate thermal control scheduling signals according to the chip power consumption and temperature status. The tenant security isolation mechanism (8) is integrated on the chip substrate (1). The tenant security isolation mechanism (8) is connected to the task profiling and scheduling mechanism (3) and the computing and storage fusion execution mechanism (2) respectively, and is used to perform hardware-level isolation of tasks of different tenants.

2. The heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The general computing core (201), parallel computing core (202), neural network acceleration core (203), network protocol processing core (204), storage access control core (205) and security encryption core (206) are all connected to the shared cache unit (207) through the on-chip data exchange mechanism (4).

3. A heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The shared cache unit (207) is a unified cache accessed by the general computing core (201), parallel computing core (202), neural network acceleration core (203), network protocol processing core (204), storage access control core (205) and security encryption core (206). The near data cache unit (208) is communicatively connected to the storage access control core (205).

4. A heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The task profile scheduling mechanism (3) includes a task receiving unit (301), a task feature extraction unit (302), a business type identification unit (303), a priority determination unit (304), a resource matching decision unit (305), a task queue caching unit (306), a dynamic migration control unit (307), an execution feedback unit (308), and a scheduling strategy update unit (309). The task receiving unit (301), the task feature extraction unit (302), the business type identification unit (303), the priority determination unit (304), and the resource matching decision unit (305) are connected in sequence. The resource matching decision unit (305) is connected in communication with the task queue caching unit (306), the dynamic migration control unit (307), and the execution feedback unit (308), respectively. The execution feedback unit (308) is connected in communication with the scheduling strategy update unit (309).

5. A heterogeneous computing chip for DICT computing power data centers according to claim 4, characterized in that: The task receiving unit (301) is communicatively connected to the computer room interconnection interface mechanism (5), and the resource matching decision unit (305) is communicatively connected to the resource status sensing mechanism (6), the power consumption and thermal control coordination mechanism (7), the task queue cache unit (306), the dynamic migration control unit (307), and the execution feedback unit (308), respectively.

6. A heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The on-chip data exchange mechanism (4) includes an on-chip interconnect bus (401), which is connected to a task tag channel (402) and a data transfer channel (403). The on-chip interconnect bus (401) is also connected to a cache consistency control unit (404), which is connected to a shared cache unit (207) and a near data cache unit (208).

7. A heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The resource status sensing mechanism (6) includes a core load detection unit (601), a cache occupancy detection unit (602), a bandwidth congestion detection unit (603), a power consumption detection unit (604), a temperature detection unit (605), and a fault status detection unit (606). The core load detection unit (601), cache occupancy detection unit (602), bandwidth congestion detection unit (603), power consumption detection unit (604), temperature detection unit (605), and fault status detection unit (606) are all communicatively connected to the task profile scheduling mechanism (3).

8. A heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The power consumption and thermal control coordination mechanism (7) includes a power consumption threshold management unit (701), a temperature zone judgment unit (702), a frequency reduction control unit (703), a task current limiting unit (704), and a thermal migration control unit (705). The thermal migration control unit (705) is communicatively connected to the task profile scheduling mechanism (3).

9. A heterogeneous computing chip for DICT computing power data centers according to claim 1, characterized in that: The tenant security isolation mechanism (8) includes a tenant identifier storage unit (801), an access permission verification unit (802), an isolation address mapping unit (803), and a security execution zone (804), wherein the isolation address mapping unit (803) is communicatively connected to the security execution zone (804).

10. A heterogeneous computing chip for DICT computing power data centers and its task scheduling method, as described in any one of claims 1-9, characterized in that... Includes the following steps: S1: Task reception, receiving tasks to be executed from the DICT computing power data center management platform, server operating system, virtualization platform or container orchestration platform through the data center interconnection interface mechanism (5); S2: Task feature extraction, the task feature extraction unit (302) extracts the business source, data scale, calculation operator type, data packet format, storage access mode, latency constraints, tenant identifier and security level information of the task to be executed, and forms a task feature set; S3: Service type identification. The service type identification unit (303) divides the tasks to be executed into communication signaling tasks, network forwarding tasks, AI inference tasks, parallel computing tasks, storage access tasks, security encryption tasks, or mixed service tasks according to the task feature set. S4: Priority determination, the priority determination unit (304) determines the task execution priority based on the business type, service level agreement, latency requirements, tenant level and reliability requirements of the task, and assigns a corresponding priority label to the task; S5: Resource status acquisition, resource status sensing mechanism (6) collects the load rate, cache utilization rate, available bandwidth, current power consumption, core temperature and fault status information of each computing core in real time; S6: Task profile generation, the task profile scheduling agency (3) integrates task type, task priority, latency constraint, data migration amount, storage access frequency, tenant identifier, power consumption constraint and temperature constraint to generate a task profile to describe the task to be executed; S7: Target core matching, resource matching decision unit (305) matches the task profile with the real-time resource status of each computing core and selects the target computing core; S8: On-chip task distribution, the task profile scheduling mechanism (3) sends the task tag, task data and tenant identifier to the target computing core through the on-chip data exchange mechanism (4), and maintains the data consistency of the shared cache unit (207) and the near data cache unit (208) through the cache consistency control unit (404); S9: Task execution and feedback, the target computing core executes the task, and the execution feedback unit (308) collects task execution latency, cache hit rate, bandwidth usage, power consumption change, temperature change and abnormal status information; S10: Dynamic migration judgment, task profile scheduling mechanism (3) judges whether the target computing core is overloaded, temperature exceeds threshold, bandwidth congestion, execution timeout or fault state according to the execution feedback information. If yes, execute S11; otherwise, execute S12. S11: Task dynamic migration, the dynamic migration control unit (307) migrates unfinished tasks to standby computing cores, or splits unfinished tasks into multiple subtasks and assigns them to multiple computing cores for parallel execution; S12: Security isolation verification, the tenant security isolation mechanism (8) verifies the tenant identifier, access permissions and isolation address mapping relationship during task execution and when the result is returned; S13: Scheduling policy update, the scheduling policy update unit (309) updates the scheduling policy library according to the task completion time, resource usage, energy consumption data, migration times and abnormal records.

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