Interrupt signal processing method, apparatus, device, medium, program product and chip

Abstract

The present disclosure relates to an interrupt signal processing method, device, equipment, medium, program product and chip. The interrupt signal processing method comprises: in response to a target physical interrupt signal, determining a target processing mode based on preset configuration information; in response to the target processing mode being a first processing mode, generating and processing a first virtual interrupt signal in a kernel running state; and in response to the target processing mode being a second processing mode, generating a second virtual interrupt signal in a virtual machine monitoring state and processing the second virtual interrupt signal in the kernel running state. The first processing mode and the second processing mode can respectively implement pass-through and trapping of the interrupt signal, the performance overhead, response delay and cache pollution can be reduced by using the first processing mode, different target physical interrupt signals can correspond to different target processing modes, each target physical interrupt signal can be independently subjected to fine-grained routing control, the processing efficiency and flexibility of the interrupt signal can be improved, and thus the overall performance of the virtualization system can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of virtualized interrupt handling, specifically to an interrupt signal processing method, apparatus, device, medium, program product, and chip. Background Technology

[0002] Interrupt signals, as control signals that notify system processes to stop their current operations and prioritize specific tasks or events, are the foundation of interrupt mechanisms. They enable computer systems to respond quickly to asynchronous events and schedule resources. In virtualization systems, physical hardware resources are abstracted as virtual resources, requiring physical interrupt signals to be converted into virtual interrupt signals before being processed by the corresponding operating system of the virtual machine. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides an interrupt signal processing method, apparatus, device, medium, program product, and chip.

[0004] According to a first aspect of the present disclosure, an interrupt signal processing method is provided, applied to a processor, the processor being configured with a kernel running state and a virtual machine monitoring state, the interrupt signal processing method comprising: In response to a target physical interruption signal, a target processing mode matching the target physical interruption signal is determined based on preset configuration information, wherein the preset configuration information is used to characterize the preset processing modes corresponding to multiple preset physical interruption signals respectively; In response to the target processing mode being a first processing mode, in the kernel running state of the processor, a first virtual interrupt signal is generated based on the target physical interrupt signal, and the first virtual interrupt signal is processed in the kernel running state; In response to the target processing mode being the second processing mode, in the virtual machine monitoring state of the processor, a second virtual interrupt signal is generated based on the target physical interrupt signal, and the second virtual interrupt signal is processed in the kernel running state.

[0005] In this embodiment, when a target physical interrupt signal is detected, a target processing mode is determined based on preset configuration information. Depending on whether the target processing mode is a first processing mode or a second processing mode, a first virtual interrupt signal is generated in kernel running mode or a second virtual interrupt signal is generated in virtual machine monitoring mode. This allows for the processing of both the first and second virtual interrupt signals in kernel running mode, realizing the routing, conversion, and response of interrupt signals within the virtualization system. By controlling the routing conversion method of interrupt signals through the target processing mode, the first and second processing modes can respectively achieve interrupt signal pass-through and trapping. The first processing mode can reduce performance overhead, response latency, and cache pollution caused by frequent switching of processor states (privilege levels). Furthermore, different target physical interrupt signals can correspond to different target processing modes, enabling independent fine-grained routing control for each target physical interrupt signal. This improves the processing efficiency and flexibility of interrupt signals, thereby enhancing the overall performance of the virtualization system.

[0006] In some embodiments of this disclosure, generating a first virtual interrupt signal based on the target physical interrupt signal includes: The processor generates the first virtual interrupt signal based on the target physical interrupt signal; The generation of the second virtual interrupt signal based on the target physical interrupt signal includes: The virtual machine monitor generates the second virtual interrupt signal based on the target physical interrupt signal.

[0007] In this embodiment, in the first processing mode and kernel running state, the processor generates a first virtual interrupt signal based on the target physical interrupt signal, and in the second processing mode and virtual machine monitoring state, the virtual machine monitoring program generates a second virtual interrupt signal based on the target physical interrupt signal. This allows the first and second processing modes to achieve interrupt signal pass-through and trapping through hardware and software respectively. It can simplify the transmission path, improve response speed, reduce performance loss and improve compatibility by using hardware mechanisms while retaining conventional software mechanisms, thereby further improving the overall performance of the virtualization system.

[0008] In some embodiments of this disclosure, the step of generating the first virtual interrupt signal by the processor based on the target physical interrupt signal includes: Switching from the kernel running state to the virtual machine monitoring state is prohibited; Generate first mapping information, which is used to convert physical interrupt signals into virtual interrupt signals; The first virtual interrupt signal is generated based on the target physical interrupt signal and the first mapping information; The step of generating the second virtual interrupt signal based on the target physical interrupt signal using a virtual machine monitor includes: Generate second mapping information, which is used to convert physical interrupt signals into virtual interrupt signals; The second virtual interrupt signal is generated based on the target physical interrupt signal and the second mapping information.

[0009] In this embodiment, by disabling the switch from kernel running state to virtual machine monitoring state and generating first mapping information, a first virtual interrupt signal is generated based on the target physical interrupt signal and the first mapping information. Furthermore, by generating second mapping information and generating a second virtual interrupt signal based on the target physical interrupt signal and the second mapping information, the conversion of the target physical interrupt signal can be achieved through both hardware-based pass-through EL1 and software-based trap EL2 methods. Using the first and second mapping information as the basis for generating the first and second virtual interrupt signals respectively ensures accurate mapping, real-time response, resource isolation, and reliable operation when converting physical interrupt signals to virtual interrupt signals, further improving the processing efficiency and flexibility of the target physical interrupt signal.

[0010] In some embodiments of this disclosure, the first mapping information is stored in a first target register, and the second mapping information is stored in a second target register. Both the first target register and the second target register are located in a general interrupt controller that is communicatively connected to the processor.

[0011] In this embodiment, a first target register and a second target register are configured in the general-purpose interrupt controller that communicates with the processor to store the first mapping information and the second mapping information, respectively. This provides a guarantee for writing and reading the first and second mapping information, thereby providing a basis for generating the first and second virtual interrupt signals. Storing the first and second mapping information required for interrupt processing through system registers ensures data integrity, security, and memory access speed, improving the efficiency and reliability of the interrupt mechanism. Furthermore, configuring independent first and second target registers for the first and second mapping information respectively avoids mutual occupation of register resources, ensuring the stability of the interrupt mechanism and further improving the processing efficiency of the target physical interrupt signal and the overall performance of the virtualization system.

[0012] In some embodiments of this disclosure, determining the target processing mode matching the target physical interruption signal based on preset configuration information includes: In response to the satisfaction of preset control conditions, based on the preset configuration information, a target processing mode matching the target physical interrupt signal is determined. The preset control conditions include the processor being in the virtual machine monitoring state and the signal type of the target physical interrupt signal being the target type.

[0013] In this embodiment, the processor is in virtual machine monitoring state and the signal type of the target physical interrupt signal is the target type as a preset control condition. The satisfaction of the preset control condition is used as the selection condition for the target processing mode and the trigger condition for the application. The preset control condition is used to check the current scene when the target physical interrupt signal is identified, so that the current scene can match the scene requirements of the first processing mode and the second processing mode, ensuring the smooth execution of the interrupt signal processing process.

[0014] In some embodiments of this disclosure, the preset configuration information includes: Routing control information, wherein the routing control information is used to characterize the preset processing mode corresponding to each preset physical interruption signal as either the first processing mode or the second processing mode; Security mask information, which is used to characterize whether the kernel operation passthrough state of each preset physical interrupt signal is disabled or enabled.

[0015] In this embodiment, routing control information and security mask information are used as preset configuration information. The routing control information and security mask information can be used to select and allocate preset processing modes for each preset physical interruption signal and independently control whether to disable the first processing mode. This ensures accurate mapping, real-time response, resource isolation and reliable operation when determining the target processing mode, and further improves the processing efficiency and flexibility of the target physical interruption signal.

[0016] In some embodiments of this disclosure, determining the target processing mode matching the target physical interruption signal based on preset configuration information includes: Based on the routing control information and the security mask information, the preset processing mode and the kernel pass-through state corresponding to the target physical interrupt signal are determined; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being enabled, the first processing mode is taken as the target processing mode; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being disabled, the second processing mode is set as the target processing mode; In response to the preset processing mode being the second processing mode, the second processing mode is taken as the target processing mode.

[0017] In this embodiment, based on routing control information and security mask information, the preset processing mode and kernel pass-through state corresponding to the target physical interrupt signal are determined. Based on different preset processing modes and kernel pass-through states, the first processing mode and the second processing mode are selected as the target processing mode. This allows the selection of the target processing mode to simultaneously take into account the target physical interrupt signal's allocation of preset processing modes and the independent control over whether to disable the first processing mode, which is beneficial to further improve the rationality and flexibility of the target processing mode.

[0018] In some embodiments of this disclosure, the preset configuration information further includes preset mapping information and global control information. The preset mapping information is used to generate first mapping information and second mapping information, and the global control information is used to control whether to prohibit the generation of the first virtual interrupt signal in the first processing mode.

[0019] In this embodiment, preset mapping information and global control information are used together with routing control information and security mask information as preset configuration information. The first mapping information and the second mapping information can be generated and the global control of whether to disable the first processing mode can be realized through preset mapping information and global control information, which further ensures the rationality and flexibility in determining the target processing mode and generating virtual interrupt signals, and improves the overall performance of the virtualization system.

[0020] In some embodiments of this disclosure, the routing control information, the security mask information, the preset mapping information, and the global control information are respectively stored in a third target register, a fourth target register, a fifth target register, and a sixth target register, and the third target register, the fourth target register, the fifth target register, and the sixth target register are all located in a general interrupt controller that is communicatively connected to the processor.

[0021] In this embodiment, a third, fourth, fifth, and sixth target registers are configured in the general-purpose interrupt controller, which is connected to the processor, to store routing control information, security mask information, preset mapping information, and global control information, respectively. This provides assurance for writing and reading the routing control information, security mask information, preset mapping information, and global control information, thereby providing a basis for determining the target processing mode and generating virtual interrupt signals. Storing the routing control information, security mask information, preset mapping information, and global control information required for interrupt processing in system registers ensures data integrity, security, and memory access speed, improves the efficiency and reliability of the interrupt mechanism, and further enhances the processing efficiency of target physical interrupt signals and the overall performance of the virtualization system.

[0022] In some embodiments of this disclosure, a seventh target register stores pass-through status information, which is used to characterize whether there is a first virtual interrupt signal generated based on the target physical interrupt signal and not processed. The seventh target register is located in a general interrupt controller that is communicatively connected to the processor.

[0023] In this embodiment, a seventh target register is set in the general interrupt controller that communicates with the processor to store pass-through status information, which provides a guarantee for reading the pass-through status information. The pass-through status information can record which target physical interrupt signals have been passed through to EL1 through the first processing mode but have not yet been processed, ensuring that unprocessed interrupt signals are correctly processed when switching virtual processing units, and further improving the overall performance of the virtualization system.

[0024] In some embodiments of this disclosure, the processor corresponds to multiple virtual processing units, and the interrupt signal processing method further includes: In response to a switching request for the virtual processing unit, a virtual unit switching process is performed to switch the current processing unit to the target processing unit; The virtual unit switching process includes: The generation of the first virtual interrupt signal is prohibited in the first processing mode; Save the preset configuration information and mapping information corresponding to the current processing unit to the first context information corresponding to the current processing unit; Wait for the processing of the first virtual interrupt signal corresponding to the current processing unit to be completed; Read the preset configuration information and mapping information corresponding to the target processing unit from the second context information corresponding to the target processing unit; The first virtual interrupt signal is allowed to be generated in the first processing mode; Execute the instructions corresponding to the target virtual unit.

[0025] In this embodiment, when a switching request for a virtual processing unit is detected, a virtual unit switching process is executed to switch the current processing unit to the target processing unit. This enables the switching of different virtual processing units when multiple virtual processing units share a single processor. The disabling and restoration of the first processing mode avoids erroneous routing caused by intermediate states during the switching process. Furthermore, the first and second context structures are used to save and restore preset configuration information and mapping information that match the virtual processing unit. This ensures that each virtual processing unit can control the routing conversion method of interrupt signals through the target processing mode, thereby improving the processing efficiency and flexibility of interrupt signals and the overall performance of the virtualization system.

[0026] In some embodiments of this disclosure, the target physical interrupt signal includes a private peripheral interrupt signal.

[0027] In this embodiment, the private peripheral interrupt signal is used as the target physical interrupt signal to ensure that the type and characteristics of the target physical interrupt signal can match the virtualization requirements, hardware and software collaboration and privilege permissions of the first processing mode and kernel running state. This provides a guarantee for the implementation of the first processing mode and improves the processing efficiency and flexibility of the private peripheral interrupt signal as well as the overall performance of the virtualization system.

[0028] According to a second aspect of the present disclosure, an interrupt signal processing apparatus is provided, applied to a processor, the processor being configured with a kernel running state and a virtual machine monitoring state, the interrupt signal processing apparatus comprising: The determining module is used to determine a target processing mode that matches the target physical interruption signal based on preset configuration information in response to the target physical interruption signal. The preset configuration information is used to characterize the preset processing modes corresponding to multiple preset physical interruption signals respectively. A first processing module is configured to, in response to the target processing mode being a first processing mode, generate a first virtual interrupt signal based on the target physical interrupt signal in the kernel running state of the processor, and process the first virtual interrupt signal in the kernel running state. The second processing module is configured to, in response to the target processing mode being the second processing mode, generate a second virtual interrupt signal based on the target physical interrupt signal in the virtual machine monitoring state of the processor, and process the second virtual interrupt signal in the kernel running state.

[0029] In some embodiments of this disclosure, the first processing module is further configured to: The processor generates the first virtual interrupt signal based on the target physical interrupt signal; The second processing module is also used for: The virtual machine monitor generates the second virtual interrupt signal based on the target physical interrupt signal.

[0030] In some embodiments of this disclosure, the preset configuration information includes: Routing control information, wherein the routing control information is used to characterize the preset processing mode corresponding to each preset physical interruption signal as either the first processing mode or the second processing mode; Security mask information, which is used to characterize whether the kernel operation passthrough state of each preset physical interrupt signal is disabled or enabled.

[0031] In some embodiments of this disclosure, the determining module is further configured to: Based on the routing control information and the security mask information, the preset processing mode and the kernel pass-through state corresponding to the target physical interrupt signal are determined; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being enabled, the first processing mode is taken as the target processing mode; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being disabled, the second processing mode is set as the target processing mode; In response to the preset processing mode being the second processing mode, the second processing mode is taken as the target processing mode.

[0032] In some embodiments of this disclosure, the processor corresponds to multiple virtual processing units, and the interrupt signal processing device further includes a switching module, the switching module being used for: In response to a switching request for the virtual processing unit, a virtual unit switching process is performed to switch the current processing unit to the target processing unit; The virtual unit switching process includes: The generation of the first virtual interrupt signal is prohibited in the first processing mode; Save the preset configuration information and mapping information corresponding to the current processing unit to the first context information corresponding to the current processing unit; Wait for the processing of the first virtual interrupt signal corresponding to the current processing unit to be completed; Read the preset configuration information and mapping information corresponding to the target processing unit from the second context information corresponding to the target processing unit; The first virtual interrupt signal is allowed to be generated in the first processing mode; Execute the instructions corresponding to the target virtual unit.

[0033] According to a third aspect of the present disclosure, an electronic device is provided, the electronic device comprising: processor; Memory used to store processor-executable instructions; The processor is configured to execute the interrupt signal processing method as described in the first aspect.

[0034] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the interrupt signal processing method as described in the first aspect.

[0035] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the interrupt signal processing method as described in the first aspect.

[0036] According to a sixth aspect of the present disclosure, a chip is provided, the chip being configured to perform the interrupt signal processing method as described in the first aspect.

[0037] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: by controlling the routing conversion method of interrupt signals through the target processing mode, the first processing mode and the second processing mode can respectively realize the pass-through and trap of interrupt signals. The first processing mode can reduce the performance overhead, response latency and cache pollution caused by frequent switching of processor state, i.e. privilege level. Different target physical interrupt signals can correspond to different target processing modes, and fine-grained routing control can be performed independently on each target physical interrupt signal, which is conducive to improving the processing efficiency and flexibility of interrupt signals, thereby improving the overall performance of the virtualization system.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0040] Figure 1 This is a flowchart illustrating an interrupt signal processing method according to an exemplary embodiment.

[0041] Figure 2 This is a flowchart illustrating, according to an exemplary embodiment, how a processor generates a first virtual interrupt signal based on a target physical interrupt signal.

[0042] Figure 3 This is a flowchart illustrating, according to an exemplary embodiment, how a virtual machine monitor generates a second virtual interrupt signal based on a target physical interrupt signal.

[0043] Figure 4 This is a flowchart illustrating, according to an exemplary embodiment, a target processing mode that matches a target physical interruption signal based on preset configuration information.

[0044] Figure 5 This is a flowchart illustrating a virtual unit switching process according to an exemplary embodiment.

[0045] Figure 6 This is a block diagram illustrating an interrupt signal processing apparatus according to an exemplary embodiment.

[0046] Figure 7 This is a block diagram of an electronic device according to an exemplary embodiment.

[0047] In the picture: 10 - Determining module; 20 - First processing module; 30 - Second processing module; 400 - Electronic device; 402 - Processing component; 404 - Memory; 406 - Power supply component; 408 - Multimedia component; 410 - Audio component; 412 - Input / output interface; 414 - Sensor component; 416 - Communication component; 420 - Processor. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0049] Interrupt signals, as control signals that notify a system process to stop its current operation and prioritize handling a specific task or event, are the foundation of interrupt mechanisms in computer systems used to achieve rapid response to asynchronous events and resource scheduling. Virtualization technology abstracts physical hardware into virtual resources to improve resource utilization, system reliability, and management flexibility, and has been widely applied in fields such as cloud computing, automotive electronics, edge computing, and embedded platforms. In virtualization systems, physical interrupt signals need to be converted into virtual interrupt signals and routed to the operating system corresponding to the virtual machine for processing.

[0050] In related technologies, all physical interrupt signals need to be processed in the processor's virtual machine monitor state. This means the processor must first trap into the virtual machine monitor state, generate a corresponding virtual interrupt signal via software, inject it into the virtual machine's operating system, and then return to the processor's kernel running state to process the virtual interrupt signal through the virtual machine's operating system. However, the interrupt signal processing methods using these technologies involve frequent switching between the kernel running state and the virtual machine monitor state during the routing, conversion, injection, and response processes. This results in excessive computational overhead for pipeline flushing and context switching, with response latency reaching the microsecond level. Furthermore, memory disturbances and cache pollution reduce instruction execution efficiency, thus affecting the interrupt signal processing efficiency and the overall performance of the virtualization system.

[0051] Based on this, this disclosure provides an interrupt signal processing method. When a target physical interrupt signal is identified, a target processing mode is determined according to preset configuration information. Depending on whether the target processing mode is a first processing mode or a second processing mode, a first virtual interrupt signal is generated in kernel running mode or a second virtual interrupt signal is generated in virtual machine monitoring mode. This allows for the processing of the first and second virtual interrupt signals in kernel running mode, realizing the routing, conversion, and response of interrupt signals in the virtualization system. By controlling the routing and conversion method of interrupt signals through the target processing mode, the first and second processing modes can respectively realize the pass-through and trapping of interrupt signals. The first processing mode can be used to reduce performance overhead, response latency, and cache pollution caused by frequent switching of processor states (i.e., privilege levels). Furthermore, different target physical interrupt signals can correspond to different target processing modes, enabling fine-grained routing control for each target physical interrupt signal independently. This is beneficial for improving the processing efficiency and flexibility of interrupt signals, thereby improving the overall performance of the virtualization system.

[0052] In one exemplary embodiment, an interrupt signal processing method is provided, applied to a processor or an electronic device configured with a processor. The processor is configured with a kernel running state and a virtual machine monitoring state, enabling the processor to provide hardware support for the operation of virtualization systems and virtual machines. The kernel running state and the virtual machine monitoring state are two different states of the processor, i.e., running modes, representing two privilege levels (Exception Levels) and virtualization levels of the processor. The kernel running state corresponds to the guest operating system kernel, i.e., kernel privilege level EL1, and the virtual machine monitoring state corresponds to the virtual machine monitor, i.e., virtualization privilege level EL2. The processor may also be configured with a user state, i.e., user-mode privilege level EL0.

[0053] refer to Figure 1 As shown, the interrupt signal handling method includes: S100. In response to the target physical interrupt signal, based on the preset configuration information, determine the target processing mode that matches the target physical interrupt signal. The preset configuration information is used to characterize the preset processing modes corresponding to multiple preset physical interrupt signals.

[0054] In step S100, the processor is configured with preset configuration information, which reflects the correspondence between multiple preset physical interrupt signals and multiple preset processing modes. Each preset physical interrupt signal has a corresponding preset processing mode, allowing different preset physical interrupt signals to correspond to different preset processing modes. The preset physical interrupt signal is a hardware-generated physical interrupt signal, and the preset processing mode is a routing conversion method for that physical interrupt signal.

[0055] When the processor identifies any target physical interrupt signal, it determines the target processing mode matching the target physical interrupt signal based on preset configuration information. This serves as the basis for subsequent routing of the target physical interrupt signal. For example, the target physical interrupt signal can be generated by triggering a timer expiration, and the type of the target physical interrupt signal can be selected according to requirements. The preset configuration information can be set and adjusted according to the fine-grained pass-through, security, and mapping requirements of the physical interrupt signal, and can be stored, for example, in a system register communicatively connected to the processor.

[0056] S200, in response to the target processing mode being the first processing mode, in the kernel running state of the processor, a first virtual interrupt signal is generated based on the target physical interrupt signal, and the first virtual interrupt signal is processed in the kernel running state.

[0057] In step S200, if the target processing mode determined according to the preset configuration information is the first processing mode, then the target physical interrupt signal is routed by passing through EL1. That is, in the kernel running state of the processor, a corresponding first virtual interrupt signal is generated according to the target physical interrupt signal, and the first virtual interrupt signal is processed directly in the kernel running state. This allows the processor to maintain the kernel running state, i.e., EL1, in the first processing mode, thereby providing a new direct path for the target physical interrupt signal that selects the first processing mode. This avoids frequent switching of the processor state, i.e., privilege level, and reduces the performance overhead, response latency, and cache pollution caused by frequent switching.

[0058] S300, in response to the target processing mode being the second processing mode, generates a second virtual interrupt signal based on the target physical interrupt signal under the virtual machine monitoring state of the processor, and processes the second virtual interrupt signal under the kernel running state.

[0059] In step S300, if the target processing mode determined according to the preset configuration information is the second processing mode, then the target physical interrupt signal is routed by trapping EL2. That is, in the virtual machine monitoring state of the processor, a corresponding second virtual interrupt signal is generated according to the target physical interrupt signal, and then the kernel running state is switched to process the second virtual interrupt signal. This makes the processor need to switch between the kernel running state and the virtual machine monitoring state, i.e., EL1 and EL2, in the second processing mode, thereby preserving the traditional trapping path for the target physical interrupt signal that selects the second processing mode.

[0060] For example, in the preset configuration information, preset physical interrupt signal A corresponds to the first processing mode, and preset physical interrupt signal B corresponds to the second processing mode. When the target physical interrupt signal is preset physical interrupt signal A, the first processing mode is selected to generate the first virtual interrupt signal in the kernel running state, bypassing the intervention of the Hypervisor, and injecting the first virtual interrupt signal into the Guest OS through the virtual processor interface. In the kernel running state, i.e., EL1, the first virtual interrupt signal is processed through the Guest OS. When the target physical interrupt signal is preset physical interrupt signal B, the second processing mode is selected to generate the second virtual interrupt signal in the virtual machine monitoring state, relying on the intervention of the Hypervisor, and switching to the kernel running state, i.e., EL1, through the Guest OS via the exception return (ERET) instruction, the second virtual interrupt signal is processed. After the processing of the first or second virtual interrupt signal is completed, if the first or second virtual interrupt signal is associated with the target physical interrupt signal through the hardware flag HW, the processor will automatically complete the deactivation of the target physical interrupt signal.

[0061] In this embodiment, when a target physical interrupt signal is detected, a target processing mode is determined based on preset configuration information. Depending on whether the target processing mode is a first processing mode or a second processing mode, a first virtual interrupt signal is generated in kernel running mode or a second virtual interrupt signal is generated in virtual machine monitoring mode. This allows for the processing of both the first and second virtual interrupt signals in kernel running mode, realizing the routing, conversion, and response of interrupt signals within the virtualization system. By controlling the routing conversion method of interrupt signals through the target processing mode, the first and second processing modes can respectively achieve interrupt signal pass-through and trapping. The first processing mode can reduce performance overhead, response latency, and cache pollution caused by frequent switching of processor states (privilege levels). Furthermore, different target physical interrupt signals can correspond to different target processing modes, enabling independent fine-grained routing control for each target physical interrupt signal. This improves the processing efficiency and flexibility of interrupt signals, thereby enhancing the overall performance of the virtualization system.

[0062] In some embodiments, generating a first virtual interrupt signal based on a target physical interrupt signal includes: having a processor generate a first virtual interrupt signal based on a target physical interrupt signal.

[0063] When the target processing mode is the first processing mode, the processor needs to generate the first virtual interrupt signal based on the target physical interrupt signal. That is, the target physical interrupt signal is routed and converted through EL1 in hardware, and the resulting first virtual interrupt signal is injected into the Guest OS.

[0064] Generating a second virtual interrupt signal based on the target physical interrupt signal includes: generating a second virtual interrupt signal based on the target physical interrupt signal using a virtual machine monitor.

[0065] When the target processing mode is the second processing mode, the virtual machine monitoring program corresponding to the virtual machine monitoring state needs to generate a second virtual interrupt signal based on the target physical interrupt signal. That is, the target physical interrupt signal is routed and converted by trapping EL2 in software, and the resulting second virtual interrupt signal is injected into the passenger operating system GuestOS.

[0066] In this implementation, the processor generates a first virtual interrupt signal based on the target physical interrupt signal in the first processing mode and kernel running state, and the virtual machine monitor generates a second virtual interrupt signal based on the target physical interrupt signal in the second processing mode and virtual machine monitoring state. This enables the first and second processing modes to achieve interrupt signal pass-through and trapping through hardware and software respectively. It can simplify the transmission path, improve response speed, reduce performance loss and improve compatibility by using hardware mechanisms while retaining conventional software mechanisms, thereby further improving the overall performance of the virtualization system.

[0067] In some embodiments, reference Figure 2 As shown, the processor generates a first virtual interrupt signal based on the target physical interrupt signal, including: S210. Prevent switching from kernel running state to virtual machine monitoring state.

[0068] In step S210, when the target processing mode is the first processing mode, and the processor generates the first virtual interrupt signal in the kernel running state, it is necessary to first prevent the processor from switching from the kernel running state to the virtual machine monitoring state in order to suppress the target physical interrupt signal from falling into EL2 and ensure that the processor is always in the kernel running state, i.e., EL1, so as to avoid the switching of privilege level and context.

[0069] S220. Generate first mapping information, which is used to convert physical interrupt signals into virtual interrupt signals.

[0070] S230. Based on the target physical interrupt signal and the first mapping information, generate the first virtual interrupt signal.

[0071] In steps S220 and S230, first mapping information corresponding to the target physical interrupt signal is generated. The first mapping information is used to convert the physical interrupt signal into a virtual interrupt signal and can serve as the basis for converting the target physical interrupt signal into a first virtual interrupt signal. Based on the target physical interrupt signal and the first mapping information, the first virtual interrupt signal is generated, thus realizing the hardware routing conversion method of passing through EL1.

[0072] refer to Figure 3 As shown, the virtual machine monitor generates a second virtual interrupt signal based on the target physical interrupt signal, including: S310. Generate second mapping information, which is used to convert physical interrupt signals into virtual interrupt signals.

[0073] S320: Generate a second virtual interrupt signal based on the target physical interrupt signal and the second mapping information.

[0074] In steps S310 and S320, when the target processing mode is the second processing mode, and the virtual machine monitoring program generates the second virtual interrupt signal in the virtual machine monitoring state, the second mapping information corresponding to the target physical interrupt signal is generated. The second mapping information is used to convert the physical interrupt signal into a virtual interrupt signal and can be used as the basis for converting the target physical interrupt signal into the second virtual interrupt signal. Then, based on the target physical interrupt signal and the second mapping information, the second virtual interrupt signal is generated, thus realizing the software routing conversion method of EL2 trap.

[0075] For example, the first mapping information and the second mapping information can be generated based on the target physical interrupt signal and the preset mapping information in the preset configuration information. The first mapping information and the second mapping information may include the flag bit pINTID of the target physical interrupt signal, the flag bit vINTID of the virtual interrupt signal corresponding to the target physical interrupt signal, the hardware flag bit HW indicating whether the target physical interrupt signal and the virtual interrupt signal are linked, the flag bit vPriority indicating the priority of the virtual interrupt, and the state flag bit State indicating the signal processing state.

[0076] In this embodiment, by disabling the switch from kernel running state to virtual machine monitoring state and generating first mapping information, a first virtual interrupt signal is generated based on the target physical interrupt signal and the first mapping information. Furthermore, by generating second mapping information and generating a second virtual interrupt signal based on the target physical interrupt signal and the second mapping information, the conversion of the target physical interrupt signal can be achieved through both hardware-based pass-through EL1 and software-based trap EL2 methods. Using the first and second mapping information as the basis for generating the first and second virtual interrupt signals respectively ensures accurate mapping, real-time response, resource isolation, and reliable operation when converting physical interrupt signals to virtual interrupt signals, further improving the processing efficiency and flexibility of the target physical interrupt signal.

[0077] In some embodiments, the first mapping information is stored in the first target register, and the second mapping information is stored in the second target register. Both the first target register and the second target register are located in a general interrupt controller that is communicatively connected to the processor.

[0078] The Generic Interrupt Controller (GIC), which communicates with the processor, is the core component for managing interrupt signals. System registers can be configured in the GIC's virtualized interface to store the information needed to manage interrupt signals. The GIC has a first destination register and a second destination register. The first destination register stores first mapping information, and the second destination register stores second mapping information.

[0079] When generating the first mapping information, the first target register can be automatically filled according to the preset mapping information and written into the first target register to provide a basis for the generation of the first virtual interrupt signal. When generating the second mapping information, the second target register can be automatically filled according to the preset mapping information and written into the second target register to provide a basis for the generation of the second virtual interrupt signal.

[0080] For example, the second destination register may include a register set List Register (ICH_LR0_EL2~ICH_LR15_EL2), and the first destination register may include a dedicated register List Register (ICH_HLR_EL2) independent of the second destination register. Flags pINTID, vINTID, HW, vPriority, and State can all be fields written to the first destination register (i.e., the first mapping information) and fields written to the second destination register (i.e., the second mapping information). In this embodiment, a first target register and a second target register are configured in the general-purpose interrupt controller that communicates with the processor to store the first mapping information and the second mapping information, respectively. This provides a guarantee for writing and reading the first and second mapping information, thereby providing a basis for generating the first and second virtual interrupt signals. Storing the first and second mapping information required for interrupt processing through system registers ensures data integrity, security, and memory access speed, improving the efficiency and reliability of the interrupt mechanism. Furthermore, configuring independent first and second target registers for the first and second mapping information respectively avoids mutual occupation of register resources, ensuring the stability of the interrupt mechanism and further improving the processing efficiency of the target physical interrupt signal and the overall performance of the virtualization system.

[0081] In some embodiments, determining a target processing mode that matches a target physical interrupt signal based on preset configuration information includes: in response to satisfying preset control conditions, determining a target processing mode that matches a target physical interrupt signal based on preset configuration information, wherein the preset control conditions include the processor being in virtual machine monitoring state and the signal type of the target physical interrupt signal being a target type.

[0082] Before determining the target processing mode that matches the target physical interruption signal based on the preset configuration information, it is necessary to first determine whether the current situation meets the preset control conditions. If the preset control conditions are met, it means that the current scenario is suitable for the selection and application of the target processing mode, and the routing conversion method of the interruption signal is controlled by the target processing mode. If the preset control conditions are not met, it means that the current scenario is not suitable for the selection and application of the target processing mode, and the interruption signal can be processed or alarmed according to other rules or logic.

[0083] The processor can be in virtual machine monitoring state, and the target physical interrupt signal type can be set as the target type as the preset control condition. The preset control condition can check whether the current environment is virtualized and whether the identified physical interrupt signal can be used as the target physical interrupt signal. This ensures that the current scenario when controlling the routing conversion method of the interrupt signal through the target processing mode can match the scenario requirements of the interrupt signal processing process, thereby ensuring the smooth execution of the interrupt signal processing process.

[0084] For example, the processor can query the status flag current_EL and the exception flag HCR_EL2.IMO in the system register. When current_EL=EL2 and HCR_EL2.IMO=1, it means that the processor is currently in a virtualization environment and is in virtual machine monitoring mode. It also checks whether the signal type of the physical interrupt signal matches the target type of private peripheral interrupt signal. Based on whether the processor is in virtual machine monitoring mode and whether the signal type of the target physical interrupt signal is the target type, it determines whether the preset control conditions are met.

[0085] In this embodiment, the processor is in virtual machine monitoring state and the signal type of the target physical interrupt signal is the target type as a preset control condition. The satisfaction of the preset control condition is used as the selection condition for the target processing mode and the trigger condition for the application. The preset control condition is used to check the current scene when the target physical interrupt signal is identified, so that the current scene can match the scene requirements of the first processing mode and the second processing mode, ensuring the smooth execution of the interrupt signal processing process.

[0086] In some embodiments, the preset configuration information includes routing control information and security mask information. The routing control information is used to characterize the preset processing mode corresponding to each preset physical interrupt signal as either a first processing mode or a second processing mode. The security mask information is used to characterize the kernel operation passthrough state of each preset physical interrupt signal as either disabled or enabled.

[0087] The preset configuration information used to characterize the correspondence between preset physical interruption signals and preset processing modes may include routing control information and security mask information. The routing control information can reflect whether the preset processing mode corresponding to each preset physical interruption signal is the first processing mode or the second processing mode, so as to realize the selection and allocation of the processing mode for each preset physical interruption signal.

[0088] The security mask information can reflect whether the kernel operation passthrough state of each preset physical interrupt signal is disabled or enabled, so as to realize independent control over whether each preset physical interrupt signal is allowed to pass through EL1, that is, whether each preset physical interrupt signal is allowed to generate the first virtual interrupt signal in the kernel operation state in the corresponding first processing mode, thereby preventing critical preset physical interrupt signals, such as preset physical interrupt signals that must be processed in the second processing mode for security reasons, from being improperly configured.

[0089] For example, the routing control information may include a routing flag bit [N] for a preset physical interrupt signal, where N is the interrupt signal identifier INTID corresponding to the preset physical interrupt signal, bit

[27] corresponds to the preset physical interrupt signal INTID27 triggered by the virtual timer, and bit

[30] corresponds to the preset physical interrupt signal INTID30 triggered by the physical timer. When the routing flag bit [N] = 0, it means that the preset processing mode corresponding to the preset physical interrupt signal is the first processing mode, i.e., the pass-through mode; when the routing flag bit [N] = 1, it means that the preset processing mode corresponding to the preset physical interrupt signal is the second processing mode, i.e., the trap mode.

[0090] Security mask information may include, for example, a security flag bit [N] for preset physical interrupt signals. When security flag bit [N] = 0, the kernel passthrough state is disabled, prohibiting the processing of the target physical interrupt signal in both the first processing mode and the kernel running state, and prohibiting the first processing mode from being used as the target processing mode. When security flag bit [N] = 1, the kernel passthrough state is enabled, allowing the processing of the target physical interrupt signal in both the first processing mode and the kernel running state, and allowing the first processing mode to be used as the target processing mode. The security mask information can be configured and locked once during the initialization phase to prevent tampering during runtime.

[0091] In this embodiment, routing control information and security mask information are used as preset configuration information. The routing control information and security mask information can be used to select and allocate preset processing modes for each preset physical interruption signal and independently control whether to disable the first processing mode. This ensures accurate mapping, real-time response, resource isolation and reliable operation when determining the target processing mode, and further improves the processing efficiency and flexibility of the target physical interruption signal.

[0092] In some embodiments, reference Figure 4 As shown, based on preset configuration information, a target processing mode matching the target physical interruption signal is determined, including: S110. Based on routing control information and security mask information, determine the preset processing mode and kernel passthrough state corresponding to the target physical interrupt signal.

[0093] In step S110, based on the routing control information in the preset configuration information, it is determined whether the preset processing mode corresponding to the preset physical interrupt signal, which is the target physical interrupt signal, is the first processing mode or the second processing mode. Based on the security mask information in the preset configuration information, it is determined whether the kernel running passthrough state corresponding to the preset physical interrupt signal, which is the target physical interrupt signal, is the disabled state or the enabled state.

[0094] S120. In response to the preset processing mode being the first processing mode and the kernel running pass-through state being enabled, the first processing mode is set as the target processing mode.

[0095] In step S120, if the preset processing mode corresponding to the target physical interrupt signal is the first processing mode, and the kernel passthrough state is enabled, it means that the first processing mode has been selected and allocated for the target physical interrupt signal, and the target physical interrupt signal is allowed to select the first processing mode. Then, the first processing mode is taken as the target processing mode corresponding to the target physical interrupt signal. For example, when the routing flag bit [N] of the target physical interrupt signal is 1 and the security flag bit [N] is 1, the target processing mode is determined to be the first processing mode.

[0096] S130. In response to the preset processing mode being the first processing mode and the kernel running passthrough state being disabled, the second processing mode is set as the target processing mode.

[0097] In step S130, if the preset processing mode corresponding to the target physical interrupt signal is the first processing mode, and the kernel passthrough state is disabled, it means that the first processing mode has been selected and allocated for the target physical interrupt signal. However, for security reasons, the first processing mode is prohibited for the target physical interrupt signal. In this case, the second processing mode is used as the target processing mode corresponding to the target physical interrupt signal. For example, when the routing flag bit [N] of the target physical interrupt signal is 1 and the security flag bit [N] is 0, the target processing mode is determined to be the second processing mode.

[0098] S140. In response to the preset processing mode being the second processing mode, the second processing mode is used as the target processing mode.

[0099] In step S140, if the preset processing mode corresponding to the target physical interrupt signal is the second processing mode, it means that the second processing mode has been selected and allocated for the target physical interrupt signal. Therefore, it is no longer necessary to consider its kernel passthrough state, and the second processing mode is directly used as the target processing mode corresponding to the target physical interrupt signal. For example, when the routing flag bit[N] of the target physical interrupt signal is 0, the target processing mode is determined to be the second processing mode.

[0100] In this embodiment, based on routing control information and security mask information, the preset processing mode and kernel pass-through state corresponding to the target physical interrupt signal are determined. Based on different preset processing modes and kernel pass-through states, the first processing mode and the second processing mode are selected as the target processing mode. This allows the selection of the target processing mode to simultaneously take into account the target physical interrupt signal's allocation of preset processing modes and the independent control over whether to disable the first processing mode, which is beneficial to further improve the rationality and flexibility of the target processing mode.

[0101] In some embodiments, the preset configuration information further includes preset mapping information and global control information. The preset mapping information is used to generate first mapping information and second mapping information, and the global control information is used to control whether to prohibit the generation of the first virtual interrupt signal in the first processing mode.

[0102] In addition to routing control information and security mask information, the preset configuration information also includes preset mapping information and global control information. The preset mapping information is used to generate the first mapping information and the second mapping information. The first mapping information and the second mapping information can be generated based on the preset mapping information to provide a basis for the generation of the first virtual interrupt signal and the second virtual interrupt signal.

[0103] Global control information is used to control whether to prohibit the generation of the first virtual interrupt signal in the first processing mode, that is, whether to prohibit all target physical interrupt signals from selecting the first processing mode as the target processing mode, thereby controlling the global enabling and disabling of the pass-through function. When the generation of the first virtual interrupt signal is prohibited in the first processing mode, the second virtual interrupt signal must be generated in the second processing mode and the virtual machine monitoring state. This enables the global control information to provide atomic global switching capabilities during virtual processing unit context switching, simultaneously disabling the pass-through of all target physical interrupt signals and avoiding incorrect routing of interrupt signals due to intermediate states during switching.

[0104] For example, the preset mapping information may include a flag bit vINTID for the virtual interrupt signal corresponding to each preset physical interrupt signal, a flag bit vPriority indicating the priority of the virtual interrupt, and an enable flag bit Enable controlling whether to convert the physical interrupt signal into a virtual interrupt signal. When generating the first mapping information and the second mapping information based on the preset mapping information, the flag bits vINTID and vPriority in the preset mapping information can be read and written to the first destination register or the second destination register.

[0105] Global control information may include, for example, the global control flag PPIDE. When PPIDE=0, all target physical interrupt signals are prohibited from selecting the first processing mode, thus preventing the generation of the first virtual interrupt signal in the first processing mode. When PPIDE=1, all target physical interrupt signals are allowed to select the first processing mode, thus allowing the generation of the first virtual interrupt signal in the first processing mode. Therefore, when the global control information is used as the preset configuration information, the target processing mode can only be determined to be the first processing mode when the routing flag bit [N]=1, the security flag bit [N]=1, and PPIDE=1.

[0106] In this embodiment, preset mapping information and global control information are used together with routing control information and security mask information as preset configuration information. The first mapping information and the second mapping information can be generated and the global control of whether to disable the first processing mode can be realized through preset mapping information and global control information, which further ensures the rationality and flexibility in determining the target processing mode and generating virtual interrupt signals, and improves the overall performance of the virtualization system.

[0107] In some embodiments, routing control information, security mask information, preset mapping information, and global control information are stored in a third target register, a fourth target register, a fifth target register, and a sixth target register, respectively. The third target register, the fourth target register, the fifth target register, and the sixth target register are all located in a general interrupt controller that is communicatively connected to the processor.

[0108] The general-purpose interrupt controller also includes a third, fourth, fifth, and sixth target registers, which can store routing control information, security mask information, preset mapping information, and global control information, respectively. When determining the target processing mode, routing control information, security mask information, and global control information can be read from the third, fourth, and sixth target registers to provide a basis for determining the target processing mode. When generating the first and second virtual interrupt signals, preset mapping information is read from the fifth target register to provide a basis for generating the first and second mapping information.

[0109] For example, the third destination register may include a routing control register (ICH_PPI_ROUTE_EL2), where the routing flag bit [N] can be written as a field to the third destination register. The third destination register can be set to 64 bits, including routing flag bits divided into standard control bits and extended control bits, as well as reserved bits. The third destination register is only accessible in virtual machine monitoring state, i.e., EL2. The fourth destination register may include a security mask register (ICH_PPI_ROUTE_MASK_EL2), where the security flag bit [N] can be written as a field to the fourth destination register. The fourth destination register can be set to 64 bits to match the third destination register. The fifth destination register may include a mapping register group (ICH_PPI_VMAP_EL2[N]), where the vINTID flag, vPriority flag, and Enable flag can be written as fields to the fifth destination register, and reserved bits are set in each mapping register. The sixth destination register may include a system register (ICH_HCR_EL2.PPIDE), where the global control flag bit PPIDE can be added as a control bit to the system register.

[0110] In this embodiment, a third, fourth, fifth, and sixth target registers are configured in the general-purpose interrupt controller, which is connected to the processor, to store routing control information, security mask information, preset mapping information, and global control information, respectively. This provides assurance for writing and reading the routing control information, security mask information, preset mapping information, and global control information, thereby providing a basis for determining the target processing mode and generating virtual interrupt signals. Storing the routing control information, security mask information, preset mapping information, and global control information required for interrupt processing in system registers ensures data integrity, security, and memory access speed, improves the efficiency and reliability of the interrupt mechanism, and further enhances the processing efficiency of target physical interrupt signals and the overall performance of the virtualization system.

[0111] In some embodiments, the seventh target register stores pass-through status information, which is used to characterize whether there is a first virtual interrupt signal generated based on the target physical interrupt signal and not processed. The seventh target register is located in a general interrupt controller that is communicatively connected to the processor.

[0112] The general-purpose interrupt controller also includes a seventh target register, which stores pass-through status information. This information reflects whether there is a first virtual interrupt signal generated from a target physical interrupt signal but not yet processed. Specifically, it indicates whether each target physical interrupt signal has a first virtual interrupt signal generated in the first pass-through mode that has not yet been responded to. This pass-through status information allows the hypervisor to query the interrupt signal status during virtual processing unit scheduling and switching.

[0113] For example, the pass-through status information may include a pass-through status flag bit[N]. When the pass-through status flag bit[N]=1, it indicates that the target physical interrupt signal INTIDN has a corresponding first virtual interrupt signal that has not been processed. When the pass-through status flag bit[N]=0, it indicates that the target physical interrupt signal INTIDN does not have a corresponding first virtual interrupt signal that has not been processed. The seventh destination register may include a pass-through status register (ICH_PPI_DIRECT_STATUS_EL2). The pass-through status flag bit can be used as a field to be written to the seventh destination register, and the seventh destination register is read-only.

[0114] In this embodiment, a seventh target register is set in the general interrupt controller that communicates with the processor to store pass-through status information, which provides a guarantee for reading the pass-through status information. The pass-through status information can record which target physical interrupt signals have been passed through to EL1 through the first processing mode but have not yet been processed, ensuring that unprocessed interrupt signals are correctly processed when switching virtual processing units, and further improving the overall performance of the virtualization system.

[0115] In some embodiments, the processor corresponds to multiple virtual processing units, and the interrupt signal processing method further includes: in response to a switching request for a virtual processing unit, performing a virtual unit switching process to switch the current processing unit to the target processing unit.

[0116] The processor corresponds to multiple virtual processing units (vCPUs), meaning that multiple virtual processing units share the processor, allowing the processor to support the operation of only one virtual processing unit at a time. When a switching request for a virtual processing unit is detected, the processor needs to execute the corresponding virtual unit switching process to switch the currently running processing unit to the target processing unit that needs to be run next.

[0117] refer to Figure 5 As shown, the virtual unit switching process includes: S410, Prohibit the generation of the first virtual interrupt signal in the first processing mode.

[0118] In step S410, at the start of the virtual unit switching process, it is necessary to prevent all target physical interrupt signals from selecting the first processing mode to generate the first virtual interrupt signal in the kernel running state, so as to avoid intermediate states during the switching process that could lead to incorrect routing of interrupt signals.

[0119] S420. Save the preset configuration information and mapping information corresponding to the current processing unit to the first context information corresponding to the current processing unit.

[0120] In step S420, the preset configuration information, first mapping information and second mapping information corresponding to the current processing unit are saved to the first context information corresponding to the current processing unit to ensure the stable operation of the interrupt handling mechanism in the current processing unit after switching back to the current processing unit.

[0121] S430, Wait for the first virtual interrupt signal corresponding to the current processing unit to be processed.

[0122] In step S430, the system waits for the unprocessed first virtual interrupt signal in the current processing unit to be processed, ensuring that each unprocessed first virtual interrupt signal is correctly processed before switching virtual processing units.

[0123] S440: Read the preset configuration information and mapping information corresponding to the target processing unit from the second context information corresponding to the target processing unit.

[0124] In step S440, the second context information corresponding to the target processing unit stores the preset configuration information and mapping information corresponding to the target processing unit. The preset configuration information and mapping information corresponding to the target processing unit are read from the second context information to provide a basis for the implementation of the interrupt handling mechanism.

[0125] S450, allows the generation of a first virtual interrupt signal in the first processing mode.

[0126] In step S450, the restriction on generating the first virtual interrupt signal in the first processing mode is lifted, so that the target virtual unit can continue to control the routing and conversion of the interrupt signal through the target processing mode during operation.

[0127] S460, Execute the instructions corresponding to the target virtual unit.

[0128] In step S460, the processor executes the instructions corresponding to the target virtual unit, enabling the processor to switch to the target processing unit to continue executing the interrupt signal processing method shown in the above embodiments.

[0129] For example, during the virtual unit switching process, the global control flag PPIDE is first configured to 0 to prevent all target physical interrupt signals from generating the first virtual interrupt signal in the kernel running state by selecting the first processing mode. The fields in the routing control register, security mask register, and dedicated registers—namely, the preset configuration information and mapping information—are written into the context structure of the current processing unit vCPU_A and stored in memory. Then, based on the pass-through status flag Bit[N], it is checked whether there are any unprocessed first virtual interrupt signals waiting to be processed, and the fields in the routing control register, security mask register, and dedicated registers are cleared. Next, the preset configuration information and mapping information of the target processing unit vCPU_B are read from the context structure of the target processing unit vCPU_B, rewritten to the routing control register, security mask register, and dedicated registers, and the global control flag PPIDE is configured to 1. Finally, an exception handling return instruction switches to the target processing unit vCPU_B to execute the instruction stream of the target processing unit vCPU_B.

[0130] In this embodiment, when a switching request for a virtual processing unit is detected, a virtual unit switching process is executed to switch the current processing unit to the target processing unit. This enables the switching of different virtual processing units when multiple virtual processing units share a single processor. The disabling and restoration of the first processing mode avoids erroneous routing caused by intermediate states during the switching process. Furthermore, the first and second context structures are used to save and restore preset configuration information and mapping information that match the virtual processing unit. This ensures that each virtual processing unit can control the routing conversion method of interrupt signals through the target processing mode, thereby improving the processing efficiency and flexibility of interrupt signals and the overall performance of the virtualization system.

[0131] In some embodiments, the target physical interrupt signal includes a private peripheral interrupt signal.

[0132] Private Peripheral Interrupt (PPI) signals are interrupt signals that are associated only with a specific processor core and are not shared with other processor cores. They are characterized by flexible triggering methods, diverse application scenarios, and high response efficiency. PPI signals can be used as target physical interrupt signals. When the processor recognizes a PPI signal, it determines the target processing mode that matches the PPI signal based on preset configuration information, and then selects either a pass-through or trap approach to route the PPI signal according to the target processing mode.

[0133] In this case, for other non-target physical interrupt signals besides private peripheral interrupt signals, such as shared peripheral interrupt (SPI) signals, the second processing mode is automatically used as the target processing mode to route the shared peripheral interrupt signal through a trap. That is, the second virtual interrupt signal is generated in the virtual machine monitoring state and processed in the kernel running state.

[0134] In this embodiment, the private peripheral interrupt signal is used as the target physical interrupt signal to ensure that the type and characteristics of the target physical interrupt signal can match the virtualization requirements, hardware and software collaboration and privilege permissions of the first processing mode and kernel running state. This provides a guarantee for the implementation of the first processing mode and improves the processing efficiency and flexibility of the private peripheral interrupt signal as well as the overall performance of the virtualization system.

[0135] In one exemplary embodiment, an interrupt signal processing device is provided, applied to a processor, the processor being configured with a kernel running state and a virtual machine monitoring state, referenced to... Figure 6 As shown, the interrupt signal processing device includes a determining module 10, a first processing module 20, and a second processing module 30. The determining module 10, in response to a target physical interrupt signal, determines a target processing mode matching the target physical interrupt signal based on preset configuration information. The preset configuration information characterizes preset processing modes corresponding to multiple preset physical interrupt signals. The first processing module 20, in response to the target processing mode being the first processing mode, generates a first virtual interrupt signal based on the target physical interrupt signal and processes the first virtual interrupt signal in the kernel running state of the processor. The second processing module 30, in response to the target processing mode being the second processing mode, generates a second virtual interrupt signal based on the target physical interrupt signal and processes the second virtual interrupt signal in the kernel running state of the processor.

[0136] In this embodiment, when a target physical interrupt signal is detected, the determining module 10 determines the target processing mode based on preset configuration information. Depending on whether the target processing mode is the first processing mode or the second processing mode, it selects to generate either the first virtual interrupt signal via the first processing module 20 in kernel running mode or the second virtual interrupt signal via the second processing module 30 in virtual machine monitoring mode. This allows for the processing of both the first and second virtual interrupt signals in kernel running mode, realizing the routing, conversion, and response of interrupt signals within the virtualization system. By controlling the routing conversion method of interrupt signals through the target processing mode, the first and second processing modes can respectively achieve interrupt signal pass-through and trapping. The first processing mode can reduce performance overhead, response latency, and cache pollution caused by frequent switching of processor states (privilege levels). Furthermore, different target physical interrupt signals can correspond to different target processing modes, enabling independent fine-grained routing control for each target physical interrupt signal. This improves the processing efficiency and flexibility of interrupt signals, thereby enhancing the overall performance of the virtualization system.

[0137] In one embodiment, the first processing module 20 is further configured to: generate a first virtual interrupt signal based on the target physical interrupt signal using a processor; the second processing module 30 is further configured to: generate a second virtual interrupt signal based on the target physical interrupt signal using a virtual machine monitor.

[0138] In one embodiment, the first processing module 20 is further configured to: prevent switching from the kernel running state to the virtual machine monitoring state; generate first mapping information, the first mapping information being used to convert physical interrupt signals into virtual interrupt signals; and generate a first virtual interrupt signal based on the target physical interrupt signal and the first mapping information; the second processing module 30 is further configured to: generate second mapping information, the second mapping information being used to convert physical interrupt signals into virtual interrupt signals; and generate a second virtual interrupt signal based on the target physical interrupt signal and the second mapping information.

[0139] In one embodiment, the first mapping information is stored in a first target register, and the second mapping information is stored in a second target register. Both the first target register and the second target register are located in a general interrupt controller that is communicatively connected to the processor.

[0140] In one embodiment, the determining module 10 is further configured to: in response to satisfying preset control conditions, determine a target processing mode that matches the target physical interrupt signal based on preset configuration information, wherein the preset control conditions include the processor being in virtual machine monitoring state and the signal type of the target physical interrupt signal being the target type.

[0141] In one embodiment, the preset configuration information includes: routing control information, which is used to characterize the preset processing mode corresponding to each preset physical interrupt signal as either a first processing mode or a second processing mode; and security mask information, which is used to characterize the kernel operation passthrough state of each preset physical interrupt signal as either a disabled state or an enabled state.

[0142] In one embodiment, the determining module 10 is further configured to: determine the preset processing mode and kernel pass-through state corresponding to the target physical interrupt signal based on routing control information and security mask information; in response to the preset processing mode being the first processing mode and the kernel pass-through state being enabled, use the first processing mode as the target processing mode; in response to the preset processing mode being the first processing mode and the kernel pass-through state being disabled, use the second processing mode as the target processing mode; and in response to the preset processing mode being the second processing mode, use the second processing mode as the target processing mode.

[0143] In one embodiment, the preset configuration information further includes preset mapping information and global control information. The preset mapping information is used to generate first mapping information and second mapping information, and the global control information is used to control whether to prohibit the generation of the first virtual interrupt signal in the first processing mode.

[0144] In one embodiment, routing control information, security mask information, preset mapping information, and global control information are stored in a third target register, a fourth target register, a fifth target register, and a sixth target register, respectively. The third target register, the fourth target register, the fifth target register, and the sixth target register are all located in a general interrupt controller that is communicatively connected to the processor.

[0145] In one embodiment, the seventh target register stores pass-through status information, which is used to characterize whether there is a first virtual interrupt signal generated based on the target physical interrupt signal and not processed. The seventh target register is located in a general interrupt controller that is communicatively connected to the processor.

[0146] In one embodiment, the interrupt signal processing device further includes a switching module, which is configured to: in response to a switching request for a virtual processing unit, execute a virtual unit switching process to switch the current processing unit to a target processing unit; the virtual unit switching process includes: disabling the generation of a first virtual interrupt signal in a first processing mode; saving preset configuration information and mapping information corresponding to the current processing unit to a first context information corresponding to the current processing unit; waiting for the processing of the first virtual interrupt signal corresponding to the current processing unit to be completed; reading the preset configuration information and mapping information corresponding to the target processing unit from the second context information corresponding to the target processing unit; allowing the generation of a first virtual interrupt signal in the first processing mode; and executing the instruction corresponding to the target virtual unit.

[0147] In one embodiment, the target physical interrupt signal includes a private peripheral interrupt signal.

[0148] In one exemplary embodiment, an electronic device is provided. The electronic device may include, for example, a server host, a cloud host, or a terminal device such as a mobile phone or tablet computer. The electronic device is configured with a processor, and the electronic device is able to execute the interrupt signal processing method shown in the above embodiments or combinations thereof through the processor.

[0149] refer to Figure 7 As shown, the electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0150] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0151] Memory 404 is configured to store various types of data to support the operation of electronic device 400. Examples of such data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, videos, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0152] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0153] Multimedia component 408 includes a screen that provides an output interface between electronic device 400 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera module and / or a rear-facing camera module. When electronic device 400 is in an operating mode, such as shooting mode or video mode, the front-facing camera module and / or rear-facing camera module may receive external multimedia data. Each front-facing camera module and rear-facing camera module may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0154] Audio component 410 is configured to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) configured to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0155] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0156] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may receive the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0157] Communication component 416 is configured to facilitate wired or wireless communication between electronic device 400 and other terminals. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0158] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods shown in the above embodiments or combinations thereof.

[0159] In one exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the methods shown in the above embodiments or combinations thereof. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage terminal, etc. When the instructions in the storage medium are executed by the processor of the terminal, the terminal is able to perform the methods shown in the above embodiments or combinations thereof.

[0160] In one exemplary embodiment, a computer program product is provided, including a computer program or instructions that, when executed by a processor, implement the methods shown in the above embodiments or combinations thereof.

[0161] In one exemplary embodiment, a chip is provided, which is configured to perform the methods shown in the above embodiments or combinations thereof.

[0162] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0163] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0164] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0165] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0166] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0167] The examples in this document may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and rules. In the examples, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, when implementing each example, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained through appropriate means, in accordance with relevant laws and regulations. The specific methods of notification and / or authorization can vary depending on the actual situation and application scenario; the scope of the solution is not limited in this regard.

[0168] In this manual and the sample solutions, any processing of personal information will be conducted only under legal grounds (such as obtaining the consent of the data subject or being necessary for the performance of a contract) and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

Claims

1. An interrupt signal processing method, characterized in that, Applied to a processor, the processor being configured with a kernel running state and a virtual machine monitoring state, the interrupt signal handling method includes: In response to a target physical interruption signal, a target processing mode matching the target physical interruption signal is determined based on preset configuration information, wherein the preset configuration information is used to characterize the preset processing modes corresponding to multiple preset physical interruption signals respectively; In response to the target processing mode being a first processing mode, in the kernel running state of the processor, a first virtual interrupt signal is generated based on the target physical interrupt signal, and the first virtual interrupt signal is processed in the kernel running state; In response to the target processing mode being the second processing mode, in the virtual machine monitoring state of the processor, a second virtual interrupt signal is generated based on the target physical interrupt signal, and the second virtual interrupt signal is processed in the kernel running state.

2. The interrupt signal processing method according to claim 1, characterized in that, The step of generating a first virtual interrupt signal based on the target physical interrupt signal includes: The processor generates the first virtual interrupt signal based on the target physical interrupt signal; The generation of the second virtual interrupt signal based on the target physical interrupt signal includes: The virtual machine monitor generates the second virtual interrupt signal based on the target physical interrupt signal.

3. The interrupt signal processing method according to claim 2, characterized in that, The step of generating the first virtual interrupt signal based on the target physical interrupt signal by the processor includes: Switching from the kernel running state to the virtual machine monitoring state is prohibited; Generate first mapping information, which is used to convert physical interrupt signals into virtual interrupt signals; The first virtual interrupt signal is generated based on the target physical interrupt signal and the first mapping information; The step of generating the second virtual interrupt signal based on the target physical interrupt signal using a virtual machine monitor includes: Generate second mapping information, which is used to convert physical interrupt signals into virtual interrupt signals; The second virtual interrupt signal is generated based on the target physical interrupt signal and the second mapping information.

4. The interrupt signal processing method according to claim 3, characterized in that, The first mapping information is stored in a first target register, and the second mapping information is stored in a second target register. Both the first target register and the second target register are located in a general interrupt controller that is communicatively connected to the processor.

5. The interrupt signal processing method according to claim 1, characterized in that, The step of determining the target processing mode that matches the target physical interruption signal based on preset configuration information includes: In response to the satisfaction of preset control conditions, based on the preset configuration information, a target processing mode matching the target physical interrupt signal is determined. The preset control conditions include the processor being in the virtual machine monitoring state and the signal type of the target physical interrupt signal being the target type.

6. The interrupt signal processing method according to claim 1, characterized in that, The preset configuration information includes: Routing control information, wherein the routing control information is used to characterize the preset processing mode corresponding to each preset physical interruption signal as either the first processing mode or the second processing mode; Security mask information, which is used to characterize whether the kernel operation passthrough state of each preset physical interrupt signal is disabled or enabled.

7. The interrupt signal processing method according to claim 6, characterized in that, The step of determining the target processing mode that matches the target physical interruption signal based on preset configuration information includes: Based on the routing control information and the security mask information, the preset processing mode and the kernel pass-through state corresponding to the target physical interrupt signal are determined; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being enabled, the first processing mode is taken as the target processing mode; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being disabled, the second processing mode is set as the target processing mode; In response to the preset processing mode being the second processing mode, the second processing mode is taken as the target processing mode.

8. The interrupt signal processing method according to claim 6, characterized in that, The preset configuration information also includes preset mapping information and global control information. The preset mapping information is used to generate first mapping information and second mapping information, and the global control information is used to control whether to prohibit the generation of the first virtual interrupt signal in the first processing mode.

9. The interrupt signal processing method according to claim 8, characterized in that, The routing control information, the security mask information, the preset mapping information, and the global control information are stored in the third target register, the fourth target register, the fifth target register, and the sixth target register, respectively. The third target register, the fourth target register, the fifth target register, and the sixth target register are all located in the general interrupt controller that is communicatively connected to the processor.

10. The interrupt signal processing method according to claim 1, characterized in that, The seventh target register stores pass-through status information, which is used to characterize whether there is a first virtual interrupt signal generated based on the target physical interrupt signal and not processed. The seventh target register is located in a general interrupt controller that is communicatively connected to the processor.

11. The interrupt signal processing method according to any one of claims 1 to 10, characterized in that, The processor corresponds to multiple virtual processing units, and the interrupt signal processing method further includes: In response to a switching request for the virtual processing unit, a virtual unit switching process is performed to switch the current processing unit to the target processing unit; The virtual unit switching process includes: The generation of the first virtual interrupt signal is prohibited in the first processing mode; Save the preset configuration information and mapping information corresponding to the current processing unit to the first context information corresponding to the current processing unit; Wait for the processing of the first virtual interrupt signal corresponding to the current processing unit to be completed; Read the preset configuration information and mapping information corresponding to the target processing unit from the second context information corresponding to the target processing unit; The first virtual interrupt signal is allowed to be generated in the first processing mode; Execute the instructions corresponding to the target virtual unit.

12. The interrupt signal processing method according to any one of claims 1 to 10, characterized in that, The target physical interrupt signal includes a private peripheral interrupt signal.

13. An interrupt signal processing device, characterized in that, Applied to a processor, the processor being configured with a kernel running state and a virtual machine monitoring state, the interrupt signal handling device includes: The determining module is used to determine a target processing mode that matches the target physical interruption signal based on preset configuration information in response to the target physical interruption signal. The preset configuration information is used to characterize the preset processing modes corresponding to multiple preset physical interruption signals respectively. A first processing module is configured to, in response to the target processing mode being a first processing mode, generate a first virtual interrupt signal based on the target physical interrupt signal in the kernel running state of the processor, and process the first virtual interrupt signal in the kernel running state. The second processing module is configured to, in response to the target processing mode being the second processing mode, generate a second virtual interrupt signal based on the target physical interrupt signal in the virtual machine monitoring state of the processor, and process the second virtual interrupt signal in the kernel running state.

14. The interrupt signal processing device according to claim 13, characterized in that, The first processing module is also used for: The processor generates the first virtual interrupt signal based on the target physical interrupt signal; The second processing module is also used for: The virtual machine monitor generates the second virtual interrupt signal based on the target physical interrupt signal.

15. The interrupt signal processing device according to claim 13, characterized in that, The preset configuration information includes: Routing control information, wherein the routing control information is used to characterize the preset processing mode corresponding to each preset physical interruption signal as either the first processing mode or the second processing mode; Security mask information, which is used to characterize whether the kernel operation passthrough state of each preset physical interrupt signal is disabled or enabled.

16. The interrupt signal processing apparatus according to claim 15, characterized in that, The determining module is also used for: Based on the routing control information and the security mask information, the preset processing mode and the kernel pass-through state corresponding to the target physical interrupt signal are determined; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being enabled, the first processing mode is taken as the target processing mode; In response to the preset processing mode being the first processing mode and the kernel running passthrough state being disabled, the second processing mode is set as the target processing mode; In response to the preset processing mode being the second processing mode, the second processing mode is taken as the target processing mode.

17. The interrupt signal processing apparatus according to any one of claims 13 to 16, characterized in that, The processor corresponds to multiple virtual processing units, and the interrupt signal processing device further includes a switching module, which is used for: In response to a switching request for the virtual processing unit, a virtual unit switching process is performed to switch the current processing unit to the target processing unit; The virtual unit switching process includes: The generation of the first virtual interrupt signal is prohibited in the first processing mode; Save the preset configuration information and mapping information corresponding to the current processing unit to the first context information corresponding to the current processing unit; Wait for the processing of the first virtual interrupt signal corresponding to the current processing unit to be completed; Read the preset configuration information and mapping information corresponding to the target processing unit from the second context information corresponding to the target processing unit; The first virtual interrupt signal is allowed to be generated in the first processing mode; Execute the instructions corresponding to the target virtual unit.

18. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store processor-executable instructions; The processor is configured to perform the interrupt signal processing method as described in any one of claims 1 to 12.

19. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the interrupt signal processing method as described in any one of claims 1 to 12.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the interrupt signal processing method as described in any one of claims 1 to 12.

21. A chip, characterized in that, The chip is configured to perform the interrupt signal processing method as described in any one of claims 1 to 12.

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