Dynamic random access memory defect isolation method and system

Abstract

The application provides a dynamic random access memory defect isolation method, which comprises the following steps: acquiring address information of at least one defective physical page in a dynamic random access memory; in the process of constructing a page table managed by a memory management unit, only a non-defective physical page in the dynamic random access memory is used to establish a virtual address to physical address mapping relationship based on the address information of the defective physical page, and / or in the case that the page table managed by the memory management unit has been established, a page table entry corresponding to the defective physical page in the page table is executed state configuration based on the address information of the defective physical page, so that the page table entry is in an unallocatable state; and in response to a memory allocation request, the memory management unit performs address conversion according to the state configured page table, so that the defective physical page does not participate in the allocation of the physical memory. The application isolates the defective physical page by software configuring the memory management unit, and screens the dynamic random access memory defects without the need of hardware modification.

Description

Technical Field

[0001] This invention relates to the fields of computer architecture and memory management technology, specifically to a method and system for isolating defects in dynamic random access memory. Background Technology Dynamic Random Access Memory (DRAM) is a core storage component of computer systems, and its manufacturing yield and long-term reliability directly affect the overall system performance and user experience. Limited by the physical limitations of semiconductor manufacturing processes, DRAM chips inevitably contain a certain number of defective memory cells during production. These defects include single-bit failures due to process variations, row or column short circuits or open circuits, and adjacent bit coupling failures. Furthermore, during product use, factors such as electromigration, hot carrier injection, and device aging can generate new defective cells in DRAM. With the continuous miniaturization of process nodes and the application of three-dimensional stacked structures (such as high-bandwidth memories), the density and complexity of defective cells are further increasing, placing higher demands on defect management technologies.

[0002] Currently, mainstream DRAM defect handling solutions primarily employ hardware redundancy replacement mechanisms. Specifically, a certain number of redundant rows and columns are pre-designed within the DRAM chip. During the packaging and testing phase, a built-in self-test (BIST) circuit scans the memory array to identify defective physical addresses. The mapping between defective addresses and redundant resources (i.e., repair mapping information) is programmed and stored in non-volatile memory elements (such as electrically programmable fuses (eFuse) or Flash memory). After the chip powers on, the controller loads the repair mapping information into the on-chip memory structure (such as a register file or SRAM) and compares and matches the access addresses through on-chip control logic. When a defective address is matched, the access request is redirected to the corresponding redundant row or column, thereby shielding the defective memory cell. Furthermore, in some application scenarios, error detection and correction (ECC) technology can be combined to detect and correct memory errors generated during operation.

[0003] However, the above-mentioned technical solutions still have certain limitations in practical applications.

[0004] First, the hardware resource overhead is significant. To implement defect handling functionality, redundant rows or columns and non-volatile memory resources for storing repair information need to be reserved during the chip design phase, along with address comparison and control logic. This typically accounts for 5% to 20% of the DRAM controller area, significantly increasing chip area, power consumption, and design complexity.

[0005] Secondly, repair capabilities have a fixed upper limit. The scale of redundant resources (including the number of redundant rows / columns and non-volatile memory capacity) is determined during the design phase and cannot be dynamically adjusted according to the actual defect distribution. When the number of defects exceeds the preset redundancy capacity, the relevant chips will be deemed faulty and cannot be repaired, thus affecting product yield.

[0006] Secondly, there is insufficient maintainability throughout the product lifecycle. Existing solutions typically configure defect handling information during the factory testing phase, making it difficult to continuously handle defects added during product use. Furthermore, since this repair mechanism relies on hardware redundancy resources and their corresponding fixed configurations, it is difficult for the software layer to effectively intervene in or update new defects. Once a new defect exceeds the redundancy capacity during operation, the only solution is often to replace the hardware or scrap the product, significantly increasing the maintenance costs and usage risks of the end product. Summary of the Invention

[0007] This invention addresses the problems of high hardware resource overhead, limited repair capabilities, and insufficient maintainability throughout the lifecycle of existing technologies by providing a method and system for isolating dynamic random access memory (DRAM) defects based on a Memory Management Unit (MMU). This invention reuses the existing Memory Management Unit in the SoC system without requiring any modification to the Memory Management Unit hardware itself, achieving address-level isolation of DRAM defects through firmware or operating system kernel configuration.

[0008] This invention no longer relies on reserving redundant rows or columns within the dynamic random access memory (DRAM) chip for hardware replacement. Instead, it utilizes the page table management mechanism of the memory management unit to manage and isolate defective physical pages at the system level. By obtaining the address information of the defective physical page and excluding its mapping during the page table construction phase, and / or configuring the corresponding page table entry after page table creation to make it unallocatable, access to the defective physical page is avoided during the virtual-to-physical address mapping process. This effectively shields the defective storage unit, allowing memory allocation requests initiated by the operating system's memory management module, applications, or hardware host devices to bypass the defective region. Thus, defect isolation of DRAM is achieved without relying on traditional hardware redundancy repair mechanisms.

[0009] Compared to existing technologies, this invention transforms defect handling from an implementation method that relies on redundant hardware resources to one based on firmware / operating system kernel and memory management mechanisms. This effectively reduces the dependence on on-chip redundant resources and dedicated control logic, thereby reducing hardware area and design complexity.

[0010] Meanwhile, due to the excellent scalability of the page table management mechanism, this invention is not limited by the preset number of redundant resources. It can flexibly isolate defective physical pages according to the actual detected defects, thereby avoiding chip failure due to the number of defects exceeding the hardware repair capacity, which is beneficial to improving product yield. In addition, because the physical address is reconstructed through the address mapping mechanism of the memory management unit, even if the isolation of defective physical pages causes discontinuity in the physical address space, the virtual address space can still remain continuous, thus being transparent to the upper-layer software.

[0011] Furthermore, this invention supports the detection of new defects during system operation and the updating of the address information of defective physical pages. It also achieves isolation of new defects by reconfiguring the page table and / or re-establishing the mapping relationship between the virtual address and physical address of non-defective physical pages, thereby enabling continuous management of dynamic random access memory throughout the product lifecycle and improving the long-term reliability and maintainability of the system.

[0012] In a first aspect, the present invention provides a method for isolating defects in a dynamic random access memory (DRAM), applied to an on-chip system including a memory management unit, the method comprising: Obtain the address information of at least one defective physical page in the dynamic random access memory; If the page table managed by the memory management unit has been established, based on the address information of the defective physical page, the state configuration of the page table entry corresponding to the defective physical page in the page table is performed to make it unallocatable. In response to a memory allocation request, the memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

[0013] Secondly, the present invention also provides a dynamic random access memory defect isolation system, the system being applied to a system-on-a-chip including a memory management unit, the system comprising: An acquisition unit is used to acquire the address information of at least one defective physical page in the dynamic random access memory; The page table processing unit is used, during the process of constructing the page table managed by the memory management unit, to establish a virtual address to physical address mapping relationship only for non-defective physical pages in the dynamic random access memory based on the address information of the defective physical page, and not to establish any mapping relationship for the defective physical page, and / or, when the page table managed by the memory management unit has been established, to perform state configuration on the page table entry corresponding to the defective physical page based on the address information of the defective physical page, so that it is in an unallocatable state; A translation unit is used to respond to a memory allocation request. The memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

[0014] Compared with the prior art, the present invention has the following beneficial effects: First, addressing the issue that existing technologies commonly rely on redundant rows and columns of hardware resources for defect repair, this invention reuses an existing memory management unit in the system-on-chip. This eliminates the need to modify the memory management unit's hardware structure; isolation of dynamic random access memory defects can be achieved solely through firmware or operating system kernel configuration. This fundamentally eliminates the reliance on dedicated hardware redundancy resources and related control logic, significantly reducing chip area overhead and design complexity. Simultaneously, it eliminates the need for dedicated storage spaces such as registers or SRAM in the DRAM controller for storing repair information, and avoids reliance on large-scale non-volatile memory resources (such as eFuse). In typical implementations, this can save approximately 5% to 20% of controller area and reduce power consumption.

[0015] Secondly, in existing technologies, the number of redundant resources is fixed during the chip design phase, and its defect repair capability has an upper limit. When the number of defects exceeds a preset range, the chip cannot be repaired and is deemed a failure. This invention isolates defective physical pages based on a page table management mechanism, so that the defect handling capability is no longer limited by the preset number of redundant resources, but can be flexibly adjusted according to the actual detected defects. This effectively avoids chip scrapping due to exceeding the defect limit, and helps improve product yield. In extreme cases, as long as there are still usable physical page resources in the dynamic random access memory, the defective area can be continuously masked through page table adjustments, thereby significantly improving the tolerance for the number of defects.

[0016] Furthermore, in existing technologies, defect repair information is typically fixed once during factory testing (e.g., via eFuse), making it difficult to update during product use and unable to address new defects that arise during operation. This invention supports dynamic detection of new defects during system operation and isolates these defects by updating the defect's physical address information, reconfiguring address mapping relationships, and / or re-establishing non-defective physical page address mapping relationships. This enables continuous management of the dynamic random access memory throughout the entire product lifecycle, significantly improving the system's long-term reliability and maintainability. After product shipment, no hardware repair or memory device replacement is required; defect isolation is achieved simply by updating defect records and reconfiguring page tables and / or re-establishing non-defective physical page address mapping relationships via firmware or operating system kernel, significantly reducing maintenance costs.

[0017] Furthermore, existing technologies primarily replace or shield physical storage units at the hardware level, lacking coordinated optimization with system-level address management mechanisms. This invention reconstructs the physical address space through the address mapping mechanism of the memory management unit. Even if defective physical regions are isolated, causing discontinuities in the physical address space, the continuity of the virtual address space can still be maintained through address mapping. This is transparent to the operating system and applications, does not affect the normal operation of upper-layer software, and requires no adaptation or modification to the upper-layer software.

[0018] Finally, compared to solutions that rely solely on underlying hardware circuits for defect handling, this invention moves defect management capabilities up to the system software and memory management mechanism layer, achieving collaborative optimization between hardware and software. This not only reduces hardware implementation costs but also provides excellent versatility and scalability, making it applicable to various types of dynamic random access memory and different system architectures. In practical engineering applications, it offers greater flexibility and wider applicability.

[0019] Furthermore, this invention provides multiple implementation methods, including initialization marking, page table pruning, and combinations thereof, offering exceptional flexibility. The initialization marking method isolates defects by running a defect marking program after the page table is established, simplifying implementation and facilitating incremental updates during runtime. The page table pruning method directly eliminates defective regions during the page table construction phase, resulting in a more concise and efficient page table that reduces page table space usage and address translation overhead. When a hybrid approach combining page table pruning with initialization marking is adopted, an optimal page table structure can be obtained in the initial stage, while the initialization marking mechanism flexibly addresses new defects throughout the product lifecycle, achieving a complementary advantage of both methods. By providing these multiple technical paths that can be implemented independently or in combination, this invention allows for flexible selection based on different product forms, performance requirements, and maintenance strategies. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of the dynamic random access memory defect isolation method provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the on-chip system architecture in the initialization marking method provided in this embodiment of the invention; Figure 3 This is a flowchart of the initial isolation phase using the initialization marking method provided in an embodiment of the present invention; Figure 4This is a flowchart of the page table pruning method used in the initial isolation stage provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of the defect isolation principle of dynamic random access memory provided in an embodiment of the present invention; Figure 6 This is a block diagram of a dynamic random access memory defect isolation system provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Invention Overview As mentioned above, the present invention provides a method and system for isolating defects in dynamic random access memory (DRAM). By configuring the memory management unit in software, defective physical pages are isolated, thus shielding DRAM defects without the need for hardware modifications.

[0024] Exemplary methods Figure 1 This is a flowchart of a dynamic random access memory defect isolation method provided in an embodiment of the present invention. The dynamic random access memory includes at least one of high bandwidth memory (HBM), low power double data rate memory (LPDDR), or double data rate memory (DDR).

[0025] The High Bandwidth Memory (HBM) is a type of DRAM using 3D stacking technology. It achieves high-bandwidth interconnection by vertically stacking multiple DRAM dies and utilizing through-silicon vias (TSVs). It has a bandwidth and capacity density far exceeding that of traditional planar DRAM and is widely used in high-performance computing, graphics processing units (GPUs), and artificial intelligence accelerators. The Low Power Double Data Rate Memory (LPDDR) is a low-power DRAM designed for mobile devices and embedded systems. It features low voltage, low power consumption, and high data rate and is mainly used in power-sensitive scenarios such as smartphones, tablets, and automotive electronics. The Double Data Rate Memory (DDR) is currently the most mainstream general-purpose DRAM type. It achieves high-bandwidth transmission by transmitting data on both the rising and falling edges of the clock signal and is widely used in general-purpose computing platforms such as personal computers, servers, and workstations.

[0026] In the technical solution of this invention, all types of DRAM may develop physical defects due to manufacturing processes, long-term aging, or other factors. This invention utilizes a memory management unit page table mapping mechanism to uniformly isolate defective physical pages in these different types of DRAM, achieving effective defect management without relying on traditional hardware redundancy replacement circuits.

[0027] The method is applied to a System-on-Chip (SoC) that includes a memory management unit. An SoC is a system-level integrated circuit that integrates a central processing unit, memory control unit, interface circuits, and other functional modules onto a single chip. It achieves data interaction and collaborative operation between these modules through an on-chip bus or interconnect network, thereby forming a complete computing and control platform. For example, as... Figure 2 As shown, the system-on-a-chip mainly includes firmware (including a boot program), a memory management unit (integrated in the CPU), non-volatile memory (Flash / eFuse), a DRAM controller, and high-bandwidth memory (HBM) or other 3D stacked dynamic random access memory.

[0028] The firmware (such as BIOS, U-Boot, or a customized Boot ROM program) is the first software code executed after the system powers on. It is responsible for initializing basic hardware such as the CPU, memory controller, and clock, and for establishing the address mapping data structure used by the memory management unit. Firmware is usually stored in non-volatile media such as ROM or NOR Flash and is loaded into the CPU for execution in the early stages of system startup.

[0029] The bootloader, as a specific implementation or component of firmware, is typically located in the early or middle stages of the system boot process. Its main functions include loading the operating system kernel, passing system parameters, and completing some platform-related initialization configurations. In different system architectures, the bootloader can be a single-level or multi-level structure (such as a first-stage Boot ROM program and a second-stage Bootloader), and can work in conjunction with other firmware modules to complete the system boot process.

[0030] The memory management unit (MMU), integrated into the CPU, is responsible for translating virtual addresses used by upper-level software into actual physical addresses. Internally, the MMU includes submodules such as page table base address registers, address translation logic, and a bypass translation buffer (TLB). When the CPU executes a memory access instruction, the MMU automatically receives the virtual address, finds the corresponding physical address by traversing the page table or querying the TLB, and checks access permissions. If permissions are insufficient or page table entries are invalid, appropriate exception handling is triggered. The MMU also records the mapping relationship between virtual and physical addresses, as well as the access permissions and status information of each page, through the page table.

[0031] The non-volatile memory (e.g., NOR Flash, NAND Flash, or one-time programmable memory eFuse) is used to store the address information and related configuration data of the defective physical page.

[0032] The DRAM controller is a bridge module in the on-chip system that connects the CPU / memory management unit and the DRAM memory chips. Its main functions include: parsing memory access requests (read / write commands and physical addresses) from the CPU or memory management unit; converting addresses to DRAM row and column addresses according to JEDEC standards (such as DDR4, DDR5, LPDDR, etc.); generating corresponding row activation, column selection, precharge, and other command timing sequences; and controlling data transmission on the data lines. Simultaneously, the DRAM controller is also responsible for handling periodic tasks such as DRAM refresh, self-refresh, and power management; providing an access interface to the dynamic random access memory; and cooperating with the memory management unit to execute physical address access requests.

[0033] High-bandwidth memory (HBM) or other 3D stacked dynamic random access memory serves as the actual physical storage medium for carrying application and system data.

[0034] This invention reuses an existing memory management unit in a SoC system without requiring modification to the memory management unit hardware itself, achieving address-level isolation of DRAM defects through firmware / operating system kernel configuration. Based on the above design concept, this invention has the following technical effects: First, no new dedicated hardware resources are required. This invention does not rely on additional hardware redundancy structures (such as redundant rows / columns, eFuse, dedicated repair registers, or SRAM lookup tables), but instead reuses the existing memory management unit and its page table structure in the SoC to achieve defect isolation. Compared with traditional hardware redundancy schemes that typically require a certain area of ​​DRAM controller, this invention achieves effective DRAM defect isolation without significantly increasing chip area, thereby helping to reduce manufacturing costs and power consumption.

[0035] Secondly, the implementation is simple and highly compatible. Since no modification to the memory management unit hardware structure is required, this invention can be directly applied to existing SoC platforms with integrated memory management units; deployment can be completed simply by introducing defect isolation logic into the firmware or operating system kernel. This solution can work collaboratively with existing software stacks (including operating system memory management modules, drivers, and applications) without requiring adaptation modifications to upper-layer software.

[0036] Furthermore, the firmware / operating system kernel-based implementation offers excellent scalability. Since the defect isolation logic of the initialization marking method, page table pruning method, and hybrid implementation methods is entirely software-controlled and does not rely on hardware-fixed repair information, the defect address list can be updated throughout the product lifecycle. This supports continuous management of newly added defects during operation, improving the long-term reliability of the system.

[0037] Furthermore, this invention can work in conjunction with existing hardware repair mechanisms. In one embodiment, a hardware redundancy repair scheme is used to handle some defects within a DRAM chip, while this invention is used to isolate defects that hardware redundancy cannot cover or that are added during operation, thereby forming a multi-layered defect management mechanism and further improving the system's defect tolerance.

[0038] In addition to the traditional memory management unit integrated into the central processing unit as described in the above examples, this invention is also applicable to input output memory management units (IOMMUs), system memory management units (SMMUs), or other hardware units with address translation capabilities.

[0039] The Input / Output Memory Management Unit (IOMMU) is primarily used for address translation and protection of memory accesses initiated by peripheral masters such as PCIe, USB, and DMA, mapping the virtual addresses used by peripherals to the correct physical addresses. This invention can isolate DRAM defects on peripheral access paths by configuring the page tables of the IOMMU in the same state, thereby protecting the reliability of critical operations such as DMA transfers. The System Memory Management Unit (SMMU) is commonly used in multi-core processors or heterogeneous computing systems to provide unified address management and access control for multiple masters within the system. This invention can also achieve system-wide defect isolation by configuring the page tables managed by the SMMU to uniformly mark defective physical pages.

[0040] Furthermore, the technical solution of this invention is not limited to the specific type of memory management unit mentioned above; any hardware module with page table management or address remapping functions can be applied. As long as the module can complete the conversion from virtual address to physical address according to the software-configured mapping table (or equivalent data structure), this invention can achieve software-level isolation of defects by configuring the state or pruning the mapping of defective physical pages in the corresponding mapping table.

[0041] To achieve effective isolation and management of defective physical pages, this embodiment includes the following steps S101~S303: S101: Obtain the address information of at least one defective physical page in the dynamic random access memory; Specifically, in order to effectively isolate and manage defective physical pages, the address information of the defective physical pages is read from the non-volatile memory.

[0042] The non-volatile memory includes at least one of electrically programmable fuses (eFuse), flash memory, one-time programmable memory (OTP), or read-only memory (ROM). eFuse is suitable for storing small amounts of configuration information (e.g., a few KB to tens of KB) that do not require frequent updates; it is programmed once by applying high voltage to blow an internal fuse upon power-up. Flash memory supports multiple erase and write operations and is suitable for storing defect address lists that may be updated throughout the product lifecycle, but it requires reserved storage space and management using a file system or raw data read / write interface. OTP and ROM provide lower-cost one-time or fixed storage solutions.

[0043] Furthermore, the defective physical page address information can originate from detection results at different stages, specifically including: during the packaging test stage, a comprehensive scan of the DRAM is performed using the built-in self-test (BIST) to identify all defective physical addresses, and the scan results obtained; and / or during the system operation stage, newly added defective physical pages are identified by a memory detection program. For example, during system power-on self-test, maintenance window, or when an anomaly is detected (such as frequent ECC error correction), a dedicated memory detection program is run to rescan the DRAM and discover newly added defective physical pages.

[0044] The memory detection program is a diagnostic firmware or operating system kernel module used to verify the read and write operations of DRAM physical memory arrays. Its core function is to detect physical defects in memory cells by executing specific read and write patterns. Specifically, the program first writes a predefined data pattern (e.g., all 0s, all 1s, checkerboard 0xAA / 0x55, pseudo-random sequence, etc.) to the physical address range to be detected, then reads the data in the address range and compares it with the expected written value. If the read value matches the expected value, the memory cell is determined to be normal; if they do not match, the physical address is determined to be defective, and the address is recorded in the defect list. To cover different types of faults (such as single-bit fixed faults, adjacent bit coupling faults, row / column short-circuit faults, etc.), the memory detection program typically runs multiple different read and write patterns in a loop, each pattern designed for a specific fault model. For example, the March algorithm and its variants (such as MATS+, March C-, March LR, etc.) are widely used for DRAM fault detection, enabling high-coverage defect identification with a shorter test time.

[0045] During the packaging and testing phase, chip manufacturers typically perform a high-coverage scan test on the entire memory array using built-in self-test (BIST) circuitry after DRAM packaging is complete. This test runs various preset test patterns to detect multiple defect types, such as single-bit faults, row / column faults, and adjacent bit coupling faults, and generates a complete list of defect physical addresses. Subsequently, this defect address information is written to non-volatile memory and persistently stored as an initial defect record.

[0046] During product operation, to achieve dynamic updates of defect information, this invention supports continuous monitoring of the DRAM health status during actual system use. Specifically, when the system performs a power-on self-test, enters the maintenance window, or detects memory-related anomalies (such as ECC error correction counts exceeding a preset threshold, frequent memory errors recorded in the system log, blue screens, or significant performance degradation), a dedicated memory detection program can be triggered. This detection program rescans the DRAM physical address space using a specific read / write pattern, identifies newly added defective physical pages, and adds the address information of the newly added defective physical pages to the defective physical page address information stored in non-volatile memory.

[0047] The added defective physical page address information is read by the firmware during the next system startup and used to perform corresponding update operations on the page table. According to different embodiments of the present invention, this update operation includes: using an initialization marking method to perform incremental state configuration on the page table entries corresponding to the newly added defective page (i.e., only marking the newly added defective page without reconfiguring the entire page table). This incremental update mechanism reduces the configuration overhead during system startup and ensures the timeliness and integrity of defect isolation; and / or using a page table pruning method to establish a virtual address-to-physical address mapping relationship only for non-defective physical pages in the dynamic random access memory, and not establishing any mapping relationship for the defective physical page. Both methods have their own characteristics when dealing with newly added defects during the runtime phase: the initialization marking method is simple to implement and has low overhead, and can quickly incrementally mark newly added defects, making it particularly suitable for scenarios that require frequent dynamic updates of defect information, have high real-time requirements, or have limited firmware modification capabilities; the page table pruning method, by re-planning the mapping relationship, makes the final page table more concise and efficient. Although the computational load during a single update is relatively large, it achieves better address translation performance and lower page table memory usage.

[0048] Since the defective address information in the non-volatile memory remains valid after the system is powered off, the firmware will reread the updated complete list of defective addresses upon the next system startup and update the page table of the memory management unit accordingly.

[0049] By employing a two-stage defect information acquisition and update mechanism—combining full-scale BIST scanning during the packaging and testing phase with dynamic detection during product operation—this invention achieves continuous management of DRAM defects across its entire lifecycle. Compared to existing technologies that only solidify defect repair information once during factory testing and are ill-equipped to handle new defects added during product use, this invention offers the following technical advantages: First, this invention supports continuous monitoring of the health status of DRAM after product shipment. When new defective cells are generated due to factors such as aging, electromigration, hot carrier injection, or temperature stress, the system can identify and record the new defective address through a dedicated detection program, thereby overcoming the limitation that traditional defect repair schemes based on hardware redundancy resources are difficult to expand repair capabilities after leaving the factory.

[0050] Secondly, this invention writes the addresses of newly added defects detected during the operational phase into non-volatile memory and updates the page table upon the next system startup, enabling the defect isolation capability to dynamically expand as defect information accumulates. Under the initialization marking mechanism, there is no need to fully rebuild the existing page table; only the page table entries corresponding to newly added defects are adjusted, thereby ensuring system operating efficiency while continuously enhancing defect management capabilities. Theoretically, as long as available physical page resources remain, newly added defects can be continuously masked without requiring hardware rework or memory device replacement.

[0051] Furthermore, by unifying the management of BIST test results during the packaging and testing phase with dynamic test results during the operational phase, this invention constructs a defect management mechanism at the system level that covers the entire product lifecycle. This mechanism organically combines the isolation of known defects at the factory with the isolation of newly added defects during operation, transforming defect handling capabilities from a one-time static configuration to a continuously evolving dynamic management process. This not only ensures the basic reliability of the product at the time of delivery but also significantly improves the stability and maintainability of the product during long-term operation.

[0052] Furthermore, the combination of the aforementioned two-stage defect management mechanism with the page table-based address mapping isolation method enables defect information to directly affect system-level address allocation and access control paths without relying on the underlying hardware redundancy replacement structure, thus forming a technical implementation path that differs from traditional redundant row / column repair and fuse programming schemes.

[0053] In addition, to adapt to the memory management strategies of different systems, the isolation granularity of the defective physical pages is a standard page, a large page, or a spanning page range.

[0054] The standard page typically refers to a 4KB page, which is the most commonly used memory management granularity in operating systems. It is suitable for scenarios with high isolation precision requirements, such as consumer electronics or high-reliability systems sensitive to defect locations. The large page includes 2MB large pages and 1GB huge pages, which are suitable for high-performance computing, servers, and large model training scenarios. They can significantly reduce the number of page table entries, lower the TLB miss rate, and improve address translation efficiency. The spanning range refers to the unified isolation of multiple consecutive physical pages, which is suitable for situations where defect areas are concentrated or distributed in blocks.

[0055] In practical implementation, the system can flexibly select an appropriate isolation granularity based on defect detection results and the current memory management strategy. For example, when a single or a small number of scattered defects are detected, a 4KB standard page can be used for fine-grained isolation; when the defect area is large or concentrated, a 2MB or 1GB large page can be used for coarse-grained isolation to reduce the number of page table modifications and system overhead. When configuring or pruning page tables, the firmware or operating system kernel will perform batch state configuration or mapping processing on the corresponding range of page table entries according to the selected granularity, thereby achieving efficient defect isolation.

[0056] S102: During the process of constructing the page table managed by the memory management unit, based on the address information of the defective physical page, a virtual address to physical address mapping relationship is established only for non-defective physical pages in the dynamic random access memory, and no mapping relationship is established for the defective physical page. And / or if the page table managed by the memory management unit has been established, based on the address information of the defective physical page, the state configuration is performed on the page table entry corresponding to the defective physical page in the page table, so that it is in an unallocatable state.

[0057] The technical solution of this invention covers two main stages and two parallel implementation methods, realizing full lifecycle management of defects in dynamic random access memory.

[0058] The two phases include: initial defect detection and recording during the packaging and testing phase, and dynamic detection and updating of new defects during the product operation phase. During the packaging and testing phase, a comprehensive scan of the DRAM is performed using the built-in self-test (BIST) to obtain the initial defect physical page address information and write it to the non-volatile memory. During the product operation phase, when the system detects a memory anomaly, a dedicated detection program is run to identify new defects and update the defect address list in the non-volatile memory.

[0059] To address the defect address information obtained in the two aforementioned stages, this invention provides two parallel and independently implementable isolation methods: initialization marking and page table pruning. Initialization marking involves configuring the state of defective pages by running a defect marking program after the page table has been established. Page table pruning skips defective physical pages during the page table construction stage, establishing mapping relationships only for valid physical space. Both methods can be used individually or combined to form a hybrid implementation, thereby ensuring initial isolation effectiveness while supporting flexible handling of newly added defects during the runtime phase.

[0060] By organically combining the two stages and two methods mentioned above, this invention breaks through the limitations of traditional hardware redundancy solutions, which have fixed repair capabilities and are difficult to update dynamically, and realizes the continuous expansion of defect isolation capabilities across the entire lifecycle.

[0061] Specifically, based on the address information of the defective physical page, the defective physical page is isolated, including the following implementation methods: In one implementation, only page table pruning is used. During page table construction, only virtual address-to-physical address mappings are established for non-defective physical pages in the dynamic random access memory (DRAM), and no mappings are established for defective physical pages. When a new defect is detected during product operation, the page table construction process can be re-executed during the next system startup, removing the new defective physical page from the mapping. The core of this approach is to isolate the defective region at its source during the page table construction phase, ensuring that defective physical pages do not enter the address mapping system from the beginning of system startup, thus making them completely invisible from the operating system's perspective. This approach allows for a more compact page table structure, reducing the number of page table entries and lowering page table storage overhead and traversal complexity during address translation. Furthermore, since defective pages do not participate in any mappings, no additional defect marking or status update operations are required during system operation, thus avoiding runtime overhead. In addition, this approach can achieve zero defect exposure after system initialization, making it suitable for application scenarios with high reliability and performance requirements, where defect information is relatively complete at the factory stage. However, this method is highly dependent on the completeness of defect information. When new defects are added during operation, the page table needs to be rebuilt to complete the update, which limits its flexibility.

[0062] In another implementation, only an initialization marking method is used. That is, with the page tables managed by the memory management unit already established, based on the address information of the defective physical page, the page table entry corresponding to the defective physical page is configured to be in an unallocatable state. When a new defect is detected during product operation, incremental state configuration can be performed on the page table entry corresponding to the new defective page during the next system startup, without rebuilding the entire page table. The advantage of this method is that the page table first performs a full mapping of all physical pages in a conventional manner, and then logically isolates the defective page through software, thereby decoupling the page table construction process from the defect handling process. Since the defect information does not need to be obtained in advance during the page table construction phase, the firmware can reuse the standard initialization process, reducing implementation complexity. Simultaneously, the defect marking program can be flexibly deployed as an independent module in the firmware or operating system kernel, facilitating cross-platform adaptation and subsequent maintenance. Furthermore, this method supports incremental updates for new defects; isolation can be completed simply by marking the new defective page, avoiding the system overhead of rebuilding the entire page table and possessing good dynamic scalability. However, since the initial page table contains all physical pages, defective pages need to be excluded through subsequent marking. Therefore, it is slightly inferior to the page table pruning method in terms of page table size and the thoroughness of isolation during the initialization phase.

[0063] In another implementation, a combination of the two methods described above can be used. Specifically, in the initial stage of the system, a page table is constructed using a page table pruning method to isolate known defects at their source. Then, when a new defect is detected during system operation, an initialization marking method is used to incrementally configure the state of the newly added defective page. It should be noted that this specification focuses on the hybrid implementation method of first using the page table pruning method and then the initialization marking method. The reverse combination of first using the initialization marking method and then the page table pruning method is not listed separately in this invention. This is because the reverse combination has high implementation complexity and no significant performance advantage in practical engineering, and its technical effect can be covered by the aforementioned hybrid method and the two basic methods.

[0064] This hybrid approach organically combines page table pruning with initialization marking, enabling the defect isolation mechanism to possess both the efficiency of the initial stage and the flexibility of the operational stage. During system shipment or initial startup, known defects are completely eliminated through the pruning mechanism, achieving zero defect exposure. During long-term product operation, when new defects arise due to aging, voltage fluctuations, or temperature stress, there is no need to rebuild the page table; isolation is achieved simply by marking the status of the newly added defective pages, significantly reducing maintenance overhead during system operation. Furthermore, this approach, combined with the mechanism of obtaining initial defect information through built-in self-testing during the packaging and testing phase and dynamically detecting new defects during the operational phase, forms a defect management strategy that spans the entire product lifecycle. This allows defect isolation capabilities to continuously evolve over time, significantly improving long-term reliability and maintainability while ensuring system performance. Compared to a single strategy, this combined approach achieves a better balance between performance, implementation complexity, and dynamic adaptability, making it suitable for complex systems with high requirements for reliability, performance, and lifecycle management.

[0065] The page table is established by the firmware during system startup. The page table is a core data structure used by the memory management unit (MMU) to translate virtual addresses into physical addresses. It is typically stored in system memory and consists of one or more page table entries. Each page table entry corresponds to a fixed-size physical page (e.g., a 4KB standard page or a 2MB large page), containing the page's starting physical address, access permissions, caching policy, validity status, and other attribute information. When performing address translation, the MMU traverses the page table using the virtual address as an index, finds the corresponding page table entry, and completes the mapping based on the physical address recorded in the page table entry. During system initialization, after completing the basic configuration of the memory controller, the firmware constructs an initial page table based on the system memory layout, ensuring that the page table contains the mapping relationship between the physical address space and the virtual address space of the dynamic random access memory (DRAM). At this time, the page table includes page table entries corresponding to all physical pages, including defective physical pages that will be isolated later.

[0066] In the initialization marking method, the unallocatable state means that the corresponding physical page will not be selected or accessed in subsequent memory allocation and address mapping processes. This state can be reflected by at least one of the valid bits, permission bits, or attribute bits of the page table entry.

[0067] After the page table is established, the initialization marking method performs the isolation operation for defective physical pages in software. Specifically, the state configuration of the page table entries is completed by the defect marking program, which is executed by the firmware or operating system (OS) kernel.

[0068] The defect marking program is a software module used to modify the state of page table entries. Its core function is to locate the corresponding page table entry based on a pre-acquired list of defective physical page addresses, and modify its status field or permission field to an unallocatable state (e.g., clearing the valid bit, marking it as reserved, or setting it to prohibit read and write access). This program can be implemented independently or integrated as part of firmware or operating system kernel.

[0069] The defect marking program can traverse the corresponding page table entries in the page table according to the pre-acquired list of defect physical page addresses, and modify their status fields or permission fields one by one. In a multi-level page table structure, the target page table entry can be located by step-by-step indexing, or batch updates can be completed by using the page table traversal interface to improve processing efficiency.

[0070] The operating system kernel is the core of the operating system, responsible for fundamental functions such as system process scheduling, memory allocation, device drivers, and interrupt handling. In terms of memory management, the operating system kernel maintains the system's page table structure and provides interfaces for memory allocation and deallocation. Unlike firmware, which executes only in the early stages of system startup, the operating system kernel remains resident in memory and runs continuously after system startup. Therefore, it can dynamically respond to defect detection events during system operation and perform page table state configuration operations in real time or with a delay.

[0071] Regarding the division of responsibilities for page table creation and state configuration, the design logic is as follows: The page table is created by the firmware during system startup. This is because in the early stages of system startup, before the operating system is loaded, the firmware is the only available execution environment, responsible for completing basic hardware initialization and building the page table framework. The reason why the state configuration of the page table entries can be executed by either the firmware or the operating system kernel is that the isolation operation for defective physical pages has different triggering times: When state configuration is performed during the system initialization phase (i.e., before the operating system is loaded), since the operating system has not yet started, the state configuration of page table entries can only be completed by the firmware executing the defect marking program. When the state configuration is executed after system initialization or during system operation, the operating system has already started and is resident in memory. At this time, the operating system kernel can execute the defect marking program to dynamically modify the state of page table entries.

[0072] This design enables the invention to cover both defect isolation at the manufacturing stage (managed by firmware) and dynamic isolation of newly added defects during product use (managed by the operating system kernel), thus achieving full lifecycle management of DRAM defects.

[0073] Furthermore, the state configuration of the page table entry that puts the defective physical page into an unallocatable state includes: Configure the page table entry corresponding to the defective physical page to an invalid, reserved, or unavailable state; and / or set the access permissions of the page table entry corresponding to the defective physical page to prohibit read and write operations.

[0074] In this context, "invalid state" refers to the page table entry having its valid flag cleared, preventing a valid mapping from being established during address translation; "reserved state" means the page table entry is marked as a system-reserved resource and does not participate in regular memory allocation; "unavailable state" means the page table entry is marked as unallocable during memory management and is therefore skipped during free memory management; and "read / write prohibited" means setting access permissions to trigger an access exception for that physical page. These methods can be used individually or in combination. Configuring a page table entry as invalid can be achieved by clearing the valid bit, making the page unavailable during address translation; configuring it as reserved or unavailable can be achieved by setting specific attribute bits, causing the operating system to skip the physical page in its memory allocation strategy; and setting access permissions to read / write prohibited can be achieved by modifying permission bits (such as the read / write bit).

[0075] The state configuration of the page table entry is performed at at least one of the following times: during system initialization; after system initialization is completed; when a new defective physical page is detected during system operation.

[0076] Specifically, performing state configuration during system initialization means that after the firmware completes the initial page table construction but before the operating system loads, it immediately calls the defect marking program to mark the defective page table. At this time, the defective physical page has never entered the memory pool managed by the operating system. Performing state configuration after system initialization means that after the operating system kernel has started and completed the memory management module initialization, the kernel service program dynamically loads the defect address information and modifies the page table. At this time, the defective physical page may have been recorded as a free page by the operating system, and after state configuration, it will be removed from the free page list. Performing state configuration when a new defective physical page is detected during system operation means that after the system identifies a new defect through ECC error correction logs or a dedicated detection program, it writes the new defect address to non-volatile memory in real time, and the operating system kernel immediately or at the next system startup performs state configuration on the corresponding page table entry to ensure that the new defect is isolated in a timely manner.

[0077] As an optional embodiment, such as Figure 3 The initial isolation phase shown uses the initialization marking method. After the system is powered on: S301: The firmware (including the bootloader) first reads a pre-stored list of defective addresses from non-volatile memory. For example, the list of defective addresses can be an array containing the starting addresses of multiple defective physical pages, each address corresponding to a physical page that needs to be isolated. The end of the list is identified by a specific end marker or address length field. S302: Next, the initial page table is constructed, and the entire physical address space is fully mapped. That is, according to the physical address range of DRAM, a corresponding page table entry is created in the page table for each addressable physical page, and the initial mapping relationship with its virtual address space is established. At this time, all physical pages are in an allocatable state. S303: After the page table is built, for known defective physical pages, the firmware or operating system kernel runs a defect marking program to mark the corresponding page table entry as unavailable. For example, the defect marking program traverses the list of defective addresses, finds the corresponding page table entry for each defective physical page by calculating its index position in the page table, and then modifies the status field of the page table entry, such as clearing the Present / Valid bit or marking its type as OS reserved, so that the memory management unit cannot allocate the physical page to any memory access request during address translation. S304: Subsequently, the operating system (OS) starts up and can only perceive the effective physical memory range after the defective pages are removed. Specifically, during the initialization process, the operating system scans the page table or calls the memory detection function to obtain the range of available physical memory. Since the page table entries corresponding to the defective physical pages have been marked as unavailable, the operating system does not include them in the total amount of available memory when performing memory resource detection. Therefore, from the system's perspective, these defective physical pages are completely invisible. S305: When the operating system allocates memory, it will only perform the allocation operation on the valid physical pages, and eventually enter the normal operating state.

[0078] Specifically, when the page table has been established, this invention proactively configures the state of the page table entries corresponding to defective physical pages during the system initialization phase (e.g., setting them to an unavailable state), so that these defective physical pages do not participate in the subsequent memory allocation process from the beginning.

[0079] It should be noted that, unlike existing technologies that use on-access remapping to spare or abnormal address regions, this invention configures defective physical pages as unallocable during the page table configuration phase. When the operating system allocates physical memory, its memory management algorithm only traverses and retrieves page table entries that are in an available state. Page table entries corresponding to defective pages marked as unavailable will not appear in the allocable resource pool at all. Therefore, there is no need to perform address comparison and matching on each access, and no additional delay caused by address remapping will occur.

[0080] As another optional embodiment, such as Figure 4 The initial isolation phase shown uses the page table pruning method. After the system is powered on: S401: Similar to S301, the firmware reads a pre-stored list of defect addresses from non-volatile memory.

[0081] S402: Skip defective physical pages directly when building page tables.

[0082] Unlike the full mapping method of the initialization marking method, this embodiment embeds defective address information during the page table construction process. Specifically, when the firmware traverses the DRAM physical address space to create a page table entry for each physical page, it first checks whether the address of the current physical page exists in the defective address list read by S401. If it exists, the physical page is skipped, no page table entry is created for it, and no virtual address mapping is assigned to it; if it does not exist, a corresponding page table entry is created for the physical page, a mapping relationship from virtual address to physical address is established, and the corresponding access permissions and status bits are set. In this way, defective physical pages are completely excluded during the page table construction stage and never enter the mapping range of the page table.

[0083] S403: Virtual address mapping is established only for valid physical space.

[0084] The firmware only traverses the non-defective physical address range in DRAM, creating a corresponding page table entry for each valid physical page and establishing an initial mapping relationship with its virtual address space. Since defective physical pages are skipped, the constructed page table only contains mapping information for valid physical pages, and the number of page table entries is equal to the number of valid physical pages. This page table structure is more concise than a full page table, occupies less memory space, and eliminates subsequent modification operations on defective page table entries.

[0085] S404: OS boot, available physical memory is the effective physical space.

[0086] Similar to S304, the operating system (OS) begins booting and executes the kernel initialization process. During the memory management module initialization, the OS scans the page tables or calls memory detection functions to determine the range of available physical memory. Since defective physical pages are not mapped during the page table construction phase, the OS is unaware of these defective pages when scanning the page tables and therefore does not include them in the total available memory. From the system's perspective, the range of available physical memory is the effective physical space after removing defective physical pages; defective physical pages are completely invisible to the operating system.

[0087] S405: OS memory allocation is performed on a contiguous virtual address space, eventually entering normal operation.

[0088] Similar to S305, when allocating memory, the operating system's memory management algorithm selects only available pages from the valid physical pages recorded in the page table. Since defective physical pages do not exist in the page table, the operating system will never allocate them to any requester. Furthermore, although the physical address space may become discontinuous due to the removal of defective pages, the virtual address space remains continuous for upper-layer software after being mapped by the page table, and applications do not need to be aware of the existence of underlying physical defects.

[0089] In summary, with Figure 3 Compared to the initialization marking method shown, this embodiment (page table trimming method) has the following main differences in implementation principle and technical effect: Regarding page table construction strategies, Figure 3 Using a full mapping approach, a complete page table containing all physical pages of DRAM is first constructed, and then defective pages are marked post-processedly using a defect marking program; Figure 4 The pruning mapping method skips defective physical pages directly based on the defect address list during the page table construction process, and only establishes mapping relationships for valid physical pages, which is a form of pre-emptive exclusion.

[0090] Regarding the timing of defect handling Figure 3 The isolation operation occurs after the page table is built and is a post-processing markup; Figure 4 The isolation operation is embedded in the page table construction phase, which is a source-level pruning. This results in significant differences in the page table structure: Figure 3 The page table contains page table entries for all physical pages (including defective pages that have been marked), and the page table is quite large; Figure 4 The page table contains only page table entries for valid physical pages, making its structure more concise, its memory footprint smaller, and its address translation efficiency higher.

[0091] In short, Figure 3 (Initialization marking method) and Figure 4 The (page table pruning method) has fundamental differences in page table construction strategy, defect isolation timing, and page table space usage. It can be flexibly selected according to the different needs of specific products in terms of performance, real-time performance, maintainability, and implementation complexity.

[0092] It should be noted that, Figure 3 and Figure 4 The content shown refers to the implementation method of the initial isolation stage of the present invention, and does not limit the handling strategy after new defects are detected during the product operation stage.

[0093] In practical applications, for systems that use the initialization marking method as the initial isolation method ( Figure 3 If a new defect is detected during product operation, it can be handled using incremental state configuration (incremental marking) during the next system startup, or the page table pruning process can be re-executed; for systems that use page table pruning as the initial isolation method ( Figure 4 If a new defect is detected during product operation, it can be handled by re-pruning the page table during the next system startup, or by combining the initialization marking method to incrementally configure the state of the new defect page.

[0094] S103: In response to a memory allocation request, the memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

[0095] The memory allocation request typically includes the required virtual address range or memory size. Upon receiving the allocation request, the memory management unit (MMU) traverses the configured page tables, using the virtual address as an index, to find the corresponding page table entry level by level. During the search, the MMU first obtains the physical address of the root page table from the page table base address register, and then reads each level of page table entry sequentially based on the different level index fields of the virtual address until the final target page table entry is found. Because the page table entry corresponding to the defective physical page is configured to an unallocatable state (e.g., the valid bit is cleared, marked as reserved, or the permission bit is set to disable read / write), the MMU will determine that the page table entry is invalid or inaccessible during address translation, and therefore will not return the address of the defective physical page as the translation result. The operating system's memory management module ignores these page table entries marked as unallocatable when traversing the page tables to construct a list of free pages.

[0096] The memory allocation request can be initiated by different entities. Specifically, the memory allocation request can be initiated by the operating system memory management module, an application, or a hardware host device.

[0097] Memory allocation requests initiated by the operating system's memory management module typically respond to memory allocation calls such as malloc and mmap from the system kernel or user processes. Their allocation strategies involve a series of operations, including free page traversal, page table entry updates, and TLB flushing. While applications do not directly call the memory management unit, they indirectly initiate memory allocation requests through the operating system kernel. The actual allocation process is also completed by the operating system's memory management module in conjunction with the memory management unit. Memory allocation requests initiated by hardware master devices (such as GPUs and network cards supporting IOMMU) are different. These devices typically access physical memory through address translation performed by the IOMMU with minimal reliance on real-time CPU involvement. In this case, the IOMMU can perform address translation based on an independent address mapping table or a mapping relationship consistent with the system page table. It can also configure and shield defective physical pages based on the state of page table entries.

[0098] As an optional embodiment, such as Figure 2 The initial isolation phase shown employs an initialization marking method. After the system powers on, the firmware (including the bootloader) reads pre-stored defect address information from non-volatile memory (this information can be generated and written by the BIST / detection program during the packaging test phase or the system runtime phase). Subsequently, the firmware marks the corresponding defective physical page as unavailable by configuring the page table managed by the memory management unit. Based on the updated page table, the memory management unit translates the virtual address issued by the upper-layer software into a valid physical address, thereby bypassing the defective physical region.

[0099] When a memory allocation request attempts to access a defective physical page that has been marked as unallocable, the page table directly blocks the access, preventing it from reaching the DRAM controller and the defective physical region below it. The valid physical memory region can then be accessed normally.

[0100] Through the above mechanism, the present invention achieves effective isolation of defective regions in the physical address space, while ensuring the continuity and transparency of the virtual address space to upper-layer software.

[0101] To more clearly illustrate the address mapping isolation effect of the present invention, further explanation is provided below in conjunction with the accompanying drawings.

[0102] like Figure 5 As shown, this invention implements software mapping from virtual addresses to physical addresses through the page table of the memory management unit. In the virtual address space, the operating system and applications see contiguous virtual memory pages; after translation by the page table of the memory management unit, these pages are mapped to the physical address space. Defective physical address regions (highlighted in the diagram) are marked as unallocatable in the page table. The memory management unit automatically bypasses these defective physical pages during address translation, thereby achieving effective isolation of defects.

[0103] As can be seen from the figure, although there are isolated defective regions in the physical address space (the physical address space may not be contiguous), the virtual address space remains completely continuous and transparent to the upper-layer software. The operating system and applications do not need to be aware of the existence of the underlying physical defects, nor will they perform any access or allocation operations on the defective physical addresses.

[0104] Exemplary System Accordingly, embodiments of the present invention also provide a dynamic random access memory defect isolation system, which is applied to a system-on-a-chip including a memory management unit. Figure 6 This is a block diagram of a dynamic random access memory defect isolation system provided in an embodiment of the present invention, such as... Figure 6 As shown, the system 100 provided in this embodiment includes: The acquisition unit 101 is used to acquire the address information of at least one defective physical page in the dynamic random access memory; Page table processing unit 102 is used to, during the process of constructing the page table managed by the memory management unit, establish a virtual address to physical address mapping relationship only for non-defective physical pages in the dynamic random access memory based on the address information of the defective physical page, and not establish any mapping relationship for the defective physical page, and / or, when the page table managed by the memory management unit has been established, perform state configuration on the page table entry corresponding to the defective physical page based on the address information of the defective physical page, so that it is in an unallocatable state; The translation unit 103 is used to respond to a memory allocation request. The memory management unit performs a virtual address to physical address translation according to the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

[0105] The acquisition unit 101 further includes: This module is used to read pre-stored defective physical page address information from non-volatile memory.

[0106] The defective physical page address information includes: scan results obtained through the built-in self-test during the packaging test phase.

[0107] The defective physical page address information includes: newly added defective physical pages identified by the memory detection program during system operation.

[0108] The page table is created by the firmware during system startup.

[0109] The page table processing unit 102 is used to perform defect marking procedures executed by the firmware or operating system kernel.

[0110] The page table processing unit 102 is used for: Configure the page table entry corresponding to the defective physical page to an invalid, reserved, or unavailable state; and / or Set the access permissions of the page table entry corresponding to the defective physical page to be disabled for reading and writing.

[0111] The page table processing unit 102 is configured to perform state configuration of the page table entries at at least one of the following times: System initialization phase; After system initialization is complete; When a new defective physical page is detected during system operation.

[0112] The system 100 further includes an update unit 104, which is used to add the address information of the newly added defective physical page to the defective physical page address information stored in the non-volatile memory when a newly added defective physical page is detected during system operation.

[0113] The acquisition unit 101 is used to read the added defective physical page address information when the system starts up again. The page table processing unit 102 is used to perform incremental state configuration on the page table and / or only establish a virtual address to physical address mapping relationship for non-defective physical pages in the dynamic random access memory, and not establish any mapping relationship for the defective physical pages.

[0114] The memory allocation request is initiated by the operating system memory management module, an application, or a hardware host device.

[0115] The isolation granularity of the defective physical page is a standard page, a large page, or a spanning page range.

[0116] The dynamic random access memory includes at least one of high-bandwidth memory, low-power double data rate memory, or double data rate memory.

[0117] The memory management unit includes at least one of the following: a memory management unit in a central processing unit, an input / output memory management unit, a system memory management unit, or a hardware unit with address translation functionality.

[0118] The address information of the defective physical page is stored in a non-volatile memory, which includes at least one of an electrically programmable fuse, flash memory, one-time programmable memory, or read-only memory.

[0119] It should be noted that although the operation of the dynamic random access memory defect isolation method of the present invention is described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0120] Furthermore, although several devices, units, or modules of the dynamic random access memory defect isolation system have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the invention, the features and functions of two or more modules described above can be embodied in a single module. Conversely, the features and functions of a single module described above can be further divided and embodied by multiple modules.

[0121] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0122] This invention provides: 1. A method for isolating defects in dynamic random access memory, applied to a system-on-a-chip including a memory management unit, characterized in that the method comprises: Obtain the address information of at least one defective physical page in the dynamic random access memory; During the construction of the page table managed by the memory management unit, based on the address information of the defective physical page, a virtual address to physical address mapping relationship is established only for non-defective physical pages in the dynamic random access memory, and no mapping relationship is established for the defective physical page. And / or when the page table managed by the memory management unit has been established, based on the address information of the defective physical page, the state configuration is performed on the page table entry corresponding to the defective physical page in the page table, so that it is in an unallocatable state. In response to a memory allocation request, the memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

[0123] 2. The method according to item 1, characterized in that the step of obtaining the address information of at least one defective physical page in the dynamic random access memory further includes: Read the pre-stored defective physical page address information from non-volatile memory.

[0124] 3. The method according to item 2, wherein the defective physical page address information includes: scan results obtained through built-in self-test during the packaging test phase.

[0125] 4. The method according to item 2, wherein the defective physical page address information includes: newly added defective physical pages identified by the memory detection program during system operation.

[0126] 5. The method according to item 1, wherein the page table is established by the firmware during system startup.

[0127] 6. The method according to item 5, wherein the state configuration of the page table entry is performed by a defect marking program executed by the firmware or operating system kernel.

[0128] 7. The method according to item 1, characterized in that the state configuration of the page table entry that puts the defective physical page in an unallocatable state includes: Configure the page table entry corresponding to the defective physical page to an invalid, reserved, or unavailable state; and / or Set the access permissions of the page table entry corresponding to the defective physical page to be disabled for reading and writing.

[0129] 8. The method according to item 1, characterized in that the state configuration of the page table entry is performed at at least one of the following times: System initialization phase; After system initialization is complete; When a new defective physical page is detected during system operation.

[0130] 9. The method according to item 1, characterized in that the method further includes: when a new defective physical page is detected during system operation, adding the address information of the new defective physical page to the defective physical page address information stored in the non-volatile memory.

[0131] 10. The method according to item 9, characterized in that the added defective physical page address information is read when the system is started again, and is used to perform incremental state configuration on the page table and / or establish a virtual address to physical address mapping relationship only for non-defective physical pages in the dynamic random access memory, and not establish any mapping relationship for the defective physical pages.

[0132] 11. The method according to item 1, wherein the memory allocation request is initiated by the operating system memory management module, an application, or a hardware host device.

[0133] 12. The method according to item 1, wherein the isolation granularity of the defective physical page is a standard page, a large page, or a spanning page range.

[0134] 13. The method according to item 1, wherein the dynamic random access memory includes at least one of a high-bandwidth memory, a low-power double data rate memory, or a double data rate memory.

[0135] 14. The method according to item 1, wherein the memory management unit includes at least one of a memory management unit in a central processing unit, an input / output memory management unit, a system memory management unit, or a hardware unit with address translation function.

[0136] 15. The method according to item 1, wherein the address information of the defective physical page is stored in a non-volatile memory, the non-volatile memory comprising at least one of an electrically programmable fuse, flash memory, one-time programmable memory, or read-only memory.

[0137] 16. A dynamic random access memory defect isolation system, the system being applied to a system-on-a-chip including a memory management unit, characterized in that the system comprises: An acquisition unit is used to acquire the address information of at least one defective physical page in the dynamic random access memory; The page table processing unit is used, during the process of constructing the page table managed by the memory management unit, to establish a virtual address to physical address mapping relationship only for non-defective physical pages in the dynamic random access memory based on the address information of the defective physical page, and not to establish any mapping relationship for the defective physical page, and / or, when the page table managed by the memory management unit has been established, to perform state configuration on the page table entry corresponding to the defective physical page based on the address information of the defective physical page, so that it is in an unallocatable state; A translation unit is used to respond to a memory allocation request. The memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

[0138] 17. The system according to claim 16, wherein the acquisition unit further comprises: This module is used to read pre-stored defective physical page address information from non-volatile memory.

[0139] 18. The system according to item 17, wherein the defective physical page address information includes: scan results obtained through built-in self-test during the packaging test phase.

[0140] 19. The system according to item 17, wherein the defective physical page address information includes: newly added defective physical pages identified by the memory detection program during system operation.

[0141] 20. The system according to item 16, wherein the page table is established by the firmware during system startup.

[0142] 21. The system according to claim 20, wherein the page table processing unit is used to perform a defect marking program executed by the firmware or operating system kernel.

[0143] 22. The system according to claim 16, characterized in that the page table processing unit is used for: Configure the page table entry corresponding to the defective physical page to an invalid, reserved, or unavailable state; and / or Set the access permissions of the page table entry corresponding to the defective physical page to be disabled for reading and writing.

[0144] 23. The system according to claim 16, characterized in that the page table processing unit is configured to perform state configuration of the page table entries at at least one of the following times: System initialization phase; After system initialization is complete; When a new defective physical page is detected during system operation.

[0145] 24. The system according to claim 16, characterized in that the system further includes an update unit, which is used to add the address information of the newly added defective physical page to the defective physical page address information stored in the non-volatile memory when a newly added defective physical page is detected during system operation.

[0146] 25. The system according to item 24, characterized in that the acquisition unit is used to read the added defective physical page address information when the system is started again, and the page table processing unit is used to perform incremental state configuration on the page table and / or establish a virtual address to physical address mapping relationship only for non-defective physical pages in the dynamic random access memory, and not establish any mapping relationship for the defective physical pages.

[0147] 26. The system according to item 16, wherein the memory allocation request is initiated by the operating system memory management module, an application program, or a hardware host device.

[0148] 27. The system according to item 16, wherein the isolation granularity of the defective physical page is a standard page, a large page, or a spanning page range.

[0149] 28. The system according to claim 16, wherein the dynamic random access memory comprises at least one of a high-bandwidth memory, a low-power double data rate memory, or a double data rate memory.

[0150] 29. The system according to claim 16, wherein the memory management unit comprises at least one of a memory management unit in a central processing unit, an input / output memory management unit, a system memory management unit, or a hardware unit with address translation function.

[0151] 30. The system according to claim 16, wherein the address information of the defective physical page is stored in a non-volatile memory, the non-volatile memory comprising at least one of an electrically programmable fuse, flash memory, one-time programmable memory, or read-only memory.

Claims

1. A method for isolating defects in dynamic random access memory, applied to an on-chip system including a memory management unit, characterized in that, The method includes: Obtain the address information of at least one defective physical page in the dynamic random access memory; During the construction of the page table managed by the memory management unit, based on the address information of the defective physical page, a virtual address to physical address mapping relationship is established only for non-defective physical pages in the dynamic random access memory, and no mapping relationship is established for the defective physical page. And / or when the page table managed by the memory management unit has been established, based on the address information of the defective physical page, the state configuration is performed on the page table entry corresponding to the defective physical page in the page table, so that it is in an unallocatable state. In response to a memory allocation request, the memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

2. The method according to claim 1, characterized in that, The step of obtaining the address information of at least one defective physical page in the dynamic random access memory further includes: Read the pre-stored defective physical page address information from non-volatile memory.

3. The method according to claim 2, characterized in that, The defective physical page address information includes: scan results obtained through the built-in self-test during the packaging test phase.

4. The method according to claim 2, characterized in that, The defective physical page address information includes: newly added defective physical pages identified by the memory detection program during system operation.

5. The method according to claim 1, characterized in that, The page table is created by the firmware during system startup.

6. The method according to claim 5, characterized in that, The state configuration of the page table entries is accomplished by a defect marking program executed by the firmware or operating system kernel.

7. The method according to claim 1, characterized in that, The state configuration of the page table entry that puts the defective physical page in an unallocatable state includes: Configure the page table entry corresponding to the defective physical page to an invalid, reserved, or unavailable state; and / or Set the access permissions of the page table entry corresponding to the defective physical page to be disabled for reading and writing.

8. The method according to claim 1, characterized in that, The state configuration of the page table entry is performed at least one of the following times: System initialization phase; After system initialization is complete; When a new defective physical page is detected during system operation.

9. The method according to claim 1, characterized in that, The method further includes: when a new defective physical page is detected during system operation, adding the address information of the new defective physical page to the defective physical page address information stored in the non-volatile memory.

10. A dynamic random access memory defect isolation system, said system being applied to a system-on-a-chip including a memory management unit, characterized in that, The system includes: An acquisition unit is used to acquire the address information of at least one defective physical page in the dynamic random access memory; The page table processing unit is used, during the process of constructing the page table managed by the memory management unit, to establish a virtual address to physical address mapping relationship only for non-defective physical pages in the dynamic random access memory based on the address information of the defective physical page, and not to establish any mapping relationship for the defective physical page, and / or, when the page table managed by the memory management unit has been established, to perform state configuration on the page table entry corresponding to the defective physical page based on the address information of the defective physical page, so that it is in an unallocatable state; A translation unit is used to respond to a memory allocation request. The memory management unit performs a virtual address to physical address translation based on the page table after the status configuration, so that the defective physical page does not participate in the allocation of physical memory.

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