An integrated circuit test data reliability evaluation method based on an AI large model

Abstract

The application discloses an integrated circuit test data reliability evaluation method based on an AI large model, and relates to the technical field of intelligent chips, comprising the following steps: collecting and preprocessing integrated circuit test data to generate an integrated circuit test data set; rearranging the test data set and marking test paths to generate a test path channel graph; pairing initial and retest records and associating contact detection records to generate an initial and retest back connection sample; inputting the back connection sample into an improved TimesNet model to generate a test reliability feature package; arranging data distortion tracks and device abnormality tracks to construct a double-track reliability evidence matrix; normalizing and track-weighting the double-track evidence matrix to generate a test record double-score sequence; matching score intervals and associating device abnormality scores to generate a reliability evaluation result. The application realizes the differentiated evaluation and source tracing of integrated circuit test data distortion and device abnormality by improving the TimesNet model.

Description

Technical Field

[0001] This invention relates to the field of intelligent chip technology, and in particular to a method for evaluating the reliability of integrated circuit test data based on a large AI model. Background Technology

[0002] Integrated circuit manufacturing processes are evolving towards higher integration and multifunctionality, leading to a continuous increase in test data generated during wafer testing, packaging testing, and finished product testing. Automated test equipment performs voltage, current, timing, functional, continuity, and contact state checks according to test procedures, recording chip identification, test batch, test equipment, test program version, test items, test rounds, test values, test limits, logic pins, physical channels, and test conclusions. Integrated circuit test data reflects both the chip's electrical performance and manufacturing status, and is also influenced by test program paths, pin channel mappings, test contact states, and initial and retest operations. Existing reliability evaluation methods primarily employ limit comparison, repeatability statistics, process capability analysis, and outlier detection to determine whether test values ​​exceed limits, whether batch data deviates, and whether initial and retest conclusions are consistent. Some methods utilize machine learning models or temporal neural networks to analyze test data, generating reliability evaluation results through classification, prediction, or anomaly scoring.

[0003] Existing methods typically arrange test records from different test program versions, test items, and test rounds into a simple table or a single time sequence, without describing common trunks, conditional branches, and convergence points. Test items are prone to misalignment under different execution paths, leading to inconsistencies in the comparison benchmarks between initial and retest records. Logic pins and physical channels are often merged into a single channel feature, making it difficult to distinguish deviations caused by chip pin changes, physical channel drift, and pin-channel mapping changes. Existing initial and retest analyses mostly rely on direct comparisons of test values ​​or test conclusions, lacking correlation analysis between continuous test values, contact resistance, test current, and test paths. Data distortion caused by poor contact and channel anomalies is easily misidentified as device malfunctions. Existing artificial intelligence evaluation methods mostly represent the test record status with a single anomaly score, failing to distinguish between test program branch deviations, pin-channel deviations, contact deviations, and chip-specific deviations. Evidence of data distortion and device malfunctions are mixed together, making it difficult to accurately correlate reliability levels with chips, test rounds, and test items, affecting the accuracy of test data reliability evaluation and the ability to trace the source of anomalies.

[0004] Therefore, how to provide a reliability evaluation method for integrated circuit test data based on AI large models is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] One objective of this invention is to propose a reliability evaluation method for integrated circuit test data based on an AI large-scale model. This invention utilizes test program path reconstruction, initial and retest record reconnection, an improved TimesNet model, dual-track reliability evidence organization, and track-based weighted evaluation techniques. It details the process of constructing integrated circuit test path channel diagrams, generating initial and retest reconnection samples, extracting branch deviations, channel deviations, contact deviations, and chip retention deviations, processing data distortion evidence and device anomaly evidence separately, and determining reliability levels. This achieves a differentiated evaluation of integrated circuit test data distortion and device anomalies. Compared to existing evaluation methods based on single timing or anomaly scores, this invention offers advantages such as accurate test program branch representation, clear correspondence between initial and retest records, strong ability to distinguish between logic pin and physical channel deviations, clear traceability range for contact anomalies, and the ability to link reliability evaluation results to specific test items.

[0006] A method for reliability evaluation of integrated circuit test data based on an AI large model according to an embodiment of the present invention includes: Collect integrated circuit test data and preprocess it to generate an integrated circuit test dataset; Rearrange the integrated circuit test dataset according to the test procedure order, mark the common trunk, conditional branches and convergence anchor points, connect the logic pins and physical channels to the test items, and generate the test path channel diagram. Extract the initial test record and retest record from the test path channel diagram, match them according to chip identifier and test round, associate them with the contact detection record of the corresponding test item, and generate initial and retest reconnection samples; The initial and retested samples are input into the improved TimesNet model, which includes a test branch spectrum splitting block, a pin channel dual coordinate block, and a contact anomaly rollback block to generate a test reliability feature package. Branch deviation, channel deviation and contact deviation in the test reliability feature package are incorporated into the data distortion track, and chip retention deviation is incorporated into the device anomaly track to construct a dual-track reliability evidence matrix. The evidence values ​​of the dual-track reliability evidence matrix are normalized and weighted by track to generate a dual-score sequence of test records. Extract the data distortion scores from the dual-score sequence of test records, match them with preset score ranges and determine the reliability level, associate the device anomaly scores with the corresponding test items, and generate reliability evaluation results for integrated circuit test data.

[0007] Optionally, the integrated circuit test data specifically includes chip identifier, test batch identifier, test machine identifier, test station identifier, test program version, test item identifier, test item execution order, branch conditions, convergence position, test round, test timestamp, test value, upper limit value, lower limit value, test conclusion, logic pin identifier, physical channel identifier, pin channel mapping relationship, continuity test value, contact resistance, and test current.

[0008] Optionally, generating the integrated circuit test dataset includes: Unify the data format of integrated circuit test data, verify the integrity of fields and the order of limit values, mark missing field records and inverted limit value records, and generate field verification data; A composite index is built for the field validation data based on chip identifier, test round, test project identifier and test timestamp. Duplicate records are merged and conflicting records are marked to generate deduplicated test data. The test timestamps of the deduplication test data are converted into a unified time base, sorted according to chip identifier, test round, and test timestamp, and time series correction test data is generated. The timing correction test data, along with field missing markers, limit inversion markers, and conflict markers, are encapsulated using a combined index to generate an integrated circuit test dataset.

[0009] Optionally, generating the test path channel diagram includes: The integrated circuit test dataset is grouped according to the test program version, the test items and execution order of each group are extracted, and adjacent test items are connected according to the execution order to generate a test item order chain; Mark consecutive test items in the test item sequence chain that are not controlled by branch conditions as common trunks, and mark consecutive test items controlled by the same branch conditions as condition branches to generate test program branch chains. Compare the test items after the end of each conditional branch in the test program branch chain, mark the first identical test item as the merging anchor point, and generate the test path structure; Connect the logic pins and physical channels to the corresponding test items in the test path structure, establish node connections according to the test item execution order, conditional branch direction, and pin channel mapping relationship, and generate a test path channel diagram.

[0010] Optionally, generating the initial and retest reconnection samples includes: The test records in the test path channel diagram are collected according to the chip identifier. The earliest test round of each chip is marked as the initial test round, and the remaining test rounds are marked as retest rounds, generating a round mark record set. The test rounds are divided into a set of test round markers. For the same chip, the initial test round and each retest round are paired with corresponding records according to the test item identifier to generate initial and retest record pairs. Map the initial and retest records to the test path channel diagram according to the test project identifier. Based on the logical pin identifiers and physical channel identifiers of the initial and retest records, connect the corresponding contact detection records to the mapping nodes to build the initial and retest back-connection chain. Arrange the mapping nodes in the initial and retest reconnection chain according to the execution order of the test items, encapsulate the initial and retest record pairs, contact detection records, common trunk markers, conditional branch markers, convergence anchor point markers, and node connection relationships to generate initial and retest reconnection samples.

[0011] Optionally, generating the test reliability feature package includes: An improved TimesNet model is constructed, which includes a test branch spectrum splitting block, a pin channel dual coordinate block, and a contact anomaly rollback block; The initial and retested samples are input into the test branch spectrum splitting block. According to the common trunk, conditional branches, and merging anchor points, the initial test record and the retest record are divided into the trunk test sequence and the branch test sequence, respectively. Fast Fourier transform is performed on each test sequence, and the periodic components with the first K positions of the spectrum amplitude are selected. The initial test periodic components and the retest periodic components are aligned according to the conditional branch mark, and spliced ​​at the merging anchor point according to the test item execution order. The test branch spectrum representation is output, where K is a positive integer not greater than the total number of spectrum components. Input the test branch spectrum representation into the pin channel dual coordinate block, establish coordinate indexes according to the logical pin identifier and physical channel identifier respectively, align the initial test cycle component and the retest cycle component under the same test item and corresponding cycle, calculate the logical pin coordinate difference and physical channel coordinate difference respectively, cross-stitch the two types of coordinate differences according to the test item position, and output the pin channel dual coordinate representation. Input the pin channel dual coordinate representation, contact detection records and node connection relationships in the initial and retest reconnection samples into the contact anomaly rewind block. Based on the node connection relationship, locate the mapping node of the contact detection record, align the continuous test values, contact resistance and test current of the initial test stage and the retest stage, calculate the corresponding difference and splice it into a contact change vector. Pass the contact change vector in reverse order along the initial and retest reconnection chain and add it to the pin channel dual coordinate representation corresponding to the node passed through, and output the contact anomaly rewind representation. Based on the periodic components in the test branch spectrum characterization, the contact anomaly rewind characterization is mapped in two dimensions. Two-dimensional convolutions are performed in the intra-period direction and the inter-period direction, respectively. The convolution results are weighted and fused based on the spectral amplitude of the corresponding periodic components. After residual connection and linear mapping, the branch deviation, channel deviation, contact deviation and chip retention deviation corresponding to each test record are obtained, and the test reliability feature package is generated. The initial and retest samples were divided into training and validation sets. The improved TimesNet model was trained using the training set. The test branch spectrum reconstruction loss, pin channel coordinate decoupling loss, contact change folding loss, and chip retention deviation consistency loss were combined as the joint loss. The parameters of the test branch spectrum splitting block, pin channel dual coordinate block, contact anomaly folding block, two-dimensional convolutional layer, and linear mapping layer were updated through backpropagation. The improved TimesNet model training was completed when the absolute value of the difference between the validation set joint loss of adjacent training cycles and the validation set joint loss of the previous training cycle were all less than 0.05% within 7 consecutive training cycles.

[0012] Optionally, constructing the dual-track reliability evidence matrix includes: According to the chip identifier, test round, test item identifier and test item execution order, the branch deviation, channel deviation, contact deviation and chip retention deviation in the test reliability feature package are aligned, and evidence line numbers are set according to the corresponding test records to generate a reliability evidence index table. Based on the reliability evidence index table, branch deviation, channel deviation, and contact deviation are sequentially written into the three data distortion evidence columns of the same evidence row to construct a data distortion track; Based on the evidence row number of the data distortion track, the chip retention deviations corresponding to the same chip identifier, test round, and test item identifier are written into the device anomaly evidence column to construct the device anomaly track; Align the data distortion track and the device anomaly track according to the evidence row numbers, and place the three data distortion evidence columns and one device anomaly evidence column side by side to construct a dual-track reliability evidence matrix.

[0013] Optionally, generating the test record dual-score sequence includes: According to the evidence column, subtract the corresponding preset lower bound from the evidence value in the dual-track reliability evidence matrix, and then divide by the difference between the preset upper bound and the preset lower bound to generate a normalized evidence matrix, where the preset upper bound is greater than the preset lower bound. Configure separate evidence weights for each evidence column within the data distortion track and the device anomaly track, with the sum of the separate evidence weights within each track being 1; The normalized evidence value in the same evidence row is multiplied by the corresponding track-specific evidence weight and summed by track to obtain the data distortion score and device anomaly score, forming a dual-score record. The dual-score records are arranged according to the evidence row order of the dual-track reliability evidence matrix, and associated with the corresponding chip identifier, test round, and test item identifier to generate a test record dual-score sequence.

[0014] Optionally, the matching of preset score ranges and determination of reliability levels includes: Extract the data distortion scores and their associated chip identifiers, test rounds, and test item identifiers from the dual-score sequence of test records, and generate a test record distortion score table; The data distortion scores in the test record distortion score table are compared with the preset score intervals, and the data distortion scores are assigned to the corresponding score intervals to generate a score interval matching table. Based on the preset correspondence between score ranges and reliability levels, the reliability level is marked for each test record in the score range matching table, and a test data reliability level table is generated.

[0015] Optionally, the generation of integrated circuit test data reliability evaluation results includes: Based on the chip identifier, test round, and test item identifier, the reliability level is aligned with the data distortion score and device anomaly score to generate test record evaluation items; Map the device anomaly score in the test record evaluation item to the node with the same test item identifier in the test path channel diagram, record the execution order of the test items in the corresponding node, and generate device anomaly associated evaluation items; The device anomaly association evaluation items are arranged according to chip identifier, test round, and test item execution order. The reliability evaluation results of integrated circuit test data are generated by packaging chip identifier, test round, test item identifier, reliability level, data distortion score, and device anomaly score.

[0016] The beneficial effects of this invention are: This invention proposes a reliability evaluation method for integrated circuit test data based on an AI large model. By rearranging integrated circuit test data, marking common trunks, conditional branches, and convergence anchors in the test program, and connecting logic pins and physical channels to the corresponding test items, a test path channel diagram is constructed. This method can preserve the execution relationship between different test program paths, reduce test record misalignment caused by conditional branch switching and convergence position changes, and improve the completeness and accuracy of integrated circuit test data path representation.

[0017] This invention constructs a preliminary test and retest loop to connect the preliminary test records, retest records, and contact detection records of the same chip. It employs an improved TimesNet model that includes a test branch spectrum splitting block, a pin channel dual coordinate block, and a contact anomaly rewind block to extract branch deviation, channel deviation, contact deviation, and chip retention deviation. This allows it to distinguish test deviations caused by changes in test program path, logic pin changes, physical channel drift, contact anomalies, and changes in the chip itself. This reduces the probability of misjudging poor contact or test channel anomalies as device malfunctions and improves the accuracy of preliminary test and retest data analysis and anomaly source identification.

[0018] This invention incorporates branch deviation, channel deviation, and contact deviation into a data distortion track, and chip retention deviation into a device anomaly track. Through evidence value normalization and track-based weighting, it generates data distortion and device anomaly scores, determines the reliability level based on the data distortion scores, and associates the device anomaly scores with corresponding test items, achieving separate evaluation of test data reliability and device anomaly states. The generated evaluation results can be associated with chip identification, test round, and test items, possessing advantages such as clear evaluation criteria, traceable anomaly sources, accurate test item location, and strong adaptability to different batches of test data. It can be applied to wafer testing, packaging testing, and integrated circuit finished product testing scenarios. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of a method for evaluating the reliability of integrated circuit test data based on a large AI model, as proposed in this invention. Figure 2 This is a schematic diagram of the structure of the improved TimesNet model for an integrated circuit test data reliability evaluation method based on an AI large model proposed in this invention. Figure 3 This is a schematic diagram illustrating the construction of a dual-track reliability evidence matrix for an integrated circuit test data reliability evaluation method based on an AI large model proposed in this invention. Detailed Implementation

[0020] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0021] refer to Figure 1 , Figure 2 and Figure 3 A reliability evaluation method for integrated circuit test data based on an AI large model, comprising: Collect integrated circuit test data and preprocess it to generate an integrated circuit test dataset; Rearrange the integrated circuit test dataset according to the test procedure order, mark the common trunk, conditional branches and convergence anchor points, connect the logic pins and physical channels to the test items, and generate the test path channel diagram. Extract the initial test record and retest record from the test path channel diagram, match them according to chip identifier and test round, associate them with the contact detection record of the corresponding test item, and generate initial and retest reconnection samples; The initial and retested samples are input into the improved TimesNet model, which includes a test branch spectrum splitting block, a pin channel dual coordinate block, and a contact anomaly rollback block to generate a test reliability feature package. Branch deviation, channel deviation and contact deviation in the test reliability feature package are incorporated into the data distortion track, and chip retention deviation is incorporated into the device anomaly track to construct a dual-track reliability evidence matrix. The evidence values ​​of the dual-track reliability evidence matrix are normalized and weighted by track to generate a dual-score sequence of test records. Extract the data distortion scores from the dual-score sequence of test records, match them with preset score ranges and determine the reliability level, associate the device anomaly scores with the corresponding test items, and generate reliability evaluation results for integrated circuit test data.

[0022] In this embodiment, the integrated circuit test data specifically includes chip identifier, test batch identifier, test machine identifier, test station identifier, test program version, test item identifier, test item execution order, branch conditions, convergence position, test round, test timestamp, test value, upper limit value, lower limit value, test conclusion, logic pin identifier, physical channel identifier, pin channel mapping relationship, continuous test value, contact resistance, and test current.

[0023] In this embodiment, generating the integrated circuit test dataset includes: The data format for unified integrated circuit test data is standardized, field integrity and limit order are verified, missing field records and records with inverted limits are marked, and field verification data is generated, including: Generate field validation data, specifically: Establish a field rule table corresponding to the test program version, and record the field standard name, data type, unit of measurement, and required status; Convert the identifier field to string format, convert the test item execution order and test round number to integer format, convert the test quantity value, upper limit value, lower limit value, continuous test value, contact resistance and test current to floating point format, and unify the measurement unit according to the test item identifier; parse the test timestamp into an absolute time integer at the μs level; Verify each piece of integrated circuit test data, set empty values ​​for required fields or fields that cannot be converted to the corresponding data type, and set a field missing flag; When the test program version or chip identifier is missing, it is filled back from the test file header; when the test round is missing, it is filled back from the round segment mark; when the test item identifier is missing, the test program configuration is matched according to the test item execution order; when the test timestamp is missing, a missing placeholder code containing the original record line number is written. Compare the lower limit value with the upper limit value of a record that contains both upper and lower limits. If the lower limit value is greater than the upper limit value, set a limit inversion flag. The standardized test records, field missing markers, and limit inversion markers are encapsulated to generate field validation data. A composite index is built for the field validation data based on chip identifier, test round, test project identifier, and test timestamp. Duplicate records are merged and conflicting records are marked to generate deduplicated test data, where: Generate deduplication test data as follows: The data is validated by dividing the fields according to the test batch identifier and test program version. Within each division result, a four-tuple composite index is generated for each record in a fixed order of chip identifier, test round, test project identifier and test timestamp. When the index field contains a missing placeholder, the original record row number in the missing placeholder is retained. Group the field validation data according to the composite index, compare all business fields and validation flags in the same group except for the composite index fields and the original record row number. If all the comparison contents are the same, the corresponding record is identified as a duplicate record and the record with the smallest original record row number is retained. If any comparison content is different, the corresponding record is identified as a conflict record, all conflict records are retained and the same conflict group number is set, and the group sequence number is set according to the original record row number; The composite index, retained records, field missing markers, limit inversion markers, conflict markers, conflict group numbers, and group sequence numbers are encapsulated to generate deduplication test data. The test timestamps of the deduplicated test data are converted to a unified time base, and sorted according to chip identifier, test round, and test timestamp to generate timing correction test data, where: Generate timing correction test data, specifically as follows: During the test equipment calibration phase, calibration pulses are synchronously input to each test equipment. The calibration timestamp recorded by the test equipment is subtracted from the calibration timestamp recorded by the reference clock to obtain the clock offset of the corresponding test equipment. Subtract the corresponding clock offset from the μs-level absolute time integer in the deduplication test data to obtain the corrected absolute time; The earliest calibration absolute time within the same test batch is determined as the time base origin. The calibration absolute time of each record is subtracted from the time base origin and then divided by 1000 to obtain the calibration test timestamp in ms. For records with missing test timestamps as placeholders, locate the valid timestamps before and after the test items in the same chip and test round according to the execution order. When there are valid timestamps before and after the test, divide the time difference between the two times by the number of consecutive missing records and add 1 to obtain the interpolation interval, and accumulate them item by item to generate the correction test timestamp. When only one valid timestamp exists, increment or decrease the timestamps according to the median of the time differences between adjacent valid records in the same group; when no valid timestamp exists, retain the missing placeholder code. Deduplicated test data are sorted in ascending order by chip identifier, test round, and correction test timestamp. When the correction test timestamps are the same, they are sorted by the execution order of the test items and the sequence number in the conflict group. Records with missing placeholder test timestamps are arranged after the valid timestamp records in the same round. Keep the four-tuple composite index unchanged, write the correction test timestamp to the corresponding record, and generate time series correction test data; The timing correction test data, along with field missing markers, limit inversion markers, and conflict markers, are encapsulated using a combined index to generate an integrated circuit test dataset.

[0024] In this embodiment, generating the test path channel diagram includes: The integrated circuit test dataset is grouped according to the test program version. Test items and their execution order are extracted from each group. Adjacent test items are connected according to their execution order to generate a test item order chain, where: The test item order chain is generated as follows: The integrated circuit test dataset is divided according to the test program version. Records with complete test project identifiers and test project execution order are selected. The test project identifier and test project execution order are combined into project order pairs. Duplicate project order pairs are merged, and the retained project order pairs are set as test project nodes. Within each test program version group, test project nodes are arranged in ascending order according to the execution order of the test projects. Sequential connections are set between adjacent test project nodes, and the predecessor and successor nodes of each node are recorded. The test program version, test project node, test project execution order and order connection relationship are encapsulated to generate a test project order chain; In the test item sequence chain, consecutive test items not controlled by branch conditions are marked as the common trunk, and consecutive test items controlled by the same branch condition are marked as conditional branches, generating a test program branch chain, where: The test program branch chain is generated as follows: Associate test project nodes with branch conditions in the integrated circuit test dataset according to the test program version, test project identifier, and test project execution order; When the branch condition is empty, the corresponding node is marked as an uncontrolled node. When the branch condition is not empty, the branch condition is split into condition object, comparison relation and condition value according to the comparison operator, and the corresponding node is marked as a controlled node. Traverse the test project nodes along the sequential connection relationship, group consecutive uncontrolled nodes into the same common trunk, group consecutive controlled nodes with the same condition object, comparison relationship and condition value into the same condition branch, and set the branch direction by the combination of comparison relationship and condition value. When the node control state or branch conditions change, a new common trunk or conditional branch is created. Record the starting node, ending node, branch condition, branch direction, and adjacent connection relationship of each common trunk and conditional branch to generate the test program branch chain; Compare the test items following the end of each conditional branch in the test program's branch chain, mark the first identical test item as the merge anchor point, and generate the test path structure, where: The test path structure is generated as follows: According to the test program version, conditional branches with different branch directions are grouped into the same branch group based on the condition that they originate from the same common trunk end and have the same conditional object, and the end node of each conditional branch is recorded. Starting from each end node, traverse backwards along the sequential connection relationship according to the execution order of the test items, skipping nodes belonging to other branch directions within the same branch group, to form the end successor item sequence respectively; Compare the test item identifiers and test item execution order in each end successor item sequence, and mark the test item node that is commonly contained in all sequences and has the smallest execution order as the convergence anchor point; Record the path relationships between the end of the common trunk, the start and end nodes of conditional branches, the branch directions, and the merging anchor points to generate the test path structure; Connect logic pins and physical channels to the corresponding test items in the test path structure. Establish node connections according to the test item execution order, conditional branch direction, and pin channel mapping relationship to generate a test path channel diagram, where: Generate the test path channel diagram, specifically as follows: The test project nodes are located according to the test program version, test project identifier, and test project execution order. The logic pin identifier, physical channel identifier, and pin channel mapping relationship of the corresponding test record are extracted from the integrated circuit test dataset. Set the logic pin nodes using the test program version and logic pin identifier, and set the physical channel nodes using the test machine identifier, test station identifier, and physical channel identifier; Along the common trunk and conditional branches, connect adjacent test item nodes according to the test item execution order. Connect the end of the common trunk to the first node of each conditional branch and write the branch direction. Connect the end of each conditional branch to the corresponding merging anchor point to form a test path connection. Establish project pin connections between test project nodes and logical pin nodes, project channel connections between test project nodes and physical channel nodes, and pin channel connections between logical pin nodes and physical channel nodes respectively, and merge duplicate connections with the same start node, end node, and connection type. Based on the test program version, test project identifier, and test project execution order, the test records in the integrated circuit test dataset are associated with the corresponding test project nodes to generate a test record index relationship; Encapsulate the relationships between test project nodes, logical pin nodes, physical channel nodes, test path connections, project pin connections, project channel connections, pin channel connections, and test record indexes to generate a test path channel diagram.

[0025] In this embodiment, generating the initial and retested samples includes: The test records in the test path channel diagram are collected according to the chip identifier. The earliest test round of each chip is marked as the initial test round, and the remaining test rounds are marked as retest rounds, generating a round mark record set. The test round marker record set is divided according to chip identification and test round. For the same chip, records are paired according to the test item identifier between the initial test round and each subsequent test round to generate initial and subsequent test record pairs. Generate initial and retest record pairs, specifically as follows: The initial test rounds of the same chip are paired with each retest round, and the test records in each round pair are grouped according to the test item identifier. When a group contains only one initial test record and one retest record, they are directly paired; when a group contains multiple records, they are first matched according to the logical pin identifiers, and then the group numbers are set according to the test item execution order, test timestamp, and the ascending order of the conflict group number. Initial test records and retest records with the same group number are then paired. For test item records that exist only on one side or records that are not fully paired, write the test item identifier, logic pin identifier, and group sequence number of the non-missing record into the missing record, and set an initial test missing mark or a retest missing mark; encapsulate the round pair identifier, initial test record, retest record, and missing mark to generate an initial and retest record pair; Map the initial and retest records to the test path channel diagram according to the test item identifier. Based on the logical pin identifiers and physical channel identifiers of the initial and retest records, connect the corresponding contact detection records to the mapping nodes to construct the initial and retest back-connection chain, where: The initial and subsequent test-back connection is constructed as follows: Based on the test program version, test item identifier, and test item execution order in the initial test record and retest record, locate the test item node in the test path channel diagram; copy the located test item node, write the chip identifier and test round, and generate the initial test mapping node and retest mapping node; when one side record is missing and the test item node is not located, copy the test item identifier and path position of the non-missing mapping node to generate the missing mapping node. Records with complete continuous test values, contact resistance, and test current are selected from the integrated circuit test dataset. Non-missing mapping nodes are matched according to chip identifier, test round, logic pin identifier, and physical channel identifier. Candidate records with test timestamps no later than the corresponding test records are selected. The test timestamps of the corresponding test records are subtracted from the test timestamps of the candidate records, and the candidate record with the smallest difference is selected as the contact detection record and connected to the mapping node. If no candidate record is matched or the mapping node is missing, a contact absence flag is set. The initial and retest record pairs are processed according to the round pair identifiers. Within the initial and retest rounds, the mapping nodes are connected according to the test path connection, branch direction, and test item execution order. A round back-connection connection is established between each initial and retest record pair, pointing from the retest mapping node to the initial test mapping node. The test path connection, round back-connection connection, and contact detection record connection are combined to construct the initial and retest back-connection chain. Arrange the mapping nodes in the initial and retest reconnection chain according to the execution order of the test items, encapsulate the initial and retest record pairs, contact detection records, common trunk markers, conditional branch markers, convergence anchor point markers, and node connection relationships to generate initial and retest reconnection samples.

[0026] In this embodiment, generating the test reliability feature package includes: An improved TimesNet model is constructed, comprising a test branch spectrum splitting block, a pin channel dual-coordinate block, and a contact anomaly rollback block, wherein: The improved TimesNet model is constructed as follows: The traditional TimesNet model retains the data embedding layer, periodic 2D mapping, 2D convolutional layer, spectral amplitude weighted aggregation layer, residual connection, and linear mapping layer. The period discovery part in TimesBlock that directly performs fast Fourier transform on the complete test sequence and filters the main period is replaced with the test branch spectrum splitting block. The test branch spectrum splitting block is connected after the data embedding layer. The test sequence is split according to the common trunk, conditional branches, and confluence anchor points. The periodic components are extracted and the initial and retest branches are aligned. Between the test branch spectrum splitting block and the periodic two-dimensional mapping, a pin channel dual coordinate block and a contact anomaly rollback block are added in sequence. The pin channel dual coordinate block receives the test branch spectrum representation, logical pin identifier, and physical channel identifier, and performs initial and retest coordinate alignment, subtraction, and cross splicing. The contact anomaly rollback block receives the pin channel dual coordinate representation, contact detection record, and node connection relationship, generates a contact change vector, and transmits it in reverse order along the initial and retest rollback chain. The improved TimesNet model is obtained by using a two-dimensional periodic mapping, a two-dimensional convolutional layer, a spectral amplitude weighted aggregation layer, a residual connection, and a linear mapping layer to represent the contact anomaly convolutional characterization input. The initial and retest samples are input into the test branch spectrum splitting block. Based on the common trunk, conditional branches, and merging anchor points, the initial and retest records are divided into trunk test sequences and branch test sequences, respectively. A Fast Fourier Transform is performed on each test sequence, and the top K periodic components by spectral amplitude are selected. The initial and retest periodic components are aligned according to the conditional branch markers, and then concatenated at the merging anchor points according to the test item execution order. The test branch spectrum representation is output, where K is a positive integer not greater than the total number of spectral components. The test branch spectrum splitting block includes: Path segmentation index table: stores the execution order of test projects, path type, conditional branch markers, branch direction, merging anchor points, and node positions; Initial and retest dual-sequence queues: caching initial test features and retest features respectively; Branch slice address generator: determines the splitting position and zero-padding length of the trunk test sequence and branch test sequence; Fast Fourier Transform (FFT) computation array: calculates the complex spectral coefficients and spectral amplitudes of each test sequence; K-value register: stores the number K of cycle components selected; Spectrum amplitude priority queue: Select the first K frequency indices based on the joint spectrum amplitude; Periodic component alignment table: Generates initial and retest periodic features and alignment masks according to conditional branch markers and frequency indices; Anchor point splicing buffer queue: splices periodic features according to the merged anchor points and the execution order of test items, records branch boundaries and outputs test branch spectrum representation; The process of testing the branch spectrum splitting block is as follows: The initial and retest feedback samples are divided according to the round pair identifier, and each round pair is processed one by one; assuming that a round pair contains L mapping nodes, the data embedding layer converts each mapping node into a D-dimensional feature vector, where D is set to 128, and the initial and retest double sequence queues form an initial test feature matrix and a retest feature matrix of size L×D respectively. The path segment index table writes the test item execution order, path type, conditional branch flag, branch direction, merging anchor point position, and node position of each mapped node into a path index matrix of size L×6; The branch slice address generator determines B segments based on the union of the initial test path segments and the retest path segments, and extracts the initial test features and retest features of the b-th segment according to the path index matrix. The K-value register is set to K=5. The branch slice address generator writes the missing mapping node as a D-dimensional zero vector and pads the end of the segment with zeros, so that the segment length of the initial test feature and the retest feature is unified to Lb, and Lb is not less than 2K+1. The output segment feature tensor has a size of 2×Lb×D, where 2 represents the initial test round and the retest round. The Fast Fourier Transform (FFT) computation array performs FFT on the D feature channels in the segment feature tensor along the node position direction, retaining the spectral coefficients in the range from zero frequency to the highest non-repetition frequency, and obtaining a complex spectral tensor of size 2×Fb×D, where Fb is equal to Lb divided by 2, rounded down and then added by 1, and the spectral amplitude of the zero frequency component is set to 0. For each non-zero frequency index, calculate the modulus of the initial and retested complex spectral coefficients respectively. Add the modulus of the D characteristic channels and divide by D to obtain the initial and retested spectral amplitudes. Then calculate the average of the two spectral amplitudes to obtain the joint spectral amplitude. The spectrum amplitude priority queue arranges the non-zero frequency indices in descending order of joint spectrum amplitude, outputs the first K frequency indices, divides the segment length Lb by each frequency index and takes the integer part to obtain the K period lengths; The periodic component alignment table uses the conditional branch marker and frequency index as the combination key to write the segment feature tensor of size 2×Lb×D into K period positions respectively, generating a segment periodic feature tensor of size 2×K×Lb×D, and writing the corresponding period length, initial measured spectrum amplitude and remeasured spectrum amplitude into the period record. When one side of the conditional branch is missing, the corresponding periodic feature is written as 0 and the alignment mask is set to 0, while the alignment mask of the remaining positions is set to 1. The anchor point splicing buffer queue is arranged into B segments according to the execution order of the test items. Branch boundary markers are written at the locations where the conditional branch direction changes, and only one merging anchor point is retained at the same merging location. By concatenating the segment periodic feature tensor along the node position direction, a branch periodic feature tensor of size 2×K×L′×D is obtained. At the same time, a period length matrix of size B×K, a spectral amplitude tensor of size 2×B×K, and an alignment mask of size 2×K×L′ are generated, where L′ is the number of nodes after concatenation. The branch periodic feature tensor, period length matrix, spectral amplitude tensor, path marker, branch boundary marker and alignment mask are encapsulated according to round pair identifiers, and the test branch spectrum representation is output. The test branch spectrum representation is input into the pin channel dual-coordinate block. Coordinate indices are established according to the logical pin identifier and the physical channel identifier, respectively. Under the same test item and corresponding period, the initial test period component and the retest period component are aligned. The logical pin coordinate difference and the physical channel coordinate difference are calculated separately. The two types of coordinate differences are cross-stitched according to the test item position, and the pin channel dual-coordinate representation is output, where: The pin channel dual coordinate block includes: Periodic feature cache: caches the test branch spectrum representation and node attribute index table; Logic pin coordinate index table: maps logic pin identifiers and coordinate vectors; Physical Channel Coordinate Index Table: Maps physical channel combination identifiers and coordinate vectors; Dual-coordinate encoding array: Two types of coordinate vectors are written into the periodic features respectively; Test Project Cycle Positioning Table: Records the test project, section, cycle, and location of the test project; Initial and retest alignment queue: Pairing initial and retest coordinate features; Logic Pin Differential Calculator: Calculates the coordinate difference between initial and retested logic pins; Physical Channel Difference Calculator: Calculates the coordinate difference between the physical channels in the initial and subsequent measurements; Dual-coordinate cross-stitch array: stitches together two types of coordinate differences according to the location of the test item; Coordinate fusion projector: maps the stitching result and outputs a dual-coordinate representation of the pin channels; The processing procedure for the pin channel dual coordinate block is as follows: The periodic feature buffer receives the test branch spectrum characterization and extracts the branch periodic feature tensor, period length matrix, spectrum amplitude tensor, path marker, branch boundary marker, alignment mask and node attribute index table of size 2×K×L′×D, where D is 128, K is 5 and L′ is the number of nodes after splicing. During model initialization, the number of logical pin identifiers P in the training data and the number of physical channel combination identifiers C, which consist of test machine identifiers, test station identifiers and physical channel identifiers, are counted. The logical pin coordinate index table and the physical channel coordinate index table are set to trainable coordinate matrices with a size of P+1 rows by 32 columns and C+1 rows by 32 columns, respectively. The last row is set as a zero vector, and the identifiers that do not appear in the training data are mapped to the last row. The remaining coordinate vectors are uniformly initialized using Xavier. Query the logical pin coordinate vectors and physical channel coordinate vectors of the initial test record and the retest record according to the node attribute index table, and copy the 32-dimensional coordinate vectors to K cycle positions; The dual-coordinate encoding array concatenates each 128-dimensional periodic feature with the corresponding 32-dimensional coordinate vector to generate a logic pin coordinate feature tensor and a physical channel coordinate feature tensor, both with a size of 2×K×L′×160. The test project cycle positioning table uses the test project identifier, test project execution order, segment identifier, and cycle position as positioning keys, and records the node positions corresponding to each positioning key; The initial and retest alignment queues are paired with the initial and retest coordinate features according to the positioning key, and the positions with alignment mask 0 are written into a 160-dimensional zero vector. The logic pin differential calculator subtracts the corresponding initial logic pin coordinate features from the retested logic pin coordinate features, generating a logic pin coordinate difference tensor of size K×L′×160; The physical channel differential calculator uses the same calculation order to generate a physical channel coordinate difference tensor with a size of K×L′×160; The dual-coordinate cross-stitching array divides the 160 feature components of the two types of coordinate differences into 8 groups, each group containing 20 consecutive feature components, and arranges them alternately according to the logical pin group and the physical channel group to generate a dual-coordinate stitching tensor with a size of K×L′×320. The coordinate fusion projector uses a weight matrix of size 320×128 and a bias vector of size 128 to perform a linear mapping on the dual coordinate splicing tensor, and then performs GELU activation and layer normalization in sequence to obtain a dual coordinate feature tensor of size K×L′×128. The dual-coordinate feature tensor is encapsulated with the corresponding period length matrix, spectral amplitude tensor, path marker, branch boundary marker, alignment mask and node attribute index table, and the pin channel dual-coordinate representation is output. The pin channel dual-coordinate representation, contact detection records from the initial and retest reconnection samples, and node connection relationships are input into the contact anomaly rewind block. Based on the node connection relationships, the mapping nodes for the attached contact detection records are located. The continuous test values, contact resistance, and test current between the initial and retest stages are aligned, and the corresponding differences are calculated and concatenated into a contact change vector. This contact change vector is then passed in reverse order along the initial and retest reconnection chain and added to the pin channel dual-coordinate representation corresponding to the nodes along the path. The resulting contact anomaly rewind representation is then output, where: Contact anomaly rewind block includes: Dual-coordinate representation of the buffer: dual-coordinate representation of the buffer pin channels; Dual queues for contact record keeping: caching initial contact detection records and re-contact detection records respectively; Contact Node Index Table: Records the connection relationship between contact detection records and mapping nodes; Initial and retest contact alignment queue: Pairing initial and retest contact quantities; Contact Difference Scale Register: Stores the scaling parameters for the difference between the three types of contact quantities; Contact Three-Quantity Differential Calculator: Calculates the initial and retest differences of continuous test values, contact resistance, and test current; Contact vector projector: stitches together contact differences and vacancy markers and completes dimension mapping; Reverse stack: Store reverse nodes according to the initial, retest, and reverse chain; Wrap-up weight lookup table: stores wrap-up weights for different connection types; Node rollback accumulator: Weights the contact change vector and writes it to the nodes it passes through; Output buffer for rewind characterization: Output contact anomaly rewind characterization; The process for handling abnormal rollback blocks is as follows: The dual-coordinate representation of the receiver pin channel of the dual-coordinate representation buffer is performed by extracting the dual-coordinate feature tensor, period length matrix, spectral amplitude tensor, path marker, branch boundary marker, alignment mask and node attribute index table of size K×L′×D, where K is 5, D is 128 and L′ is the number of nodes. The contact record is cached in two queues according to the round and the identifier, respectively, for the initial contact detection record and the re-contact detection record; The contact node index table, based on the contact detection record connection and node attribute index table, converts the contact detection records into node positions in a dual-coordinate feature tensor, and records the test item execution order, conditional branch markers, and contact absence markers. The initial and retest contact alignment queue is connected back to the paired initial and retest mapping nodes along the round, and the continuous test values, contact resistance and test current are extracted to form an initial test contact quantity matrix, a retest contact quantity matrix and a contact effective mark matrix, each with a size of Q×3, where Q is the number of contact record pairs; when there are corresponding contact quantities on both sides of the initial and retest, the contact effective mark is set to 1, otherwise it is set to 0; During model initialization, the 95th percentile of the absolute value of the difference between the initial and retest values ​​of the three types of contact quantities with a valid contact marker of 1 in the training data is calculated. Each percentile is compared with 0.000001 and the larger value is written into the contact difference scale register. For positions where the effective contact mark is 1, the contact difference calculator subtracts the initial contact value from the remeasured contact value, divides by the corresponding difference scaling parameter, and limits the resulting value to the range of -1 to 1. For positions where the effective contact mark is 0, the normalized contact difference is set to 0 and the missing mark is set to 1, generating a normalized contact difference matrix and a missing mark matrix of size Q×3. The contact vector projector concatenates three normalized contact differences with three missing markers to generate a contact change input matrix of size Q×6. Then, it performs linear mapping and GELU activation using a weight matrix of size 6×128 and a 128-dimensional bias vector to generate a contact change vector matrix of size Q×128, and copies each contact change vector to K period positions. The reverse stack is started from the mapping node of the retest contact detection record. When the retest contact detection record is missing, it starts from the corresponding initial test mapping node. Each stack item carries the condition branch mark of the actual execution of the corresponding test round. The predecessor node is pushed in the opposite direction of the test path connection. When the branch boundary mark is encountered, the cross-branch push stops. When the retest mapping node is reached, the corresponding initial test mapping node is pushed in the retest connection along the round. When the merging anchor point is reached, only the predecessor node with the same condition branch mark is pushed in. The already pushed node is not pushed in again. The rollback weight lookup table sets the trainable weight parameters for ordinary test path connections, round rollback connections, and test path connections with the endpoint being the rendezvous anchor point. Each weight parameter is limited to between 0 and 1 after being transformed by the Sigmoid function, and the initial weights after transformation are set to 0.9, 0.99, and 0.8 respectively. Each time a node is popped from the reverse stack, the initial contact change vector is multiplied by the product of the connection weights from the starting point to the current node to generate the current node's wrap vector. The node rollback accumulator sums the rollback vectors that arrive at the same node, and then divides them by the number of contact change vectors that arrive at the corresponding node to obtain a contact rollback tensor of size K×L′×128. Nodes that do not receive rollback vectors are written into a 128-dimensional zero vector. The contact rollback tensor is added element by element to the dual-coordinate feature tensor to generate a contact anomaly enhancement tensor. The rollback representation output buffer encapsulates the contact anomaly enhancement tensor with the corresponding period length matrix, spectral amplitude tensor, path marker, branch boundary marker, alignment mask, and node attribute index table, and outputs the contact anomaly rollback representation. Based on the periodic components in the test branch spectrum representation, a two-dimensional mapping is performed on the contact anomaly rewind representation. Two-dimensional convolutions are performed in the intra-period direction and the inter-period direction, respectively. The convolution results are weighted and fused based on the spectral amplitude of the corresponding periodic components. After residual connection and linear mapping, the branch deviation, channel deviation, contact deviation, and chip retention deviation corresponding to each test record are obtained, generating a test reliability feature package, in which: Generate a test reliability feature package, specifically as follows: A contact anomaly enhancement tensor of size K×L′×128 is extracted from the contact anomaly rollback characterization. It is divided into B non-overlapping segments according to path markers and branch boundary markers, and the period length and spectral amplitude of each segment are obtained. For the k-th periodic component of the b-th segment, divide the number of nodes in the segment by the corresponding period length and round up to get the number of period rows. Then, insert a 128-dimensional zero vector at the end of the segment and rearrange the segment features into a two-dimensional feature tensor of period row number × period length × 128. Two-dimensional convolution is performed along the periodic direction using a 1×3 convolution kernel, with one column of zero values ​​padded on each side of the column direction. Two-dimensional convolution is performed along the periodic direction using a 3×1 convolution kernel, with one row of zero values ​​padded on each side of the row direction. The stride of both convolutions is 1, and the number of output channels is 128. The two convolution results are concatenated along the channel direction. The number of channels is mapped from 256 to 128 through 1×1 two-dimensional convolution. After GELU activation, the convolution is expanded row by row, and the zero-padded positions are removed to obtain the periodic convolution result. Calculate the average of the initial and retested spectral amplitudes for the same segment, perform Softmax normalization on the K average spectral amplitudes to obtain the periodic fusion weights, sum the K periodic convolution results according to the periodic fusion weights, and add them element by element to the pre-mapping segment features that are summed according to the same weights, perform layer normalization, and obtain the segment fusion features; The fused features of B segments are written back to the corresponding positions of the contact anomaly enhancement tensor according to the node positions, resulting in a reliability fusion feature matrix of size L′×128. Four sets of weight matrices and bias vectors of size 128×1 are used to perform linear mapping and Softplus processing respectively, forming a bias matrix of size L′×4. The four columns are branch bias, channel bias, contact bias and chip retention bias respectively. Query the node attribute index table according to the node position, write the retest round as the test round, and encapsulate each row of the deviation matrix with the chip identifier, test round, test item identifier, test item execution order, path marker, branch boundary marker, alignment mask and missing marker to generate a test reliability feature package; The initial and retest samples were divided into training and validation sets. The improved TimesNet model was trained using the training set. The test branch spectrum reconstruction loss, pin channel coordinate decoupling loss, contact change folding loss, and chip retention deviation consistency loss were combined as a joint loss. The parameters of the test branch spectrum splitting block, pin channel dual coordinate block, contact anomaly folding block, 2D convolutional layer, and linear mapping layer were updated through backpropagation. The improved TimesNet model training was complete when the absolute value of the difference between the validation set joint loss in adjacent training epochs and the validation set joint loss in the previous training epoch were all less than 0.05% over seven consecutive training epochs. The improved TimesNet model is trained as follows: The initial and retest samples were grouped according to the chip identification. 80% of the chip groups were assigned to the training set and 20% to the validation set. Samples corresponding to the same chip were assigned to the same dataset. The training set was divided into training batches of 64 samples and input into the improved TimesNet model to obtain branch bias, channel bias, contact bias and chip retention bias. Record pairs with complete initial and retest test values, upper limit values ​​and lower limit values ​​and no inverted markings were selected. The absolute value of the difference between the initial test value and the retest test value was divided by the larger value between the absolute value of the difference between the upper limit value and the lower limit value and 0.000001. The resulting ratio was limited to the range of 0 to 1 to obtain the test value bias benchmark. Write the K initial and retested spectral coefficients back to their corresponding frequency positions, padding the remaining frequency positions with zeros. Perform an inverse fast Fourier transform, average the absolute values ​​of the reconstructed sequence differences along the feature dimension to obtain the branch spectrum deviation benchmark, calculate the mean square error with the branch deviation to obtain the test branch spectrum reconstruction loss. Calculate the mean square of the inner product of the normalized logic pin coordinate difference and the physical channel coordinate difference, average the absolute value of the physical channel coordinate difference along the feature dimension, and calculate the mean square error with the channel deviation. Add the two to obtain the pin-channel coordinate decoupling loss. Squaring the absolute values ​​of the normalized differences of the three types of contact quantities... The mean value is multiplied by 0.9 raised to the power of the number of reconnections. The average value of the calculation results reaching the same node is taken to obtain the contact change benchmark. The mean square error of the contact deviation is calculated to obtain the contact change roll-back loss. The branch spectrum deviation benchmark, channel deviation benchmark, and contact change benchmark are subtracted from the test value deviation benchmark and the negative value is set to 0 to obtain the chip retention deviation benchmark. The mean square error of the chip retention deviation and the corresponding benchmark is calculated. The mean square difference of the chip retention deviation under the same chip identifier and test item identifier with at least 2 retest rounds is calculated. The two are added together to obtain the chip retention deviation consistency loss. The four losses are multiplied by 0.30, 0.20, 0.25, and 0.25 respectively and then summed to obtain the joint loss. Backpropagation is performed using the AdamW optimizer with an initial learning rate of 0.001 and a weight decay coefficient of 0.0001. The trainable parameters of the improved TimesNet model are updated. Starting from the second training epoch, the absolute value of the difference between the joint losses of adjacent validation sets is divided by the larger of the joint loss of the validation set in the previous training epoch and 0.0000001 to obtain the relative rate of change of loss. When the relative rate of change of loss is less than 0.05% for seven consecutive training epochs, the training of the improved TimesNet model is completed.

[0027] In this embodiment, constructing the dual-track reliability evidence matrix includes: According to chip identifier, test round, test item identifier, and test item execution order, the branch deviation, channel deviation, contact deviation, and chip retention deviation in the test reliability feature package are aligned, evidence line numbers are set according to the corresponding test records, and a reliability evidence index table is generated, in which: Generate a reliability evidence index table, specifically as follows: According to the encapsulation order of the test reliability feature package, set the feature record number for each feature record, and extract the corresponding chip identifier, test round, test item identifier, test item execution order and four deviations; The chip identifier, test round, test item identifier, and test item execution order are combined into a record key. Branch deviation, channel deviation, contact deviation, and chip retention deviation in the same feature record are aligned to the same record key. Feature records with the same record key but different feature record numbers are retained separately. Feature records are arranged sequentially according to chip identifier, test round, test item identifier, test item execution order and feature record number. Evidence line numbers are set continuously starting from 1. The correspondence between evidence line number, feature record number, record combination key and four deviations is encapsulated to generate a reliability evidence index table. Based on the reliability evidence index table, branch deviation, channel deviation, and contact deviation are sequentially written into the three data distortion evidence columns of the same evidence row to construct a data distortion track; Based on the evidence row number of the data distortion track, the chip retention deviations corresponding to the same chip identifier, test round, and test item identifier are written into the device anomaly evidence column to construct the device anomaly track; Align the data distortion track and the device anomaly track according to the evidence row numbers, and place the three data distortion evidence columns and one device anomaly evidence column side by side to construct a dual-track reliability evidence matrix.

[0028] In this embodiment, generating the test record dual-score sequence includes: Based on the evidence column, subtract the corresponding preset lower bound from the evidence value in the dual-track reliability evidence matrix, and then divide by the difference between the preset upper bound and the preset lower bound to generate a normalized evidence matrix, where the preset upper bound is greater than the preset lower bound. Generate a normalized evidence matrix, specifically as follows: The improved TimesNet model, trained by inputting the initial and retest feedback samples from the validation set, generates a validation set test reliability feature package. Based on the validation set test reliability feature package, a validation set reliability evidence index table is generated, and a dual-track reliability evidence matrix for the validation set is constructed. Let M be the number of evidence rows in the dual-track reliability evidence matrix of the verification set. Sort the M evidence values ​​of the four evidence columns in ascending order, starting from 1. Calculate the sorting position, and set the evidence value at the corresponding position after multiplying 0.05 by M and rounding up as the preset lower bound. Set the evidence value at the corresponding position after multiplying 0.95 by M and rounding up as the preset upper bound. When the two benchmarks are equal, set the sum of the preset lower bound and 0.000001 as the preset upper bound. Fix and save the benchmark boundaries of the four evidence columns. According to the evidence column, subtract the corresponding preset lower bound from the evidence value in the dual-track reliability evidence matrix, and then divide by the difference between the preset upper bound and the preset lower bound. Set the calculation result less than 0 to 0 and the calculation result greater than 1 to 1. Write the normalized evidence values ​​according to the original evidence row number and evidence column order to generate a normalized evidence matrix; Assign separate evidence weights to each evidence column within the data distortion track and the device anomaly track, with the sum of the separate evidence weights within each track being 1. Configure the weights of evidence for each track as follows: Extract the validation set test branch spectrum reconstruction loss, validation set pin channel coordinate decoupling loss, and validation set contact change folding loss from ... Calculate 1 divided by the sum of the average loss of each validation set and 0.000001 to obtain the inverse coefficients of the losses corresponding to branch bias, channel bias and contact bias. Divide each inverse coefficient of loss by the sum of the three inverse coefficients of loss to obtain the track-by-track evidence weights of the three evidence columns within the data distortion track. Set the weight of the track-specific evidence column of the chip retention deviation evidence column within the device abnormal track to 1, and associate the weight of each track-specific evidence column with the corresponding evidence column; The normalized evidence value in the same evidence row is multiplied by the corresponding track-specific evidence weight and summed by track to obtain the data distortion score and device anomaly score, forming a dual-score record. The dual-score records are arranged according to the evidence row order of the dual-track reliability evidence matrix, and associated with the corresponding chip identifier, test round, and test item identifier to generate a test record dual-score sequence.

[0029] In this embodiment, matching the preset score range and determining the reliability level includes: Extract the data distortion scores and their associated chip identifiers, test rounds, and test item identifiers from the dual-score sequence of test records, and generate a test record distortion score table; The data distortion scores in the test record distortion score table are compared with the preset score intervals, and the data distortion scores are assigned to the corresponding score intervals to generate a score interval matching table, where: Generate a score range matching table, specifically as follows: The boundaries of the first to fourth score intervals are set to 0 to 0.25, 0.25 to 0.50, 0.50 to 0.75 and 0.75 to 1, respectively. The first score interval includes both the lower and upper boundaries, while the other score intervals do not include the lower boundary but do include the upper boundary. According to the record order of the test record distortion score table, compare the data distortion score with the interval boundary, write the corresponding score interval number, and encapsulate the chip identifier, test round, test item identifier, data distortion score, score interval number and interval boundary to generate a score interval matching table; Based on the preset correspondence between score ranges and reliability levels, the reliability level is marked for each test record in the score range matching table, generating a test data reliability level table, where: Generate a reliability level table for the test data, specifically as follows: The first score range to the fourth score range correspond to the reliability levels from Level 1 to Level 4, with Level 1 being the highest and Level 4 being the lowest. The reliability level is written into the corresponding test record according to the score range number, and the chip identifier, test round, test item identifier, data distortion score, score range number and reliability level are encapsulated to generate a test data reliability level table.

[0030] In this embodiment, generating reliability evaluation results for integrated circuit test data includes: Based on chip identification, test round, and test item identification, the reliability level is aligned with the data distortion score and device anomaly score to generate test record evaluation items, including: Generate test record evaluation items, specifically: Extract the reliability level records from the test data reliability level table and the double score records from the test record double score sequence, respectively. Form a record combination key according to the chip identifier, test round, and test item identifier, and group them according to the record combination key. Within each group, the reliability level records are arranged according to the original record order, the double score records are arranged according to the evidence row order, the two types of records with the same order position are paired, the order position of the double score record in the double score sequence of the test record is determined as the evidence row number, and the reliability level, data distortion score and device anomaly score are written into the same evaluation record. Determine the feature record number in the reliability evidence index table based on the evidence line number, and extract the corresponding test program version and test item execution order from the test reliability feature package; The evidence line number, feature record number, chip identifier, test round, test program version, test item identifier, test item execution order, reliability level, data distortion score, and device anomaly score are encapsulated to generate test record evaluation items; Map the device anomaly scores in the test record evaluation entries to nodes with the same test item identifier in the test path channel diagram, record the execution order of the test items at the corresponding nodes, and generate device anomaly association evaluation entries, where: The generated device anomaly correlation evaluation items are as follows: Extract the test program version, test project identifier, and test project execution order from each test record evaluation item. Filter test project nodes with the same test program version and test project identifier in the test path channel diagram to generate a candidate mapping node set. Candidate mapping nodes with the same execution order of test items are retained. When there are multiple retained nodes, common trunk markers, conditional branch markers, and convergence anchor markers are extracted from the test reliability feature package according to the feature record sequence number, and matched with the corresponding markers of the retained nodes to determine the target mapping node. The evidence line number, device anomaly score, and target mapping node identifier are combined to form a node mapping record, which is then encapsulated with the test record evaluation items, the test item execution order of the target mapping node, the common trunk marker, the conditional branch marker, and the convergence anchor point marker to generate device anomaly association evaluation items. The device anomaly association evaluation items are arranged according to chip identifier, test round, and test item execution order. The reliability evaluation results of integrated circuit test data are generated by packaging chip identifier, test round, test item identifier, reliability level, data distortion score, and device anomaly score.

[0031] Example 1: To verify the feasibility of this invention in practice, it was applied to an integrated circuit packaging test batch. Data from four final test stations and two retest stations were selected for reliability evaluation. The test subjects were 9600 mixed-signal chips, of which 1268 chips entered retesting after initial test failure, resulting in a total of 1,304,160 test records. The test records simultaneously showed issues such as poor test socket contact, physical channel drift, and chip-specific abnormalities. Traditional fixed-limit methods can only identify whether test values ​​exceed limits, but cannot determine whether the exceedance results stem from distorted test data or chip defects.

[0032] The system collects chip identifier, batch identifier, machine identifier, workstation identifier, program version, test item, execution order, branch conditions, test round, test timestamp, test value, upper and lower limits, logic pins, physical channels, and contact detection data from each test record. Leakage current is uniformly converted to μA, static current to mA, continuous test values ​​to V, and contact resistance to Ω. During processing, 1846 records with missing fields, 217 records with inverted limits, and 3264 duplicate records are detected. A joint index is constructed based on chip identifier, test round, test item identifier, and test timestamp. 3091 duplicate records with identical content are merged, and conflict markers are added to the remaining 173 records. The test time of each workstation is converted to a millisecond sequence relative to the test start point, resulting in 1,301,069 valid records and generating an integrated circuit test dataset.

[0033] The integrated circuit test dataset was grouped according to the test program version, resulting in two sets of test data: version V3.5 corresponding to 3360 chips and version V3.6 corresponding to 6240 chips. Taking version V3.6 as an example, the test program contains 144 test items. T001 to T054 and T091 to T144 are marked as common trunks, T055 to T066, T067 to T078, and T079 to T090 are marked as three conditional branches, and the first identical test item T091 after the three conditional branches is marked as the convergence anchor point. The test path channel diagram forms 144 test item nodes, 32 logic pin nodes, and 48 physical channel nodes.

[0034] Logic pin P17 is connected to test items T063 and T096, and physical channel CH06 is connected to the corresponding node of P17. Based on the test results of T054, chip C18420 enters the corresponding conditional branches from T055 to T066, returns to the common trunk via T091, and the actual execution path includes 120 test items. The node connections are checked according to the test item execution order; the conditional branch entry points, convergence anchor points, and pin channel connection positions are all consistent with the test program execution log, generating a test path channel diagram.

[0035] The initial test and retest records of chip C18420 are extracted from the test path channel diagram. Initial test round R0 and retest round R1 are paired according to the test item identifier to form 120 initial and retest record pairs. The initial measurement value of T063 is 2.38μA, exceeding the 2.00μA upper limit, while the retest measurement value is 0.91μA. The logic pins corresponding to both rounds of records are P17, the physical channel for the initial test is CH06, and the physical channel for the retest is CH14. The initial test continuity test value, contact resistance, and test current are -0.68V, 0.47Ω, and 99.7μA, respectively, while the corresponding retest values ​​are -0.72V, 0.13Ω, and 100.1μA, respectively. The initial and retest records and contact detection records are connected to the T063 node and arranged in execution order to generate an initial and retest feedback sample containing 120 mapped nodes.

[0036] Before model deployment, 128,000 historical initial and retest connection samples were collected, of which 89,600 samples constituted the training set, 19,200 samples constituted the validation set, and 19,200 samples constituted the test set. The improved TimesNet model was set up with 16-cycle building blocks, a feature dimension of 768, and 126 million parameters. The training samples included 4,260 samples before and after test socket cleaning, 3,180 samples of physical channel swapping, 2,760 samples of conditional branch switching, and 3,940 samples of continuous out-of-limit behavior across workstations. Samples where the test socket value recovered and the contact resistance decreased after cleaning were marked with contact deviation; samples where the anomaly moved with the physical channel were marked with channel deviation; samples where the anomaly changed with the branch path were marked with branch deviation; and samples that still exceeded the limit in the same direction in the alternative channel were marked with chip retention deviation.

[0037] The joint loss was composed of test branch spectrum reconstruction loss, pin channel coordinate decoupling loss, contact change retracement loss, and chip retention deviation consistency loss. After 58 training cycles, the joint loss on the validation set decreased from 1.926 to 0.184. The changes in joint loss over seven consecutive training cycles were 0.043%, 0.038%, 0.032%, 0.027%, 0.022%, 0.016%, and 0.011%, respectively, indicating successful model training. The training labels for the C18420 chip were 0.72, 0.85, 0.93, and 0.08, corresponding to branch deviation, channel deviation, contact deviation, and chip retention deviation, respectively.

[0038] The sample corresponding to chip C18420 is input into the test branch spectrum splitting block. Two rounds of records are divided according to the common trunk, conditional branches, and convergence anchor points. A Fast Fourier Transform is performed on each test sequence. The period lengths of the top 5 spectral amplitudes are 5, 10, 20, 24, and 60 test positions, corresponding to spectral amplitudes of 0.31, 0.24, 0.19, 0.15, and 0.11, respectively. The initial and retested periodic components are aligned according to the conditional branch markers and spliced ​​at T091 according to the test item execution order, resulting in a 120×768-dimensional test branch spectrum representation.

[0039] The test branch spectrum representation is input into the pin channel dual-coordinate block to establish 32 logic pin coordinates and 48 physical channel coordinates. The initial and retest cycle components are aligned under T063 and the corresponding cycle, and the logic pin coordinate difference of 0.74 and the physical channel coordinate difference of 0.86 are calculated respectively. The two types of coordinate differences are cross-stitched according to the test item positions to form a 120×1536-dimensional pin channel dual-coordinate representation.

[0040] The contact anomaly rewind block locates the node corresponding to T063, and concatenates the continuity test value difference of -0.04V, the contact resistance difference of -0.34Ω, and the test current difference of 0.4μA into a contact change vector. This contact change vector is then propagated in reverse order along the initial and retest rewind chain to nodes T060, T061, and T062, and added to the corresponding pin channel dual-coordinate representation. After processing, the average anomaly response of the CH06 associated node increases from 0.46 to 0.83, while the average anomaly response of other nodes is 0.18, yielding the contact anomaly rewind characterization.

[0041] The contact anomaly rewind representation is mapped to a two-dimensional tensor based on five periodic components. Two-dimensional convolutions are then performed in the intra-period direction and the inter-period direction, and the convolution results are fused according to spectral amplitudes of 0.31, 0.24, 0.19, 0.15, and 0.11. After residual connection and linear mapping, the branch bias, channel bias, contact bias, and chip retention bias corresponding to T063 are 0.68, 0.82, 0.91, and 0.14, respectively, with differences from the training labels of 0.04, 0.03, 0.02, and 0.06. A test reliability feature package containing 120 bias records is generated.

[0042] 120 deviation records are arranged according to chip identifier, test round, test item identifier, and test item execution order, and evidence row numbers are set. Branch deviation, channel deviation, and contact deviation are written into the data distortion track, and chip retention deviation is written into the device anomaly track. After being aligned according to the evidence row numbers, a dual-track reliability evidence matrix of 120 rows and 4 evidence columns is formed.

[0043] The lower bound of the preset benchmark for each evidence column is set to 0, and the upper bound is set to 1. After normalization, the four evidence values ​​corresponding to T063 remain 0.68, 0.82, 0.91, and 0.14. The three weights of the data distortion track are set to 0.30, 0.35, and 0.35, respectively. The data distortion score of T063 is the sum of 0.68×0.30, 0.82×0.35, and 0.91×0.35, which equals 0.8095. The weight of the device anomaly track is set to 1, and the device anomaly score is 0.14. The 120 sets of dual scores are arranged in the order of the evidence rows to generate a test record dual score sequence.

[0044] The preset values ​​are 0 to 0.20 for Level 1 Reliability, 0.20 to 0.45 for Level 2 Concern, 0.45 to 0.70 for Level 3 Suspicious, and 0.70 to 1 for Level 4 Unreliability. The data distortion score of T063, 0.8095, falls into the Level 4 Unreliable range, and the device anomaly score of 0.14 is associated with node T063. After cleaning the test socket and re-pressing it, the T063 test value became 0.94 μA, and the contact resistance decreased to 0.12 Ω. Further verification of 200 chips showed that the initial and retest inconsistency rate recorded for CH06 decreased from 8.6% to 1.2%, indicating that the initial test anomaly of T063 originated from the contact condition.

[0045] The C20736 chip was selected to verify the device anomaly track. The initial measurement value of T083 was 3.17mA, and the remeasured value was 3.12mA, both below the lower limit of 3.40mA. After changing the test socket and switching the physical channel, the measured value was 3.15mA, and the contact resistance remained between 0.09Ω and 0.11Ω. The improved TimesNet model output branch bias was 0.23, channel bias was 0.18, contact bias was 0.12, and chip retention bias was 0.86, resulting in a data distortion score of 0.1715 and a device anomaly score of 0.86. T083 was marked as Level 1 reliable data and associated with a high device anomaly score. Independent electrical verification still yielded results below the lower limit, indicating that the measured value effectively reflects the chip's own anomaly.

[0046] 19,200 completed test records were selected from the test set for comparison, including 5,820 records of data distortion, 3,160 records of device abnormality, and 10,220 records of normal operation.

[0047] The data distortion identification accuracy of the method of this invention is 94.7% and 78.2% compared with the traditional fixed limit method; The recall rates for data distortion were 93.1% and 74.6%, respectively. The accuracy rates for device anomaly identification were 92.8% and 80.5%, respectively. The accuracy rates for reliability level determination were 93.6% and 76.9%, respectively. The false positive rates for contact distortion were 4.9% and 22.3%, respectively. The manual review time for each batch of test data was 34 minutes and 96 minutes, respectively.

[0048] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for reliability evaluation of integrated circuit test data based on AI large-scale models, characterized in that, include: Collect integrated circuit test data and preprocess it to generate an integrated circuit test dataset; Rearrange the integrated circuit test dataset according to the test procedure order, mark the common trunk, conditional branches and convergence anchor points, connect the logic pins and physical channels to the test items, and generate the test path channel diagram. Extract the initial test record and retest record from the test path channel diagram, match them according to chip identifier and test round, associate them with the contact detection record of the corresponding test item, and generate initial and retest reconnection samples; The initial and retested samples are input into the improved TimesNet model, which includes a test branch spectrum splitting block, a pin channel dual coordinate block, and a contact anomaly rollback block to generate a test reliability feature package. Branch deviation, channel deviation and contact deviation in the test reliability feature package are incorporated into the data distortion track, and chip retention deviation is incorporated into the device anomaly track to construct a dual-track reliability evidence matrix. The evidence values ​​of the dual-track reliability evidence matrix are normalized and weighted by track to generate a dual-score sequence of test records. Extract the data distortion scores from the dual-score sequence of test records, match them with preset score ranges and determine the reliability level, associate the device anomaly scores with the corresponding test items, and generate reliability evaluation results for integrated circuit test data.

2. The method for reliability evaluation of integrated circuit test data based on an AI large model according to claim 1, characterized in that, The integrated circuit test data specifically includes chip identifier, test batch identifier, test machine identifier, test station identifier, test program version, test item identifier, test item execution order, branch conditions, convergence position, test round, test timestamp, test value, upper limit value, lower limit value, test conclusion, logic pin identifier, physical channel identifier, pin channel mapping relationship, continuous test value, contact resistance, and test current.

3. The method for reliability evaluation of integrated circuit test data based on AI large model according to claim 1, characterized in that, The generation of the integrated circuit test dataset includes: Unify the data format of integrated circuit test data, verify the integrity of fields and the order of limit values, mark missing field records and inverted limit value records, and generate field verification data; A composite index is built for the field validation data based on chip identifier, test round, test project identifier and test timestamp. Duplicate records are merged and conflicting records are marked to generate deduplicated test data. The test timestamps of the deduplication test data are converted into a unified time base, sorted according to chip identifier, test round, and test timestamp, and time series correction test data is generated. The timing correction test data, along with field missing markers, limit inversion markers, and conflict markers, are encapsulated using a combined index to generate an integrated circuit test dataset.

4. The method for reliability evaluation of integrated circuit test data based on an AI large model according to claim 1, characterized in that, The generation of the test path channel diagram includes: The integrated circuit test dataset is grouped according to the test program version, the test items and execution order of each group are extracted, and adjacent test items are connected according to the execution order to generate a test item order chain; Mark consecutive test items in the test item sequence chain that are not controlled by branch conditions as common trunks, and mark consecutive test items controlled by the same branch conditions as condition branches to generate test program branch chains. Compare the test items after the end of each conditional branch in the test program branch chain, mark the first identical test item as the merging anchor point, and generate the test path structure; Connect the logic pins and physical channels to the corresponding test items in the test path structure, establish node connections according to the test item execution order, conditional branch direction, and pin channel mapping relationship, and generate a test path channel diagram.

5. The method for reliability evaluation of integrated circuit test data based on AI large model according to claim 1, characterized in that, The generation of initial and retest reconnection samples includes: The test records in the test path channel diagram are collected according to the chip identifier. The earliest test round of each chip is marked as the initial test round, and the remaining test rounds are marked as retest rounds, generating a round mark record set. The test rounds are divided into a set of test round markers. For the same chip, the initial test round and each retest round are paired with corresponding records according to the test item identifier to generate initial and retest record pairs. Map the initial and retest records to the test path channel diagram according to the test project identifier. Based on the logical pin identifiers and physical channel identifiers of the initial and retest records, connect the corresponding contact detection records to the mapping nodes to build the initial and retest back-connection chain. Arrange the mapping nodes in the initial and retest reconnection chain according to the execution order of the test items, encapsulate the initial and retest record pairs, contact detection records, common trunk markers, conditional branch markers, convergence anchor point markers, and node connection relationships to generate initial and retest reconnection samples.

6. The method for reliability evaluation of integrated circuit test data based on an AI large model according to claim 1, characterized in that, The generated test reliability feature package includes: An improved TimesNet model is constructed, which includes a test branch spectrum splitting block, a pin channel dual coordinate block, and a contact anomaly rollback block; The initial and retested samples are input into the test branch spectrum splitting block. According to the common trunk, conditional branches, and merging anchor points, the initial test record and the retest record are divided into the trunk test sequence and the branch test sequence, respectively. Fast Fourier transform is performed on each test sequence, and the periodic components with the first K positions of the spectrum amplitude are selected. The initial test periodic components and the retest periodic components are aligned according to the conditional branch mark, and spliced ​​at the merging anchor point according to the test item execution order. The test branch spectrum representation is output, where K is a positive integer not greater than the total number of spectrum components. Input the test branch spectrum representation into the pin channel dual coordinate block, establish coordinate indexes according to the logical pin identifier and physical channel identifier respectively, align the initial test cycle component and the retest cycle component under the same test item and corresponding cycle, calculate the logical pin coordinate difference and physical channel coordinate difference respectively, cross-stitch the two types of coordinate differences according to the test item position, and output the pin channel dual coordinate representation. Input the pin channel dual coordinate representation, contact detection records and node connection relationships in the initial and retest reconnection samples into the contact anomaly rewind block. Based on the node connection relationship, locate the mapping node of the contact detection record, align the continuous test values, contact resistance and test current of the initial test stage and the retest stage, calculate the corresponding difference and splice it into a contact change vector. Pass the contact change vector in reverse order along the initial and retest reconnection chain and add it to the pin channel dual coordinate representation corresponding to the node passed through, and output the contact anomaly rewind representation. Based on the periodic components in the test branch spectrum characterization, the contact anomaly rewind characterization is mapped in two dimensions. Two-dimensional convolutions are performed in the intra-period direction and the inter-period direction, respectively. The convolution results are weighted and fused based on the spectral amplitude of the corresponding periodic components. After residual connection and linear mapping, the branch deviation, channel deviation, contact deviation and chip retention deviation corresponding to each test record are obtained, and the test reliability feature package is generated. The initial and retest samples were divided into training and validation sets. The improved TimesNet model was trained using the training set. The test branch spectrum reconstruction loss, pin channel coordinate decoupling loss, contact change folding loss, and chip retention deviation consistency loss were combined as the joint loss. The parameters of the test branch spectrum splitting block, pin channel dual coordinate block, contact anomaly folding block, two-dimensional convolutional layer, and linear mapping layer were updated through backpropagation. The improved TimesNet model training was completed when the absolute value of the difference between the validation set joint loss of adjacent training cycles and the validation set joint loss of the previous training cycle were all less than 0.05% within 7 consecutive training cycles.

7. The method for reliability evaluation of integrated circuit test data based on an AI large model according to claim 1, characterized in that, The construction of the dual-track reliability evidence matrix includes: According to the chip identifier, test round, test item identifier and test item execution order, the branch deviation, channel deviation, contact deviation and chip retention deviation in the test reliability feature package are aligned, and evidence line numbers are set according to the corresponding test records to generate a reliability evidence index table. Based on the reliability evidence index table, branch deviation, channel deviation, and contact deviation are sequentially written into the three data distortion evidence columns of the same evidence row to construct a data distortion track; Based on the evidence row number of the data distortion track, the chip retention deviations corresponding to the same chip identifier, test round, and test item identifier are written into the device anomaly evidence column to construct the device anomaly track; Align the data distortion track and the device anomaly track according to the evidence row numbers, and place the three data distortion evidence columns and one device anomaly evidence column side by side to construct a dual-track reliability evidence matrix.

8. The method for reliability evaluation of integrated circuit test data based on AI large model according to claim 1, characterized in that, The generation of the test record dual-score sequence includes: According to the evidence column, subtract the corresponding preset lower bound from the evidence value in the dual-track reliability evidence matrix, and then divide by the difference between the preset upper bound and the preset lower bound to generate a normalized evidence matrix, where the preset upper bound is greater than the preset lower bound. Configure separate evidence weights for each evidence column within the data distortion track and the device anomaly track, with the sum of the separate evidence weights within each track being 1; The normalized evidence value in the same evidence row is multiplied by the corresponding track-specific evidence weight and summed by track to obtain the data distortion score and device anomaly score, forming a dual-score record. The dual-score records are arranged according to the evidence row order of the dual-track reliability evidence matrix, and associated with the corresponding chip identifier, test round, and test item identifier to generate a test record dual-score sequence.

9. The method for reliability evaluation of integrated circuit test data based on an AI large model according to claim 1, characterized in that, The matching of preset score ranges and determination of reliability levels includes: Extract the data distortion scores and their associated chip identifiers, test rounds, and test item identifiers from the dual-score sequence of test records, and generate a test record distortion score table; The data distortion scores in the test record distortion score table are compared with the preset score intervals, and the data distortion scores are assigned to the corresponding score intervals to generate a score interval matching table. Based on the preset correspondence between score ranges and reliability levels, the reliability level is marked for each test record in the score range matching table, and a test data reliability level table is generated.

10. The method for reliability evaluation of integrated circuit test data based on AI large model according to claim 1, characterized in that, The reliability evaluation results of the generated integrated circuit test data include: Based on the chip identifier, test round, and test item identifier, the reliability level is aligned with the data distortion score and device anomaly score to generate test record evaluation items; Map the device anomaly score in the test record evaluation item to the node with the same test item identifier in the test path channel diagram, record the execution order of the test items in the corresponding node, and generate device anomaly associated evaluation items; The device anomaly association evaluation items are arranged according to chip identifier, test round, and test item execution order. The reliability evaluation results of integrated circuit test data are generated by packaging chip identifier, test round, test item identifier, reliability level, data distortion score, and device anomaly score.

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