A monitoring method of a multi-core processor, a terminal and a computer storage medium

Abstract

The embodiment of the present application discloses a kind of monitoring method of multi-core processor, comprising: by first core, the clock interrupt count of second core in preset time is monitored;If clock interrupt count does not change, determine that the second core occurs exception.The embodiment of the present application also discloses a kind of monitoring device of multi-core processor and computer storage medium.

Description

[0001] Case Analysis

[0002] This case is a divisional application of the invention patent application with application number "201810058181.1", application date "January 22, 2018", and title "A monitoring method, terminal and computer storage medium for a multi-core processor". Technical Field

[0003] This invention relates to the field of communications, and more particularly to a monitoring method for multi-core processors, a terminal, and a computer storage medium. Background Technology

[0004] With the advent of the information age, computer users have placed higher demands on computer performance. Single-core processors (Central Processing Units, CPUs) can no longer meet the needs of daily work and life, hence the emergence of multi-core processors. A multi-core processor integrates two or more complete computing engines (cores) within a single CPU. The processing of business tasks by a multi-core processor is inseparable from the monitoring of the multi-core processor cores.

[0005] Current technology for monitoring the cores of multi-core processors relies on a watchdog timer monitoring a specific thread. This method only detects anomalies within the core where that thread resides, failing to monitor other cores. Therefore, during multi-core processor operation, if the core containing the aforementioned thread is functioning correctly, while several other cores malfunction and are associated with multiple critical tasks, the multi-core processor will detect that the core containing the thread is functioning correctly. However, in reality, other cores have already malfunctioned, causing several important tasks to fail. Clearly, current technology suffers from the inability to monitor all cores within a multi-core processor. Summary of the Invention

[0006] In view of this, the present invention aims to provide a monitoring method, terminal, and computer storage medium for multi-core processors, solving the problem in the prior art that it is impossible to monitor all cores in a multi-core processor, improving the monitoring efficiency of multi-core processors, and enhancing the reliability of multi-core processors.

[0007] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0008] Firstly, a method for monitoring multi-core processors is provided, the method comprising:

[0009] The first core monitors the clock interrupt count of the second core within a preset time.

[0010] If the clock interrupt count does not change, it is determined that the second core has malfunctioned.

[0011] Secondly, a terminal is provided, the terminal comprising: a multi-core processor and a storage medium configured to store executable instructions, wherein:

[0012] The processor is configured to execute stored executable instructions, the executable instructions including:

[0013] The first core monitors the clock interrupt count of the second core within a preset time.

[0014] If the clock interrupt count does not change, it is determined that the second core has malfunctioned.

[0015] Thirdly, a computer-readable storage medium is provided, the computer-readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the steps of the multi-core processor monitoring method as described in the first aspect.

[0016] The multi-core processor monitoring method, terminal, and computer storage medium provided in this invention monitor the clock interrupt count of a second core within a preset time using a first core. If the clock interrupt count does not change, it is determined that the second core has malfunctioned. In other words, the multi-core processor monitoring method provided in this invention can determine that a monitored core has malfunctioned if any core in the multi-core processor monitors other cores and finds that their clock interrupt counts have not changed within a preset time. This ensures that the cores of the multi-core processor can monitor each other, and that all cores are under monitoring. This solves the problem in the prior art that it is impossible to monitor all cores within a multi-core processor, improves the monitoring efficiency of the multi-core processor, and enhances the reliability of the multi-core processor. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a multi-core processor monitoring method according to an embodiment of the present invention;

[0018] Figure 2 This is another flowchart illustrating the monitoring method for multi-core processors according to an embodiment of the present invention;

[0019] Figure 3 This is another flowchart illustrating the monitoring method for multi-core processors according to an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0022] It should be understood that the phrases "embodiments of the present invention" or "foreign embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of the present invention. Therefore, "embodiments of the present invention" or "in the foreign embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of the present invention, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. The sequence numbers of the above-described embodiments of the present invention are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0023] This invention provides a monitoring method for multi-core processors. The monitoring method is executed by a multi-core processor, which integrates two or more complete cores. Since the most basic programs used daily, such as operating systems, support parallel processing, when multiple single-threaded programs are running simultaneously on a multi-core processor, the operating system sends the instructions of the multiple programs to multiple cores respectively, thereby greatly speeding up the completion of multiple programs simultaneously.

[0024] Based on the foregoing embodiments, the monitoring method for multi-core processors provided by the embodiments of the present invention will be described in detail below. (See also...) Figure 1 As shown, the method includes:

[0025] S101: Monitors the clock interrupt count of the second core within a preset time using the first core.

[0026] Here, for a multi-core processor (hereinafter referred to as the processor), the first core can be any one of the cores in the processor. The second core is different from the first core; the number of second cores can be one or more. This embodiment of the invention does not specifically limit the number of cores contained in the processor. Each core in the processor has its own non-maskable clock interrupt; this clock interrupt can be considered the heartbeat of each core. In this embodiment of the invention, the processor uses clock interrupt count as a primary factor in determining whether the core's operating state is abnormal.

[0027] In this embodiment of the invention, if the monitoring time is too short, the monitoring may end before the clock interrupt count of the monitored core has had time to be updated, thus failing to obtain the clock interrupt count of the monitored core and consequently failing to obtain the actual situation of the monitored core. If the monitoring time is too long, the monitored core may have already malfunctioned before the end of the monitoring period, but the processor cannot obtain the monitoring results in time, resulting in a delay in feedback regarding the malfunction of the monitored core, and thus failing to obtain the actual situation of the monitored core. Therefore, this embodiment of the invention proposes that the monitoring of the clock interrupt count of the monitored core must be limited to a certain time interval, i.e., a preset time period, to be meaningful. It should be noted that the clock interrupt period of each core of the processor can be the same, such as the clock interrupt period of each core being T. The value of the above time interval is at least greater than one clock interrupt period.

[0028] In practical applications, assume the processor has N (N≥2) cores, each numbered core0, core1, ... core2. N-1 When the processor powers on and enters the monitoring initialization state, it can set the clock interrupt cycle for each core. For example, the clock interrupt cycle for each core can be set to T. In this embodiment of the invention, before S101 described above, the second core can also be determined in the following two ways.

[0029] The first method involves identifying the core in a multi-core processor that is adjacent to the first core as the second core.

[0030] Here, the processor first determines the first core, which can be any one of all cores. For example, if the first core is core1, then the processor determines the cores adjacent to the first core as the second cores, resulting in cores 0 and 2. Or, for example, if the first core is core9, then the processor determines the cores adjacent to the first core as the second cores, resulting in cores 8 and 9. 10 Of course, if the processor is a dual-core processor with only two cores, then if the processor designates one core as the first core, the other core, which is adjacent to the first core, will be designated as the second core.

[0031] The second method involves identifying the second core as any core in a multi-core processor other than the first core.

[0032] Here, similar to the first method described above for determining the first core, the processor first determines the first core, which can be any one of all cores. For example, if the first core is core1, then the processor determines the cores other than the first core as the second cores, resulting in core0 and cores 2 through 10 as the second cores. N-1 For example, if the first core is core9, then the processor determines that the cores other than the first core are the second cores, thus the second cores are core0 to core8 and core... 10 ~core N-1 Of course, if the processor is a dual-core processor with only two cores, then if the processor designates one core as the first core, the other core, i.e., the remaining core, will be designated as the second core.

[0033] It should be noted that in the first method, the monitoring target of the first core is the core adjacent to it, i.e., at least one core and at most two cores; while in the second method, the monitoring target of the first core is all cores other than the first core, i.e., at least one core and at most N-1 cores. In other words, when N is relatively large, meaning the processor has many cores, using the second method to monitor the second core through the first core results in a larger number of monitoring targets for the first core, inevitably increasing processing time. Therefore, the first method has higher monitoring efficiency than the second method. Of course, in this embodiment of the invention, the method for determining the second core of the processor is not specifically limited, but rather focuses on implementing the multi-core processor monitoring method of this invention.

[0034] S102: If the clock interrupt count does not change, it is determined that an abnormality has occurred in the second core.

[0035] Here, assuming the processor monitors its adjacent cores 0 and 2 via core 1, the processor increments its own heartbeat count n during the clock interrupt handling of each core and records the timestamp corresponding to the clock interrupt. For example, the processor confirms that the timestamps of the clock interrupts of core 0 and core 2 are t0 and t2, respectively, and the clock interrupt counts for the current timestamps of core 0 and core 2 are n0 and n2, respectively.

[0036] Furthermore, the processor monitors the clock interrupt counts of cores 0 and 2 within a preset time using core 1, and obtains a timestamp t from the real-time clock on the current core 1. x , and t x The corresponding interrupt counts for core0 and core2 are n respectively. 0’ and n 2’ Next, if the processor confirms that the timestamp difference satisfies t...x -t0>T and n0=n 0’ , or t x -t2>t and n2=n 2’ In other words, if the processor confirms that the clock interrupt counts of core0 and core2 have not changed, then it determines that core0 and core2 are abnormal.

[0037] In this embodiment of the invention, determining that the second core has malfunctioned in step S102 may include the following steps:

[0038] Step A1: Obtain the clock interrupt count and determine whether the clock interrupt count is equal to the preset value.

[0039] Here, to improve the accuracy of core anomaly monitoring, after the first core detects the clock interrupt count of the second core at a preset time, it is necessary to determine whether the clock interrupt count is a preset value corresponding to the preset time. For example, when the first preset time T1 satisfies T≤T1<2T, the preset value S corresponding to the first preset time T1 is... 10 If the value is 1, then the processor, in its first core, detects the clock interrupt count S of the second core at a first preset time. 11 Next, it is necessary to determine the clock interrupt count S. 11 Is it S? 10 When the second preset time T2 satisfies T≤T2<3T, the preset value S corresponding to the second preset time T2 is... 20 If the value is 2, then the processor, in its first core, detects the clock interrupt count S of the second core at a second preset time. 21 Next, it is necessary to determine the clock interrupt count S. 21 Is it S? 20 When the third preset time T3 satisfies T≤T3<4T, the preset value S corresponding to the third preset time T3 is... 30 If the value is 3, then the processor detects the clock interrupt count S of the second core at a third preset time in the first core. 31 Next, it is necessary to determine the clock interrupt count S. 31 Is it S? 30 In this embodiment of the invention, T is the clock interrupt period set during processor initialization.

[0040] Step A2: If the clock interrupt count is not equal to the preset value, it is determined that an abnormality has occurred in the second core.

[0041] The preset values ​​correspond to the preset times.

[0042] Here, after the processor detects the clock interrupt count of the second core within a preset time through the first core, it compares the clock interrupt count with a preset value. If the clock interrupt count is not equal to the preset value, it determines that the second core has malfunctioned. This malfunction may be caused by a program error or by an abnormal condition that the core must handle. In this embodiment of the invention, if the processor detects an malfunction in the second core through the first core, it can output a prompt message to inform the user of the location and / or cause of the malfunction. This allows the user to promptly handle different malfunctions, enhancing the reliability of the multi-core processor.

[0043] Based on the foregoing embodiments, in this embodiment of the invention, see... Figure 2 As shown, after step A1 above, the multi-core processor monitoring method provided in this embodiment of the invention further includes:

[0044] Step A3: If the clock interrupt count equals the preset value, it is confirmed that no abnormality has occurred in the second core.

[0045] If the processor determines that the second core is not malfunctioning, then the processor continues to monitor the second core in real time through the first core.

[0046] In practical applications, when a correspondence between preset values ​​and preset times is set in step A1 above, the processor, upon obtaining the clock interrupt count S corresponding to the first preset time T1, the second preset time T2, and the third preset time T3, 11 S 21 S 31 Then; the above S 11 With S 10 Comparison, S 21 With S 20 Comparison, S 31 With S 30 By comparison, the following monitoring results can be obtained: S 11 equals S 10 S 21 equals S 20 S 31 Not equal to S 30 In other words, during the process of the processor monitoring the second core through the first core, it detects that the second core is in a normal state within a first preset time and a second preset time, but detects that the second core is in an abnormal state within a third preset time, and determines that the second core has malfunctioned.

[0047] As described above, the multi-core processor monitoring method provided by this invention monitors the clock interrupt count of a second core within a preset time using a first core; if the clock interrupt count does not change, it is determined that the second core has malfunctioned. In other words, the multi-core processor monitoring method provided by this invention can determine that a monitored core has malfunctioned when any core in the multi-core processor monitors other cores and finds that their clock interrupt counts have not changed within a preset time. This ensures that the cores of the multi-core processor can monitor each other, and that all cores are under monitoring. This solves the problem in the prior art that it is impossible to monitor all cores within a multi-core processor, improves the monitoring efficiency of the multi-core processor, and enhances the reliability of the multi-core processor.

[0048] Based on the foregoing embodiments, embodiments of the present invention provide a method for monitoring multi-core processors, comprising the following steps:

[0049] S201: The processor monitors the clock interrupt count of the second core within a preset time through the first core.

[0050] S202: If the clock interrupt count has not changed, the processor determines that an abnormality has occurred in the second core.

[0051] S203: The processor verifies the accuracy of the result of the second core exception.

[0052] Here, during the process of the processor monitoring the clock interrupt count of the second core within a preset time through the first core, if the second core is busy processing other tasks, causing a delay in updating its own clock interrupt count, then the first core will only detect that the clock interrupt count of the second core has not changed within the preset time, which will inevitably lead to a misjudgment. Therefore, in this embodiment of the invention, after the processor detects an anomaly in the second core through the first core, it can also verify whether the result of the second core's anomaly is accurate. In this way, the processor avoids unnecessary processing of the second core, which is actually in a normal state, thereby saving resources.

[0053] S204: If the verification result is accurate, the processor processes the information on the second core.

[0054] Here, if the processor detects an anomaly in the second core through the first core and verifies that the anomaly in the second core is accurate, then the processor processes the information on the anomaly-stricken second core. This improves information processing efficiency.

[0055] Based on the foregoing embodiments, optionally, in other embodiments of the present invention, the above-mentioned step S203, verifying whether the result of the second core malfunction is accurate, may include the following steps:

[0056] First, control the first core to send an inter-core interrupt to the second core.

[0057] Here, whenever the processor detects an anomaly in the second core through the first core, it controls the first core to send an inter-core interrupt to the second core; this inter-core interrupt is a non-maskable interrupt. For the second core, when an inter-core interrupt (IPI) arrives, if the second core is in a normal state, then the second core must respond to the inter-core interrupt. Conversely, if the second core is in an abnormal state, then the second core cannot respond to the inter-core interrupt.

[0058] Secondly, monitor whether the first core receives a response message from the second core in response to the inter-core interrupt.

[0059] Here, after the processor controls the first core to send the inter-core interrupt to the second core, the processor detects whether the first core has received a response message from the second core in response to the inter-core interrupt.

[0060] Finally, if the first core does not receive a response message from the second core regarding the inter-core interrupt feedback, the verification result is confirmed to be accurate.

[0061] Here, if the processor detects that the first core has not received a response message from the second core regarding the inter-core interrupt, it indicates that the second core is unable to respond to the inter-core interrupt, meaning the second core is indeed malfunctioning; therefore, the processor determines the verification result to be accurate. If the processor detects that the first core has received a response message from the second core regarding the inter-core interrupt, it indicates that the second core can respond to the inter-core interrupt, meaning the second core is not malfunctioning; therefore, the processor determines the verification result to be incorrect. In this case, the processor's monitoring of the second core's clock interrupt count within a preset time period, which is not equal to a preset value, only indicates that the second core was busy processing other tasks within the preset time period and did not update its own clock interrupt count in a timely manner, but the second core is still in a normal state at this time.

[0062] Based on the foregoing embodiments, optionally, in other embodiments of the present invention, if the verification result of S204 is accurate, processing the information on the second core may include the following steps:

[0063] If the verification result is accurate, the information recorded on the second core is initialized.

[0064] Here, initializing the information recorded on the second core is equivalent to resetting the second core. This initialization process may include reloading the code segment, data segment, and the mapping relationship between physical addresses and physical virtual address spaces, thereby enabling the second core to restart.

[0065] Alternatively, if the verification result is accurate, move the thread on the second core to the specified address.

[0066] Here, the processor transfers the execution of code from the thread on the second core to a specified address, allowing the thread on the second core to run normally. For example, thread 1, which was originally executed by the second core, is transferred to the third core, which is the core within the processor that has not experienced any exceptions.

[0067] Based on the foregoing embodiments, optionally, in other embodiments of the present invention, the method for monitoring multi-core processors provided in the embodiments of the present invention is applied to a multi-core processor as an example to describe the method in detail. See also Figure 3 As shown, the method includes:

[0068] S301: Multi-core processor initialization;

[0069] The multi-core processor initialization includes: setting the monitoring time interval T, and initializing cores core0, core1, core2...core N-1 The corresponding timestamps T0, T1, T2...T N-1 And initialize the core clock interrupt counts N0, N1, N2…N N-1 .

[0070] S302: The multi-core processor determines the clock interrupt count of its adjacent cores within a first preset time (e.g., the first preset time T1 satisfies T≤T1<2T) by monitoring the clock interrupt of the first core. Specifically, when the multi-core processor waits for the clock interrupt of core1 to arrive, it obtains its own updated clock interrupt count N1 from core1. ， and the current timestamp T X Get the current clock interrupt count N0 for core0 and core2. ， and N2 ， .

[0071] S303: The multi-core processor determines whether the clock interrupt count is equal to a first preset value. Specifically, the first preset value S... 10 The value is 1. Here, the processor determines that core0 and core2 are in the corresponding clock interrupt count N0. ， -N0 and N2 ， Is -N2 equal to the first preset value S? 10 .

[0072] S304: If the multi-core processor determines that the clock interrupt count is not equal to the first preset value, it indicates that an abnormality has occurred in the second core.

[0073] Correspondingly, the multi-core processor determines that the clock interrupt count is equal to the first preset value, confirms that the second core has not experienced any abnormalities, and continues to monitor the second core through the first core.

[0074] S305: Multi-core processor controls the first core to send inter-core interrupts to the second core.

[0075] S306: The multi-core processor monitors whether the first core has received a response message from the second core in response to the inter-core interrupt.

[0076] S307: The multi-core processor detects that the first core has not received a response message from the second core for the inter-core interrupt feedback, indicating that the second core has malfunctioned, and processes the information on the second core.

[0077] Correspondingly, the multi-core processor detects that the first core has received a response message from the second core in response to the inter-core interrupt, indicating that the second core has not experienced any abnormalities, and continues to monitor the second core through the first core.

[0078] The multi-core processor monitoring method provided in this invention monitors the clock interrupt count of a second core within a preset time using a first core. If the clock interrupt count is not equal to a preset value corresponding to the preset time, it is determined that the second core has malfunctioned. In other words, the multi-core processor monitoring method provided in this invention can determine that a monitored core has malfunctioned when any core in the multi-core processor monitors other cores and finds that their clock interrupt counts within a preset time are not equal to the preset value corresponding to that preset time. This ensures that the cores of the multi-core processor can monitor each other, and that all cores are under monitoring. This solves the problem in the prior art that it is impossible to monitor all cores within a multi-core processor, improves the monitoring efficiency of the multi-core processor, and enhances its reliability.

[0079] Based on the foregoing embodiments, this invention provides a terminal 40 that can be applied to... Figure 1-3 In the corresponding embodiment, the monitoring method for multi-core processors is provided, see [link to relevant documentation]. Figure 4 As shown, the terminal includes at least: a multi-core processor 41 and a storage medium 42 configured to store executable instructions, wherein:

[0080] The multi-core processor 41 is configured to execute stored executable instructions, which are used to perform the following steps:

[0081] The first core monitors the clock interrupt count of the second core within a preset time.

[0082] If the clock interrupt count does not change, it indicates that an anomaly has occurred in the second core.

[0083] Furthermore, when the processor determines that the second core has encountered an exception, it can perform the following steps:

[0084] Obtain the clock interrupt count and determine if the clock interrupt count is equal to a preset value;

[0085] If the clock interrupt count is not equal to the preset value, it is determined that an abnormality has occurred in the second core; the preset value corresponds to the preset time.

[0086] Furthermore, before executing the above-mentioned process of monitoring the clock interrupt count of the second core within a preset time by the first core, the processor can perform the following steps:

[0087] In a multi-core processor, the core adjacent to the first core is identified as the second core.

[0088] Furthermore, before executing the above-mentioned process of monitoring the clock interrupt count of the second core within a preset time by the first core, the processor can perform the following steps:

[0089] The cores in a multi-core processor other than the first core are designated as the second cores.

[0090] Furthermore, the executable instructions are also used to implement the following steps:

[0091] If the clock interrupt count equals the preset value, it confirms that no abnormality has occurred in the second core.

[0092] Furthermore, after the processor determines that the second core has malfunctioned if the clock interrupt count remains unchanged, it can perform the following steps:

[0093] Verify whether the result of the second core anomaly is accurate;

[0094] If the verification result is accurate, the information on the second core will be processed.

[0095] Furthermore, when the processor executes the above verification to determine whether the result of the second core exception is accurate, it can perform the following steps:

[0096] Control the first core to send an inter-core interrupt to the second core;

[0097] Monitor whether the first core receives a response message from the second core in response to the inter-core interrupt;

[0098] If the first core does not receive a response message from the second core regarding the inter-core interrupt feedback, the verification result is determined to be accurate.

[0099] Furthermore, if the processor executes the above verification and the result is accurate, when processing the information on the second core, it can perform the following steps:

[0100] If the verification result is accurate, initialize the information recorded on the second core; or...

[0101] If the verification result is accurate, move the thread on the second core to the specified address.

[0102] As can be seen from the above, the terminal provided by the embodiments of the present invention can determine that the monitored core has malfunctioned when any one core of a multi-core processor monitors the clock interrupt count of other cores within a preset time period and finds that the count is not equal to or unchanged from the preset time period. This ensures that the cores of the multi-core processor can monitor each other and that all cores are under monitoring. This solves the problem in the prior art that it is impossible to monitor all cores in a multi-core processor, improves the monitoring efficiency of the multi-core processor, and enhances the reliability of the multi-core processor.

[0103] Based on the foregoing embodiments, this embodiment provides a computer storage medium that can be applied to the terminal in one or more of the above embodiments. The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to perform the following steps:

[0104] The first core monitors the clock interrupt count of the second core within a preset time.

[0105] If the clock interrupt count does not change, it indicates that an anomaly has occurred in the second core.

[0106] Furthermore, after the processor determines that the second core has malfunctioned if the clock interrupt count remains unchanged, it can perform the following steps:

[0107] Obtain the clock interrupt count and determine whether the clock interrupt count is equal to a preset value;

[0108] If the clock interrupt count is not equal to the preset value, it is determined that the second core has malfunctioned; wherein, the preset value corresponds to the preset time.

[0109] Furthermore, before executing the above-mentioned process of monitoring the clock interrupt count of the second core within a preset time by the first core, the processor can perform the following steps:

[0110] In a multi-core processor, the core adjacent to the first core is identified as the second core.

[0111] Furthermore, before executing the above-mentioned process of monitoring the clock interrupt count of the second core within a preset time by the first core, the processor can perform the following steps:

[0112] The cores in a multi-core processor other than the first core are designated as the second cores.

[0113] Furthermore, the executable instructions are also used to implement the following steps:

[0114] If the clock interrupt count equals the preset value, it confirms that no abnormality has occurred in the second core.

[0115] Furthermore, when the processor determines that an exception has occurred in the second core, it can perform the following steps:

[0116] Verify whether the result of the second core anomaly is accurate;

[0117] If the verification result is accurate, the information on the second core will be processed.

[0118] Furthermore, when the processor executes the above verification to determine whether the result of the second core exception is accurate, it can perform the following steps:

[0119] Control the first core to send an inter-core interrupt to the second core;

[0120] Monitor whether the first core receives a response message from the second core in response to the inter-core interrupt;

[0121] If the first core does not receive a response message from the second core regarding the inter-core interrupt feedback, the verification result is determined to be accurate.

[0122] Furthermore, if the processor executes the above verification and the result is accurate, when processing the information on the second core, it can perform the following steps:

[0123] If the verification result is accurate, initialize the information recorded on the second core; or...

[0124] If the verification result is accurate, move the thread on the second core to the specified address.

[0125] It should be noted that the specific implementation process of the steps executed by the processor in this embodiment can be referred to Figure 1-3 The implementation process of the multi-core processor monitoring method provided in the corresponding embodiment will not be described in detail here.

[0126] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0127] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0128] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0129] In addition, in the various embodiments of the present invention, each functional unit can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0130] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0131] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0132] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for monitoring multi-core processors, characterized in that, The multi-core processor includes at least two cores, each core including a clock interrupt, each core being configured with its own clock interrupt count, and each core being used to update its own clock interrupt count when processing its own clock interrupt, the method including: The clock interrupt count of the second core is monitored by the first core within a preset time; wherein the first core is any core in the multi-core processor, and the second core is at least one core different from the first core; If the clock interrupt count of the second core does not change within a preset time, it is determined that the second core has malfunctioned.

2. The method according to claim 1, characterized in that, Each core is also used to store a timestamp corresponding to its own clock interrupt count when handling its own clock interrupt; The method of monitoring the clock interrupt count of the second core within a preset time through the first core includes: The clock interrupt count of the second core at different timestamps is monitored through the first core to determine the clock interrupt count of the second core within a preset time period; wherein, the time interval between the different timestamps is the preset time period.

3. The method according to claim 2, characterized in that, The step of monitoring the clock interrupt count of the second core at different timestamps through the first core and determining the clock interrupt count of the second core within a preset time period includes: The clock interrupt count of the second core at the current timestamp is obtained through the first core. The clock interrupt count corresponding to the current timestamp is compared with the clock interrupt count of the second core corresponding to the historical timestamp; wherein the time interval between the current timestamp and the historical timestamp is the preset time. Based on the comparison results, the clock interrupt count of the second core within a preset time period is determined.

4. The method according to claim 3, characterized in that, The step of determining the clock interrupt count of the second core within a preset time period based on the comparison results includes: The clock interrupt count of the second core within a preset time period is determined based on the difference between the clock interrupt count corresponding to the current timestamp and the clock interrupt count of the second core corresponding to the historical timestamp.

5. The method according to claim 3 or 4, characterized in that, The current timestamp is obtained by the first core from the real-time clock of the multi-core processor.

6. The method according to any one of claims 1-4, characterized in that, The preset time is greater than one clock interrupt cycle of the second core.

7. The method according to claim 1, characterized in that, The determination that the second core has malfunctioned includes: Determine whether the clock interrupt count of the second core within a preset time is equal to a preset value; If the clock interrupt count of the second core within a preset time is not equal to the preset value, it is determined that the second core has malfunctioned; wherein, the preset value and the preset time have a corresponding relationship.

8. The method according to claim 1, characterized in that, Before monitoring the clock interrupt count of the second core within a preset time by the first core, the method includes: The core adjacent to the first core in the multi-core processor is identified as the second core.

9. The method according to claim 1, characterized in that, Before monitoring the clock interrupt count of the second core within a preset time by the first core, the method includes: The cores of the multi-core processor other than the first core are identified as the second core.

10. The method according to claim 7, characterized in that, The method further includes: If the clock interrupt count of the second core within a preset time is equal to the preset value, it is determined that the second core has not malfunctioned.

11. The method according to claim 1, characterized in that, After determining that the second core has malfunctioned if the clock interrupt count of the second core does not change within a preset time, the method includes: Verify whether the result of the second core malfunction is accurate; If the verification result is accurate, the information on the second core is processed.

12. The method according to claim 11, characterized in that, The verification of the accuracy of the result of the second core's anomaly includes: Control the first core to send an inter-core interrupt to the second core; Monitor whether the first core receives a response message from the second core in response to the inter-core interrupt; If the first core does not receive the response message from the second core regarding the inter-core interrupt, the verification result is determined to be accurate.

13. A terminal, characterized in that, The terminal includes at least: a multi-core processor and a storage medium configured to store executable instructions. The multi-core processor includes at least two cores, each core including a clock interrupt. Each core is configured with its own clock interrupt count, and each core is used to update its own clock interrupt count when processing its own clock interrupt, wherein: The processor is configured to execute stored executable instructions, the executable instructions including: The clock interrupt count of the second core is monitored by the first core within a preset time; wherein the first core is any core in the multi-core processor, and the second core is at least one core different from the first core; If the clock interrupt count of the second core does not change within a preset time, it is determined that the second core has malfunctioned.

14. The terminal according to claim 13, characterized in that, When it is determined that the second core has encountered an anomaly, the following steps are performed: Determine whether the clock interrupt count of the second core within a preset time is equal to a preset value; If the clock interrupt count of the second core within a preset time is not equal to the preset value, it is determined that the second core has malfunctioned; wherein, the preset value and the preset time have a corresponding relationship.

15. The terminal according to claim 13, characterized in that, Each core is also used to store a timestamp corresponding to its own clock interrupt count when handling its own clock interrupt. When the first core monitors the clock interrupt count of the second core within a preset time, it is used to perform the following steps: The clock interrupt count of the second core at different timestamps is monitored through the first core to determine the clock interrupt count of the second core within a preset time period; wherein, the time interval between the different timestamps is the preset time period.

16. A computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions configured to execute the monitoring method for a multi-core processor provided in any one of claims 1 to 12.

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