AI-based device behavior data analysis method, system, and storage medium

Abstract

The application provides an AI-based device behavior data analysis method and system and a storage medium, relates to the technical field of computers, and obtains a processor core occupation mark sequence and a memory page active mark sequence of a computer device to be monitored in a continuous collection period; a processor core occupation mark propagation path network is generated by reconstructing the occupation mark propagation path of the processor core occupation mark sequence, and a memory page active mark propagation path network is generated by reconstructing the active mark propagation path of the memory page active mark sequence; the intersection clustering mode of the mark propagation paths in the two propagation path networks is mapped through cross-resource mark propagation intersection, and a processor memory mark propagation intersection association graph is generated; and a resource jitter suppression instruction for a target process set is generated according to the split timing characteristics of the mark propagation intersection clustering in the association graph. The application can realize accurate association analysis of cross-resource collaborative occupation, and effectively improves the generation accuracy of the resource jitter suppression instruction.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to an AI-based method, system, and storage medium for analyzing device behavior data. Background Technology

[0002] In the process of analyzing the behavior data of computer devices, load monitoring is a key task. Common computer device load monitoring solutions in the existing technology mainly collect processor core utilization data and memory usage data, and make independent threshold judgments on processor resources and memory resources respectively. When the utilization of a certain type of resource exceeds the preset threshold, the device is determined to be in a high load state, and corresponding load balancing or process scheduling operations are triggered accordingly.

[0003] However, the aforementioned existing technical solutions have significant shortcomings in practical applications. On the one hand, existing technologies only focus on the static occupancy value or usage ratio of a single resource type at a certain moment, failing to capture the dynamic propagation and evolution of resource occupancy over time. In particular, the linkage occupancy effect caused by process scheduling and data exchange between different processor cores and different memory pages is completely ignored. On the other hand, existing technologies treat processor resources and memory resources as independent monitoring objects. When making load judgments and control decisions, they do not consider the cross-resource collaborative occupancy characteristics caused by the operation of the same set of processes. This leads to a large deviation between the monitoring results and the actual load situation when facing complex multi-process concurrent scenarios. Consequently, the generation of resource jitter suppression instructions lacks accurate basis, easily resulting in false or missed suppression, reducing the overall efficiency and stability of system resource scheduling. Summary of the Invention

[0004] In view of the aforementioned problems, and in conjunction with the first aspect of the present invention, embodiments of the present invention provide an AI-based device behavior data analysis method, the method comprising: The processor core occupancy marker sequence and memory page active marker sequence of the computer device under monitoring are obtained during a continuous acquisition period. The processor core occupancy marker sequence records the binary marker bit of the occupancy status of each processor core at each acquisition time point. The memory page active marker sequence records the binary marker bit of the active status of each memory page at each acquisition time point. The processor core occupancy mark propagation path is reconstructed for the processor core occupancy mark propagation path network, and the memory page active mark propagation path is reconstructed for the memory page active mark propagation path network. The intersection clustering pattern of the marker propagation paths in the processor core occupied marker propagation path network and the intersection clustering pattern of the marker propagation paths in the memory page active marker propagation path network are mapped across resources to generate a processor memory marker propagation intersection association graph. Based on the splitting timing characteristics of the clusters in the processor memory mark propagation intersection graph, resource jitter suppression instructions for the target process set are generated.

[0005] Furthermore, embodiments of the present invention also provide an AI-based device behavior data analysis system, comprising: A processor; a machine-readable storage medium for storing machine-executable instructions of the processor; wherein the processor is configured to execute the above-described AI-based device behavior data analysis method by executing the machine-executable instructions.

[0006] Based on the above, by reconstructing the occupancy mark propagation path of the processor core occupancy mark sequence and the memory page active mark sequence, the binary mark bits at discrete time points can be restored into a mark propagation path network with spatiotemporal continuity. This allows for the understanding of the implicit correlation propagation relationships between processor cores and memory pages caused by process activities. On this basis, the intersection cluster patterns in the two types of propagation path networks are correlated and fused through cross-resource mark propagation intersection mapping. The generated processor memory mark propagation intersection correlation graph can accurately depict the collaborative occupancy topology of processor resources and memory resources caused by the operation of the same target process set. This elevates the monitoring perspective from the independent state of a single resource to the global correlation state of multi-resource collaborative occupancy. Furthermore, by generating resource jitter suppression instructions for the target process set based on the splitting timing characteristics of the mark propagation intersection clusters in the processor memory mark propagation intersection correlation graph, the true source process set of resource jitter can be accurately identified based on the complete lifecycle timing of the intersection cluster from formation to splitting. This avoids the problem of false jitter suppression instructions caused by ignoring cross-resource collaborative features in existing technologies, thereby significantly improving the accuracy of load status monitoring and the effectiveness of resource jitter suppression. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the execution flow of the AI-based device behavior data analysis method provided in an embodiment of the present invention.

[0008] Figure 2 This is a logical schematic diagram of the AI-based device behavior data analysis method provided in an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of exemplary hardware and software components of the AI-based device behavior data analysis system provided in an embodiment of the present invention. Detailed Implementation

[0010] Figure 1 This is a flowchart illustrating an AI-based device behavior data analysis method according to an embodiment of the present invention. The following is a summary of the process. Figure 2 A detailed introduction will be provided.

[0011] Step S110: Obtain the processor core occupancy marker sequence and memory page active marker sequence of the computer device to be monitored during the continuous acquisition period.

[0012] In this embodiment, a sampling probe is first deployed at the operating system kernel layer of the computer device to be monitored. This probe samples the run queue status of each processor core at fixed time intervals t. When a process is running on a processor core at the sampling time, the occupancy status binary flag of that processor core is recorded as a value of 1; otherwise, it is recorded as a value of 0. For memory pages, the sampling probe checks the access bits of each physical memory page at each sampling time. When a physical memory page has been accessed by at least one read / write operation in the previous sampling interval, the active status binary flag of that physical memory page is recorded as a value of 1; otherwise, it is recorded as a value of 0. After continuously sampling for M cycles, a processor core occupancy flag sequence is obtained. This processor core occupancy flag sequence is a two-dimensional matrix, where the row index of the matrix corresponds to the processor core number c, the column index corresponds to the sampling time point t, and the matrix elements are the occupancy flag bits O(c, t) of processor core c at sampling time point t. Simultaneously, a sequence of active memory page markers is obtained. This sequence is a two-dimensional matrix, where the row index corresponds to the memory page number p, the column index corresponds to the acquisition time point t, and the matrix elements are the active marker bits A(p, t) of memory page p at acquisition time point t. During the acquisition process, all marker bit data is encrypted before transmission, and differential privacy technology is used to add noise during storage to protect sensitive information. The acquisition operation has been authorized with the informed consent of the device user.

[0013] Step S120: Reconstruct the occupancy mark propagation path of the processor core occupancy mark sequence to generate the processor core occupancy mark propagation path network, and reconstruct the active mark propagation path of the memory page active mark sequence to generate the memory page active mark propagation path network.

[0014] Step S121: Arrange the binary flag bits of the occupancy status of each processor core in the processor core occupancy flag sequence according to the acquisition time order to generate the occupancy flag time sequence of each processor core, and perform bit-by-bit XOR operation on the binary flag bits of the occupancy status of adjacent acquisition time points in the occupancy flag time sequence of each processor core to obtain the occupancy flag flipping event sequence of each processor core.

[0015] In this embodiment, for each processor core c, the occupancy flag bits of that processor core c at all acquisition time points t are extracted from the processor core occupancy flag sequence O(c,t). These bits are then arranged in ascending order of acquisition time points t to generate an occupancy flag time sequence U_c = [O(c,1), O(c,2), ..., O(c,M)]. An XOR operation is performed on the occupancy flag bits of adjacent acquisition time points in this occupancy flag time sequence U_c: for each t from 1 to M-1, F(c,t) = O(c,t) × RO(c,t+1). When F(c,t) equals 1, it indicates that an occupancy flag flip occurred at acquisition time point t+1. The occurrence time t+1 and the flip direction of each occupancy flag flip event are recorded. Arrange all occupancy mark toggling events of each processor core c in chronological order of their occurrence to obtain the occupancy mark toggling event sequence E_c=[e(c,1),e(c,2),...,e(c,K_c)] of processor core c, where K_c is the total number of occupancy mark toggling events on processor core c.

[0016] Step S122: Based on the occurrence time of the flip events in the occupancy mark flip event sequence of each processor core, each occupancy mark flip event is taken as a mark propagation node, and a time-series propagation connection edge is established between two time-adjacent mark propagation nodes on the same processor core to generate the occupancy mark propagation backbone path for each processor core.

[0017] In this embodiment, for each processor core c, each occupancy mark flipping event e(c,k) in the occupancy mark flipping event sequence E_c of that processor core c is defined as a mark propagation node N(c,k). The attributes of the mark propagation node N(c,k) include the processor core identifier c to which it belongs, the event occurrence time T(c,k), and the flipping direction D(c,k). For two adjacent occupancy mark flipping events e(c,k) and e(c,k+1) on the same processor core c, a directed temporal propagation connection edge is established between the mark propagation nodes N(c,k) and N(c,k+1). The direction of this directed temporal propagation connection edge is from the mark propagation node that occurred earlier to the mark propagation node that occurred later, and the weight of this directed temporal propagation connection edge is W(c,k) = T(c,k+1) - T(c,k). All mark propagation nodes and directed temporal propagation connection edges together constitute the occupancy mark propagation backbone path P(c) of the processor core c.

[0018] Step S123: Extract the pair of marker propagation nodes that occur at the same or adjacent acquisition time points in the main path of marker propagation of different processor cores, and establish cross-core propagation connection edges between these pair of marker propagation nodes to obtain cross-core marker propagation association.

[0019] In this embodiment, all processor core pairs c1 and c2 are traversed, where c1 is not equal to c2. For each marker propagation node N(c1, k1) on the occupancy marker propagation backbone path P(c1) of processor core c1, the event occurrence time of marker propagation node N(c1, k1) is T1. For each marker propagation node N(c2, k2) on the occupancy marker propagation backbone path P(c2) of processor core c2, the event occurrence time of marker propagation node N(c2, k2) is T2. When |T1-T2|≤1, the two marker propagation nodes are determined to be temporally adjacent. An undirected cross-core propagation connection edge is established between marker propagation node N(c1, k1) and marker propagation node N(c2, k2). The weight of this undirected cross-core propagation connection edge V(c1, k1, c2, k2) = 1 / (1+|T1-T2|). Collect all undirected cross-core propagation connection edges between all matching marker propagation node pairs to obtain cross-core marker propagation associations.

[0020] Step S124: Merge the occupancy mark propagation backbone paths of all processor cores and all cross-core propagation connection edges into a graph structure to generate an initial processor core occupancy mark propagation graph with mark propagation nodes as vertices and time-series propagation connection edges and cross-core propagation connection edges as edge sets.

[0021] In this embodiment, a graph structure G1 is constructed. The vertex set of graph structure G1 consists of all the marker propagation nodes N(c, k) on all processor cores. The edge set of graph structure G1 consists of two parts: the first part is the temporal propagation connection edges within all processor cores, and the second part is the cross-core propagation connection edges. Each marker propagation node retains its attributes. Each edge retains its type and weight. The resulting initial marker propagation graph G1 for processor core occupancy is a hybrid structure of directed and undirected graphs, where temporal propagation connection edges are directed edges and cross-core propagation connection edges are undirected edges.

[0022] Step S125: In the initial graph of processor core occupancy mark propagation, backtrack search is performed on the continuous propagation path between any two mark propagation nodes, which is composed of alternating time-series propagation connection edges and cross-core propagation connection edges. The continuous propagation path with a length exceeding the preset step threshold is extracted as the long-range dependency path of occupancy mark propagation.

[0023] In this embodiment, a depth-first search is performed on the initial graph G1 of the processor core occupancy mark propagation. Starting from each mark propagation node, the system traverses forward along directed temporal propagation edges, while allowing jumps to mark propagation nodes of other processor cores along undirected cross-core propagation edges. After each jump, the system continues traversing forward along directed temporal propagation edges, forming a continuous propagation path composed of alternating directed temporal propagation edges and undirected cross-core propagation edges. The sequence of mark propagation nodes traversed by each continuous propagation path is recorded. The length of each continuous propagation path, i.e., the number of mark propagation nodes contained in the continuous propagation path, is calculated. A step threshold L is set. Continuous propagation paths with a mark propagation node count greater than or equal to L are extracted as long-range dependency paths D for occupancy mark propagation.

[0024] Step S126: Calculate the time span of the occurrence time of the occupancy mark flipping event of all mark propagation nodes on each occupancy mark propagation long-range dependency path, and determine the propagation synchronization strength level of the occupancy mark propagation long-range dependency path based on the time span, so as to obtain the occupancy mark propagation long-range dependency path with propagation synchronization strength level.

[0025] In this embodiment, for each long-range dependency path D for occupancy mark propagation, the set of event occurrence times {T1, T2, ..., TQ} for all mark propagation nodes on path D is extracted, where Q is the length of path D. The time span S = TQ - T1 of path D is calculated. A propagation synchronization strength level R is defined. When S is less than a threshold A, the propagation synchronization strength level R is set to 3; when S is greater than or equal to A and less than or equal to B, the propagation synchronization strength level R is set to 2; when S is greater than B, the propagation synchronization strength level R is set to 1. The calculated propagation synchronization strength level R is attached as an attribute to path D, resulting in occupancy mark propagation long-range dependency path D1 with a propagation synchronization strength level.

[0026] Step S127: Aggregate the paths with common propagation nodes in all long-range dependent paths of occupancy mark propagation with propagation synchronization strength level, construct occupancy mark propagation path clusters, and extract the common intersection propagation nodes of all paths in each occupancy mark propagation path cluster as occupancy mark propagation intersection kernel nodes.

[0027] In this embodiment, all long-range dependent occupancy propagation paths D1 with propagation synchronization strength levels are clustered according to the propagation nodes they contain. Any two paths that share at least one propagation node are grouped into the same occupancy propagation path cluster. A disjoint-set data structure (DFS) algorithm is used for connected component partitioning. For each occupancy propagation path cluster, the set of propagation nodes commonly traversed by all paths within the cluster is extracted; that is, the propagation nodes contained in every path. These propagation nodes are labeled as occupancy propagation intersection kernel nodes X. If no globally common propagation node exists in a cluster, the propagation nodes traversed by more than 80% of the paths within that cluster are identified as occupancy propagation intersection kernel nodes X.

[0028] Step S128: Using the occupancy mark propagation convergence core node as a shared propagation hub, the path passing through the shared propagation hub in the long-range dependency path of occupancy mark propagation is segmented and branched to generate an occupancy mark propagation branch structure radiating outward from the occupancy mark propagation convergence core node. All occupancy mark propagation convergence core nodes and the occupancy mark propagation branch structures connected to each occupancy mark propagation convergence core node are combined to generate a processor core occupancy mark propagation path network with the occupancy mark propagation convergence core as the skeleton.

[0029] In this embodiment, for each occupancy mark propagation convergence core node X, all long-range dependency paths D1 with propagation synchronization strength levels passing through that occupancy mark propagation convergence core node X are identified. For each of these paths, the path is divided into forward segments and backward segments, with the occupancy mark propagation convergence core node X as the dividing point. These forward and backward segments are organized according to the propagation direction into a bifurcation structure centered on the occupancy mark propagation convergence core node X, where multiple forward segments merge into the occupancy mark propagation convergence core node X, and multiple backward segments branch out from the occupancy mark propagation convergence core node X. The above operation is performed on all occupancy mark propagation convergence core nodes X, and the bifurcation structure is spliced ​​together according to the sharing relationships between the mark propagation nodes. Finally, the processor core occupancy mark propagation path network Gcpu is generated.

[0030] Step S131: Arrange the active state binary flag bits of each memory page in the memory page active flag sequence according to the acquisition time order to generate the active flag time sequence of each memory page, and perform bit-by-bit XOR operation on the active state binary flag bits of adjacent acquisition time points in the active flag time sequence of each memory page to obtain the active flag flip event sequence of each memory page.

[0031] In this embodiment, for each memory page p, the active flag bits of memory page p at all acquisition time points t are extracted from the memory page active flag sequence A(p,t), and arranged in ascending order of acquisition time points t to generate an active flag time sequence V_p=[A(p,1), A(p,2), ..., A(p,M)]. An XOR operation is performed on the active flag bits of adjacent acquisition time points in this active flag time sequence V_p: for each t from 1 to M-1, G(p,t)=A(p,t)XORA(p,t+1). When G(p,t) equals 1, it indicates that an active flag flip occurred at acquisition time point t+1. The occurrence time point t+1 and the flip direction of each active flag flip event are recorded. Arrange all active mark-to-flip events of each memory page p in order of their occurrence time to obtain the active mark-to-flip event sequence F_p=[f(p,1),f(p,2),...,f(p,L_p)] of memory page p, where L_p is the total number of active mark-to-flip events on memory page p.

[0032] Step S132: Based on the occurrence time of the flip events in the active mark flip event sequence of each memory page, take each active mark flip event as a mark propagation node, and establish a time-series propagation connection edge between two mark propagation nodes that are temporally adjacent on the same memory page to generate the active mark propagation backbone path of each memory page.

[0033] In this embodiment, for each memory page p, each active mark-flip event f(p, l) in the active mark-flip event sequence F_p of memory page p is defined as a mark propagation node M(p, l). The attributes of the mark propagation node M(p, l) include the memory page identifier p to which it belongs, the event occurrence time S(p, l), and the flip direction E(p, l). For two adjacent active mark-flip events f(p, l) and f(p, l+1) on the same memory page p, a directed temporal propagation connection edge is established between the mark propagation nodes M(p, l) and M(p, l+1). The direction of this directed temporal propagation connection edge is from the mark propagation node that occurred earlier to the mark propagation node that occurred later, and the weight of this directed temporal propagation connection edge Z(p, l) = S(p, l+1) - S(p, l). All mark propagation nodes and directed temporal propagation connection edges together constitute the active mark propagation backbone path Q(p) of memory page p.

[0034] Step S133: Extract the pairs of marker propagation nodes that occur at the same or adjacent collection time points in the active marker propagation backbone paths of different memory pages, and establish cross-page propagation connection edges between these marker propagation node pairs to obtain cross-page marker propagation associations.

[0035] In this embodiment, all memory page pairs p1 and p2 are traversed, where p1 is not equal to p2. For each marker propagation node M(p1, l1) on the active marker propagation backbone path Q(p1) of memory page p1, the event occurrence time of marker propagation node M(p1, l1) is S1. For each marker propagation node M(p2, l2) on the active marker propagation backbone path Q(p2) of memory page p2, the event occurrence time of marker propagation node M(p2, l2) is S2. When |S1-S2|≤1, an undirected cross-page propagation connection edge is established between marker propagation nodes M(p1, l1) and M(p2, l2). The weight Y(p1, l1, p2, l2) of this undirected cross-page propagation connection edge is 1 / (1+|S1-S2|). All undirected cross-page propagation connection edges between marker propagation node pairs that meet the conditions are collected to obtain the cross-page marker propagation association relationship.

[0036] Step S134: Merge the active marking propagation backbone paths of all memory pages and all cross-page propagation connection edges into a graph structure to generate an initial active marking propagation graph for memory pages with marking propagation nodes as vertices and time-series propagation connection edges and cross-page propagation connection edges as edge sets.

[0037] In this embodiment, a graph structure G2 is constructed. The vertex set of graph structure G2 consists of all mark propagation nodes M(p, l) on all memory pages. The edge set of graph structure G2 consists of two parts: the first part is the temporal propagation connection edges within all memory pages, and the second part is the cross-page propagation connection edges. Each mark propagation node retains its attributes. Each edge retains its type and weight. The resulting initial graph G2 for active mark propagation of memory pages is a hybrid structure of directed and undirected graphs, where temporal propagation connection edges are directed edges and cross-page propagation connection edges are undirected edges.

[0038] Step S135: In the initial graph of active mark propagation in memory pages, backtrack search is performed on the continuous propagation path between any two mark propagation nodes, which is composed of alternating temporal propagation connection edges and cross-page propagation connection edges. The continuous propagation path with a length exceeding the preset step threshold is extracted as the long-range dependency path of active mark propagation.

[0039] In this embodiment, a depth-first search is performed on the initial graph G2 of the active mark propagation in memory pages. Starting from each mark propagation node, the system traverses forward along directed temporal propagation edges, while allowing jumps to mark propagation nodes in other memory pages along undirected cross-page propagation edges. After each jump, the system continues traversing forward along directed temporal propagation edges, forming continuous propagation paths composed of alternating directed temporal propagation edges and undirected cross-page propagation edges. The sequence of mark propagation nodes traversed by each continuous propagation path is recorded. The length of each continuous propagation path is calculated. A step threshold L is set. Continuous propagation paths with a number of mark propagation nodes greater than or equal to L are extracted as long-range dependent paths E for active mark propagation.

[0040] Step S136: Calculate the time span of the active label flipping event occurrence time of all label propagation nodes on each active label propagation long-range dependency path, and determine the propagation synchronization strength level of the active label propagation long-range dependency path based on the time span, so as to obtain the active label propagation long-range dependency path with propagation synchronization strength level.

[0041] In this embodiment, for each active marker propagation long-range dependency path E, the set of event occurrence times {S1, S2, ..., SQ} for all marker propagation nodes on the active marker propagation long-range dependency path E is extracted, where Q is the length of the active marker propagation long-range dependency path E. The time span U = SQ - S1 of the active marker propagation long-range dependency path E is calculated. A propagation synchronization strength level W is defined. When U is less than the threshold A, the propagation synchronization strength level W is set to 3; when U is greater than or equal to A and less than or equal to B, the propagation synchronization strength level W is set to 2; when U is greater than B, the propagation synchronization strength level W is set to 1. The calculated propagation synchronization strength level W is attached as an attribute to the active marker propagation long-range dependency path E, resulting in an active marker propagation long-range dependency path E1 with a propagation synchronization strength level.

[0042] Step S137: Aggregate the paths with common marker propagation nodes in all active marker propagation long-range dependency paths with propagation synchronization strength levels to construct active marker propagation path clusters, and extract the common intersection marker propagation nodes of all paths in each active marker propagation path cluster as active marker propagation intersection kernel nodes.

[0043] In this embodiment, all active labeled propagation long-range dependent paths E1 with propagation synchronization strength levels are clustered according to the labeled propagation nodes they contain. Any two paths that share at least one labeled propagation node are grouped into the same active labeled propagation path cluster. A disjoint-set data structure (DFS) algorithm is used for connected component partitioning. For each active labeled propagation path cluster, the set of labeled propagation nodes commonly traversed by all paths within the cluster is extracted; these labeled propagation nodes are labeled as active labeled propagation convergence kernel nodes Y. If no globally common labeled propagation node exists in a cluster, the labeled propagation nodes traversed by more than 80% of the paths within that cluster are identified as active labeled propagation convergence kernel nodes Y.

[0044] Step S138: Using the active mark propagation convergence core node as a shared propagation hub, the paths passing through this shared propagation hub in the long-range dependency path of active mark propagation are segmented and forked to generate an active mark propagation forking structure radiating outward from the active mark propagation convergence core node. All active mark propagation convergence core nodes and the active mark propagation forking structures connected to each active mark propagation convergence core node are combined to generate a memory page active mark propagation path network with the active mark propagation convergence core as the skeleton.

[0045] In this embodiment, for each active mark propagation convergence core node Y, all long-range dependent paths E1 with propagation synchronization strength levels passing through active mark propagation convergence core node Y are identified. For each of these paths, the path is divided into forward and backward segments, with active mark propagation convergence core node Y as the dividing point. These forward and backward segments are then organized into a bifurcated structure centered on active mark propagation convergence core node Y according to the propagation direction. The above operation is performed on all active mark propagation convergence core nodes Y, and the bifurcated structures are then spliced ​​together according to the sharing relationships between mark propagation nodes. Finally, the memory page active mark propagation path network Gmem is generated.

[0046] Step S140: Perform cross-resource mark propagation intersection mapping between the intersection clustering patterns of mark propagation paths in the processor core occupied mark propagation path network and the intersection clustering patterns of mark propagation paths in the memory page active mark propagation path network to generate a processor memory mark propagation intersection association graph.

[0047] Step S141: Extract all occupancy mark propagation intersection core nodes in the processor core occupancy mark propagation path network to form a processor-side intersection core node set, and extract all active mark propagation intersection core nodes in the memory page active mark propagation path network to form a memory-side intersection core node set.

[0048] In this embodiment, the processor core occupancy mark propagation path network Gcpu is traversed, and all occupancy mark propagation converging core nodes X are extracted. These occupancy mark propagation converging core nodes X are added to the processor-side converging core node set S1={X1, X2, ..., XU}, where U is the total number of processor-side converging core nodes. The memory page active mark propagation path network Gmem is traversed, and all active mark propagation converging core nodes Y are extracted. These active mark propagation converging core nodes Y are added to the memory-side core node set S2={Y1, Y2, ..., YV}, where V is the total number of memory-side core nodes.

[0049] Step S142: Obtain the propagation direction vector sequence of all occupancy mark propagation bifurcation structures connected to each processor-side converged core node in the processor core occupancy mark propagation path network, and obtain the propagation direction vector sequence of all active mark propagation bifurcation structures connected to each memory-side converged core node in the memory page active mark propagation path network.

[0050] In this embodiment, for each processor-side converged core node Xu in the processor-side converged core node set S1, all occupancy mark propagation fork structures radiated by Xu are identified in the processor core occupancy mark propagation path network Gcpu. Each occupancy mark propagation fork structure contains multiple branch paths. For each branch path, its propagation direction vector is extracted. The direction of this propagation direction vector is defined as the direction from the processor-side converged core node Xu to the first successor mark propagation node on the branch path, with the difference in acquisition time points as the first component and the difference in processor core numbers as the second component. The propagation direction vectors of all branch paths of the processor-side converged core node Xu are arranged in the order of the event occurrence time points of the first successor mark propagation node on the branch path to obtain the processor-side propagation direction vector sequence Uu. For each memory-side converged core node Yv in the memory-side converged core node set S2, all active mark propagation fork structures radiated by Yv are identified in the memory page active mark propagation path network Gmem. Each active mark propagation fork structure contains multiple branch paths. For each branch path, its propagation direction vector is extracted. The direction of this propagation direction vector is defined as the direction from the memory-side confluence core node Yv to the first successor marked propagation node on that branch path. The difference in acquisition time points is used as the first component, and the difference in memory page numbers is used as the second component. The propagation direction vectors of all branch paths of the memory-side confluence core node Yv are arranged in order of the event occurrence time of the first successor marked propagation node on the branch path to obtain the memory-side propagation direction vector sequence Vv.

[0051] Step S143: For each processor-side converged core node's propagation direction vector sequence and each memory-side converged core node's propagation direction vector sequence, calculate the waveform similarity of the direction vector sequences on the time axis to obtain the propagation direction waveform matching degree between processor-memory converged core pairs. Extract processor-memory converged core pairs whose propagation direction waveform matching degree exceeds a preset waveform matching threshold, and establish cross-resource marked propagation convergence corresponding edges between these processor-memory converged core pairs to obtain cross-resource converged core pair matching relationships.

[0052] In this embodiment, for each processor-side converged core node Xu and its processor-side propagation direction vector sequence Uu in the processor-side converged core node set S1, and for each memory-side converged core node Yv and its memory-side propagation direction vector sequence Vv in the memory-side converged core node set S2, the dynamic time warping algorithm is used to calculate the dynamic time warping distance Duv between Uu and Vv. The dynamic time warping distance is converted into a propagation direction waveform matching degree Ruv = 1 / (1+Duv). A waveform matching threshold H is set. When Ruv > H, it is determined that there is a cross-resource marker propagation convergence relationship between the processor-side converged core node Xu and the memory-side converged core node Yv. A cross-resource marker propagation convergence corresponding edge is established between the processor-side converged core node Xu and the memory-side converged core node Yv. All cross-resource marker propagation convergence corresponding edges that meet the conditions are collected to form a cross-resource converged core matching relationship.

[0053] Step S144: For each pair of processor memory convergence cores with established cross-resource tag propagation convergence edges, calculate the overlap of the flip time points of the occupied tag flip time series of the processor-side convergence core node and the active tag flip time series of the memory-side convergence core node in the processor memory convergence core pair. Determine the convergence tightness level between the processor memory convergence cores based on the overlap of the flip time points, and obtain the cross-resource convergence core pair edges with convergence tightness levels.

[0054] In this embodiment, for each cross-resource marker propagation intersection corresponding edge in the cross-resource intersection core matching relationship, this edge connects the processor-side intersection core node Xu and the memory-side intersection core node Yv. The set of all flip time points Tu for the processor-side intersection core node Xu in the original occupied marker flip event sequence is extracted. The set of all flip time points Tv for the memory-side intersection core node Yv in the original active marker flip event sequence is extracted. The overlap of flip time points is defined as Q = |Tu∩Tv| / min(|Tu|, |Tv|), where |Tu∩Tv| represents the number of time points in the Tu and Tv sets that have the same time point or whose time point difference does not exceed one acquisition time interval. The intersection tightness level is determined based on the overlap of flip time points Q. When Q is greater than 0.7, the intersection tightness level is set to 3; when Q is greater than or equal to 0.4 and less than or equal to 0.7, the intersection tightness level is set to 2; when Q is less than 0.4, the intersection tightness level is set to 1. The intersection density level is attached as an attribute to the corresponding edge of the cross-resource marker propagation intersection, resulting in a cross-resource intersection core edge with an intersection density level.

[0055] Step S145: Perform graph fusion on all processor-side converged core nodes, all memory-side converged core nodes, and all cross-resource converged core edges with convergence density levels to generate a cross-resource tag propagation convergence initial association graph.

[0056] In this embodiment, a graph structure G3 is constructed. The vertex set of graph structure G3 contains all nodes in the processor-side convergent core node set S1 and the memory-side convergent core node set S2. The edge set of graph structure G3 contains all cross-resource convergent core pairs with convergence density levels. G3 is a bipartite graph structure, and all edges exist only between processor-side convergent core nodes and memory-side convergent core nodes.

[0057] Step S146: In the cross-resource marker propagation and initial association graph, cross-resource convergence core pairs that pass through the same processor-side convergence core node and the same memory-side convergence core node are aggregated to generate a cross-resource convergence domain, and the convergence density level distribution pattern of all cross-resource convergence core pairs within the cross-resource convergence domain is extracted.

[0058] In this embodiment, in the cross-resource marker propagation convergence initial association graph G3, a clique detection algorithm is used to find all maximal complete binary graphs. Each maximal complete binary graph is defined as: a set of processor-side convergence core node subsets S1sub and a set of memory-side convergence core node subsets S2sub, such that there exists a cross-resource convergence core pair edge with convergence density level between each processor-side convergence core node in S1sub and each memory-side convergence core node in S2sub. Each of the above maximal complete binary graphs is called a cross-resource convergence domain Z. For each cross-resource convergence domain Z, the convergence density level values ​​of all cross-resource convergence core pairs with convergence density levels in Z are collected, and the frequencies of level 3, level 2, and level 1 are counted to obtain the convergence density level distribution pattern of Z.

[0059] Step S147: Based on the intersection density distribution pattern of all cross-resource intersection core edges in the cross-resource intersection convergence domain, mark the intersection splitting trend for each cross-resource intersection convergence domain to obtain the cross-resource intersection convergence domain with splitting trend marking.

[0060] In this embodiment, for each cross-resource convergence domain Z, its convergence density level distribution pattern is analyzed. If there is at least one cross-resource convergence core edge with a convergence density level of 1 within Z, and both endpoints of this level 1 edge are connected to other cross-resource convergence core edges with a convergence density level of 3, then Z is marked as having a splitting trend. If all cross-resource convergence core edges within Z have a convergence density level of 3, then Z is marked as stable convergence. If the convergence density level distribution within Z is uniform but shows a gradual decay trend in the time series, then Z is marked as slowly degenerating. A splitting trend label attribute is attached to Z.

[0061] Step S148: Arrange all cross-resource convergence domains with splitting trend markers according to their topological connection relationships in the cross-resource marker propagation convergence initial association graph to generate the processor memory marker propagation convergence association graph.

[0062] In this embodiment, each cross-resource convergence domain Z is treated as a supernode. If two cross-resource convergence domains Z share at least one processor-side convergence core node or at least one memory-side convergence core node, a topological connection edge is established between these two supernodes. A graph structure G4 is constructed, where the vertices of graph structure G4 are the respective cross-resource convergence domains Z, and the edges of graph structure G4 represent the resource overlap relationships between the cross-resource convergence domains. Each vertex is accompanied by its splitting trend label attribute. This graph structure G4 is the processor-memory label propagation convergence association graph.

[0063] Step S150: Generate resource jitter suppression instructions for the target process set based on the splitting timing characteristics of the clusters in the processor memory mark propagation intersection association graph.

[0064] Step S151: In the processor memory tag propagation convergence graph, locate all cross-resource convergence domains with split trend tags, and extract the processor-side convergence core nodes and memory-side convergence core nodes contained in each cross-resource convergence domain with split trend tags.

[0065] In this embodiment, each vertex in the processor memory tag propagation convergence graph G4, i.e., each cross-resource convergence domain Z, is traversed, and the splitting trend tagging attribute of Z is checked. If Z is tagged as splitting trend or slow degradation, then all processor-side convergence core node sets Zcpu and all memory-side convergence core node sets Zmem contained in Z are extracted.

[0066] Step S152: For each cross-resource convergence domain with a split trend marker, trace the long-range dependency path of occupancy marker propagation associated with each processor-side convergence core node in the processor core occupancy marker propagation path network, and extract the processor core identifiers covered by the long-range dependency path of occupancy marker propagation.

[0067] In this embodiment, for each cross-resource convergence domain Z with a splitting trend marker, for each processor-side convergence core node X in its processor-side convergence core node set Zcpu, all long-range dependency paths D1 passing through X in the processor core occupancy marker propagation path network Gcpu are identified. For each long-range dependency path D1, the processor core number to which all marker propagation nodes on path D1 belong is extracted. The deduplicated processor core numbers are then added to the set Cset.

[0068] Step S153: For each cross-resource convergence domain with a splitting trend marker, trace the long-range dependency path of active marker propagation associated with each memory-side convergence core node in the memory page active marker propagation path network, and extract the memory page identifiers covered by the long-range dependency path of active marker propagation.

[0069] In this embodiment, for each cross-resource convergence domain Z with a splitting trend marker, for each memory-side convergence core node Y in its memory-side convergence core node set Zmem, all active marker propagation long-range dependency paths E1 passing through Y are identified in the memory page active marker propagation path network Gmem. For each active marker propagation long-range dependency path E1, the memory page numbers to which all marker propagation nodes on path E1 belong are extracted. The deduplicated memory page numbers are then added to the set Pset.

[0070] Step S154: Combine the processor core identifier and memory page identifier corresponding to each cross-resource intersection convergence domain with splitting trend marker to form the resource coupling domain corresponding to the cross-resource intersection convergence domain, and obtain the set of process identifiers currently occupying the resource coupling domain. Perform splitting timing analysis on the splitting trend marker of each cross-resource intersection convergence domain with splitting trend marker, and predict the splitting start time point of the cross-resource intersection convergence domain based on the trend of the decay of the intersection tightness level of cross-resource intersection core-to-edge in the cross-resource intersection convergence domain over time.

[0071] In this embodiment, for each cross-resource intersection convergence domain Z with a splitting trend marker, its Cset and Pset are combined into a resource coupling domain Rset=(Cset, Pset). The process identifiers of any processor core or memory page currently in use within Rset are queried through the operating system kernel interface, forming a process identifier set Qset. For the intersection density levels of each cross-resource intersection core-to-core edge within Z, their temporal changes are traced. The intersection density levels within each time window are extracted from the raw data, and a decay curve of the level over time is plotted. A linear regression model is used to fit the decay curve to predict the time point Ts corresponding to when the level decays below 1; this Ts is the splitting start time point of Z.

[0072] Step S155: Summarize the predicted split start time points and all cross-resource convergence domains in the processor memory mark propagation intersection graph, construct a global split timing ranking list, and extract the set of target cross-resource convergence domains whose split start time points fall within a preset time window.

[0073] In this embodiment, all cross-resource intersection convergence domains Z and their predicted splitting start times Ts are aggregated and sorted in ascending order of Ts to generate a global splitting time series list L. A look-ahead time window W is set. Cross-resource intersection convergence domains Z whose Ts fall within the time window W are extracted from L to form the target cross-resource intersection convergence domain set TZ.

[0074] Step S156: Obtain the process identifier set of the resource coupling domain corresponding to each target cross-resource intersection aggregation domain in the target cross-resource intersection aggregation domain set, and deduplicate and merge all process identifiers to obtain the target process set. Backtrack the processor core occupation trajectory and memory page occupation trajectory of each process in the target process set, extract the occupation mark flip frequency of the process on each processor core and the active mark flip frequency on each memory page, and generate process resource jitter features.

[0075] In this embodiment, for each cross-resource intersection domain Z in the target cross-resource intersection domain set TZ, the process identifier set Qset corresponding to its resource coupling domain Rset is extracted. The process identifiers in all Qsets are combined and deduplicated to obtain the target process set Tset. For each process identifier pid in the target process set Tset, the historical usage trajectory of the process is traced back from the original collected data. The number of times the occupancy flag of the process on each processor core changes from 0 to 1 within the time window is counted, resulting in the flip frequency vector Fcpu(pid). The number of times the active flag of the process on each memory page changes from 0 to 1 within the time window is counted, resulting in the flip frequency vector Fmem(pid). Fcpu(pid) and Fmem(pid) are concatenated to obtain the resource jitter feature vector F(pid) of the process.

[0076] Step S157: Based on the process resource jitter characteristics, retrieve the process resource constraint parameter combination that matches the process resource jitter characteristics from the preset resource jitter suppression strategy template library, bind and encapsulate the process resource constraint parameter combination corresponding to each process with the process identifier, and generate a resource jitter suppression instruction for the target process set.

[0077] In this embodiment, a resource jitter suppression strategy template library is pre-built, where each template contains a feature matching condition and a combination of resource constraint parameters. The resource constraint parameter combination includes a processor core binding mask and a memory page locking range. For each process pid in the target process set Tset, the Euclidean distance between its feature vector F(pid) and the feature matching condition of each template is calculated. The template with the smallest Euclidean distance is selected, and the corresponding resource constraint parameter combination is extracted. This resource constraint parameter combination is bound to the process identifier pid and packaged into an instruction entry. The instruction entries for all process pids are aggregated to generate the resource jitter suppression instruction Ins. This resource jitter suppression instruction Ins will be sent to the operating system scheduler and memory manager for execution.

[0078] Step S210: Obtain the storage device input / output request queuing mark sequence and the network device data packet transmission / reception queuing mark sequence of the computer device to be monitored.

[0079] In this embodiment, the monitoring range of the acquisition probe is further expanded based on step S110. For storage devices, the acquisition probe checks the input / output request queue length of each storage device at each acquisition time point. When the queue length exceeds a preset first length threshold, the binary flag bit of the request queue length of the storage device is recorded as a value of 1; otherwise, it is recorded as a value of 0. For network devices, the acquisition probe checks the length of the data packet sending queue and receiving queue of each network device at each acquisition time point. When the sending queue length or the receiving queue length exceeds a preset second length threshold, the binary flag bit of the data packet queue length of the network device is recorded as a value of 1; otherwise, it is recorded as a value of 0. After continuously acquiring data for M cycles, a storage device input / output request queue flag sequence is obtained. This storage device input / output request queue flag sequence is a two-dimensional matrix, where the row index corresponds to the storage device number d, the column index corresponds to the acquisition time point t, and the matrix element is the queue flag bit Q(d,t) of storage device d at acquisition time point t. At the same time, the queuing mark sequence of network device data packets is obtained. This queuing mark sequence of network device data packets is a two-dimensional matrix. The row index corresponds to the network device number n, the column index corresponds to the collection time point t, and the matrix element is the queuing mark bit R(n,t) of network device n at the collection time point t.

[0080] Step S220: Reconstruct the queuing mark propagation path for the input / output request queuing mark sequence of the storage device to generate the queuing mark propagation path network of the storage device, and reconstruct the queuing mark propagation path for the data packet transmission / reception queuing mark sequence of the network device to generate the queuing mark propagation path network of the network device.

[0081] In this embodiment, the processing flow is exactly the same as steps S121 to S128 for the storage device queuing mark sequence Q(d,t) and the network device queuing mark sequence R(n,t). For the storage device, the queuing mark bits of each storage device d are arranged according to the acquisition time point to generate a time series. The XOR of adjacent acquisition time points is calculated to obtain the flip event sequence. Each flip event is used as a mark propagation node. A time-series propagation connection edge is established on the same storage device to generate a backbone path. Cross-device propagation connection edges are established between the mark propagation nodes of different storage devices. The nodes are fused to generate an initial graph. Long-range dependency paths are searched. The time span and synchronization strength level are calculated. Path clusters are generated by clustering. The queuing mark propagation intersection core node is extracted. A bifurcation structure is constructed, and finally, the storage device queuing mark propagation path network Gsto is generated. For the network device, the same method is used to generate the network device queuing mark propagation path network Gnet.

[0082] Step S230: Perform cross-device label propagation intersection mapping between the intersection clustering pattern of label propagation paths in the storage device queuing label propagation path network and the intersection clustering pattern of label propagation paths in the network device queuing label propagation path network to generate a storage network label propagation intersection association graph.

[0083] In this embodiment, the processing flow for Gsto and Gnet is exactly the same as that in steps S141 to S148. All queuing mark propagation intersection core nodes in the storage device queuing mark propagation path network Gsto are extracted to form the storage-side intersection core node set Ssto, and all queuing mark propagation intersection core nodes in the network device queuing mark propagation path network Gnet are extracted to form the network-side intersection core node set Snet. The waveform similarity of the propagation direction vector sequences of the storage-side nodes and network-side nodes is calculated, corresponding edges for cross-device mark propagation intersection are established, the overlap of flip time points is calculated to determine the intersection tightness level, an initial cross-device mark propagation intersection association graph is generated, cross-device intersection convergence domains are aggregated, splitting trend marking is performed, and the layout is arranged according to the topological connection relationship, finally generating the storage-network mark propagation intersection association graph Gsnet.

[0084] Step S240: Perform cross-domain label propagation intersection mapping on the processor memory label propagation intersection graph and the storage network label propagation intersection graph to generate a three-dimensional label propagation intersection graph of computing resources, storage resources, and network resources.

[0085] In this embodiment, a hypergraph structure, Gall, is constructed. Each cross-resource convergence domain Z in the processor memory tag propagation convergence graph G4 generated in step S148 is designated as a first-type supernode, and each cross-device convergence domain in the storage network tag propagation convergence graph Gsnet generated in step S230 is designated as a second-type supernode. The associations between cross-resource convergence domains in G4 involving memory-side convergence core nodes and cross-device convergence domains in Gsnet involving storage devices or network devices are identified. Specifically, if a memory page associated with a memory-side convergence core node in the first-type supernode exists in a data mapping relationship with a storage device associated with a storage device convergence core node in the second-type supernode, a cross-domain connection edge is established between the two supernodes by querying the file system page cache mapping table or direct input / output mapping table. The weight of this cross-domain connection edge is equal to the data block overlap ratio, calculated as the number of overlapping data blocks divided by the total number of data blocks. All supernodes and cross-domain connection edges are merged to generate a three-dimensional tag propagation convergence graph, Gall, representing computing resources, storage resources, and network resources.

[0086] Step S250: Analyze the splitting timing synchronization of cross-domain intersection clusters in the propagation intersection graph of computing resources, storage resources, and network resources, extract the synchronization splitting time window of the cross-domain intersection clusters, and generate a joint jitter suppression instruction chain for the global resource coupling domain based on the synchronization splitting time window of the cross-domain intersection clusters.

[0087] In this embodiment, a clique detection algorithm is used in the Gall to find all maximal complete subgraphs, each of which is called a cross-domain clique. For each cross-domain clique, the split start time points Ts of all first-class and second-class supernodes contained in the clique are collected. The difference between the maximum and minimum values ​​of these split start time points is calculated. If the difference is less than the synchronization threshold L, the clique has synchronous split characteristics. The median of all split start time points in the clique is taken as the synchronous split time point Tc of the clique. With Tc as the center, the time window width W2 is expanded before and after it to obtain the synchronous split time window [Tc-W2 / 2, Tc+W2 / 2]. The synchronous split time windows of all cross-domain cliques are arranged in chronological order to construct a joint jitter suppression instruction chain. This joint jitter suppression instruction chain is a sequence, and each sequence entry contains the start time of the time window, the end time of the time window, and a list of resource constraint actions to be executed within the window. For each time window, a joint jitter suppression instruction Ijoint is generated and appended to the resource jitter suppression instruction Ins generated in step S157 to form a chain of joint suppression instructions executed in time sequence.

[0088] Step S310: Obtain the storage device request queue tag sequence and the network device packet queue tag sequence of the computer device to be monitored.

[0089] In this embodiment, the data obtained in this step is the same as that in step S210. The storage device request queuing mark sequence is denoted as Qs(d,t), and the network device packet queuing mark sequence is denoted as Rs(n,t). The determination rule for the binary mark bit is the same as in step S210.

[0090] Step S320: Reconstruct the queuing mark propagation path for the storage device request queuing mark sequence to generate a storage device queuing mark propagation path network, and reconstruct the queuing mark propagation path for the network device data packet queuing mark sequence to generate a network device queuing mark propagation path network.

[0091] In this embodiment, the processing flow for Qs(d,t) and Rs(n,t) is exactly the same as that in steps S121 to S128. XOR operations are used to extract flip events, establish time-series propagation connections and cross-device propagation connections, generate an initial graph, search for long-range dependency paths, cluster to generate path clusters, extract queuing mark propagation intersection core nodes, construct a forking structure, and finally generate the storage device queuing mark propagation path network Gsto2 and the network device queuing mark propagation path network Gnet2.

[0092] Step S330: Perform cross-device label propagation intersection mapping between the intersection clustering pattern of label propagation paths in the storage device queuing label propagation path network and the intersection clustering pattern of label propagation paths in the network device queuing label propagation path network to generate a storage network label propagation intersection association graph.

[0093] In this embodiment, the processing flow for Gsto2 and Gnet2 is exactly the same as that in steps S141 to S148. The queuing mark propagation intersection core nodes in the storage device queuing mark propagation path network Gsto2 are extracted to form the storage-side intersection core node set Ssto2, and the queuing mark propagation intersection core nodes in the network device queuing mark propagation path network Gnet2 are extracted to form the network-side intersection core node set Snet2. The similarity of the propagation direction vector sequence waveforms is calculated, cross-device mark propagation intersection corresponding edges are established, the intersection density level is calculated, and the storage network mark propagation intersection association graph Gsnet2 is generated.

[0094] Step S340: Perform cross-domain label propagation intersection mapping on the processor memory label propagation intersection graph and the storage network label propagation intersection graph to generate a three-dimensional label propagation intersection graph of the computing and storage networks. Analyze the splitting timing synchronization of the cross-domain intersection clusters in the three-dimensional label propagation intersection graph of the computing and storage networks, and extract the synchronous splitting time window of the cross-domain intersection clusters.

[0095] In this embodiment, the processor memory tag propagation intersection graph G4 generated in step S148 and the storage network tag propagation intersection graph Gsnet2 generated in step S330 are fused using the same method as in steps S240 and S250. A hypergraph structure Gall2 is constructed, cross-domain intersection clusters are identified, the synchronicity of the splitting start time points within each cluster is calculated, and the synchronous splitting time window Ws for each cross-domain intersection cluster is extracted.

[0096] Step S350: Based on the cross-domain convergence cluster synchronization split time window, locate the occupancy mark propagation convergence core node associated with the cross-domain convergence cluster in the processor core occupancy mark propagation path network, and extract the flip interval time distribution pattern in the occupancy mark flip event sequence of the occupancy mark propagation convergence core node.

[0097] In this embodiment, for each cross-domain convergence cluster, the portion of the cluster belonging to the processor memory mark propagation convergence association graph G4 is identified. All processor-side convergence core nodes X are extracted from this portion. For each of the aforementioned processor-side convergence core nodes X, in its original occupancy mark flip event sequence E_c, the time interval sequence Ix = [T2-T1, T3-T2, ..., T_{L}-T_{L-1}] between adjacent flip events is calculated. Statistical analysis is performed on this time interval sequence Ix to calculate the mean, variance, median, and interquartile range. These four statistics are combined to form the flip interval time distribution pattern Px for the processor-side convergence core node X.

[0098] Step S360: Based on the flip interval time distribution pattern, retrieve the scheduling clock phase offset that matches the flip interval time distribution pattern from the preset process scheduling clock adjustment strategy library.

[0099] In this embodiment, a process scheduling clock adjustment strategy library is pre-constructed, where each template contains a distribution pattern feature interval and a scheduling clock phase offset Ph. The scheduling clock phase offset Ph represents the amount of time the scheduler clock should be shifted forward or backward. For each cross-domain convergence cluster, the flip interval time distribution patterns Px of all associated processor-side convergence core nodes X are weighted and averaged, with the weight taken as the value of the propagation synchronization strength level R of each processor-side convergence core node X, to obtain the comprehensive distribution pattern Pcomb of the cluster. The template that best matches Pcomb is found in the process scheduling clock adjustment strategy library, and the scheduling clock phase offset Ph corresponding to that template is retrieved.

[0100] Step S370: Bind the scheduling clock phase offset, the cross-domain convergence cluster synchronization split time window, and the target process set to generate a scheduling clock phase offset instruction for the global resource coupling domain, and attach the scheduling clock phase offset instruction to the resource jitter suppression instruction to form a joint suppression instruction.

[0101] In this embodiment, the scheduling clock phase offset Ph obtained in step S360, the synchronization split time window Ws obtained in step S340, and the target process set Tset obtained in step S156 are bound together. A scheduling clock phase offset instruction Iclk is constructed, which contains three fields: effective time window Ws, phase offset Ph, and affected process set Tset. The scheduling clock phase offset instruction Iclk is appended to the resource jitter suppression instruction Ins generated in step S157 to form a joint suppression instruction chain Icomb. This joint suppression instruction chain Icomb is sent to the scheduler module of the operating system kernel, and the scheduler offsets the scheduling clock phase Ph of the processes in the target process set Tset within the synchronization split time window Ws.

[0102] Step S410: In the processor core occupancy flag propagation path network, extract the propagation direction vector of each branch path in the occupancy flag propagation bifurcation structure radiated by each occupancy flag propagation intersection core node, calculate the direction dispersion of the propagation direction vectors of each branch path, extract the occupancy flag propagation intersection core node with the direction dispersion lower than the preset direction dispersion threshold as the directional propagation intersection core node, and extract the processor core identifier set covered by the occupancy flag propagation long-range dependency path associated with the directional propagation intersection core node in the processor core occupancy flag propagation path network.

[0103] In this embodiment, each occupancy flag propagation intersection core node X in the processor core occupancy flag propagation path network Gcpu is traversed. For node X, all branch paths in all radiated occupancy flag propagation bifurcation structures are acquired. For each branch path, its propagation direction vector Wx is extracted. The angle value θ of the above propagation direction vector is converted to a point (cosθ, sinθ) on the unit circle, and the root mean square length of these points is calculated , where N is the total number of branch paths. The direction dispersion Disp=1-Lr. The value range of Disp is from 0 to 1, and a smaller value indicates that the directions of the respective branches are more concentrated. The direction dispersion threshold Dth is set. The occupancy flag propagation intersection core node X with Disp<Dth is extracted as the directional propagation intersection core node Xdir. For each directional propagation intersection core node Xdir, all occupancy flag propagation long-range dependency paths D1 passing through Xdir are found in Gcpu, and all processor core numbers covered by these occupancy flag propagation long-range dependency paths D1 are extracted to form a directional propagation processor core identifier set Cdir.

[0104] Step S420: In the memory page active flag propagation path network, extract the active flag propagation intersection core node that has a cross-resource intersection core pair edge with the directional propagation intersection core node in the processor-memory flag propagation intersection association graph, and extract the memory page identifier set covered by the active flag propagation long-range dependency path associated with the active flag propagation intersection core node.

[0105] In this embodiment, for each directional propagation intersection core node Xdir, all memory-side intersection core nodes Ylink that have a cross-resource intersection corresponding edge with Xdir are found in the processor-memory flag propagation intersection association graph G4. For each memory-side intersection core node Ylink, all active flag propagation long-range dependency paths E1 passing through Ylink are found in the memory page active flag propagation path network Gmem, and the memory page numbers covered by these active flag propagation long-range dependency paths E1 are extracted to form a directional propagation memory page identifier set Pdir.

[0106] Step S430: combining the directed propagation processor core identifier set and the directed propagation memory page identifier set into a directed propagation resource coupling domain, and acquiring a directed propagation process identifier set that currently occupies the directed propagation resource coupling domain.

[0107] In this embodiment, Cdir and Pdir are combined into the directed propagation resource coupling domain Rdir=(Cdir, Pdir). A process identifier that is currently using any processor core or any memory page in Rdir is queried through an operating system kernel interface, to form the directed propagation process identifier set Qdir.

[0108] Step S440: performing flip frequency stability analysis on the occupation mark flip event sequence of each process in the directed propagation process identifier set, extracting the fluctuation amplitude of the occupation mark flip frequency of the process on each processor core, and marking a process whose fluctuation amplitude is lower than a preset fluctuation amplitude threshold as a steady-state jitter process.

[0109] In this embodiment, for each process identifier pid in the directed propagation process identifier set Qdir, the occupation mark flip event sequence of the process on each processor core c is extracted from the original collected data. For each processor core c, the flip frequency freq(pid, c) of the process on the processor core c is calculated as (the number of flips on the core) / (total collection duration). The standard deviation of the flip frequencies of the process on all processor cores is calculated , where μ is the average flip frequency on all processor cores, and C is the total number of processor cores. A fluctuation amplitude threshold Vth is set. When std(pid) < Vth, the process is marked as a steady-state jitter process pid_s.

[0110] Step S450: backtracking the memory page access trace of the steady-state jitter process within the directed propagation resource coupling domain, and extracting the median of the flip interval time in the active mark flip event sequence of the steady-state jitter process on each memory page.

[0111] In this embodiment, for each steady-state jitter process pid_s, the active mark flip event sequence of the process on each memory page p in the directed propagation memory page identifier set Pdir is extracted from the original collected data. For each memory page p, the time interval between adjacent active mark flip events is calculated, to obtain a time interval sequence. The median med(pid_s, p) of the time interval sequence is taken. The medians of all memory pages p are collected to form a memory page flip interval median vector Vmed(pid_s) of the steady-state jitter process pid_s.

[0112] Step S460: Based on the median flip interval time, retrieve the topology location of the memory page migration target node that matches the median flip interval time from the preset memory page migration strategy template library.

[0113] In this embodiment, a memory page migration strategy template library is pre-built, where each template contains a median flip interval range and a target node topology location NodeT. The target node topology location NodeT represents the identifier of a near-end node or a far-end node in a non-uniform memory access architecture. For each steady-state jittering process pid_s, the median med(pid_s, p) of each memory page p in its memory page flip interval median vector Vmed(pid_s) is matched with the median flip interval range in the template library, and a corresponding target node topology location NodeT(p) is selected for each memory page p.

[0114] Step S470: Bind the process identifier of the steady-state jittering process, the set of memory page identifiers of the directed propagation resource coupling domain, and the topological location of the target node for memory page migration to generate a memory page redistribution instruction for the steady-state jittering process, and attach the memory page redistribution instruction to the resource jitter suppression instruction.

[0115] In this embodiment, for each steady-state jittering process pid_s, a memory page redistribution instruction Imig is generated. This instruction contains three fields: process identifier pid_s, the set of memory pages to be migrated Pdir, and the target node topology location NodeT(p) for each memory page. The Imig instruction is appended to the resource jitter suppression instruction Ins generated in step S157. Upon receiving Imig, the operating system memory manager migrates the specified memory pages to the corresponding target nodes.

[0116] For example, the method may further include: step S510: in the processor core occupancy mark propagation path network, extract the propagation synchronization strength weight of the long-range dependency path of occupancy mark propagation between any two occupancy mark propagation converging core nodes, and construct a propagation synchronization strength weighted topology graph with the occupancy mark propagation converging core nodes as vertices.

[0117] In this embodiment, all occupancy mark propagation convergence core nodes X in the processor core occupancy mark propagation path network Gcpu are traversed. For any two different occupancy mark propagation convergence core nodes Xi and Xj, if at least one long-range dependency path D1 of occupancy mark propagation passes through both Xi and Xj, the propagation synchronization strength level R of this long-range dependency path D1 is extracted. The propagation synchronization strength level R is converted into a weight Wsync, with the conversion rule being that level 3 corresponds to a weight of 0.9, level 2 corresponds to a weight of 0.5, and level 1 corresponds to a weight of 0.2. If multiple long-range dependency paths of occupancy mark propagation connect both Xi and Xj, the maximum weight is taken. Using all occupancy mark propagation convergence core nodes X as vertices, the edges between node pairs with existing paths as edges, and Wsync as the edge weight, an undirected weighted topology graph Gsync is constructed.

[0118] Step S520: Perform community partitioning on the propagation synchronization strength weighted topology graph, and classify the occupancy marker propagation intersection kernel nodes whose propagation synchronization strength weight exceeds the preset synchronization strength threshold into the same propagation synchronization community, and extract the community boundary intersection kernel node set of each propagation synchronization community.

[0119] In this embodiment, the Louvain community detection algorithm is used to partition Gsync into communities, which iteratively assigns nodes to communities by maximizing the modularity function. The modularity calculation formula is: modularity equals (sum of edge weights within the community minus the expected sum of edge weights) divided by the total sum of edge weights. A synchronization strength threshold Wth is set. During the community partitioning process, if the edge weight Wsync between two nodes is lower than Wth, the edge is considered a weak connection and does not participate in community aggregation. After community partitioning is completed, several propagation synchronization communities Comm are obtained. For each propagation synchronization community Comm, the occupancy markers X of the propagation intersection kernel nodes that have edges between the community and the outside of the community are identified. These nodes are called the community boundary intersection kernel node set Bnd.

[0120] Step S530: For each community boundary intersection core node in the community boundary intersection core node set of each propagation synchronization community, extract the active marked propagation intersection core nodes that have cross-resource intersection core edges with the community boundary intersection core node in the memory page active marked propagation path network, and form the memory-side mapping node set of the propagation synchronization community.

[0121] In this embodiment, for each propagation synchronization community Comm, each node Xb in its community boundary convergence core node set Bnd is traversed. In the processor memory-marked propagation convergence association graph G4, all memory-side convergence core nodes Yb that have cross-resource convergence corresponding edges with Xb are identified. The aforementioned memory-side convergence core nodes Yb are added to the memory-side mapping node set Yset of the propagation synchronization community Comm.

[0122] Step S540: Based on the active mark propagation path cluster to which each active mark propagation convergence core node in the memory-side mapping node set belongs in the active mark propagation path network of the memory page, extract the memory page identifiers covered by all active mark propagation long-range dependency paths within the active mark propagation path cluster, and form the mapping memory page set of the propagation synchronization community.

[0123] In this embodiment, for each memory-side convergence core node Yb in the memory-side mapping node set Yset, the active label propagation path cluster to which Yb belongs is identified in the memory page active label propagation path network Gmem. For all active label propagation long-range dependency paths E1 within this active label propagation path cluster, the memory page numbers corresponding to all label propagation nodes on each active label propagation long-range dependency path E1 are extracted. After deduplicating all extracted memory page numbers, they are added to the mapped memory page set Pmap of the propagation synchronization community Comm.

[0124] Step S550: Summarize all processor core identifiers associated with the propagation convergence core nodes in each propagation synchronization community to obtain the community processor core set. Combine the community processor core set with the mapped memory page set to form the resource domain of the propagation synchronization community. Perform resource domain occupancy process backtracking on the resource domain of each propagation synchronization community to extract the process identifiers of any resource occupied in the community processor core set or mapped memory page set, thus forming the associated process set of the propagation synchronization community.

[0125] In this embodiment, for each propagation synchronization community Comm, the processor core numbers associated with all occupied propagation convergence core nodes X within the community are summarized to obtain the community processor core set Ccom. Ccom is combined with the mapped memory page set Pmap obtained in step S540 to form the resource domain Rcom=(Ccom, Pmap) of the propagation synchronization community Comm. Through the operating system kernel interface, the process identifiers of any processor core or any memory page currently using Rcom are queried to form the associated process set Qcom of the propagation synchronization community Comm.

[0126] Step S560: Perform cross-process flip time-series overlay analysis on the occupancy mark flip event sequence and the active mark flip event sequence of all processes in the associated process set of each propagation synchronization community, extract the overlap distribution pattern of cross-process flip events on the time axis, detect process pairs with periodic overlap of flip events based on the overlap distribution pattern of cross-process flip events on the time axis, mark the above process pairs as flip synchronization process pairs, and extract the flip overlap period length of the flip synchronization process pairs.

[0127] In this embodiment, for each process in the associated process set Qcom of each propagation synchronization community Comm, the time point sequence of occupied marker flip events and the time point sequence of active marker flip events on the time axis are extracted for each process. These two types of time point sequences are then merged into a comprehensive flip time point sequence for each process. For any two different processes in Qcom, the degree of overlap between their flip time point sequences is calculated. The time axis is divided into multiple consecutive time windows of equal length, and it is counted whether flip events occur for both processes within each time window. The overlap frequency of the flip events between the two processes is calculated, i.e., the proportion of overlapping windows to the total number of windows. When the overlap frequency exceeds a preset threshold, the two processes are marked as a flip synchronization process pair. For each flip synchronization process pair, the starting time point sequence of the overlapping windows is extracted, the interval between the starting time points of adjacent overlapping windows is calculated, and the median of these intervals is taken as the flip overlap period length Lcyc of the flip synchronization process pair.

[0128] Step S570: Retrieve process affinity mask adjustment parameters that match the flip overlap cycle length from the preset process affinity adjustment strategy template library.

[0129] In this embodiment, a process affinity adjustment strategy template library is pre-constructed. Each template contains a flip overlap period length range and a process affinity mask adjustment parameter Maf. The process affinity mask adjustment parameter Maf is a bit vector indicating which processor cores the processes in the flip synchronization process pair should be bound to. For each flip synchronization process pair, its flip overlap period length Lcyc is matched with the period length range in the template library, and the corresponding process affinity mask adjustment parameter Maf is extracted.

[0130] Step S580: Bind the process identifier of the flip synchronization process pair, the processor core identifier currently occupied by the flip synchronization process pair, and the process affinity mask adjustment parameters to generate a process affinity reconfiguration instruction for the flip synchronization process pair, and attach the process affinity reconfiguration instruction to the resource jitter suppression instruction.

[0131] In this embodiment, for each flipped synchronization process pair, a process affinity reconfiguration instruction Iaff is generated. This instruction contains three fields: the process identifiers pid1 and pid2 of the flipped synchronization process pair, the processor core identifiers currently occupied by these two processes, and the process affinity mask adjustment parameter Maf. The process affinity reconfiguration instruction Iaff is appended to the resource jitter suppression instruction Ins generated in step S157. Upon receiving Iaff, the operating system scheduler adjusts the processor core affinity binding strategy of the processes in the flipped synchronization process pair according to Maf.

[0132] Step S610: In the processor core occupancy mark propagation path network, extract the flip interval time series of the occupancy mark flipping event sequence of each occupancy mark propagation converging core node, and perform trend fitting on the flip interval time series to obtain the flip interval time trend line of each occupancy mark propagation converging core node. Extract the slope parameter of the flip interval time trend line, and mark the occupancy mark propagation converging core node with a positive slope parameter and a slope absolute value exceeding a preset slope threshold as an interval expansion type converging core node, and mark the occupancy mark propagation converging core node with a negative slope parameter and a slope absolute value exceeding a preset slope threshold as an interval contraction type converging core node.

[0133] In this embodiment, each occupancy mark propagation converging core node X in the processor core occupancy mark propagation path network Gcpu is traversed. The time interval sequence Ix between adjacent flip events is extracted from the occupancy mark flip event sequence of node X. Linear regression is performed on this time interval sequence Ix to obtain a trend line showing the time interval changing over time, with a slope of Kx. A slope threshold Kth is set. When Kx > Kth, the occupancy mark propagation converging core node X is marked as an interval expansion type converging core node Xexp. When Kx < -Kth, the occupancy mark propagation converging core node X is marked as an interval contraction type converging core node Xcon.

[0134] Step S620: In the processor memory tag propagation intersection association graph, extract the active tag propagation intersection core nodes that have cross-resource intersection core edges with the interval expansion intersection core nodes as the first type of memory-side association nodes, and extract the active tag propagation intersection core nodes that have cross-resource intersection core edges with the interval contraction intersection core nodes as the second type of memory-side association nodes.

[0135] In this embodiment, for each interval-expanding convergent core node Xexp, in the processor memory tag propagation convergent association graph G4, all memory-side convergent core nodes Y that have cross-resource convergence corresponding edges with Xexp are identified, and these memory-side convergent core nodes Y are designated as first-type memory-side associated nodes Yexp. For each interval-shrinking convergent core node Xcon, in the processor memory tag propagation convergent association graph G4, all memory-side convergent core nodes Y that have cross-resource convergence corresponding edges with Xcon are identified, and these memory-side convergent core nodes Y are designated as second-type memory-side associated nodes Ycon.

[0136] Step S630: Trace the memory page identifiers covered by the long-range dependency paths of active label propagation associated with the first type of memory-side associated nodes in the memory page active label propagation path network to obtain the expanded associated memory page set, and trace the memory page identifiers covered by the long-range dependency paths of active label propagation associated with the second type of memory-side associated nodes to obtain the contracted associated memory page set.

[0137] In this embodiment, for each first-type memory-side associated node Yexp, in the memory page active label propagation path network Gmem, all active label propagation long-range dependency paths E1 passing through Yexp are identified. The memory page numbers covered by these active label propagation long-range dependency paths E1 are extracted, and the memory page numbers corresponding to all Yexp are deduplicated and added to the expanded associated memory page set Pexp. For each second-type memory-side associated node Ycon, in the memory page active label propagation path network Gmem, all active label propagation long-range dependency paths E1 passing through Ycon are identified. The memory page numbers covered by these active label propagation long-range dependency paths E1 are extracted, and the memory page numbers corresponding to all Ycon are deduplicated and added to the shrunken associated memory page set Pcon.

[0138] Step S640: Perform trend fitting on the active label flipping interval time series of each memory page in the expanded associated memory page set, extract the slope parameter of the active label flipping interval time trend line, and mark the memory pages with positive slope parameters and absolute slope values ​​exceeding the preset slope threshold as synchronously expanded memory pages.

[0139] In this embodiment, for each memory page p in the expanded associated memory page set Pexp, the time interval sequence Ip between adjacent flip events is extracted from the active marked flip event sequence of memory page p. A linear regression is performed on this time interval sequence Ip to obtain a trend line of time interval variation over time, with a slope of Kp. When Kp > Kth, the memory page p is marked as a synchronously expanded memory page.

[0140] Step S650: Perform trend fitting on the active label flipping interval time series of each memory page in the shrinking associated memory page set, extract the slope parameter of the active label flipping interval time trend line, and mark the memory pages with negative slope parameters and absolute slope values ​​exceeding the preset slope threshold as synchronously shrinking memory pages.

[0141] In this embodiment, for each memory page p in the set of shrinking associated memory pages Pcon, the time interval sequence Ip between adjacent flip events is extracted from the active marked flip event sequence of memory page p. A linear regression is performed on this time interval sequence Ip to obtain a trend line of time interval variation over time, with a slope of Kp. When Kp < -Kth, the memory page p is marked as a synchronously shrinking memory page.

[0142] Step S660: Combine the processor core identifier associated with the interval expanding converged core node and the memory page identifier of the synchronous expanding memory page into an expanding resource coupling domain, and combine the processor core identifier associated with the interval shrinking converged core node and the memory page identifier of the synchronous shrinking memory page into a shrinking resource coupling domain.

[0143] In this embodiment, for each interval-expanding convergent core node Xexp, the processor core number associated with node Xexp is extracted, and this processor core number is combined with the number of the synchronously expanding memory page obtained in step S640 to form an expanding resource coupling domain Rexp. For each interval-shrinking convergent core node Xcon, the processor core number associated with node Xcon is extracted, and this processor core number is combined with the number of the synchronously shrinking memory page obtained in step S650 to form a shrinking resource coupling domain Rcon.

[0144] Step S670: Obtain the set of expanding process identifiers currently occupying the expanding resource coupling domain, and backtrack the distribution of processor core occupancy time and memory page resident time of each process in the expanding process identifier set to extract the median of process resource occupancy time. Obtain the set of shrinking process identifiers currently occupying the shrinking resource coupling domain, and backtrack the distribution of processor core occupancy time and memory page resident time of each process in the shrinking process identifier set to extract the median of process resource occupancy time.

[0145] In this embodiment, the process identifiers currently using any processor core or memory page in the extended resource coupling domain Rexp are queried through the operating system kernel interface, forming an extended process identifier set Qexp. For each process identifier pid in Qexp, the process's time spent on processor cores and its residence time on memory pages are traced back from the original collected data, and the median of the time spent on processor cores and the median of the residence time are taken, denoted as Texp(pid). The process identifiers currently using any processor core or memory page in the contracted resource coupling domain Rcon are queried through the operating system kernel interface, forming a contracted process identifier set Qcon. For each process identifier pid in Qcon, the process's time spent on processor cores and its residence time on memory pages are traced back from the original collected data, and the median of the time spent on processor cores and the median of the residence time are taken, denoted as Tcon(pid).

[0146] Step S680: Based on the median process resource usage time of the expansion process identifier set and the median process resource usage time of the contraction process identifier set, retrieve the expansion process resource quota reduction parameter and the contraction process resource quota increase parameter from the preset resource quota adjustment template library, respectively. Bind the expansion process resource quota reduction parameter with the expansion process identifier set to generate an expansion process quota compression instruction, bind the contraction process resource quota increase parameter with the contraction process identifier set to generate a contraction process quota expansion instruction, and attach the expansion process quota compression instruction and the contraction process quota expansion instruction to the resource jitter suppression instruction.

[0147] In this embodiment, a resource quota adjustment template library is pre-built, which includes two sub-libraries: a reduction parameter sub-library and an increase parameter sub-library. Each template in the reduction parameter sub-library contains an occupied duration range and a resource quota reduction parameter Red, which represents the percentage of processor time quota to be reduced. Each template in the increase parameter sub-library contains an occupied duration range and a resource quota increase parameter Inc, which represents the percentage of processor time quota to be increased. For the expanding process identifier set Qexp, the median Mexp of Texp(pid) for all processes in Qexp is calculated. Mexp is matched with the occupied duration range in the reduction parameter sub-library, and the corresponding resource quota reduction parameter Red is extracted. Red is bound to Qexp to generate the expanding process quota compression instruction Icut. For the shrinking process identifier set Qcon, the median Mcon of Tcon(pid) for all processes in Qcon is calculated. Mcon is matched with the occupied duration range in the increase parameter sub-library, and the corresponding resource quota increase parameter Inc is extracted. Inc is bound to Qcon to generate the shrinking process quota expansion instruction Iadd. Append Icut and Iadd after the resource jitter suppression instruction Ins generated in step S157.

[0148] Step S710: In the processor core occupancy mark propagation path network, extract the mark propagation node sequence that all occupancy mark propagation long-range dependency paths pass through, and label the mark propagation node sequence of each occupancy mark propagation long-range dependency path with node type, and label the mark propagation nodes located at both ends of the cross-core propagation connection edge as cross-core boundary nodes.

[0149] In this embodiment, each long-range dependency path D1 of occupancy mark propagation in the processor core occupancy mark propagation path network Gcpu is traversed, and the sequence of mark propagation nodes traversed by the path is extracted. For each mark propagation node in the sequence, it is checked whether the node is connected to a cross-core propagation connection edge. If the node is the endpoint of a cross-core propagation connection edge, the node is marked as a cross-core boundary node B.

[0150] Step S720: Extract the predecessor and successor label propagation nodes in the long-range dependency path of the occupied label propagation for each cross-core boundary node, and calculate the ratio of the flip time interval from the predecessor label propagation node to the cross-core boundary node to the flip time interval from the successor label propagation node to the cross-core boundary node, as the propagation flux ratio of the cross-core boundary node.

[0151] In this embodiment, for each cross-core boundary node B, on the occupied flag propagation long-range dependency path D1 where B is located, the predecessor flag propagation node Bprev and the successor flag propagation node Bnext of B are found. The toggle time interval Tprev from Bprev to B is calculated as Tprev=T(B)-T(Bprev), and the toggle time interval Tnext from B to Bnext is calculated as Tnext=T(Bnext)-T(B). The propagation flux ratio Rflux=Tprev / Tnext is calculated. A ratio greater than 1 indicates that the inflow time is longer than the outflow time, and a ratio less than 1 indicates that the inflow time is shorter than the outflow time.

[0152] Step S730: Mark cross-core boundary nodes whose propagation flux ratio exceeds the preset flux ratio interval as propagation flux abnormal nodes, and extract the processor core identifier corresponding to the occupied flag propagation backbone path where the propagation flux abnormal node is located in the processor core occupied flag propagation path network, to serve as a flux abnormal processor core.

[0153] In this embodiment, a normal flux ratio interval [Llow, Lhigh] is set, where Llow is less than 1 and Lhigh is greater than 1. For each cross-core boundary node B, when its propagation flux ratio Rflux<Llow or Rflux>Lhigh, the node B is marked as a propagation flux abnormal node Berr. For each propagation flux abnormal node Berr, the occupied flag propagation backbone path P(c) where Berr is located is found in the processor core occupied flag propagation path network Gcpu, and the processor core number c corresponding to this backbone path is extracted to serve as the flux abnormal processor core Cerr.

[0154] Step S740: In the memory page active flag propagation path network, extract the active flag propagation intersection core node that has a cross-resource intersection check edge with the propagation flux abnormal node in the processor-memory flag propagation intersection association graph, and extract the memory page identifier covered by the active flag propagation long-range dependency path associated with the active flag propagation intersection core node, to serve as a flux abnormality associated memory page.

[0155] In this embodiment, for each propagation flux abnormal node Berr, all memory-side intersection core nodes Y that have a cross-resource intersection corresponding edge with Berr are found in the processor-memory flag propagation intersection association graph G4. For each memory-side intersection core node Y, all active flag propagation long-range dependency paths E1 passing through Y are found in the memory page active flag propagation path network Gmem, the memory page numbers covered by these paths are extracted, and the above memory page numbers are deduplicated to serve as the flux abnormality associated memory page Perr.

[0156] Step S750: Combine the throughput anomaly processor core and the throughput anomaly associated memory page into a throughput anomaly resource coupling domain, obtain the process identifier set currently occupying the throughput anomaly resource coupling domain, and perform a flip burst analysis on the occupancy mark flip event sequence of each process in the process identifier set, extract the flip burst index, extract the process with the flip burst index exceeding the preset burst threshold as the burst flip process, and locate the burst flip period of the occupancy mark flip event sequence of the burst flip process, and extract the start time point and end time point of the burst flip period.

[0157] In this embodiment, Cerr and Perr are combined into a flux anomaly resource coupling domain Rerr=(Cerr, Perr). The process IDs currently occupying any resource in Rerr are queried through the operating system kernel interface, forming a process set Qerr. For each process pid in Qerr, the burst index Burst is calculated from its occupation mark flip event sequence: Burst = maximum flip density / average flip density, where flip density is the number of flips per unit time. A burst threshold Bth is set. When Burst > Bth, the process is marked as a burst flip process pid_burst. For each burst flip process pid_burst, the time interval in its occupation mark flip event sequence where the flip density exceeds twice the average density is located, and the start time Ts and end time Te of this time interval are taken.

[0158] Step S760: Calculate the time span length of the sudden flip period based on the start and end times of the sudden flip period, and retrieve the process preemption time slice granularity parameter that matches the time span length of the sudden flip period from the preset process preemption granularity adjustment strategy library.

[0159] In this embodiment, the time span length Lspan = Te - Ts of the sudden flip-off period is calculated. A process preemption granularity adjustment strategy library is pre-built, where each template contains a time span length interval and a process preemption time slice granularity parameter Gran. The process preemption time slice granularity parameter Gran represents the length of continuous running time slice allocated to the process by the scheduler. Lspan is matched with the interval in the template library, and the corresponding process preemption time slice granularity parameter Gran is retrieved.

[0160] Step S770: Bind the process identifier of the sudden flip process, the resource identifier of the throughput anomaly resource coupling domain, and the process preemption time slice granularity parameter to generate a preemption granularity reconfiguration instruction for the sudden flip process, and attach the preemption granularity reconfiguration instruction to the resource jitter suppression instruction.

[0161] In this embodiment, a preemption granularity reconfiguration instruction Igran is generated for each burst flip process pid_burst. The preemption granularity reconfiguration instruction includes three fields: the process identifier pid_burst, the identifier of the resource coupling domain Rerr, and the preemption time slice granularity parameter Gran. This preemption granularity reconfiguration instruction is appended after the resource jitter suppression instruction Ins generated in step S157.

[0162] Step S810: In the processor core occupancy mark propagation path network, count the flip event density time-series distribution of the occupancy mark flip event sequence of each occupancy mark propagation junction core node, generate a flip event density distribution curve with the acquisition period as the time unit, perform peak detection on the flip event density distribution curve, extract the peak height parameter and peak width parameter of the density peak in the flip event density distribution curve, and mark a density peak whose peak height parameter exceeds the preset peak height threshold and whose peak width parameter is lower than the preset peak width threshold as a sharp density peak.

[0163] In this embodiment, for each occupancy mark propagation junction core node X in the processor core occupancy mark propagation path network Gcpu, histogram statistics are performed on the occupancy mark flip event sequence of this node by acquisition period, and the number of flip events in each time window is the flip event density, so as to obtain the flip event density distribution curve Fdens(t). Peak detection is performed on this curve to extract the peak height value Hpeak and peak width value Wpeak of each peak. A peak height threshold Hth and a peak width threshold Wth are set. When Hpeak>Hth and Wpeak<Wth, this density peak is marked as a sharp density peak, and the node X corresponding to this peak is recorded as a sharp flip junction core node Xsharp.

[0164] Step S820: Extract the occupancy mark propagation junction core node corresponding to the sharp density peak as a sharp flip junction core node, and extract, in the processor memory mark propagation junction association graph, an active mark propagation junction core node that has a cross-resource junction pair edge with the sharp flip junction core node as a sharp flip memory-side associated node.

[0165] In this embodiment, for each sharp flip junction core node Xsharp, in the processor memory mark propagation junction association graph G4, all memory-side junction core nodes Y that have cross-resource junction corresponding edges with Xsharp are found, and the above-mentioned memory-side junction core nodes Y are taken as sharp flip memory-side associated nodes Ysharp.

[0166] Step S830: Trace the memory page identifiers covered by the long-range dependency path of the active mark propagation in the memory page active mark propagation path network associated with the sharp flip memory-side associated node to obtain the sharp flip associated memory page set. Perform time-series distribution statistics of flip event density for the active mark flip event sequence of each memory page in the sharp flip associated memory page set to generate a memory page flip event density distribution curve. Perform peak detection on the memory page flip event density distribution curve and extract the memory page density peak that overlaps with the sharp density peak on the time axis.

[0167] In this embodiment, for each sharp flip memory-side associated node Ysharp, all long-range dependent paths E1 of active mark propagation passing through Ysharp are identified in the memory page active mark propagation path network Gmem. The memory page numbers covered by these paths are extracted to obtain the sharp flip associated memory page set Psharp. For each memory page p in Psharp, its flip event density distribution curve is statistically analyzed, and all peaks on the curve are detected. The memory page density peaks on the time axis that overlap with the time windows of the sharp density peaks detected in step S810 are identified, and the memory pages p corresponding to these overlapping peaks are recorded.

[0168] Step S840: Combine the processor core identifier associated with the sharp flip converging core node and the memory page identifier with overlapping memory page density peaks into a sharp flip resource coupling domain, and obtain the set of process identifiers currently occupying the sharp flip resource coupling domain. Compare the flip event waveform phase of the occupying mark flip event sequence and the active mark flip event sequence of each process in the process identifier set, and extract the phase difference between the processor core flip event waveform and the memory page flip event waveform.

[0169] In this embodiment, the processor core number associated with Xsharp and the memory page number with overlapping peaks are combined into a sharp flip resource coupling domain Rsharp. The process IDs currently occupying any resource in Rsharp are queried through the operating system kernel interface, forming a process set Qsharp. For each process pid in Qsharp, its flip event sequence on the processor core and its flip event sequence on the memory page are extracted. These two sequences are treated as periodic waveforms, and the phase difference Δφ between the two waveforms is calculated, representing the amount of time by which the processor core flip event leads or lags the memory page flip event.

[0170] Step S850: Based on the phase difference between the processor core flip event waveform and the memory page flip event waveform, determine the process wake-up time adjustment amount required to align or optimize the phase difference, and retrieve the process wake-up time offset corresponding to the process wake-up time adjustment amount from the preset process wake-up timing adjustment strategy library.

[0171] In this embodiment, based on the phase difference Δφ, the required process wake-up time adjustment amount Adj = -Δφ is calculated, which is the amount by which the wake-up time needs to be adjusted forward or backward. A process wake-up timing adjustment strategy library is pre-built, where each template contains an adjustment range and a process wake-up time offset Offset. Adj is matched with the range in the template library, and the corresponding process wake-up time offset Offset is retrieved.

[0172] Step S860: Bind the process identifier of each process in the process identifier set, the process wake-up time offset of the corresponding process, and the resource identifier of the sharp flip resource coupling domain, generate a process wake-up timing reordering instruction for the sharp flip resource coupling domain, and attach the process wake-up timing reordering instruction to the resource jitter suppression instruction.

[0173] In this embodiment, for each process ID (PID) in Qsharp, a process wake-up timing reordering instruction (Iwake) is generated. This instruction contains three fields: process ID (PID), wake-up time offset (Offset), and the identifier of the resource coupling domain (Rsharp). This wake-up timing reordering instruction is appended to the resource jitter suppression instruction (Ins) generated in step S157.

[0174] Step S910: In the processor core occupancy mark propagation path network, extract the propagation path length of each branch path in the occupancy mark propagation bifurcation structure radiated by each occupancy mark propagation converging core node, and calculate the length dispersion of the propagation path length of each branch path. Extract the occupancy mark propagation converging core nodes whose length dispersion exceeds the preset length dispersion threshold as asymmetric propagation converging core nodes, and extract the processor core identifiers covered by the long-range dependency path of occupancy mark propagation associated with the asymmetric propagation converging core node in the processor core occupancy mark propagation path network to form an asymmetric propagation processor core set.

[0175] In this embodiment, each occupancy mark propagation convergence core node X in the GCPU is traversed, and the length Lbranch of all branch paths radiating from it is obtained. The dispersion Var of these branch path lengths is calculated as standard deviation divided by mean. A dispersion threshold Var_th is set. When Var > Var_th, the node X is marked as an asymmetric propagation convergence core node Xasym. For each Xasym, all occupancy mark propagation long-range dependency paths D1 passing through Xasym are found, and the processor core numbers covered by these paths are extracted to form the asymmetric propagation processor core set Cathy.

[0176] Step S920: Perform occupation mark duration distribution statistics on the occupation mark time series of each processor core in the asymmetric propagation processor core set, extract the median of the occupation mark duration, and mark a processor core whose median of the occupation mark duration exceeds the preset duration median interval as an abnormal resident processor core.

[0177] In this embodiment, for each processor core c in Casym, all duration sequences of consecutive occupation marks marked as 1 are extracted from its occupation mark time series, and the median Mc of this sequence is calculated. A duration median interval [Lmed, Hmed] is set. When Mc<Lmed or Mc>Hmed, the processor core c is marked as an abnormal resident processor core Cres.

[0178] Step S930: In the memory page active mark propagation path network, extract active mark propagation junction core nodes that have cross-resource junction pair edges with the asymmetric propagation junction core nodes in the processor memory mark propagation junction association graph, and trace the memory page identifiers covered by the active mark propagation long-range dependency paths associated with the active mark propagation junction core nodes, so as to form an asymmetric propagation memory page set.

[0179] In this embodiment, for each asymmetric propagation junction core node Xasym, all memory-side junction core nodes Yasym that have cross-resource junction corresponding edges with Xasym are found in G4. For each Yasym, all active mark propagation long-range dependency paths E1 passing through Yasym are found in Gmem, and the memory page numbers covered by these paths are extracted to form the asymmetric propagation memory page set Pasym.

[0180] Step S940: Perform active mark duration distribution statistics on the active mark time series of each memory page in the asymmetric propagation memory page set, extract the median of the active mark duration, and mark a memory page whose median of the active mark duration exceeds the preset duration median interval as an abnormal resident memory page.

[0181] In this embodiment, for each memory page p in Pasym, all duration sequences of consecutive active marks marked as 1 are extracted from its active mark time series, and the median Mp of this sequence is calculated. When Mp<Lmed or Mp>Hmed, the memory page p is marked as an abnormal resident memory page Pres.

[0182] Step S950: combining the processor core identifier of the abnormally resident processor core and the memory page identifier of the abnormally resident memory page into an abnormally resident resource coupling domain, acquiring the process identifier set that currently occupies the abnormally resident resource coupling domain, marking the processes in the process identifier set as abnormally resident processes, performing flip event causality analysis on the processor core occupancy flag flip event sequence and the memory page activity flag flip event sequence of each abnormally resident process, and extracting the conditional flip probability between the processor core occupancy flag flip event and the memory page activity flag flip event.

[0183] In this embodiment, Cres and Pres are combined into the abnormally resident resource coupling domain Rres. Process identifiers that currently occupy any resource in Rres are queried to form a process set Qres, and the processes in Qres are marked as abnormally resident processes. For each process pid in Qres, the conditional flip probability Pcond=P(memory page flip | processor core flip) is calculated, that is, the conditional probability that a memory page flip occurs within a time window after the processor core flip event occurs.

[0184] Step S960: According to the resource access coupling feature reflected by the conditional flip probability between the processor core occupancy flag flip event and the memory page activity flag flip event, call the decoupling operation parameter matching the resource access coupling feature from a preset process resource decoupling policy template library.

[0185] In this embodiment, the resource access coupling feature is determined according to the value of the conditional flip probability Pcond: Pcond>0.7 is strong coupling, 0.3<Pcond≤0.7 is medium coupling, and Pcond≤0.3 is weak coupling. A process resource decoupling policy template library is pre-constructed, and each template therein includes one coupling feature and one decoupling operation parameter Dpar. The decoupling operation parameter Dpar includes a processor core decoupling mask and a memory page decoupling range. The coupling feature is matched with the template, and the corresponding decoupling operation parameter Dpar is retrieved.

[0186] Step S970: Binding the process identifier of each abnormally resident process, the resource identifier of the abnormally resident resource coupling domain and the decoupling operation parameter, generating a resource decoupling instruction for the abnormally resident process, and appending the resource decoupling instruction to the resource jitter suppression instruction.

[0187] In this embodiment, for each abnormally resident process pid, a resource decoupling instruction Idec is generated. The resource decoupling instruction includes three fields: the process identifier pid, the identifier of the resource coupling domain Rres, and the decoupling operation parameter Dpar. The resource decoupling instruction is appended after the resource jitter suppression instruction Ins generated in step S157.

[0188] In one exemplary embodiment, an AI-based device behavior data analysis system is provided, which may be a terminal, server, etc., and its internal structure diagram may be as follows: Figure 3 As shown, the system includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, near-field communication, or other technologies. When the computer program is executed by the processor, it implements an AI-based device behavior data analysis method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device can be a touch layer covering the display screen, or a button, trackball, or touchpad set on the shell of an AI-based device behavior data analysis system, or an external keyboard, touchpad, or mouse, etc.

[0189] It should be noted that, in order to simplify the description of the present invention and thus help to understand one or more embodiments of the invention, multiple features may sometimes be grouped into one embodiment, drawing or description thereof in the foregoing description of the embodiments of the present invention.

Claims

1. A device behavior data analysis method based on AI, characterized in that, The method includes: The processor core occupancy marker sequence and memory page active marker sequence of the computer device under monitoring are obtained during a continuous acquisition period. The processor core occupancy marker sequence records the binary marker bit of the occupancy status of each processor core at each acquisition time point. The memory page active marker sequence records the binary marker bit of the active status of each memory page at each acquisition time point. The processor core occupancy mark propagation path is reconstructed for the processor core occupancy mark propagation path network, and the memory page active mark propagation path is reconstructed for the memory page active mark propagation path network. The intersection clustering pattern of the marker propagation paths in the processor core occupied marker propagation path network and the intersection clustering pattern of the marker propagation paths in the memory page active marker propagation path network are mapped across resources to generate a processor memory marker propagation intersection association graph. Based on the splitting timing characteristics of the clusters in the processor memory mark propagation intersection graph, resource jitter suppression instructions for the target process set are generated.

2. The AI-based device behavior data analysis method according to claim 1, characterized in that, The step of reconstructing the occupancy mark propagation path of the processor core occupancy mark sequence to generate a processor core occupancy mark propagation path network includes: Arrange the binary flag bits of the occupancy status of each processor core in the processor core occupancy flag sequence according to the acquisition time order to generate the occupancy flag time sequence of each processor core, and perform bit-by-bit XOR operation on the binary flag bits of the occupancy status of adjacent acquisition time points in the occupancy flag time sequence of each processor core to obtain the occupancy flag flip event sequence of each processor core. Based on the occurrence time of the flip events in the occupancy mark flip event sequence of each processor core, each occupancy mark flip event is taken as a mark propagation node, and a time-series propagation connection edge is established between two mark propagation nodes that are temporally adjacent on the same processor core to generate the occupancy mark propagation backbone path for each processor core. Extract the pair of marker propagation nodes that occur at the same or adjacent acquisition time points in the main path of marker propagation of different processor cores, and establish cross-core propagation connection edges between the marker propagation node pairs to obtain cross-core marker propagation association relationships; The occupancy mark propagation backbone path of all processor cores and all cross-core propagation connection edges are fused into a graph structure to generate an initial graph of processor core occupancy mark propagation with mark propagation nodes as vertices and time-series propagation connection edges and cross-core propagation connection edges as edge sets. In the initial graph of processor core occupancy mark propagation, a backtracking search is performed on the continuous propagation path between any two mark propagation nodes, which is composed of alternating time-sequential propagation connection edges and cross-core propagation connection edges. The continuous propagation path with a length exceeding a preset step threshold is extracted as the long-range dependency path of occupancy mark propagation. Calculate the time span of the occurrence time of the occupancy mark flipping event of all mark propagation nodes on each occupancy mark propagation long-range dependency path, and determine the propagation synchronization strength level of the occupancy mark propagation long-range dependency path based on the time span to obtain the occupancy mark propagation long-range dependency path with the propagation synchronization strength level. Aggregate the paths with common mark propagation nodes in all occupancy mark propagation long-range dependency paths to construct occupancy mark propagation path clusters, and extract the common intersection mark propagation node of all paths in each occupancy mark propagation path cluster as the occupancy mark propagation intersection kernel node. Using the occupancy mark propagation convergence core node as a shared propagation hub, the paths passing through this shared propagation hub in the long-range dependency path of occupancy mark propagation are segmented and branched to generate an occupancy mark propagation branch structure radiating outward from the occupancy mark propagation convergence core node. All occupancy mark propagation convergence core nodes and the occupancy mark propagation branch structures connected to each occupancy mark propagation convergence core node are combined to generate a processor core occupancy mark propagation path network with the occupancy mark propagation convergence core as its skeleton.

3. The AI-based device behavior data analysis method according to claim 1, characterized in that, The step of reconstructing the active label propagation path of the active label sequence of memory pages to generate an active label propagation path network of memory pages includes: The active state binary flag bits of each memory page in the active flag sequence are arranged in the order of acquisition time to generate the active flag time sequence of each memory page. Then, the active state binary flag bits of adjacent acquisition time points in the active flag time sequence of each memory page are XORed bit by bit to obtain the active flag flip event sequence of each memory page. Based on the occurrence time of the flip events in the active mark flip event sequence of each memory page, each active mark flip event is used as a mark propagation node, and a temporal propagation connection edge is established between two mark propagation nodes that are temporally adjacent on the same memory page to generate the active mark propagation backbone path of each memory page; Extract the pairs of marker propagation nodes that occur at the same or adjacent collection time points in the active marker propagation backbone path of different memory pages, and establish cross-page propagation connection edges between the marker propagation node pairs to obtain the cross-page marker propagation association relationship; The active marking propagation backbone path of all memory pages and all cross-page propagation connection edges are fused into a graph structure to generate an initial graph of active marking propagation of memory pages with marking propagation nodes as vertices and time-series propagation connection edges and cross-page propagation connection edges as edge sets. In the initial graph of active mark propagation in the memory page, a backtracking search is performed on the continuous propagation path between any two mark propagation nodes, which is composed of alternating temporal propagation connection edges and cross-page propagation connection edges. The continuous propagation path with a length exceeding a preset step threshold is extracted as the long-range dependency path of active mark propagation. Calculate the time span of the active label flipping event occurrence time of all label propagation nodes on each active label propagation long-range dependency path, and determine the propagation synchronization strength level of the active label propagation long-range dependency path based on the time span to obtain the active label propagation long-range dependency path with propagation synchronization strength level. All active marker propagation long-range dependency paths with common marker propagation nodes are segmented and aggregated to construct active marker propagation path clusters. The common intersection marker propagation nodes of all paths in each active marker propagation path cluster are extracted as active marker propagation intersection kernel nodes. The active label propagation convergence core node is used as a shared propagation hub. The paths in the long-range dependency path of active label propagation that pass through the shared propagation hub are segmented and branched to generate an active label propagation branch structure radiating outward from the active label propagation convergence core node. All active label propagation convergence core nodes and the active label propagation branch structures connected to each active label propagation core node are combined to generate a memory page active label propagation path network with the active label propagation convergence core as the skeleton.

4. The AI-based device behavior data analysis method according to claim 1, characterized in that, The step of performing cross-resource mark propagation intersection mapping between the intersection and clustering patterns of mark propagation paths in the processor core occupied mark propagation path network and the intersection and clustering patterns of mark propagation paths in the memory page active mark propagation path network to generate a processor memory mark propagation intersection association graph includes: Extract all occupancy mark propagation intersection core nodes from the processor core occupancy mark propagation path network to form a processor-side intersection core node set, and extract all active mark propagation intersection core nodes from the memory page active mark propagation path network to form a memory-side core node set; Obtain the propagation direction vector sequence of all occupancy mark propagation fork structures connected to each processor-side converging core node in the processor core occupancy mark propagation path network, and obtain the propagation direction vector sequence of all active mark propagation fork structures connected to each memory-side converging core node in the memory page active mark propagation path network. For each processor-side converged core node's propagation direction vector sequence and each memory-side converged core node's propagation direction vector sequence, calculate the waveform similarity of the direction vector sequences on the time axis to obtain the propagation direction waveform matching degree between processor-memory converged core pairs. Extract processor-memory converged core pairs whose propagation direction waveform matching degree exceeds a preset waveform matching threshold, and establish cross-resource marker propagation convergence corresponding edges between the processor-memory converged core pairs to obtain cross-resource core pair matching relationships. For each pair of processor memory convergence cores with established cross-resource tag propagation convergence edges, calculate the overlap of the flip time points of the occupied tag flip time series of the processor-side convergence core node and the active tag flip time series of the memory-side convergence core node in the processor memory convergence core pair. Determine the convergence tightness level between the processor memory convergence cores based on the flip time point overlap, and obtain the cross-resource convergence core pair edge with convergence tightness level. All processor-side converged core nodes, all memory-side converged core nodes, and all cross-resource converged core edges with convergence density levels are fused into a graph to generate a cross-resource marker propagation convergence initial association graph. In the cross-resource marker propagation convergence initial association graph, cross-resource converged core edges that pass through the same processor-side converged core node and the same memory-side converged core node are aggregated to generate a cross-resource convergence aggregation domain. The convergence density level distribution pattern of all cross-resource convergence core edges in the cross-resource convergence aggregation domain is extracted. Based on the distribution pattern of the intersection density of all cross-resource intersection core edges within the cross-resource intersection convergence domain, intersection splitting trend marking is performed on each cross-resource intersection convergence domain to obtain cross-resource intersection convergence domains with splitting trend marking. All cross-resource intersection convergence domains with splitting trend marking are laid out according to their topological connection relationship in the cross-resource marking propagation intersection initial association graph to generate a processor memory marking propagation intersection association graph.

5. The AI-based device behavior data analysis method according to claim 1, characterized in that, The step of generating resource jitter suppression instructions for the target process set based on the splitting timing characteristics of the clusters of marker propagation intersections in the processor memory marker propagation intersection graph includes: In the processor memory tag propagation intersection association graph, locate all cross-resource intersection convergence domains with split trend tags, and extract the processor-side intersection core nodes and memory-side intersection core nodes contained in each cross-resource intersection convergence domain with split trend tags. For each cross-resource convergence domain with a splitting trend marker, trace the long-range dependency path of occupancy marker propagation associated with each processor-side convergence core node in the processor core occupancy marker propagation path network, and extract the processor core identifiers covered by the long-range dependency path of occupancy marker propagation. For each cross-resource convergence domain with a splitting trend marker, trace the long-range dependency path of active marker propagation associated with each memory-side convergence core node in the memory page active marker propagation path network, and extract the memory page identifiers covered by the long-range dependency path of active marker propagation. The processor core identifier and memory page identifier corresponding to each cross-resource intersection convergence domain with a splitting trend marker are combined to form the resource coupling domain corresponding to the cross-resource intersection convergence domain. The set of process identifiers currently occupying the resource coupling domain is obtained. The splitting trend marker of each cross-resource intersection convergence domain with a splitting trend marker is analyzed for splitting timing. Based on the trend of the decay of the intersection tightness level of cross-resource intersection core-to-edge in the cross-resource intersection convergence domain over time, the splitting start time point of the cross-resource intersection convergence domain is predicted. The predicted split start time point is summarized with the split start time points of all cross-resource convergence domains in the processor memory mark propagation intersection correlation graph to construct a global split timing ranking list, and the set of target cross-resource convergence domains whose split start time points fall within a preset time window is extracted. Obtain the process identifier set of the resource coupling domain corresponding to each target cross-resource intersection convergence domain set, and deduplicate and merge all process identifiers to obtain the target process set. Backtrack the processor core occupation trajectory and memory page occupation trajectory of each process in the target process set, extract the occupation mark flip frequency of the process on each processor core and the active mark flip frequency on each memory page, and generate process resource jitter features. Based on the process resource jitter characteristics, a combination of process resource constraint parameters matching the process resource jitter characteristics is retrieved from a preset resource jitter suppression strategy template library. The process resource constraint parameter combination corresponding to each process is bound and encapsulated with the process identifier to generate a resource jitter suppression instruction for the target set of processes. The process resource constraint parameter combination includes a processor core binding mask and a memory page locking range.

6. The AI-based device behavior data analysis method according to claim 1, characterized in that, The method further includes: The storage device input / output request queuing mark sequence and the network device data packet transmission / reception queuing mark sequence of the computer device to be monitored are obtained. The storage device input / output request queuing mark sequence records the binary mark bit of the request queuing length of each storage device at each collection time point. The network device data packet transmission / reception queuing mark sequence records the binary mark bit of the data packet queuing length of each network device at each collection time point. The queuing mark propagation path is reconstructed for the input / output request queuing mark sequence of the storage device to generate a queuing mark propagation path network for the storage device, and the queuing mark propagation path is reconstructed for the data packet transmission / reception queuing mark sequence of the network device to generate a queuing mark propagation path network for the network device. The intersection clustering pattern of the label propagation path in the storage device queuing label propagation path network and the intersection clustering pattern of the label propagation path in the network device queuing label propagation path network are mapped across devices to generate a storage network label propagation intersection association graph. Perform a cross-domain label propagation intersection mapping on the processor memory label propagation intersection graph and the storage network label propagation intersection graph to generate a three-dimensional label propagation intersection graph for computing resources, storage resources, and network resources. The timing synchronization of splitting in cross-domain convergence clusters in the propagation intersection graph of computing resources, storage resources, and network resources is analyzed. The synchronization splitting time window of the cross-domain convergence clusters is extracted, and a joint jitter suppression instruction chain oriented towards the global resource coupling domain is generated based on the synchronization splitting time window of the cross-domain convergence clusters.

7. The AI-based device behavior data analysis method according to claim 1, characterized in that, The method further includes: The storage device request queuing mark sequence and the network device data packet queuing mark sequence of the computer device to be monitored are obtained. The storage device request queuing mark sequence records the request queuing binary mark bit of each storage device at each collection time point. The network device data packet queuing mark sequence records the data packet queuing binary mark bit of each network device at each collection time point. The queuing mark propagation path of the storage device request queuing mark sequence is reconstructed to generate a storage device queuing mark propagation path network, and the queuing mark propagation path of the network device data packet queuing mark sequence is reconstructed to generate a network device queuing mark propagation path network. The intersection clustering pattern of the label propagation path in the storage device queuing label propagation path network and the intersection clustering pattern of the label propagation path in the network device queuing label propagation path network are mapped across devices to generate a storage network label propagation intersection association graph. The processor memory label propagation intersection graph and the storage network label propagation intersection graph are subjected to cross-domain label propagation intersection secondary mapping to generate a computing and storage network three-dimensional label propagation intersection graph. The splitting timing synchronization of the cross-domain intersection clusters in the computing and storage network three-dimensional label propagation intersection graph is analyzed, and the synchronous splitting time window of the cross-domain intersection clusters is extracted. Based on the cross-domain convergence cluster synchronous splitting time window, locate the occupancy mark propagation convergence core node associated with the cross-domain convergence cluster in the processor core occupancy mark propagation path network, and extract the flip interval time distribution pattern in the occupancy mark flip event sequence of the occupancy mark propagation convergence core node; According to the flip interval time distribution pattern, the scheduling clock phase offset that matches the flip interval time distribution pattern is retrieved from the preset process scheduling clock adjustment strategy library. The scheduling clock phase offset is used to adjust the scheduling clock phase of the process scheduler for the target process set. The scheduling clock phase offset, the cross-domain convergence cluster synchronization split time window, and the target process set are bound together to generate a scheduling clock phase offset instruction for the global resource coupling domain, and the scheduling clock phase offset instruction is appended to the resource jitter suppression instruction to form a joint suppression instruction.

8. The AI-based device behavior data analysis method according to claim 1, characterized in that, The method further includes: In the processor core occupancy mark propagation path network, the propagation direction vectors of each branch path in the occupancy mark propagation bifurcation structure radiated by each occupancy mark propagation converging core node are extracted, and the directional dispersion of the propagation direction vectors of each branch path is calculated. Occupancy mark propagation converging core nodes with directional dispersion below a preset directional dispersion threshold are extracted as directional propagation converging core nodes. In the processor core occupancy mark propagation path network, the set of processor core identifiers covered by the long-range dependency path of occupancy mark propagation associated with the directional propagation converging core node is extracted. In the memory page active marking propagation path network, extract the active marking propagation intersection core node that has a cross-resource intersection core edge with the directional propagation intersection core node in the processor memory marking propagation intersection association graph, and extract the set of memory page identifiers covered by the active marking propagation long-range dependency path associated with the active marking propagation intersection core node; The processor core identifier set and the memory page identifier set are combined into a directed propagation resource coupling domain, and the directed propagation process identifier set currently occupying the directed propagation resource coupling domain is obtained; Perform a flip frequency stability analysis on the occupancy mark flip event sequence of each process in the directed propagation process identifier set, extract the fluctuation amplitude of the occupancy mark flip frequency of the process on each processor core, and mark the process with the fluctuation amplitude below the preset fluctuation amplitude threshold as a steady-state jitter process; The memory page access trajectory of the steady-state jittering process within the directed propagation resource coupling domain is backtracked, and the median flip interval time of the active marked flip event sequence of the steady-state jittering process on each memory page is extracted; Based on the median flip interval time, the topology location of the memory page migration target node that matches the median flip interval time is retrieved from the preset memory page migration strategy template library. The topology location of the memory page migration target node is used to indicate the migration target of the memory page between memory nodes. The process identifier of the steady-state jittering process, the set of memory page identifiers of the directed propagation resource coupling domain, and the topological location of the target node for memory page migration are bound together to generate a memory page redistribution instruction for the steady-state jittering process, and the memory page redistribution instruction is appended to the resource jitter suppression instruction.

9. An AI-based device behavior data analysis system, characterized in that, include: processor; A machine-readable storage medium for storing machine-executable instructions of the processor; The processor is configured to execute the AI-based device behavior data analysis method of any one of claims 1 to 8 by executing the machine-executable instructions.

10. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-executable instructions, the processor reads the machine-executable instructions from the machine-readable storage medium, and the processor executes the machine-executable instructions, causing the AI-based device behavior data analysis system to perform the AI-based device behavior data analysis method as described in any one of claims 1 to 8.

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