Thermal frequency adjustment method and thermal frequency adjustment system

Abstract

The application provides a heat-aware frequency adjustment method and a heat-aware frequency adjustment system, which can be applied to the technical field of integrated circuit chip thermal management. The method is applied to a computing platform, the computing platform comprising a host processor and an acceleration chip, the acceleration chip internally being provided with an on-chip intelligent control module, a temperature aggregation unit and a dynamic voltage frequency adjustment control interface, and comprising the following steps: reading a service load feature from a shared state buffer area and reading a central junction temperature from the temperature aggregation unit; constructing a cross-layer state vector according to the service load feature and the central junction temperature; inputting the cross-layer state vector into a decision model, scoring each frequency action in a frequency action set, and selecting a target frequency from the frequency action set according to the scoring result; and writing a control value corresponding to the target frequency to the dynamic voltage frequency adjustment control interface through an out-of-band control link interface, so as to drive a clock unit and / or a voltage adjustment unit to perform frequency switching.

Description

Technical Field

[0001] This application relates to the field of integrated circuit chip thermal management technology, and more specifically to a thermal sensing frequency adjustment method and a thermal sensing frequency adjustment system. Background Technology

[0002] 3D stacking technology vertically stacks multiple layers of Dynamic Random Access Memory (DRAM) on top of logic chips, significantly improving memory bandwidth and density. However, this also results in the underlying logic chips being covered by memory, losing their direct heat dissipation surface and easily forming a "heat accumulation effect" in the central area. Existing dynamic voltage and frequency regulation technologies typically deploy frequency decisions on the host processor side, requiring status acquisition and control command issuance via the operating system, drivers, and Peripheral Component Interconnect Express (PCIe) link.

[0003] However, in high-load scenarios such as large-model, long-context inference, the host-side link is prone to congestion and jitter, causing frequency control to fail to respond promptly to rapid temperature rises within the chip. Furthermore, since the sampling period for host-side service load characteristics is typically in the millisecond range, while the sampling period for chip thermal status is in the microsecond range, the asynchronous sampling frequencies and update times can easily lead to asynchronous inputs where "service status lags behind, temperature status is real-time," resulting in a mismatch between frequency modulation decisions and actual thermal conditions. Therefore, a method is urgently needed to improve the thermal safety and frequency regulation stability of 3D stacked chips under dynamic inference loads. Summary of the Invention

[0004] In view of the above problems, this application provides a thermal sensing frequency regulation method and thermal sensing frequency regulation system to improve the thermal safety and frequency regulation stability of three-dimensional stacked chips under dynamic inference load.

[0005] According to the first aspect of this application, a thermal sensing frequency adjustment method is provided. The method is applied to a heterogeneous computing platform, which includes a host processor and an acceleration chip. The acceleration chip internally includes an on-chip intelligent control module, a temperature aggregation unit, and a dynamic voltage and frequency adjustment control interface. The on-chip intelligent control module includes an on-chip control core, a shared state buffer, and an out-of-band control link interface. The on-chip control core is connected to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface. The shared state buffer stores service load characteristics from the host processor side. The method includes: reading the service load characteristics from the shared state buffer and reading the central junction temperature from the temperature aggregation unit, whereby the central junction temperature is obtained by fusing temperature signals from multiple thermal sensors inside the acceleration chip; constructing a cross-layer state vector based on the service load characteristics and the central junction temperature; inputting the cross-layer state vector into a decision model to score each frequency action in a set of frequency actions and selecting a target frequency from the set of frequency actions based on the scoring results; and writing the control value corresponding to the target frequency to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface to drive the clock unit and / or voltage adjustment unit to perform frequency switching.

[0006] According to an embodiment of this application, the sampling period for the service load characteristics is a first sampling period, and the execution period of the on-chip control core is a second sampling period, wherein the second sampling period is shorter than the first sampling period.

[0007] According to an embodiment of this application, reading service load characteristics from a shared state buffer includes: determining whether the service load characteristics in the shared state buffer have been updated; if the service load characteristics have been updated, reading the current service load characteristics; if the service load characteristics have not been updated, keeping the service load characteristics of the previous first sampling period unchanged as the service load characteristics of the current period.

[0008] According to embodiments of this application, the cross-layer state vector also includes microarchitectural features of the acceleration chip, including at least one of front-end constrained ratio, memory constrained ratio, and instruction retirement rate.

[0009] According to an embodiment of this application, the method further includes: in response to the central junction temperature being higher than or equal to a first preset threshold and lower than a second preset threshold, introducing a thermal penalty term into the scoring function of the decision model, wherein the thermal penalty term increases as the central junction temperature increases; and when the central junction temperature is higher than or equal to a third preset threshold, restoring the temporarily pruned low-frequency action and limiting the highest selectable frequency level.

[0010] According to an embodiment of this application, the frequency action set includes multiple discrete frequency levels. The decision model maintains historical score statistics for each frequency action. The method further includes: marking frequency actions that are continuously below a preset threshold and low-frequency intervals below them as low exploration value intervals based on the historical score statistics for each frequency action; and performing temporary pruning on the frequency actions corresponding to the low exploration value intervals through an action mask table.

[0011] According to embodiments of this application, the method further includes: in a subsequent control cycle after the execution frequency switch, generating a feedback evaluation result for the target frequency based on power consumption information, instruction retirement rate information, and center junction temperature; and incrementally updating the parameters of the decision model based on the feedback evaluation result.

[0012] According to an embodiment of this application, writing control values ​​corresponding to the target frequency to the dynamic voltage frequency adjustment control interface through the out-of-band control link interface includes: in response to the difference between the target frequency and the current frequency being greater than a preset step size threshold, decomposing the target frequency into multiple intermediate frequencies; and gradually writing control values ​​corresponding to the multiple intermediate frequencies to the dynamic voltage frequency adjustment control interface in multiple control cycles.

[0013] One aspect of this application provides a thermal sensing frequency adjustment system, which is located inside an accelerator chip. The system includes: a temperature convergence unit configured to fuse temperature signals from multiple thermal sensors inside the accelerator chip and output a center junction temperature; an on-chip intelligent control module including an on-chip control core, a shared state buffer, and an out-of-band control link interface; the on-chip control core being connected to a dynamic voltage and frequency adjustment control interface via the out-of-band control link interface; the shared state buffer storing service load characteristics from the host processor side; the on-chip control core being configured to read service load characteristics from the shared state buffer and read the center junction temperature from the temperature convergence unit; construct a cross-layer state vector based on the service load characteristics and the center junction temperature; input the cross-layer state vector into a decision model to score each frequency action in the frequency action set and select a target frequency based on the scoring results; and a dynamic voltage and frequency adjustment control interface connected to the on-chip intelligent control module via the out-of-band control link interface, configured to receive control values ​​corresponding to the target frequency and drive a clock unit and / or a voltage adjustment unit to perform frequency switching.

[0014] According to one aspect of the present application, a computer program product is provided, including a computer program or instructions that, when executed by a processor, implement the steps of the method according to the embodiment.

[0015] According to embodiments of this application, since the on-chip control core operates frequency adjustment decisions independently of the host processor, it does not rely on the host processor's computing resources and PCIe communication links. The frequency adjustment task and the inference task do not compete for physical resources, thus not reducing the throughput of large language model inference. Because the latency for the on-chip control core to read service load characteristics from the shared state buffer is in the nanosecond range, the latency for reading the central junction temperature from the temperature aggregation unit is also in the nanosecond range, and the latency for writing to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface is in the nanosecond range, the entire decision-making closed loop is completed within the acceleration chip. It does not require communication with the host processor across the PCIe bus. The latency of the control link is determined solely by the computational latency of the on-chip control core, which is far less than the millisecond latency of existing host-side dominant solutions, enabling timely response to rapid temperature rises within the chip. Since the cross-layer state vector integrates host-side service characteristics and chip-side central junction temperature, the decision model can simultaneously perceive changes in load pressure and thermal state. Before the temperature rises, it predicts the heat accumulation trend based on load characteristics and takes early frequency reduction measures, avoiding forced "cliff-like" frequency reduction triggered by the temperature reaching the hardware threshold. Because the on-chip control core writes directly to the dynamic voltage and frequency adjustment control interface through the out-of-band control link, the frequency adjustment command does not go through the operating system and driver layer, eliminating the latency uncertainty and jitter caused by the software protocol stack, and improving the timing predictability of frequency adjustment. Attached Figure Description

[0016] The contents of this application, as well as other objects, features, and advantages, will become clearer from the following description of embodiments of this application with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of the architecture of a thermal sensing frequency adjustment system according to an embodiment of this application is shown;

[0018] Figure 2 A flowchart of a thermal sensing frequency adjustment method according to an embodiment of this application is shown;

[0019] Figure 3 A flowchart illustrating the decision-making process of thermal sensing reinforcement learning according to an embodiment of this application is shown;

[0020] Figure 4 A diagram showing the thermal threshold and motion space switching according to an embodiment of this application is provided.

[0021] Figure 5 A schematic block diagram of a thermal sensing frequency adjustment system according to an embodiment of this application is shown. Detailed Implementation

[0022] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0025] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0026] First, the terminology appearing in the embodiments of this application will be explained:

[0027] Computing platform: refers to a hardware system that integrates various computing resources, including a host processor and accelerator chips. The host processor and accelerator chips are connected via a PCIe bus or other inter-chip interconnect links.

[0028] Host processor: The main control processor in a computing platform, used to run the operating system, drivers, and large language model inference framework. The host processor is the core chip in the computing platform responsible for general computing and system management.

[0029] Acceleration chip: A processor in a computing platform dedicated to accelerating specific computing tasks, such as a GPU or AI acceleration chip, used to perform inference calculations on large language models. The acceleration chip connects to the host processor via the PCIe bus, accepting task scheduling and data transfer from the host processor.

[0030] On-chip intelligent control module: A hardware control unit located inside the acceleration chip, which independently performs thermal sensing closed-loop frequency adjustment decisions, separate from the host processor. The on-chip intelligent control module includes an on-chip control core, a shared state buffer, and an out-of-band control link interface.

[0031] On-chip control core: The core computing component of the on-chip intelligent control module. The on-chip control core is used to perform frequency adjustment decision calculations. Its main frequency is much lower than that of the main execution core of the accelerator chip, and its power consumption is extremely low. It is dedicated to thermal management tasks.

[0032] Shared state cache: Accelerates on-chip storage resources within the chip, used to store the business load characteristics of the host processor. The shared state cache is located on the same chip as the on-chip control core, and the latency for the on-chip control core to access this cache is in the nanosecond range.

[0033] Out-of-band control link interface: A dedicated communication interface between the on-chip intelligent control module and the dynamic voltage and frequency adjustment control interface. "Out-of-band" refers to the main data link that is independent of the accelerator chip and the host processor, and does not pass through the PCIe bus or operating system protocol stack. It is used to transmit thermal management control commands.

[0034] Temperature convergence unit: This is the temperature signal processing circuit inside the accelerator chip, used to fuse temperature signals from multiple thermal sensors within the chip. The fusion method of the temperature convergence unit includes taking the maximum value, average value, or weighted average value, and outputting the center junction temperature.

[0035] Central junction temperature: This is the temperature value obtained by fusing temperature signals from multiple thermal sensors inside the accelerator chip using a temperature convergence unit. It represents the junction temperature of the central region of the accelerator chip's logic layer. The central junction temperature is the core thermal input parameter for the thermal sensing frequency adjustment in this application.

[0036] Dynamic voltage and frequency regulation control interface: This accelerates the chip's internal hardware interface for controlling operating frequency and voltage, reusing the chip's original dynamic voltage and frequency regulation controller and power management hardware. This interface receives the control value corresponding to the target frequency and drives the clock unit and / or voltage regulation unit to perform frequency switching.

[0037] Business load characteristics: These are operational metrics reflecting the current inference task load pressure. They originate from the host processor side and are collected by the host-side metric collection module and written to the shared state cache. Business load characteristics include at least one of the following: request queue length, batch size, task stage throughput, GPU memory utilization, and data transmission burst intensity.

[0038] Cross-layer state vector: A feature vector constructed by the on-chip control core by fusing workload characteristics and central junction temperature. "Cross-layer" refers to the fusion of software / service layer information from the host side and physical layer information from the accelerator chip side, enabling frequency adjustment decisions to simultaneously reflect workload changes and chip thermal status. The cross-layer state vector may also include the microarchitectural characteristics of the accelerator chip.

[0039] Decision Model: A lightweight policy model that is pre-configured or updated online, stored in tightly coupled memory accessible by the on-chip control core. The decision model takes a cross-layer state vector as input and outputs a score value corresponding to each frequency action in the set of frequency actions.

[0040] Frequency action set: This includes a set of multiple discrete frequency levels, each corresponding to a selectable chip operating frequency. The frequency levels are arranged in an ordered set of actions according to their frequency range.

[0041] Microarchitectural characteristics: Hardware performance metrics reflecting the operational status of the microarchitecture within the accelerator chip, acquired by the chip's internal performance monitoring unit or hardware performance counters. Microarchitectural characteristics include at least one of the following: front-end constrained ratio, memory constrained ratio, and instruction retirement rate.

[0042] Front-end stall ratio: The percentage of clock cycles during which the front-end unit of the accelerator chip cannot provide instructions to the execution unit in a timely manner. The front-end unit includes the instruction fetch unit and the decode unit. When an instruction cache miss or branch prediction error occurs, the front-end unit cannot continue to supply instructions. The front-end stall ratio can be obtained by reading the front-end stall performance counter inside the processor.

[0043] Memory-constrained percentage: The percentage of clock cycles in which instructions have entered the execution unit but cannot be completed due to memory access latency or execution unit resource contention. The memory-constrained percentage can be obtained by reading the processor's internal back-end pause performance counter.

[0044] Instruction retirement rate: The percentage of instructions that successfully execute and commit their results out of the total number of instructions issued. An instruction is retired when it completes all execution phases and writes its result back to a register or memory. The instruction retirement rate can be obtained by reading the processor's internal instruction retirement counter.

[0045] Action mask table: A data structure stored in the on-chip control core's tightly coupled memory, used to identify whether each frequency action is a valid action within the current control cycle. Each frequency action in the action mask table corresponds to a valid bit; a valid bit of 1 indicates that the action can be selected, and a valid bit of 0 indicates that the action has been temporarily pruned.

[0046] Thermal penalty term: A penalty value is introduced into the decision model's scoring function within the warning temperature range, which increases with the increase of the central junction temperature. The thermal penalty term deducts more points from the scores of high-frequency actions, thereby suppressing the tendency to select high-frequency actions and achieving a smooth transition from high to low frequencies.

[0047] Temporarily pruned low-frequency actions: Within the normal temperature range, the decision model, based on historical scoring statistics, marks actions with frequencies consistently below a preset threshold and the corresponding low-frequency intervals as low-exploration-value intervals, and uses an action mask table to mark these intervals as invalid. Temporarily pruned low-frequency actions can be restored to valid status within the high-temperature protection range using the action mask table.

[0048] Zero-order hold: A data hold method in which the previous sampled value is kept unchanged even if no new sampled value is obtained. In this application, when the on-chip control core determines that the service load characteristics in the shared state buffer have not been updated, the service load characteristics of the previous first sampling period are kept unchanged as the service load characteristics of the current period.

[0049] Feedback evaluation results: After completing the frequency switch, the on-chip control core generates evaluation results in subsequent control cycles based on power consumption information, instruction retirement rate information, and center junction temperature. These feedback evaluation results are used to evaluate the actual effect of the previously selected target frequency operation.

[0050] Preset step size threshold: A pre-configured limit on the maximum change in frequency in a single operation, used to prevent voltage undershoot caused by a single large frequency jump. When the difference between the target frequency and the current frequency exceeds the preset step size threshold, the on-chip control core decomposes the target frequency into multiple intermediate frequencies, gradually approaching the target frequency over multiple control cycles.

[0051] To address the technical challenges, embodiments of this application provide a thermal sensing frequency adjustment method. This method is applied to a computing platform, which includes a host processor and an acceleration chip. The acceleration chip internally houses an on-chip intelligent control module, a temperature aggregation unit, and a dynamic voltage and frequency adjustment control interface. The on-chip intelligent control module includes an on-chip control core, a shared state buffer, and an out-of-band control link interface. The on-chip control core is connected to the dynamic voltage and frequency adjustment control interface via the out-of-band control link interface. The shared state buffer stores service load characteristics from the host processor side. The method includes: reading service load characteristics from the shared state buffer and reading the central junction temperature from the temperature aggregation unit, whereby the central junction temperature is obtained by fusing temperature signals from multiple thermal sensors within the acceleration chip; constructing a cross-layer state vector based on the service load characteristics and the central junction temperature; inputting the cross-layer state vector into a decision model to score each frequency action in a set of frequency actions and selecting a target frequency from the set based on the scoring results; and writing the control value corresponding to the target frequency to the dynamic voltage and frequency adjustment control interface via the out-of-band control link interface to drive the clock unit and / or voltage adjustment unit to perform frequency switching.

[0052] Figure 1 A schematic diagram of the architecture of a thermal sensing frequency adjustment system according to an embodiment of this application is shown.

[0053] like Figure 1 As shown, the computing platform used in this system includes a host CPU and an accelerator chip (such as a GPU or AI accelerator chip). The host CPU and the accelerator chip are connected via a Peripheral Component Interconnect Express (PCIe) bus or other inter-chip interconnect links. The host CPU is the main control processor in the computing platform, used to run the operating system, drivers, and large language model inference framework; the accelerator chip is a processor in the computing platform dedicated to accelerating specific computing tasks, used to perform inference computations on large language models.

[0054] like Figure 1As shown, a host-side metrics acquisition module 110 is deployed on the host processor 100 side. The host-side metrics acquisition module is a functional module running on the host processor as software, a driver, or a daemon process, used to collect service load characteristics from the application layer, runtime framework, driver layer, or operating system interface. Service load characteristics include, but are not limited to, request queue length, batch size, task stage throughput, video memory utilization, and data transmission burst intensity, used to reflect the load pressure of the current inference task. The host-side metrics acquisition module periodically collects service load characteristics at a first sampling period (typically 0.8ms to 1ms), and writes the collected service load characteristics into the shared state buffer inside the acceleration chip via the PCIe bus and Direct Memory Access (DMA), updating the timestamp and write completion flag.

[0055] The acceleration chip 120 is equipped with a temperature convergence unit 121, an on-chip intelligent control module 122, and a dynamic voltage and frequency scaling (DVFS) control interface 123.

[0056] Temperature aggregation unit 121 is a temperature signal processing circuit inside the accelerator chip. Its input is connected to multiple thermal sensors distributed in the logic computing area, central hotspot area, and related areas of the memory stack of the accelerator chip. Multiple thermal sensors are distributed within the three-dimensional stacked accelerator chip, monitoring the temperature of different areas. The temperature aggregation unit fuses multiple temperature signals and outputs the central junction temperature T_center. The fusion method for the central junction temperature can be taking the maximum value, average value, or weighted average value, used to characterize the junction temperature of the central region of the logic layer of the accelerator chip.

[0057] The on-chip intelligent control module 122 is a hardware control unit independent of the host processor within the accelerator chip 120. It is located inside the accelerator chip and is used to perform thermal sensing closed-loop frequency adjustment decisions. The on-chip intelligent control module includes an on-chip control core, a shared state buffer, and an out-of-band control link interface.

[0058] The on-chip control core is the core computing component of the on-chip intelligent control module. It is preferably a fifth-generation Reduced Instruction Set Computer V Microcontroller Unit (RISC-V MCU), but can also be an embedded core of other instruction set architectures or a dedicated hardwired logic state machine. The on-chip control core performs frequency regulation decision-making operations. Its clock frequency is much lower than that of the accelerator chip's main execution core, resulting in extremely low power consumption, and it is dedicated to thermal management tasks. The on-chip control core is also connected to tightly coupled memory (TCM) for storing the control program, state cache, action mask table, model parameters, and historical feedback information. The on-chip control core periodically executes the complete frequency regulation closed loop with a second sampling period (typically on the order of 100μs).

[0059] A shared state cache is an on-chip storage resource that accelerates the chip's internal processing capabilities, such as Static Random Access Memory (SRAM) or register files, used to store workload characteristics from the host processor side. The shared state cache resides within the same chip as the on-chip control core, and the latency for the on-chip control core to access this cache is in the nanosecond range, eliminating the need to read data across the PCIe bus.

[0060] The out-of-band control link interface is a dedicated communication interface between the on-chip intelligent control module and the DVFS control interface. "Out-of-band" refers to a main data link independent of the accelerator chip and the host processor, bypassing the PCIe bus or operating system protocol stack, and used for transmitting thermal management control commands. The out-of-band control link interface is preferably an Inter-Integrated Circuit (I2C) interface, an Improved Inter-Integrated Circuit (I3C) interface, a System Management Bus (SMBus) interface, or an on-chip dedicated control bus interface.

[0061] The dynamic voltage and frequency regulation control interface reuses the chip's original DVFS controller and power management hardware, and is connected to the on-chip intelligent control module through an out-of-band control link interface. It is used to receive the control value corresponding to the target frequency and drive the clock unit and / or voltage regulation unit to perform frequency switching.

[0062] After the host-side indicator acquisition module acquires the service load characteristics, it writes them to the shared state buffer via the PCIe bus. The on-chip control core reads the service load characteristics from the shared state buffer and the center junction temperature from the temperature aggregation unit. After making a decision, it writes the target frequency control value to the DVFS control interface through the out-of-band control link interface. After receiving the control value corresponding to the target frequency, the DVFS control interface drives the clock unit to adjust the output clock frequency and / or drives the voltage adjustment unit to adjust the operating voltage, thus performing frequency switching.

[0063] Through its architecture, the data flow and control flow of the entire thermal sensing frequency regulation system are completed in a closed loop within the accelerator chip, without passing through the host processor, operating system, and PCIe bus, thus realizing an in-situ closed-loop control architecture.

[0064] Figure 2 A flowchart of a thermal sensing frequency adjustment method according to an embodiment of this application is shown.

[0065] like Figure 2 As shown, this includes operations S210 to S240.

[0066] During operation S210, the service load characteristics are read from the shared state buffer and the central junction temperature is read from the temperature aggregation unit. The central junction temperature is obtained by the temperature aggregation unit through the fusion processing of temperature signals from multiple thermal sensors inside the acceleration chip.

[0067] In one example, the on-chip control core performs this operation at the beginning of each control cycle. The on-chip control core reads the service load characteristics stored in the shared state buffer via the internal chip bus. These service load characteristics originate from the host processor side, are collected by the host-side metrics acquisition module according to the first sampling cycle, and then written to the shared state buffer via PCIe DMA. Service load characteristics include, but are not limited to, request queue length, batch size, task stage throughput, memory utilization, and data transfer burst intensity; these characteristics reflect the load pressure of the current inference task. The shared state buffer is located inside the acceleration chip, and the latency for the on-chip control core to access this buffer is in the nanosecond range, eliminating the need for cross-PCIe bus reads.

[0068] In one example, the on-chip control core reads the center junction temperature from the temperature aggregation unit via an out-of-band control link interface or a dedicated temperature readout channel. The center junction temperature is obtained by the temperature aggregation unit through the fusion processing of temperature signals from multiple thermal sensors within the accelerator chip, representing the junction temperature of the central region of the accelerator chip's logic layer. The temperature aggregation unit outputs the latest center junction temperature value in each control cycle for the on-chip control core to read.

[0069] In operation S220, a cross-layer state vector is constructed based on the service load characteristics and the central junction temperature.

[0070] In one example, the on-chip control core fuses workload characteristics read from the shared state cache and the center junction temperature read from the temperature aggregation unit to construct a cross-layer state vector. The "cross-layer" in the cross-layer state vector refers to the fusion of software / service layer information from the host side and physical layer information from the accelerator chip side, enabling frequency adjustment decisions to simultaneously reflect workload changes and chip thermal status. The specific data format of the cross-layer state vector is a fixed-length feature vector, where workload characteristics and center junction temperature each occupy a predetermined feature dimension. The cross-layer state vector can also include microarchitectural features of the accelerator chip, such as front-end constrained ratio, memory constrained ratio, and instruction retirement rate. This application incorporates features into the "cross-layer state vector," allowing the decision model to perceive specific bottlenecks within the computing chip, thereby determining whether increasing the frequency is truly effective and avoiding ineffective heat generation caused by blindly pushing up the frequency.

[0071] In operation S230, the cross-layer state vector is input into the decision model, each frequency action in the frequency action set is scored, and the target frequency is selected from the frequency action set based on the scoring results.

[0072] In one example, the decision model is a pre-configured or online-updated lightweight policy model stored in tightly coupled memory accessible by the on-chip control core. The decision model takes a cross-layer state vector as input and outputs a score for each frequency action in the frequency action set. The frequency action set includes multiple discrete frequency levels, such as 800MHz, 900MHz, 1000MHz, 1100MHz, and 1200MHz. Each frequency level forms an ordered action set according to its frequency, with higher frequency levels corresponding to higher performance but higher power consumption and heat generation, and lower frequency levels corresponding to lower performance but lower power consumption and heat generation. The decision model scores each frequency action based on the cross-layer state vector, and the score reflects the overall benefit of selecting that frequency action under the current workload and thermal conditions. The on-chip control core selects the target frequency from the frequency action set based on the scoring results, i.e., selecting the frequency action with the highest score as the target frequency.

[0073] When operating S240, the control value corresponding to the target frequency is written to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface to drive the clock unit and / or voltage adjustment unit to perform frequency switching.

[0074] In one example, the on-chip control core encodes the target frequency selected by operation S230 into a control value compatible with the dynamic voltage-frequency regulation control interface, and sends a write command directly to the dynamic voltage-frequency regulation control interface through the out-of-band control link interface. This write command bypasses the host processor, operating system, and PCIe bus, and is directly received and parsed by the dynamic voltage-frequency regulation control interface. After receiving the control value, the dynamic voltage-frequency regulation control interface drives the clock unit to adjust the output clock frequency and / or drives the voltage regulation unit to adjust the operating voltage, completing the frequency switching.

[0075] Since the on-chip control core operates independently of the host processor in making frequency adjustment decisions, the heat-sensing frequency adjustment method provided in this application does not rely on the host processor's computing resources and PCIe communication links. The frequency adjustment task and the inference task do not compete for physical resources, and the throughput of large language model inference will not be reduced. Because the latency for the on-chip control core to read service load characteristics from the shared state buffer is in the nanosecond range, the latency for reading the central junction temperature from the temperature aggregation unit is in the nanosecond range, and the latency for writing to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface is also in the nanosecond range, the entire decision-making closed loop is completed within the accelerator chip, without needing to communicate with the host processor across the PCIe bus. The latency of the control link is determined only by the computational latency of the on-chip control core, which is far less than the millisecond latency of existing host-side dominant solutions, enabling timely response to rapid temperature rises within the chip. Since the cross-layer state vector integrates host-side service characteristics and chip-side central junction temperature, the decision model can simultaneously sense changes in load pressure and thermal state. Before the temperature rises, it predicts the heat accumulation trend based on load characteristics and takes frequency reduction measures in advance, avoiding forced "cliff-like" frequency reduction triggered when the temperature reaches the hardware threshold.

[0076] According to an embodiment of this application, the sampling period for the service load characteristics is a first sampling period, and the execution period of the on-chip control core is a second sampling period, wherein the second sampling period is shorter than the first sampling period.

[0077] In one example, the sampling period for the service load characteristics is the first sampling period. The first sampling period is the time interval at which the host-side indicator acquisition module collects the service load characteristics. The host-side indicator acquisition module is deployed on the host processor side, periodically collecting service load characteristics at millisecond intervals, and writing the collected service load characteristics into the shared state cache inside the acceleration chip via PCIe DMA. Preferably, the first sampling period is 0.8ms to 1ms.

[0078] In one example, the on-chip control core's execution cycle is the second sampling period. The second sampling period is the time interval during which the on-chip control core executes one complete frequency regulation decision process. The on-chip control core is triggered by a timer at a fixed period, periodically executing a complete closed-loop operation: reading service load characteristics from the shared state buffer, reading the central junction temperature from the temperature aggregation unit, constructing a cross-layer state vector, scoring and selecting the target frequency, and writing to the dynamic voltage and frequency regulation control interface. Preferably, the second sampling period is on the order of 100 μs. The second sampling period is shorter than the first sampling period. That is, the decision frequency of the on-chip control core is higher than the update frequency of the service load characteristics on the host side, and the difference between the two is about an order of magnitude (the first sampling period is on the order of milliseconds, and the second sampling period is on the order of microseconds).

[0079] Because the second sampling period is shorter than the first sampling period, the on-chip control core can perform multiple frequency adjustment decisions between two service feature updates on the host side. This ensures that the rhythm of temperature detection and frequency adjustment is not affected by the slow sampling period on the host side, thereby achieving microsecond-level fast closed-loop control. Since the on-chip control core operates at a higher update frequency than the host side, it can rely on the real-time sampled central junction temperature for master control and reuse the cached service load features as auxiliary references during multiple consecutive control cycles before the service load features are updated, achieving a temperature-priority fast response.

[0080] According to an embodiment of this application, reading service load characteristics from a shared state buffer includes: determining whether the service load characteristics in the shared state buffer have been updated; if the service load characteristics have been updated, reading the current service load characteristics; if the service load characteristics have not been updated, keeping the service load characteristics of the previous first sampling period unchanged as the service load characteristics of the current period.

[0081] In one example, the shared state buffer read workload characteristics include the following sub-steps:

[0082] Sub-step 1: Determine whether the service load characteristics in the shared state cache have been updated.

[0083] After each collection and write of service load characteristics, the host-side indicator acquisition module sets a write completion flag and updates the timestamp in the shared state buffer. When the on-chip control core reads the shared state buffer at the beginning of each control cycle, it first checks the write completion flag or the timestamp to determine if the service load characteristics in the buffer are the latest collected data. If the write completion flag is set and the timestamp is updated, it indicates that the host side has completed a new round of data collection and writing, and the service load characteristics in the shared state buffer are the latest; otherwise, it indicates that the host side has not yet completed a new round of collection, and the shared state buffer stores data from the previous cycle.

[0084] Sub-step two: If the service load characteristics have been updated, read the current service load characteristics. If the on-chip control core determines that the write completion flag is set, indicating that the shared state buffer stores the latest service load characteristics, then the on-chip control core directly reads the current service load characteristics from the shared state buffer. After reading, the on-chip control core clears the write completion flag and waits for the next round of host-side writing.

[0085] Sub-step 3: If the service load characteristics have not been updated, maintain the service load characteristics from the previous first sampling period unchanged as the service load characteristics for the current period. If the on-chip control core determines that the write completion flag is not set, it indicates that the host side has not yet completed this round of data acquisition and writing, and the service load characteristics in the shared state buffer are still the old data from the previous sampling period. At this time, the on-chip control core does not wait for the host side to complete the write, but directly reuses the service load characteristic value from the previous first sampling period to participate in the decision-making of the current period. This processing method is called zero-order hold, that is, keeping the previous sampled value unchanged if no new sampled value is obtained.

[0086] Because the on-chip control core directly reuses data from the previous cycle without waiting for the host side when the service load characteristics are not updated, the rhythm of temperature detection and control execution is not limited by the host side sampling cycle, avoiding decision delays caused by waiting for host side data updates. Since the central junction temperature is resampled in each control cycle, real-time thermal status information is always included in the frequency adjustment decision-making basis. Even in extreme cases where host side characteristics are not updated for a long time, the decision model can still make reasonable thermal management decisions based on real-time temperature. When the number of consecutive unupdated cycles exceeds a preset threshold, the on-chip control core can enter a conservative control mode, limiting the highest selectable frequency level through an action mask table to achieve autonomous frequency reduction protection. This zero-order hold mechanism ensures that the on-chip thermal control closed loop can still operate continuously even in the event of host side characteristic delay or short-term loss of synchronization.

[0087] According to embodiments of this application, the cross-layer state vector also includes microarchitectural features of the acceleration chip, including at least one of front-end constrained ratio, memory constrained ratio, and instruction retirement rate.

[0088] In one example, the cross-layer state vector also includes the microarchitectural features of the accelerator chip. Microarchitectural features are hardware performance metrics that reflect the operating state of the microarchitecture inside the accelerator chip, and are collected by the performance monitoring unit or hardware performance counter inside the accelerator chip.

[0089] In one example, microarchitectural features include at least one of front-end stall ratio, memory stall ratio, and instruction retirement rate. These metrics are used to precisely quantify the sources of performance bottlenecks within the chip. The front-end stall ratio refers to the proportion of clock cycles during which the front-end unit of the accelerator chip cannot promptly provide instructions to the execution unit. The front-end unit includes the fetch unit and the decode unit. When an instruction cache miss or branch prediction error occurs, the front-end unit cannot continue to supply instructions, thus idling the execution unit. The front-end stall ratio can be obtained by reading the processor's internal front-end stall performance counter; a higher value indicates a more severe fetch / decode bottleneck and limited instruction supply capability.

[0090] The memory-constrained ratio refers to the proportion of clock cycles in the total clock cycles that an instruction has entered the execution unit but cannot be completed due to memory access latency or resource contention within the execution unit. For example, when a data cache miss occurs and data needs to be read from off-chip memory, the execution unit must wait for the data to return before continuing execution. The memory-constrained ratio can be obtained by reading the processor's internal back-end stall performance counter; a higher value indicates a more severe memory access bottleneck and limited data supply capacity.

[0091] Instruction retirement rate refers to the proportion of instructions that are successfully executed and whose results are committed out of the total number of instructions issued. An instruction is retired when it completes all execution stages and writes its result back to a register or memory. The instruction retirement rate can be obtained by reading the processor's internal instruction retirement counter; a higher value indicates higher effective computational efficiency of the processor.

[0092] Because the cross-layer state vector incorporates microarchitectural features such as front-end constrained ratio, memory constrained ratio, and instruction retirement rate, the decision model can perceive not only load intensity and thermal state but also the type of computational bottleneck within the accelerator chip. When the front-end constrained ratio increases, even if the temperature is not high, increasing the frequency will not bring performance gains. This is because the performance bottleneck lies in instruction supply rather than computation speed; maintaining a low frequency is beneficial for heat dissipation without sacrificing performance. Similarly, when the memory constrained ratio increases, increasing the frequency will not improve data latency; blindly pushing the frequency will only increase ineffective heat generation. When the instruction retirement rate is high, increasing the frequency can directly translate into an increase in computational throughput. The introduction of microarchitectural features allows the decision model to determine whether "increasing the frequency is truly effective," thereby avoiding ineffective heat generation caused by blindly increasing the frequency in ineffective scenarios and improving the energy efficiency of frequency regulation while ensuring thermal safety.

[0093] According to an embodiment of this application, the method further includes: in response to the central junction temperature being higher than or equal to a first preset threshold and lower than a second preset threshold, introducing a thermal penalty term into the scoring function of the decision model, wherein the thermal penalty term increases as the central junction temperature increases; and when the central junction temperature is higher than or equal to a third preset threshold, restoring the temporarily pruned low-frequency action and limiting the highest selectable frequency level.

[0094] In one example, embodiments of this application set multiple temperature thresholds to distinguish different temperature ranges and execute differentiated control strategies in different temperature ranges.

[0095] When the center junction temperature is within the warning temperature range, i.e., higher than or equal to the first preset threshold and lower than the second preset threshold, the chip temperature is close to the high temperature range but has not yet reached the high temperature protection threshold. First preset threshold The second preset threshold is the soft intervention threshold. The high temperature protection threshold must be met. At this point, the on-chip control core adds a thermal penalty term to the scoring function of the decision model. The thermal penalty term increases with the increase of the central junction temperature; that is, the higher the central junction temperature, the greater the penalty value, and the more points are deducted from the score of selecting high-frequency actions, thereby suppressing the tendency to continue selecting high-frequency actions.

[0096] Third preset threshold For hardware protection thresholds, meet When the central junction temperature reaches or exceeds the third preset threshold, the chip temperature is very close to the critical point for hardware-forced frequency reduction or shutdown. The on-chip control core performs two levels of forced operation: First, it restores the low-frequency actions that were temporarily pruned. Low-frequency actions that were previously marked as low exploration value ranges within the normal temperature range and temporarily pruned are restored as valid actions, allowing the system to obtain a safe frequency reduction path at a lower frequency. Second, it limits the highest selectable frequency range, that is, in the action mask table, all frequency actions higher than the predetermined highest frequency range are marked as invalid, actively guiding the search range to a lower frequency range.

[0097] By introducing a thermal penalty term that increases with temperature within the warning temperature range, the decision model gradually reduces its preference for high-frequency actions as the temperature approaches high, achieving a smooth transition from high to low frequencies and avoiding transient disturbances to the power supply network caused by sudden temperature drops when the temperature approaches the hardware threshold. By restoring temporarily pruned low-frequency actions within the high-temperature protection range, previously "inefficient" low-frequency downscaling paths are reactivated, providing the system with an executable frequency reduction option in the event of a thermal emergency. Simultaneously limiting the highest selectable frequency range forces the system to switch from the high-frequency search space to the low-frequency safety range, proactively guiding the chip to a thermally safe state. This two-level control strategy forms a smooth transition protection mechanism during temperature increases, providing an active intervention path before forced hardware throttling, thus avoiding inference service latency jitter caused by precipitous frequency reduction.

[0098] According to an embodiment of this application, the frequency action set includes multiple discrete frequency levels. The decision model maintains historical score statistics for each frequency action. The method further includes: marking frequency actions that are continuously below a preset threshold and low-frequency intervals below them as low exploration value intervals based on the historical score statistics for each frequency action; and performing temporary pruning on the frequency actions corresponding to the low exploration value intervals through an action mask table.

[0099] In one example, the frequency action set includes multiple discrete frequency levels. Each frequency level corresponds to a specific chip operating frequency value, such as 800MHz, 900MHz, 1000MHz, 1100MHz, and 1200MHz. The frequency levels form an ordered action set according to their frequency, with higher frequency levels corresponding to higher performance but higher power consumption and heat generation, and lower frequency levels corresponding to lower performance but lower power consumption and heat generation.

[0100] The decision model maintains historical score statistics for each frequency action. After each decision, the on-chip control core records the score results of each frequency action within the current control cycle and updates the historical score statistics for each frequency action. The historical score statistics can be the moving average or exponentially weighted average of the scores for each frequency action over the most recent few control cycles, reflecting the long-term benefit trend of each frequency action under the current load and thermal conditions.

[0101] Based on the historical score statistics of each frequency action, the decision model marks frequency actions that are consistently below a preset threshold and the low-frequency intervals below them as low exploration value intervals. Specifically, if a frequency action scores below the preset threshold for a preset number of consecutive times (e.g., 3 consecutive times), it is determined that the frequency action has low returns under the current load conditions; since the set of frequency actions is ordered, the scores of even lower frequency intervals below this frequency action are usually not high either, and therefore are also marked as low exploration value intervals.

[0102] The decision model uses an action mask table to temporarily prune frequency actions corresponding to low exploration value intervals. The action mask table is a data structure stored in the tightly coupled memory of the on-chip control core, used to identify whether each frequency action is a valid action within the current control cycle. Each frequency action in the action mask table corresponds to a valid bit; a valid bit of 1 indicates that the action can be selected within the current control cycle, while a valid bit of 0 indicates that the action has been temporarily pruned. When the decision model determines that a frequency interval is a low exploration value interval, it clears the valid bit of the corresponding frequency actions to zero, preventing them from being included in the candidate range in subsequent scoring and selection.

[0103] Because the decision model maintains historical score statistics for actions at each frequency, it can judge the long-term benefits of each action based on the actual effects of past decisions, rather than relying solely on the instantaneous state of the current cycle, thus improving the stability and robustness of the decision. By performing temporary pruning on low-exploration-value intervals through an action mask table, the search space is reduced, and the decision model only needs to select from a limited number of high-value frequency actions, reducing ineffective exploration and improving decision efficiency. Since the pruning operation is temporary, when the temperature rises to the high-temperature protection range, the pruned low-frequency actions can be restored through the action mask table, ensuring that the system still has a complete low-frequency reduction path in thermal emergencies.

[0104] According to embodiments of this application, the method further includes: in a subsequent control cycle after the execution frequency switch, generating a feedback evaluation result for the target frequency based on power consumption information, instruction retirement rate information, and center junction temperature; and incrementally updating the parameters of the decision model based on the feedback evaluation result.

[0105] In one example, in the subsequent control cycle after the frequency switch, feedback evaluation results for the target frequency are generated based on power consumption information, instruction retirement rate information, and center junction temperature.

[0106] After completing a frequency switch, the on-chip control core continuously collects the accelerator chip's operational status information in one or more subsequent control cycles. This operational status information includes: power consumption information (obtained by reading power-related registers); instruction retirement rate information (obtained by reading the instruction retirement counter to determine the actual effective computational throughput); and center junction temperature (obtained through a temperature aggregation unit to assess actual temperature changes). The on-chip control core generates feedback evaluation results based on this information to evaluate the actual effect of the previously selected target frequency action. A positive evaluation occurs if power consumption decreases and throughput remains stable after the frequency switch; a negative evaluation occurs if the temperature continues to rise into the warning zone or high-temperature protection zone after the frequency switch; and a negative evaluation occurs if the frequency switch leads to a significant decrease in the instruction retirement rate. The parameters of the decision-making model are incrementally updated based on the feedback evaluation results.

[0107] The parameters of the decision model are stored in tightly coupled memory within the on-chip control core. The on-chip control core calculates the parameter update amount based on the feedback evaluation results and incrementally updates the parameters of the decision model. This update employs a low-complexity iterative update method, such as stochastic gradient descent or its approximate variants, and does not involve high-complexity full matrix inversion operations.

[0108] Because the feedback evaluation results are generated based on the actual power consumption, instruction retirement rate, and central junction temperature after execution, the decision model can obtain realistic feedback on the action effects. The feedback information comes from the actual effects produced by the physical hardware rather than preset rules or theoretical calculations. Therefore, online updates enable the decision model to gradually adapt to the individual characteristics of the specific chip and the actual thermal characteristics of the deployment environment. Due to the use of a low-complexity iterative update method, parameter updates do not involve computationally intensive operations such as high-complexity matrix inversion. The limited computing power of the on-chip control core is sufficient to support online updates, enabling the system to achieve adaptive frequency adjustment during runtime under resource-constrained conditions, adapting to the extreme non-stationarity of large language model workloads.

[0109] According to an embodiment of this application, writing control values ​​corresponding to the target frequency to the dynamic voltage frequency adjustment control interface through the out-of-band control link interface includes: in response to the difference between the target frequency and the current frequency being greater than a preset step size threshold, decomposing the target frequency into multiple intermediate frequencies; and gradually writing control values ​​corresponding to the multiple intermediate frequencies to the dynamic voltage frequency adjustment control interface in multiple control cycles.

[0110] In one example, writing the control value corresponding to the target frequency to the dynamic voltage-frequency regulation control interface via the out-of-band control link interface includes the following sub-steps:

[0111] Sub-step 1: In response to the difference between the target frequency and the current frequency being greater than the preset step size threshold, the target frequency is decomposed into multiple intermediate frequencies.

[0112] After selecting a target frequency, the on-chip control core compares the target frequency with the current actual operating frequency. If this difference exceeds a preset step size threshold... In this case, the on-chip control core does not directly write the target frequency to the dynamic voltage and frequency adjustment control interface. Instead, it decomposes a single frequency jump into multiple intermediate frequency steps. The preset step size threshold can be, for example, 100MHz, 150MHz, or 200MHz. The specific value is pre-configured by the system based on the electrical characteristics of the power supply network of the three-dimensional stacked chip and the allowable voltage transient response range.

[0113] Sub-step 2: Gradually write control values ​​corresponding to multiple intermediate frequencies to the dynamic voltage and frequency adjustment control interface in multiple control cycles.

[0114] After the on-chip control core decomposes the frequency into multiple intermediate frequencies, it writes a control value corresponding to one intermediate frequency in each subsequent control cycle, gradually adjusting the frequency from the current frequency to the target frequency. The difference between each intermediate frequency and the frequency of the previous cycle does not exceed a preset step size threshold, ensuring that the frequency change is gradual rather than abrupt.

[0115] Because multi-step decomposition is performed when the difference between the target frequency and the current frequency exceeds a preset step size threshold, the amount of a single frequency change is limited to an allowable range, avoiding voltage downscaling caused by a single large frequency jump, thereby reducing the risk of transient disturbances and calculation errors in the power supply network. Since multi-step approximation is completed gradually over multiple control cycles, the frequency regulation process presents a smooth, ramp-like change rather than a step-like abrupt change. The power supply network has sufficient time to respond to frequency changes, and the voltage regulator can keep up with the pace of frequency changes, further enhancing the electrical reliability of the system. The micro-step progressive frequency modulation method, combined with the temperature-graded control strategy, together achieves a complete thermal safety path from temperature sensing to smooth frequency reduction.

[0116] Figure 3 A flowchart of a thermal sensing reinforcement learning decision-making process according to an embodiment of this application is shown.

[0117] like Figure 3 As shown, this illustrates the multi-stage decision-making process executed by the on-chip control core during a complete control cycle. Figure 3 The described multi-stage decision-making process and Figure 2 The basic method flow shown corresponds to this, and further refines the temperature grading judgment and feedback update processes.

[0118] like Figure 3 As shown, the on-chip control core executes the following decision-making process in each control cycle:

[0119] During the state read phase, the on-chip control core reads the service load characteristics from the shared state buffer and checks the write completion flag to determine whether the service load characteristics in the buffer have been updated. If updated, the current characteristic value is read; otherwise, the service load characteristics from the previous first sampling period are retained as the service load characteristics for the current period. Simultaneously, the on-chip control core reads the center junction temperature T_center from the temperature aggregation unit. The center junction temperature is resampled in each control cycle and is unaffected by the service load characteristic update status.

[0120] During the state vector construction phase, the on-chip control core concatenates workload characteristics, central node temperature, and optional microarchitectural characteristics into a cross-layer state vector St. Microarchitectural characteristics include at least one of front-end constrained ratio, memory constrained ratio, and instruction retirement rate, acquired by the performance monitoring unit or hardware performance counters within the acceleration chip. The cross-layer state vector St is a fixed-length feature vector, serving as input to the decision model.

[0121] The on-chip control core determines the current temperature range based on the central junction temperature T_center. The system has three preset temperature thresholds: the first preset threshold... The second preset threshold is the soft intervention threshold. The third preset threshold is the high-temperature protection threshold. The hardware protection threshold, all three conditions must be met. The specific values ​​of each threshold can be pre-configured by the system based on the thermal characteristics of the accelerator chip, package heat dissipation conditions, and application scenarios. For example, a typical configuration is... =75℃ =82℃ =90℃.

[0122] Within the normal temperature range (T_center < With the chip temperature within a safe range, all frequency actions are functioning effectively. The on-chip control core inputs the cross-layer state vector St into the decision model, scores each frequency action in the frequency action set, and selects the target frequency based on the score results. Within this temperature range, the decision model typically tends to select higher-frequency actions to achieve higher performance.

[0123] Within the warning temperature range ( ≤T_center < The chip temperature is approaching the high-temperature range but has not yet reached the high-temperature protection threshold. The on-chip control core introduces a thermal penalty term into the scoring function of the decision model. This thermal penalty term increases with the increase of the central junction temperature; that is, the higher the central junction temperature, the larger the penalty value, and the more points are deducted from the score of selecting high-frequency actions, thus suppressing the tendency to continue selecting high-frequency actions. The thermal penalty term can be expressed as a function of temperature; for example, the penalty value is proportional to the difference between the central junction temperature and the first preset threshold, and the larger the difference, the larger the penalty value. During the temperature increase process, the score of high-frequency actions gradually decreases, while the relative score of low-frequency actions gradually increases, achieving a smooth transition from high to low frequencies. The on-chip control core performs the scoring and selection.

[0124] Within the high-temperature protection zone (T_center≥ The chip temperature is very close to the critical point where hardware-forced frequency reduction or shutdown is required. The on-chip control core recovers the temporarily pruned low-frequency actions using an action mask table. Previously, within the normal temperature range, the decision model may have marked certain low-frequency actions as low-exploration-value ranges and performed temporary pruning based on historical scoring statistics. In the high-temperature protection range, these temporarily pruned low-frequency actions are restored as valid actions, allowing the system to obtain a safe frequency reduction path at a lower frequency. The on-chip control core limits the highest selectable frequency range, marking all frequency actions above the predetermined highest frequency range as invalid, actively guiding the search range to a lower frequency range. The on-chip control core performs scoring and selection.

[0125] The on-chip control core encodes the selected target frequency into a control value compatible with the dynamic voltage and frequency regulation control interface (DVFS), and writes the corresponding control value to the DVFS via the out-of-band control link interface. After receiving the control value, the DVFS control interface drives the clock unit and / or voltage regulation unit to complete the frequency switching.

[0126] In the subsequent control cycle after a frequency switch, the on-chip control core reads power consumption registers to obtain the actual power consumption value, reads the instruction decommissioning counter to obtain the actual effective computational throughput, and obtains the actual temperature change through the temperature aggregation unit. Based on this, it generates a feedback evaluation result for the action taken at the previously selected target frequency. The feedback evaluation result is used to evaluate the actual effect of the action: if power consumption decreases and throughput remains stable after the frequency switch, it is a positive evaluation; if the temperature continues to rise to the warning zone or high-temperature protection zone after the frequency switch, it is a negative evaluation. Based on the feedback evaluation result, the on-chip control core incrementally updates the parameters of the decision model. This update uses a low-complexity iterative update method, such as stochastic gradient descent or its approximate variants, and does not involve high-complexity full matrix inversion operations.

[0127] By introducing a heat penalty term that increases with temperature within the warning temperature range, the decision model gradually reduces its preference for high-frequency actions as the temperature approaches high, achieving a smooth transition from high to low frequencies and avoiding transient disturbances to the power supply network caused by sudden temperature drops when the temperature approaches the hardware threshold. By restoring temporarily pruned low-frequency actions and limiting the highest selectable frequency range within the high-temperature protection range, the system is forced to switch from the high-frequency search space to the low-frequency safety range, providing an active intervention path before hardware-forced throttling, thus avoiding inference service latency jitter caused by precipitous frequency reduction. Since the feedback update phase uses a low-complexity iterative update method, parameter updates do not involve computationally intensive operations such as high-complexity matrix inversion. The limited computing power of the on-chip control core is sufficient to support online updates, enabling the system to achieve adaptive frequency adjustment during runtime under resource-constrained conditions, adapting to the extreme non-stationarity of large language model workloads.

[0128] Figure 4A diagram showing the switching of thermal threshold and motion space according to an embodiment of this application is provided.

[0129] like Figure 4 As shown, the temperature status threshold classification includes three temperature zones: normal temperature zone, warning temperature zone, and emergency high temperature zone (high temperature protection zone). The division of these three temperature zones is based on three preset temperature thresholds: the first preset threshold... The second preset threshold is the boundary between the normal temperature zone and the warning temperature zone. The third preset threshold is the boundary between the warning temperature zone and the emergency high temperature zone. This represents the hardware protection threshold. After reading the center junction temperature in each control cycle, the on-chip control core executes the corresponding policy response based on the temperature range of the center junction temperature, completing the action mask table adjustment and frequency selection. The figure illustrates the on-chip control core's action mask table and policy response under different temperature ranges using three parallel blocks. It should be noted that... Figure 4 The diagram illustrates the phased process. The three temperature ranges are traversed sequentially over time as the central junction temperature increases. As the central junction temperature passes through each range from low to high, the on-chip control core responds by adjusting the action mask table and selecting the frequency according to the strategy corresponding to each range.

[0130] Within the normal temperature range, the chip temperature remains within a safe range. The on-chip control core, aiming for higher energy efficiency, does not impose any thermal constraints. The on-chip control core scores each frequency action in the set of frequency actions and freely selects the frequency level within the selection space comprised of all valid actions, typically favoring higher-scoring, higher-frequency actions for higher performance. Simultaneously, within the normal temperature range, the decision model is allowed to perform free exploration and temporary pruning of low-frequency action intervals with consecutive low scores based on historical scoring statistics, thereby reducing the search space and improving decision-making efficiency.

[0131] Within the warning temperature range, the chip temperature is close to the high-temperature zone but has not yet reached the high-temperature protection threshold. The on-chip control core executes a soft thermal suppression strategy: maintaining the current action set and not changing the action mask table state, but applying a thermal penalty term that increases with temperature to the scoring function of the decision model to suppress the tendency to select high-frequency actions. The application of the thermal penalty term causes the scores of high-frequency actions to be deducted more points as the central junction temperature rises, thereby changing the relative score ranking of each frequency level while keeping the action set unchanged, achieving a smooth transition from high frequency to low frequency.

[0132] Within the emergency high-temperature zone, the chip temperature is very close to the critical point where hardware-forced frequency reduction or shutdown is required. The on-chip control core executes an active risk avoidance and frequency reduction strategy: First, it restores the low-frequency action range that was temporarily pruned due to low scores, and restores the low-frequency actions marked as invalid as valid through the action mask table, allowing the system to obtain a safe frequency reduction path at a lower frequency; Second, it limits the highest selectable frequency range, marking all frequency actions above the predetermined highest frequency range as invalid in the action mask table, actively guiding the search range to a lower frequency range. After adjusting the action mask table, the on-chip control core re-executes scoring and selection from the updated set of valid actions.

[0133] Through a linkage mechanism between temperature grading and action space switching, the system maximizes performance in the normal temperature range, achieves a smooth transition from high to low frequency through thermal penalties in the warning temperature range, and forces a switch to a safe frequency reduction path through low-frequency recovery and high-frequency limitation in the emergency high-temperature range. This forms a complete temperature-graded response system from performance optimization to smooth frequency reduction and then to forced safety. Because the action mask table maintains the valid / invalid state of actions at each frequency uniformly across temperature ranges, the strategy switching between different temperature ranges is driven by the same data structure, avoiding state conflicts or decision errors caused by inconsistent switching logic.

[0134] Based on the thermal sensing frequency adjustment method, this application also provides a thermal sensing frequency adjustment system. The following will combine... Figure 5 The system is described in detail.

[0135] Figure 5 A schematic block diagram of a thermal sensing frequency adjustment system according to an embodiment of this application is shown.

[0136] like Figure 5 As shown, the thermal sensing frequency adjustment system of this embodiment is disposed inside the accelerator chip. The system includes:

[0137] Temperature convergence unit 510 is configured to fuse temperature signals from multiple thermal sensors inside the acceleration chip and output the center junction temperature.

[0138] The on-chip intelligent control module 520 includes an on-chip control core, a shared state buffer, and an out-of-band control link interface. The on-chip control core is connected to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface. The shared state buffer stores the service load characteristics of the host processor side.

[0139] The on-chip control core is configured to read service load characteristics from the shared state buffer and read the central junction temperature from the temperature aggregation unit. It constructs a cross-layer state vector based on the service load characteristics and the central junction temperature, inputs the cross-layer state vector into the decision model to score each frequency action in the frequency action set, and selects the target frequency based on the scoring results.

[0140] The dynamic voltage and frequency adjustment control interface 530 is connected to the on-chip intelligent control module via an out-of-band control link interface. It is configured to receive control values ​​corresponding to the target frequency and drive the clock unit and / or voltage adjustment unit to perform frequency switching.

[0141] According to an embodiment of this application, a computer program product is also provided, including a computer program or instructions that, when executed by a processor, implement the steps of the method.

[0142] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0143] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0144] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

Claims

1. A method for adjusting the frequency of thermal sensing, characterized in that, The method is applied to a computing platform, which includes a host processor and an acceleration chip. The acceleration chip internally houses an on-chip intelligent control module, a temperature convergence unit, and a dynamic voltage and frequency adjustment control interface. The on-chip intelligent control module includes an on-chip control core, a shared state buffer, and an out-of-band control link interface. The on-chip control core is connected to the dynamic voltage and frequency adjustment control interface via the out-of-band control link interface. The shared state buffer stores the service load characteristics of the host processor side. The method includes: The service load characteristics are read from the shared state buffer, and the central junction temperature is read from the temperature aggregation unit. The central junction temperature is obtained by the temperature aggregation unit through the fusion processing of temperature signals from multiple thermal sensors inside the acceleration chip. Construct a cross-layer state vector based on the business load characteristics and the central junction temperature; The cross-layer state vector is input into the decision model to score each frequency action in the frequency action set, and the target frequency is selected from the frequency action set based on the scoring results. The control value corresponding to the target frequency is written to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface to drive the clock unit and / or voltage adjustment unit to perform frequency switching.

2. The method according to claim 1, characterized in that, The sampling period for the service load characteristics is the first sampling period, and the execution period of the on-chip control core is the second sampling period, wherein the second sampling period is shorter than the first sampling period.

3. The method according to claim 1, characterized in that, The step of reading the service load characteristics from the shared state cache includes: Determine whether the service load characteristics in the shared state cache have been updated; If the service load characteristics have been updated, read the current service load characteristics; If the service load characteristics have not been updated, the service load characteristics of the previous first sampling period shall be kept unchanged and used as the service load characteristics of the current period.

4. The method according to claim 1, characterized in that, The cross-layer state vector also includes the microarchitectural features of the acceleration chip, which include at least one of front-end constrained ratio, memory constrained ratio, and instruction retirement rate.

5. The method according to claim 1, characterized in that, Also includes: In response to the central junction temperature being higher than or equal to a first preset threshold and lower than a second preset threshold, a thermal penalty term is introduced into the scoring function of the decision model, and the thermal penalty term increases as the central junction temperature increases. If the central junction temperature is higher than or equal to a third preset threshold, the temporarily pruned low-frequency operation is restored, and the highest selectable frequency level is limited.

6. The method according to claim 1, characterized in that, The frequency action set includes multiple discrete frequency levels, the decision model maintains historical score statistics for each frequency action, and the method further includes: Based on the historical scoring statistics of each frequency action, frequency actions that are continuously below the preset threshold and the low frequency range below them are marked as low exploration value ranges. Temporary pruning is performed on the frequency actions corresponding to the low exploration value range using an action mask table.

7. The method according to claim 1, characterized in that, Also includes: In the subsequent control cycle after the frequency switch, a feedback evaluation result for the target frequency is generated based on the power consumption information, instruction retirement rate information and the center junction temperature. The parameters of the decision-making model are incrementally updated based on the feedback evaluation results.

8. The method according to claim 1, characterized in that, The step of writing the control value corresponding to the target frequency to the dynamic voltage-frequency adjustment control interface through the out-of-band control link interface includes: In response to the difference between the target frequency and the current frequency being greater than a preset step size threshold, the target frequency is decomposed into multiple intermediate frequencies; In multiple control cycles, control values ​​corresponding to the multiple intermediate frequencies are gradually written to the dynamic voltage and frequency adjustment control interface.

9. A thermal sensing frequency adjustment system, characterized in that, The system is located inside the acceleration chip, and the system includes: The temperature convergence unit is configured to fuse temperature signals from multiple thermal sensors inside the acceleration chip and output the center junction temperature. The on-chip intelligent control module includes an on-chip control core, a shared state buffer, and an out-of-band control link interface. The on-chip control core is connected to the dynamic voltage and frequency adjustment control interface through the out-of-band control link interface. The shared state buffer stores the service load characteristics of the host processor side. The on-chip control core is configured to read service load characteristics from the shared state buffer and read the central junction temperature from the temperature aggregation unit, construct a cross-layer state vector based on the service load characteristics and the central junction temperature, input the cross-layer state vector into the decision model to score each frequency action in the frequency action set, and select the target frequency based on the scoring results. The dynamic voltage and frequency adjustment control interface is connected to the on-chip intelligent control module through the out-of-band control link interface. It is configured to receive the control value corresponding to the target frequency and drive the clock unit and / or voltage adjustment unit to perform frequency switching.

10. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method according to any one of claims 1 to 8.

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