Debugging system and method for memory buffer chip and electronic device

Abstract

The application provides a debugging system and method of a memory buffer chip and an electronic device. A debugging subunit is in communication connection with a host through a first bus, and in communication connection with the memory buffer chip through a second bus. The first bus and the second bus are not connected to a main data path between the host and the memory buffer chip. The host is configured to send a debugging command to the debugging subunit. The debugging subunit is configured to execute the debugging command to complete a related debugging operation of the memory buffer chip. The state register and / or the control register in the memory buffer chip are modified through the debugging subunit. During the debugging process of the memory buffer chip, parameters in the BIOS of the host do not need to be modified, and the memory buffer chip does not need to be restarted. The iteration period of chip parameter optimization is shortened from minutes to seconds, and the debugging efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a debugging system and method for a memory buffer chip, as well as an electronic device. Background Technology

[0002] In modern server memory systems, the Registering Clock Driver (RCD) is a core component of Registered DIMM (RDIMM) memory modules. It is responsible for buffering and re-driving command / address signals to reduce the load on the memory controller and support higher capacity and higher frequency.

[0003] Meanwhile, the Multiplexed RankDIMM (MRDIMM) architecture for higher bandwidth introduces a Multiplexed Registering Clock Driver (MRCD) and Multiplexed Data Buffer (MDB) chipset, which improves bandwidth through data multiplexing technology.

[0004] Ensuring debugging efficiency for the aforementioned memory buffer chips (RCD, MRCD, and MDB) has become a pressing issue. Summary of the Invention

[0005] The purpose of this invention is to provide a debugging system and method for memory buffer chips, as well as an electronic device, to improve the above-mentioned problems.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a debugging system for a memory buffer chip, the debugging system for the memory buffer chip comprising: a host, a debugging subunit, and a memory buffer chip; The debugging subunit is connected to the host via a first bus and is connected to the memory buffer chip via a second bus. The first bus and the second bus are not connected to the main data path between the host memory buffer chip. The host is used to send debugging commands to the debugging subunit; The debugging subunit is used to execute the debugging command to complete the relevant debugging operations of the memory buffer chip.

[0007] Normally, debugging a memory buffer chip requires modifying parameters in the host BIOS and saving and restarting before the debugging code logic of the memory buffer chip can be entered. Because this invention adds a debugging subunit, which can modify the status registers and / or control registers in the memory buffer chip, the debugging process no longer requires modifying parameters in the host BIOS, thus eliminating the need for a restart. This reduces the iteration cycle for chip parameter optimization from minutes to seconds, significantly improving debugging efficiency.

[0008] Optionally, the memory buffer chip has reserved debugging contacts during packaging; The debugging subunit is connected to the debugging contact via the second bus; During the non-debugging phase, the debugging contact is in a high-resistance state; during the debugging phase, the debugging contact is in a low-resistance state.

[0009] During non-debugging phases, i.e., normal operation, the contacts are in a high-resistance state, which does not affect signal integrity. During the debugging phase, the debugging contacts are in a low-resistance state. As a communication interface, the debugging bus is physically isolated from the main data path, does not come into contact with critical signals, and the measurement results are accurate and reliable.

[0010] Optionally, the power supply of the debugging subunit is isolated from the power supply domain of the memory buffer chip. Even if the host system fails POST or the core power supply of the memory buffer chip is abnormal, the debugging subunit can still operate and output debugging-related data through reserved contacts.

[0011] Optionally, when memory training fails, the debugging subunit is used to read the status register and control register in the memory buffer chip and feed the reading result back to the host. The host is used to transmit the read results of memory training failures to external devices for analysis of the reasons for memory training failures.

[0012] The debugging subunit is powered and operates independently. Even if the system screen is black, debugging data can still be read, reducing the problem location time from several days to several hours and solving the debugging problem of POST failure.

[0013] Optionally, the debugging subunit is used to receive the debugging command transmitted by the host and parse the debugging command to obtain a parsing result including the operation type, target address, and target data length. When the operation type is a write operation, the parsing result also includes the target data to be written. The debugging subunit is used to perform corresponding debugging operations according to the parsing results, and to feed back the execution results of the debugging operations to the host. When the operation type is a read operation, the execution result is the read result data with a length equal to the target data length obtained by the debugging subunit from reading the target address; when the operation type is a write operation, the execution result is the operation confirmation information, which is the comparison result between the verification data with a length equal to the target data length obtained by the debugging subunit from reading the target address after completing the debugging operation and the target written data. The host is used to determine whether the current stage of debugging is successful based on the execution result. If the debugging is unsuccessful, it determines whether the number of times the debugging command is executed in the current stage has reached a set threshold. If it has not reached the threshold, it repeatedly sends the debugging command to the debugging subunit. If it has reached the threshold or the debugging is successful, it obtains the debugging command corresponding to the next stage and sends the debugging command corresponding to the next stage to the debugging subunit.

[0014] The parameters are written directly to the internal registers of the memory buffer chip via the debugging subunit, and the modified parameters take effect immediately without the need to restart the system.

[0015] Optionally, the host's BIOS firmware includes memory reference code firmware and debug code firmware; The memory reference code firmware is used to generate corresponding debugging requests according to the debugging phase, and the debugging requests include read requests and write requests. The debug code firmware is used to encapsulate the debug request to obtain the corresponding debug command, and send the debug command to the debug subunit through the first bus; The debug code firmware is also used to receive the return data from the debug subunit and extract the target-related information from the return data to the memory reference code firmware; The memory reference code firmware is used to determine whether the debugging of this stage is successful based on the target-related information.

[0016] By integrating debug code firmware into the BIOS / MRC, the MRC can initiate debug operations directly during training without the need for an external debugger. Traditional methods require specialized equipment such as logic analyzers and oscilloscopes costing tens to hundreds of thousands of dollars, while this invention only requires a standard SPI interface and a low-cost debug subunit (MCU chip), significantly reducing debug hardware costs.

[0017] Optionally, when the host's BIOS starts, the host is used to initialize the first bus; After the first bus initialization is completed, the host is used to detect whether the debugging subunit is online. If it is online, the host obtains the current version information of the debugging subunit and verifies and compares the current version information with the historically stored version information. If the verification and comparison pass, the host configures the initialization parameters of the debugging subunit, thereby enabling the debugging subunit to enter the debugging startup mode.

[0018] Verification using version information prevents malicious tampering by external devices and ensures the security of debugging.

[0019] Secondly, embodiments of the present invention provide a debugging method for a memory buffer chip, applied to the aforementioned debugging system for a memory buffer chip, the method comprising: The host sends a debugging command to the debugging subunit; The debugging subunit executes the debugging command to complete the relevant debugging operations of the memory buffer chip.

[0020] Thirdly, embodiments of the present invention provide an electronic device, including: the debugging system for the memory buffer chip described above.

[0021] Compared to existing technologies, the present invention provides a debugging system, method, and electronic device for a memory buffer chip. The debugging subunit is connected to the host via a first bus and to the memory buffer chip via a second bus. Neither the first nor the second bus is connected to the main data path between the host and the memory buffer chip. The host sends debugging commands to the debugging subunit, which executes these commands to complete the relevant debugging operations on the memory buffer chip. By modifying the status registers and / or control registers in the memory buffer chip through the debugging subunit, the debugging process does not require modification of parameters in the host BIOS or a restart. The iteration cycle for chip parameter optimization is shortened from minutes to seconds, improving debugging efficiency.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a debugging system for a memory buffer chip provided in an embodiment of the present invention.

[0025] Figure 2 This is a hardware connection diagram of the SPI bus provided in an embodiment of the present invention.

[0026] Figure 3 This is a flowchart illustrating the debugging method for a memory buffer chip provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0029] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0031] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a debugging system for a memory buffer chip provided in an embodiment of the present invention. The debugging system for the memory buffer chip includes: a host, a debugging subunit, and a memory buffer chip.

[0032] The host unit can be, but is not limited to, a Central Processing Unit (CPU) that deploys BIOS firmware. This means the CPU has a Basic Input / Output System (BIOS), and the BIOS firmware includes Memory Reference Code (MRC). The MRC is the core module in the BIOS responsible for memory initialization, acquiring optimal parameters for the memory controller and memory buffer chips (including DQ / DQS delay, ODT termination, Vref reference voltage, DFE coefficient, etc.) through a training process. The debug subunit can, but is not limited to, a Microcontroller Unit (MCU).

[0033] The debugging subunit communicates with the host via the first bus and communicates with the memory buffer chip via the second bus. The first and second buses are not connected to the main data path between the host and the memory buffer chip (in the electronic device).

[0034] The first and second buses can be either an Inter-Integrated Circuit (I2C) bus or a Serial Peripheral Interface (SPI) bus.

[0035] The host is used to send debugging commands to the debugging subunit.

[0036] The debugging subunit is used to execute debugging commands to complete the relevant debugging operations of the memory buffer chip, including reading the internal state of the memory buffer chip, modifying parameters, and capturing debugging data.

[0037] This invention provides a debugging system for a memory buffer chip. Typically, debugging a memory buffer chip requires modifying parameters in the host BIOS and saving and restarting before the debugging code logic can be accessed. Because this invention adds a debugging subunit, which can modify the status registers and / or control registers in the memory buffer chip, the debugging process no longer requires modifying the host BIOS parameters, thus eliminating the need for a restart. This reduces the iteration cycle for chip parameter optimization from minutes to seconds, significantly improving debugging efficiency.

[0038] The debugging path, consisting of the first bus and the second bus, is not connected to the main data path between the host and the memory buffer chip in the electronic device. The debugging path is physically isolated from the main data path and does not interfere with signal integrity.

[0039] Optionally, the memory buffer chip is packaged with reserved debugging contacts, including clock signal (CLK) contacts, data signal (DATA) contacts, external trigger signal (TRIG) contacts, and alarm signal (ALERT) contacts.

[0040] The debugging subunit is connected to the debugging contacts via a second bus.

[0041] During the non-debugging phase, the debugging contact is in a high-resistance state; during the debugging phase, the debugging contact is in a low-resistance state.

[0042] During normal operation (outside of debugging phase), the contacts are in a high-resistance state, which does not affect signal integrity. During debugging phase, the debugging contacts are in a low-resistance state, serving as a communication interface. State switching can be achieved via buttons, toggle switches, or software commands.

[0043] Traditional debugging methods require external devices to connect to the memory buffer chip via probes. Probe contact introduces additional load, affects signal integrity, and may distort measurement results. The debugging bus of this invention is physically isolated from the main data path, does not contact critical signals, and ensures accurate and reliable measurement results.

[0044] Optionally, the power supply of the debugging subunit is isolated from the power supply domain of the memory buffer chip.

[0045] Even if the host system fails to POST or the core power supply of the memory buffer chip is abnormal, the debugging subunit can still work and output debugging-related data through reserved contacts.

[0046] Optionally, when memory training fails (POST failure), the debug subunit is used to read the status register and control register in the memory buffer chip and feed the reading results back to the host; The host is used to transmit the read results of memory training failures to external devices for analysis of the reasons for memory training failures.

[0047] In traditional methods, when the system fails to POST, all debugging tools become essentially ineffective, and one can only rely on the POST Code LED and blind scanning with an oscilloscope. The debugging subunit of this invention is independently powered and operates independently, and can still read debugging data even when the system screen is black, reducing the problem location time from several days to several hours and solving the debugging problem of POST failure.

[0048] Regarding the specific process of the debugging subunit executing debugging commands, this embodiment of the invention also provides an optional implementation method, please refer to the following. The specific process of the debugging subunit executing debugging commands includes: The debugging subunit is used to receive debugging commands transmitted by the host and parse the debugging commands to obtain a parsing result including the operation type, target address, and target data length. When the operation type is a write operation, the parsing result also includes the target data to be written. The debugging subunit is used to perform corresponding debugging operations according to the parsing results and to feed back the results of the debugging operations to the host. When the operation type is a read operation, the execution result is the read result data with a length equal to the target data length obtained by the debugging subunit from reading the target address; when the operation type is a write operation, the execution result is the operation confirmation information, which is the comparison result between the verification data with a length equal to the target data length obtained by the debugging subunit from reading the target address after completing the debugging operation and the target written data. A read operation refers to retrieving the internal status registers or function registers of the memory buffer chip; a write operation refers to modifying the register parameters of the memory buffer chip. Write operations modify register parameters of the memory buffer chip, including but not limited to: On-Die Termination (ODT) values, Voltage Reference (Vref), Decision Feedback Equalization (DFE) coefficients, and Continuous-Time Linear Equalizer (CTLE) settings.

[0049] The host is used to determine whether the current stage of debugging is successful based on the execution result. If the debugging is unsuccessful, it determines whether the number of times the debugging command is executed in the current stage has reached the set threshold. If it has not reached the threshold, it repeatedly sends the debugging command to the debugging subunit. If it has reached the threshold or the debugging is successful, it obtains the debugging command corresponding to the next stage and sends the debugging command corresponding to the next stage to the debugging subunit.

[0050] For RCD, the parameters that can be read and written through the debugging subunit include: output drive strength, ODT termination value, PLL division ratio, and clock phase fine-tuning; For MRCD, the parameters that can be read and written through the debug subunit include: multiplexing logic configuration, clock allocation parameters, and output driver settings. For MDB, the parameters that can be read and written through the debug sub-unit include: DFE coefficients, CTLE settings, equalizer parameters, and data channel configuration.

[0051] Parameters can be directly written to the internal registers of the memory buffer chip (RCD / MRCD / MDB) via the debug subunit, and the modified parameters take effect immediately without requiring a system restart. Hot updates of chip-level parameters such as ODT, Vref, DFE coefficients, and drive strength are supported.

[0052] Optionally, the host's BIOS firmware includes memory reference code firmware and debug code firmware; The memory reference code firmware is used to generate corresponding debug requests during the debugging phase. Debug requests include read requests and write requests. Read requests also include the target address and target data length, while write requests also include the target address, target data length, and target write data.

[0053] The debug code firmware is used to encapsulate debug requests to obtain corresponding debug commands, and then send the debug commands to the debug subunit via the first bus; When a read request is received, a debug command with the operation type of read operation is generated. This debug command includes the operation type identifier, target address, and target data length corresponding to the read operation. When a read request is received, a debug command with the operation type of write operation is generated. The debug command includes the operation type identifier corresponding to the write operation, the target address, the target data length, and the target data to be written. The debug code firmware is also used to receive return data from the debug subunit and extract target-related information from the return data for the memory reference code firmware.

[0054] The returned data includes, but is not limited to, the execution results. It should be noted that the rules for extracting target-related information for each type of returned data are pre-configured.

[0055] The memory reference code firmware is used to determine whether this stage of debugging has been successful based on target-related information.

[0056] By integrating debug code firmware into the BIOS / MRC, the MRC can initiate debug operations directly during training without the need for an external debugger. Traditional methods require specialized equipment such as logic analyzers and oscilloscopes costing tens to hundreds of thousands of dollars, while this invention only requires a standard SPI interface and a low-cost debug subunit (MCU chip), significantly reducing debug hardware costs.

[0057] Traditional methods cannot read the internal register states of RCD / MRCD / MDB, making it difficult to distinguish between logic problems and signal integrity issues; this invention can directly read the internal state of the chip through the debugging subunit, accurately locating the root cause of the problem.

[0058] Traditional debugging relies on manual operation of external devices, which is inefficient and prone to errors. This invention integrates debugging code into BIOS / MRC to achieve an automated and programmable debugging process.

[0059] The example manual uses the SPI bus. The pin definitions of SPI are shown in Table 1 below: Table 1

[0060] Please refer to Figure 2 , Figure 2 This is a hardware connection diagram of the SPI bus provided in an embodiment of the present invention.

[0061] During initialization, set the SPI clock frequency (e.g., 10MHz) and operating mode (e.g., mode 0). The chip select is high (not selected) by default. When sending data, pull the chip select low and send data byte by byte. After sending, pull the chip select high. When receiving data, pull the chip select low and read data byte by byte. After reading, pull the chip select high.

[0062] For the command frame format of debugging commands, please refer to Table 2 below; for the definition of command codes, please refer to Table 3 below. Table 2

[0063] Table 3

[0064] It should be understood that the debug code firmware can write trigger conditions into the trigger configuration register of the debug subunit via bus commands (SPI commands).

[0065] Please refer to Table 4 below for the API interfaces in the embodiments of this invention: Table 4

[0066] Optionally, the host initializes the first bus (and the second bus) during the host's BIOS startup.

[0067] After the first bus initialization is completed, the host is used to detect whether the debug subunit is online. If it is not online, it exits debugging. If it is online, it obtains the current version information of the debug subunit and verifies and compares the current version information with the historically stored version information. If the verification and comparison pass, it configures the initialization parameters of the debug subunit, thereby enabling the debug subunit to enter the debug startup mode.

[0068] Verification using version information prevents malicious tampering by external devices and ensures the security of debugging.

[0069] Optionally, the debug subunit is equipped with a circular buffer (Trace Buffer) to continuously record the internal bus transactions of the memory buffer chip. The internal bus transactions include information related to the debug commands executed by the memory buffer chip (including operation type (read / write), target address, and data length).

[0070] The host (debug code firmware) is used to write trigger conditions into the trigger configuration register of the debug subunit via bus commands (SPI commands).

[0071] The debugging subunit is used to detect the target signal in the trigger condition. When the target signal meets the trigger condition, it executes a preset trigger action, which includes freezing the circular buffer and setting the status flag. The host can poll the status flags of the debug subunit via SPI. The host then reads the contents of the circular buffer and performs analysis once the status flags are set.

[0072] This invention also provides a debugging method for a memory buffer chip, applied to the aforementioned memory buffer chip debugging system. Please refer to [link / reference needed]. Figure 3 , Figure 3 This is a flowchart illustrating the debugging method for a memory buffer chip provided in an embodiment of the present invention. The debugging method for the memory buffer chip includes steps S10 and S20, as detailed below.

[0073] S10, the host sends a debugging command to the debugging subunit.

[0074] S20, the debug subunit executes debug commands to complete the relevant debug operations of the memory buffer chip.

[0075] This invention also provides an electronic device, which includes: a debugging system for the memory buffer chip described above.

[0076] In summary, the present invention provides a debugging system, method, and electronic device for a memory buffer chip. A debugging subunit is communicatively connected to the host via a first bus and to the memory buffer chip via a second bus. Neither the first nor the second bus is connected to the main data path between the host and the memory buffer chip. The host sends debugging commands to the debugging subunit, which executes these commands to complete the relevant debugging operations on the memory buffer chip. By modifying the status registers and / or control registers in the memory buffer chip through the debugging subunit, the debugging process does not require modification of parameters in the host BIOS or a restart. The iteration cycle for chip parameter optimization is shortened from minutes to seconds, improving debugging efficiency.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0078] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A debugging system for a memory buffer chip, characterized in that, The debugging system for the memory buffer chip includes: a host, a debugging subunit, and a memory buffer chip; The debugging subunit is connected to the host via a first bus and is connected to the memory buffer chip via a second bus. The first bus and the second bus are not connected to the main data path between the host memory buffer chip. The host is used to send debugging commands to the debugging subunit; The debugging subunit is used to execute the debugging command to complete the relevant debugging operations of the memory buffer chip.

2. The debugging system for the memory buffer chip as described in claim 1, characterized in that, The memory buffer chip has pre-reserved debugging contacts during packaging; The debugging subunit is connected to the debugging contact via the second bus; During the non-debugging phase, the debugging contact is in a high-resistance state; During the commissioning phase, the commissioning contact is in a low-resistance state.

3. The debugging system for the memory buffer chip as described in claim 2, characterized in that, The power supply of the debugging subunit is isolated from the power supply domain of the memory buffer chip.

4. The debugging system for the memory buffer chip as described in claim 1, characterized in that, When memory training fails, the debugging subunit is used to read the status register and control register in the memory buffer chip and feed the reading result back to the host. The host is used to transmit the read results of memory training failures to external devices for analysis of the reasons for memory training failures.

5. The debugging system for the memory buffer chip as described in claim 1, characterized in that, The debugging subunit is used to receive the debugging command transmitted by the host and parse the debugging command to obtain a parsing result including the operation type, target address, and target data length. When the operation type is a write operation, the parsing result also includes the target data to be written. The debugging subunit is used to perform corresponding debugging operations according to the parsing results, and to feed back the execution results of the debugging operations to the host. When the operation type is a read operation, the execution result is the read result data with a length equal to the target data length obtained by the debugging subunit from reading the target address; When the operation type is a write operation, the execution result is an operation confirmation message. The operation confirmation message is the comparison result of the verification data with the target data length obtained by reading the target address after the debugging subunit completes the debugging operation and the target written data. The host is used to determine whether the current stage of debugging is successful based on the execution result. If the debugging is unsuccessful, it determines whether the number of times the debugging command is executed in the current stage has reached a set threshold. If it has not reached the threshold, it repeatedly sends the debugging command to the debugging subunit. If it has reached the threshold or the debugging is successful, it obtains the debugging command corresponding to the next stage and sends the debugging command corresponding to the next stage to the debugging subunit.

6. The debugging system for the memory buffer chip as described in claim 1, characterized in that, The host's BIOS firmware includes memory reference code firmware and debug code firmware; The memory reference code firmware is used to generate corresponding debugging requests according to the debugging phase, and the debugging requests include read requests and write requests. The debug code firmware is used to encapsulate the debug request to obtain the corresponding debug command, and send the debug command to the debug subunit through the first bus; The debug code firmware is also used to receive the return data from the debug subunit and extract the target-related information from the return data to the memory reference code firmware; The memory reference code firmware is used to determine whether the debugging of this stage is successful based on the target-related information.

7. The debugging system for the memory buffer chip as described in claim 1, characterized in that, When the host computer's BIOS starts, the host computer initializes the first bus. After the first bus initialization is completed, the host is used to detect whether the debugging subunit is online. If it is online, the host obtains the current version information of the debugging subunit and verifies and compares the current version information with the historically stored version information. If the verification and comparison pass, the host configures the initialization parameters of the debugging subunit, thereby enabling the debugging subunit to enter the debugging startup mode.

8. The debugging system for the memory buffer chip as described in claim 1, characterized in that, The debugging subunit is equipped with a circular buffer for continuously recording the internal bus transactions of the memory buffer chip. The internal bus transactions include information related to the debugging commands executed by the memory buffer chip. The host is used to write the trigger conditions into the trigger configuration register of the debug subunit via bus commands; The debugging subunit is used to detect the target signal in the triggering condition. When the target signal meets the triggering condition, a preset triggering action is executed. The triggering action includes freezing the circular buffer and setting the status flag. The host is used to read the contents of the circular buffer and perform analysis when the status flag is set.

9. A debugging method for a memory buffer chip, characterized in that, A debugging system applied to the memory buffer chip according to any one of claims 1-8, the method comprising: The host sends a debugging command to the debugging subunit; The debugging subunit executes the debugging command to complete the relevant debugging operations of the memory buffer chip.

10. An electronic device, characterized in that, include: The debugging system for the memory buffer chip according to any one of claims 1-8.

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