Dynamic partition switching method and apparatus based on hybrid mode

Abstract

The application discloses a dynamic partition switching method and device based on a mixed mode. The method comprises the following steps: monitoring host write heat in real time, judging a write mode based on short-term and long-term window statistics; combining the write mode and pSLC occupancy rate, and using a decision engine with a lag control strategy to determine whether and how to adjust the partition. When expanding pSLC, blocks are selected from a TLC idle block pool for conversion; when reducing pSLC, valid data is migrated, erased and marked as a TLC mode. When the pSLC occupancy reaches a threshold, a folding operation is performed, data is moved to a TLC area, and an idle-aware scheduling strategy is used to dynamically adjust the rate according to the host IO active state. Through the method of the application, fine mode switching and data migration scheduling at the block level are realized, and data consistency during partition adjustment is ensured. Not only the deficiencies in the prior art are overcome, but also the flexibility and efficiency of the system are greatly improved.

Description

Technical Field

[0001] This invention relates to, and more specifically to, a method and apparatus for dynamic partition switching based on a hybrid mode. Background Technology

[0002] In current hybrid eMMC (Embedded Multi-Media Card) designs, NAND Flash (Not AND Flash Memory) is divided into pSLC (pseudo-Single Level Cell) and TLC (Triple-Level Cell) areas. The former is known for its high endurance and speed (1 bit / cell) but low storage density, while the latter provides high-density storage (3 bits / cell) but is slower. A typical partition ratio is 25% pSLC and 75% TLC, fixed at the factory. While this design balances performance and capacity requirements to some extent, it exposes a series of problems in specific application scenarios. For example, in write-intensive scenarios such as video surveillance, the pSLC area quickly saturates, leading to cache breakdown and severely impacting system performance; while in data storage disk applications, the pSLC area remains idle for extended periods, resulting in wasted capacity.

[0003] Existing hybrid eMMC solutions suffer from several significant drawbacks. First, under continuous write conditions, the pSLC region fills up rapidly, triggering cache breakdown and causing a sharp drop in write speed. Second, in sparse write scenarios, the fixed proportion of the pSLC region leads to unnecessary waste of storage capacity. Furthermore, the data folding operation required after the pSLC region is full competes for bandwidth with foreground I / O (Input / Output) operations, causing performance fluctuations. Finally, these solutions cannot adapt to changes in device write patterns over different time periods, resulting in an inability to maintain optimal performance throughout the device's lifecycle.

[0004] Numerous technical studies and patent applications have been published regarding NAND Flash mode switching, including JEDEC (Joint Electron Device Engineering Council) standards, papers from Samsung, Western Digital Technologies, IEEE Transactions, and related work from Kioxia Corporation. However, these existing technologies and literature primarily focus on static configuration or switching mechanisms based on simple thresholds, failing to effectively incorporate dynamic decision-making based on actual workload characteristics, remaining lifetime prediction, and urgency.

[0005] Therefore, it is necessary to design a new method to achieve fine-grained mode switching and data migration scheduling at the block level, while ensuring data consistency during partition adjustments. This not only overcomes the shortcomings of existing technologies but also significantly improves the system's flexibility and efficiency. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and apparatus for dynamic partition switching based on hybrid mode.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a dynamic partition switching method based on a hybrid mode, comprising: Real-time monitoring of host write activity, based on dual time scale statistics of short-term and long-term windows, to determine the current write mode; Based on the write mode and the current occupancy rate of the pSLC region, a partition adjustment decision engine determines whether to perform partition adjustment, and determines the adjustment direction and magnitude when deciding to perform. The partition adjustment decision engine adopts a hysteresis control strategy, which includes setting an upper limit ratio, a lower limit ratio, and a cooldown period for the pSLC region. When the decision is to expand the pSLC partition, select a block from the TLC free block pool and convert it to pSLC mode; when the decision is to shrink the pSLC partition, move the valid data in the pSLC block to be converted to other pSLC blocks, erase the block and update the type mark in the FTL mapping table to TLC mode, and add it to the TLC free block pool. When the pSLC area occupancy rate reaches a preset threshold, a folding operation is performed to re-encode the pSLC data and move it to the TLC area; The folding operation employs an idle-aware scheduling strategy, which dynamically adjusts the folding execution rate based on the host's I / O activity level.

[0008] The further technical solution is as follows: the current writing mode includes one of burst dense, continuous dense, normal or sparse; The write throughput monitoring uses an exponentially weighted moving average algorithm to calculate a smoothed estimate of the write throughput.

[0009] The further technical solution is as follows: the duration of the short-term window is shorter than the duration of the long-term window, the short-term window is used to respond to burst writes, and the long-term window is used to determine the steady-state write mode.

[0010] The further technical solution is as follows: the hysteresis control strategy includes: setting an upper limit ratio and a lower limit ratio for the pSLC region, setting a cooling period after the adjustment direction is confirmed, and using hysteresis control to avoid repeated oscillations at the threshold critical point.

[0011] The further technical solution is as follows: the process of converting a Block to pSLC mode or converting from pSLC mode includes: marking the state in the process of conversion, omitting valid data, erasing the Block, updating the type flag in the FTL mapping table, and adding it to the idle Block pool of the corresponding mode region.

[0012] The further technical solution is as follows: the idle awareness scheduling strategy includes: folding is executed at full speed during the host idle period, folding is executed at a limited speed during the host IO active period, and folding is paused when the pSLC occupancy rate exceeds a preset overload threshold.

[0013] Its further technical solutions include: When the internal temperature of the eMMC exceeds the preset temperature threshold, the folding operation is paused and resumed after the temperature drops below the preset recovery threshold.

[0014] The further technical solution is as follows: the expansion trigger condition of the hysteresis control strategy is that the current write mode is bursty dense or continuous dense and the pSLC area occupancy rate exceeds the upper limit ratio, and the reduction trigger condition is that the current write mode is sparse and the pSLC area occupancy rate is lower than the lower limit ratio.

[0015] The further technical solution is as follows: before performing the folding operation, the heat of the effective data in the pSLC area is evaluated, and the hot data is preferentially retained in the pSLC area, while the cold data is moved out to the TLC area through the folding operation.

[0016] The present invention also provides a dynamic partition switching device for pSLC / TLC hybrid mode, comprising: The write heat monitoring unit is used to monitor the host write heat in real time and determine the current write mode based on dual time scale statistics of short-term and long-term windows. The partition adjustment decision unit is used to determine whether to perform partition adjustment based on the write mode and the current occupancy rate of the pSLC region through the partition adjustment decision engine, and to determine the adjustment direction and adjustment magnitude when determining to perform adjustment. The partition adjustment decision engine adopts a hysteresis control strategy, which includes setting an upper limit ratio, a lower limit ratio, and a cooldown period for the pSLC region. The Block Role Conversion Unit is used to select a Block from the TLC Free Block Pool and convert it to pSLC mode when the decision is to expand the pSLC partition; when the decision is to shrink the pSLC partition, it moves the valid data in the pSLC Block to be converted to other pSLC Blocks, erases the Block and updates the type mark in the FTL mapping table to TLC mode, and adds it to the TLC Free Block Pool. The folding scheduling unit is used to perform folding operations when the pSLC area occupancy rate reaches a preset threshold. This involves re-encoding the pSLC data and moving it to the TLC area. An idle-aware scheduling strategy is used to dynamically adjust the folding execution rate based on the host I / O activity status.

[0017] The advantages of this invention compared to existing technologies are as follows: This invention monitors host write activity in real time and uses short-term and long-term window statistics to determine the current write mode. Based on the write mode and pSLC region occupancy, a hysteresis control strategy is employed, and the partition adjustment decision engine intelligently decides whether to perform partition adjustments, as well as their direction and magnitude. When expanding or shrinking the pSLC partition, precise data migration, erasure, and FTL mapping table updates ensure data consistency. When a preset threshold is reached, a folding operation is performed, re-encoding and moving the pSLC data to the TLC region. Simultaneously, an idle-aware scheduling strategy is applied to dynamically adjust the folding rate to adapt to changes in host I / O activity, thereby achieving block-level fine-grained mode switching and data migration scheduling. This not only overcomes the shortcomings of existing technologies but also significantly improves the system's flexibility and efficiency. Furthermore, this process considers the impact of temperature on operations, further ensuring the reliability of data processing and system stability.

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the dynamic partition switching method based on hybrid mode provided in an embodiment of the present invention; Figure 2 A schematic block diagram of a dynamic partition switching device based on a hybrid mode provided in an embodiment of the present invention; Figure 3A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] Please see Figure 1 , Figure 1 This is a flowchart illustrating a hybrid-mode-based dynamic partition switching method provided in an embodiment of the present invention. This hybrid-mode-based dynamic partition switching method is applied to a server. By real-time monitoring of host write activity and determining the current write mode based on short-term and long-term window statistics, a hysteresis control strategy is employed based on the write mode and pSLC region occupancy rate to determine whether to adjust the partition and the direction of adjustment. When expanding or shrinking the pSLC partition, precise data migration, erasure, and FTL mapping table update processes ensure data consistency. When a preset threshold is reached, a folding operation is performed, re-encoding and moving the pSLC data to the TLC region. An idle-aware scheduling strategy dynamically adjusts the folding rate based on the host's I / O activity, while also considering temperature factors for pause and resumption management. This method also includes a strategy of prioritizing hot data retention in the pSLC region to optimize read and write performance. Overall, it achieves block-level fine-grained mode switching and data migration scheduling, significantly improving the system's flexibility and efficiency, and addressing the shortcomings of existing technologies.

[0026] The method in this embodiment is applied to the controller firmware of an eMMC embedded storage device. eMMC (Embedded Multi Media Card) is an embedded non-volatile storage standard. The eMMC embedded storage device described in this invention integrates a NAND Flash storage array and a controller. The physical blocks in the NAND Flash storage array can be dynamically configured into pSLC (pseudo Single Level Cell) mode or TLC (Triple Level Cell) mode. pSLC mode simulates SLC operation by using a TLC physical block, storing only 1 bit of data per storage cell, offering high-speed writing and high endurance, but with lower storage density. TLC mode stores 3 bits of data per storage cell, offering high storage density but relatively slower write speed. The dynamic partition switching method described in this invention achieves adaptive adjustment of the ratio of pSLC and TLC regions through firmware-level logical scheduling without changing the hardware structure.

[0027] The dynamic partitioning management layer of the eMMC controller firmware mainly includes four core functional modules: a write heat monitor, a partition adjustment decision-maker, a block role manager, and a folding scheduler. The write heat monitor statistically analyzes host write behavior based on a dual-timescale window; the partition adjustment decision-maker generates partition adjustment instructions based on monitoring output and the current pSLC occupancy rate; the block role manager is responsible for executing specific block mode transitions; and the folding scheduler coordinates data merging and migration operations in the background and bandwidth contention for host I / O in the foreground. These modules work together, along with auxiliary data structures such as heat statistics tables, partition ratio tables, block status tables, oscillation protectors, and capacity calculators, to complete dynamic partitioning management.

[0028] Figure 1 This is a flowchart illustrating the dynamic partition switching method based on hybrid mode provided in this embodiment. Figure 1 As shown, the method includes the following steps S110 to S150.

[0029] S110: Real-time monitoring of host write activity, based on dual time scale statistics of short-term and long-term windows, to determine the current write mode.

[0030] In this embodiment, the current write mode includes one of burst-intensive, continuous-intensive, normal, or sparse; The write throughput monitoring uses an exponentially weighted moving average algorithm to calculate a smoothed estimate of the write throughput.

[0031] Host write activity refers to the amount and frequency of data written to the eMMC device by the host within a specific time window, typically quantified by write throughput (the number of bytes written per unit time). To balance rapid response to burst writes with accurate assessment of steady-state writes, this embodiment employs a dual-timescale monitoring mechanism combining short-term and long-term windows.

[0032] The duration of the short-term window is shorter than the duration of the long-term window. The short-term window is used to respond to burst writes, and the long-term window is used to determine the steady-state write mode.

[0033] The short-term window is set to a duration of 60 seconds, and its monitoring metrics include the instantaneous write throughput and the peak current occupancy of the pSLC region within this 60-second time interval. The purpose of the short-term window is to quickly capture sudden changes in host write behavior, such as the surge in write traffic that may occur when an in-vehicle IVI system starts up a dashcam. The long-term window is set to a duration of 3600 seconds, and its monitoring metrics include the average and peak write throughput within this 3600-second time interval. The purpose of the long-term window is to filter out short-term noise, determine the steady-state write mode of the device, and avoid frequent adjustments due to instantaneous fluctuations.

[0034] In addition to system-level write pattern determination, the write heat monitor also maintains a per-Block heat statistics table, recording the write counts for each physical block within both the short and long windows. Based on the dual-window count results, blocks are classified into dual-hot blocks (high write counts in both short and long windows), long-hot blocks (low write counts in the short window but high write counts in the long window), short-hot blocks (high write counts in the short window but low write counts in the long window), and cold blocks (low write counts in both windows). This per-Block heat classification result is passed to the Block Role Manager to guide subsequent heat assessment decisions during data migration.

[0035] Based on the write throughput data collected through the dual windows described above, this embodiment further employs an Exponentially Weighted Moving Average (EWMA) algorithm to calculate a smoothed estimate of the write throughput, thereby reducing the interference of random fluctuations on pattern judgment. The EWMA algorithm is calculated as S_t = α × X_t + (1-α) × S_{t-1}, where S_t represents the smoothed estimate at the current time, X_t represents the actual number of bytes written within the current time window, and α represents the smoothing coefficient. For short-term windows, the smoothing coefficient α_s is set to 0.2, giving higher weight to recent data so that the smoothed estimate can quickly track write changes; for long-term windows, the smoothing coefficient α_l is set to 0.02, giving higher weight to historical data so that the smoothed estimate reflects long-term trends.

[0036] To further enhance the predictability of partition adjustments, this embodiment introduces a trend extrapolation prediction model based on the aforementioned dual EWMA smoothing estimation. This trend extrapolation prediction model uses the deviation between the short-term and long-term smoothing estimates as a trend signal to predict the write throughput over the next N cycles. Its calculation formula is X_pred(t+N)=S_short(t)+N×[S_short(t)-S_long(t)]. Wherein, if the trend signal is positive, it indicates that the write rate is accelerating, prompting the system to prepare to expand the pSLC partition in advance; if the trend signal is negative, it indicates that the write rate is decelerating, prompting the system to consider shrinking the pSLC partition to release capacity.

[0037] Based on the aforementioned dual-window monitoring and prediction algorithm, this embodiment classifies the current write mode into the following four categories: Burst mode, where the write throughput is significantly higher than the long-term average within a short window and exhibits burst characteristics; Sustained mode, where the write throughput remains consistently high within a long window; Normal mode, where the write throughput is at a moderate level and fluctuates smoothly; and Idle mode, where the write throughput is extremely low or there are no write operations for a long time. The classification result of the current write mode will serve as one of the core inputs for subsequent partition adjustment decisions.

[0038] To verify the effectiveness of the write activity prediction algorithm, this embodiment uses 100 hours of onboard IVI test data for verification. Under a 10-second prediction window, the mean absolute error (MAE) is 0.5 MB / min, with a decision accuracy of 94%; under a 60-second prediction window, the MAE is 2.1 MB / min, with a decision accuracy of 89%; and under a 300-second prediction window, the MAE is 8.7 MB / min, with a decision accuracy of 82%. These verification results demonstrate that the dual-window monitoring and prediction mechanism of this embodiment can accurately predict host write behavior within an acceptable error range.

[0039] S120. Based on the writing mode and the current occupancy rate of the pSLC area, the partition adjustment decision engine determines whether to perform partition adjustment, and determines the adjustment direction and adjustment range when determining to perform. The partition adjustment decision engine adopts a hysteresis control strategy.

[0040] In this embodiment, the current pSLC region occupancy rate refers to the percentage of pSLC physical blocks currently occupied by valid data out of the total number of pSLC physical blocks. The partition adjustment decision engine is a logical decision unit integrated into the eMMC controller firmware. It receives the current write mode output by the write heat monitor and the current pSLC region occupancy rate fed back in real time by the capacity calculator, and comprehensively determines whether to trigger the expansion, reduction, or maintenance operation of the pSLC partition ratio.

[0041] The hysteresis control strategy includes: setting an upper limit ratio and a lower limit ratio for the pSLC region, setting a cooling period after the adjustment direction is confirmed, and using hysteresis control to avoid repeated oscillations at the threshold critical point.

[0042] The expansion trigger condition of the hysteresis control strategy is that the current write mode is bursty dense or continuous dense and the pSLC region occupancy rate exceeds the upper limit ratio, and the reduction trigger condition is that the current write mode is sparse and the pSLC region occupancy rate is lower than the lower limit ratio.

[0043] The lag control strategy also includes a trend confirmation mechanism: the partition adjustment decision engine will only officially trigger the partition adjustment operation when three consecutive monitoring windows indicate the same adjustment direction, thus avoiding misjudgment caused by instantaneous noise.

[0044] In the quantitative execution of the aforementioned hysteresis control strategy, the trigger condition for expanding the pSLC partition further requires that the short-term write throughput exceeds 120% of the upper limit threshold and lasts for at least 3 sampling cycles; the trigger condition for shrinking the pSLC partition further requires that the long-term write throughput is below 80% of the lower limit threshold and lasts for at least 30 sampling cycles. Furthermore, the amount of a single adjustment is limited to no more than 10% of the total number of blocks to avoid drastic oscillations.

[0045] To avoid repeated oscillations in the partition ratio around the threshold, the partition adjustment decision engine employs a hysteresis control strategy. The core of this hysteresis control strategy lies in introducing a dual protection mechanism of hysteresis interval and cooldown period. Specifically, an upper limit ratio and a lower limit ratio are set for the pSLC region. The upper limit ratio refers to the maximum capacity percentage that the pSLC region is allowed to reach, set to 50% of the total capacity in this embodiment; the lower limit ratio refers to the minimum capacity percentage that the pSLC region is allowed to shrink to, set to 5% of the total capacity in this embodiment. Hysteresis control means that no new adjustments are triggered within a preset interval near the target adjustment ratio. For example, when the pSLC partition ratio is within a hysteresis interval of ±5% of the target value, even if the monitored indicators fluctuate slightly, the partition adjustment decision engine maintains the current ratio unchanged. The cooldown period refers to the period after any partition adjustment operation is completed, during which the system will not perform adjustments in the same direction for a preset time. In this embodiment, the minimum cooldown period is 5 minutes; in another embodiment, for scenarios where write modes change slowly, the cooldown period can be extended to 24 hours to prevent frequent switching caused by instantaneous fluctuations in write load.

[0046] In the triggering logic of the hysteresis control strategy, the triggering condition for expanding the pSLC partition is that the current write mode is bursty or sustained intensive, and the current occupancy rate of the pSLC region exceeds the upper limit ratio; the triggering condition for shrinking the pSLC partition is that the current write mode is sparse, and the current occupancy rate of the pSLC region is lower than the lower limit ratio. To further enhance stability, the triggering conditions also include trend confirmation requirements: expansion triggering requires short-term write throughput to exceed 120% of the upper limit threshold and last for at least 3 sampling cycles; shrinking triggering requires long-term write throughput to be lower than 80% of the lower limit threshold and last for at least 30 sampling cycles. Furthermore, the single adjustment amount is limited to no more than 10% of the total number of blocks to achieve gradual adjustment.

[0047] The partition adjustment decision engine has a built-in rule matrix used to map the current write mode and the current pSLC region occupancy rate to specific adjustment actions and amounts. For example, when the current write mode is bursty and the pSLC occupancy rate is greater than 80%, the decision engine determines that the pSLC partition needs to be expanded, with an adjustment amount of increasing the total number of blocks by 10%; when the current write mode is bursty but the pSLC occupancy rate is less than 40%, the current ratio remains unchanged; when the current write mode is continuous and the pSLC occupancy rate is greater than 70%, the pSLC partition is expanded, with an adjustment amount of increasing the total number of blocks by 5%; when the current write mode is normal and the pSLC occupancy rate is between 40% and 70%, the current ratio remains unchanged; when the current write mode is sparse and the pSLC occupancy rate is less than 20%, the pSLC partition is shrunk, with an adjustment amount of reducing the total number of blocks by 5%; when the current write mode is sparse and the pSLC occupancy rate is less than 10%, the pSLC partition is shrunk, with an adjustment amount of reducing the total number of blocks by 10%.

[0048] This embodiment also introduces an adaptive threshold adjustment mechanism based on historical write patterns. For devices that have consistently exhibited write-intensive behavior, the system automatically lowers the long-term threshold triggered by pSLC shrinkage, ensuring that the pSLC partition maintains relatively ample buffer space and preventing cache breakdown during subsequent burst writes due to frequent shrinkage. For devices that have consistently exhibited write-sparse behavior, the system automatically lowers the short-term threshold triggered by pSLC expansion, ensuring that the pSLC partition only expands when necessary, reducing capacity waste. This adaptive threshold adjustment is achieved by analyzing a historical write pattern statistics table, ensuring that devices in different application scenarios can obtain the optimal partitioning strategy.

[0049] S130. When the decision is to expand the pSLC partition, select a block from the TLC free block pool and convert it to pSLC mode; when the decision is to shrink the pSLC partition, move the valid data in the pSLC block to be converted to other pSLCBlocks, erase the block and update the type mark in the FTL mapping table to TLC mode, and add it to the TLC free block pool.

[0050] In this embodiment, the process of converting a Block to pSLC mode or converting from pSLC mode includes: marking the state during conversion, omitting valid data, erasing the Block, updating the type flag in the FTL mapping table, and adding it to the idle Block pool of the corresponding mode region.

[0051] In this embodiment, the TLC idle block pool refers to a logical resource pool composed of physical blocks currently in TLC mode that do not store valid data. Similarly, the pSLC idle block pool is composed of physical blocks in pSLC mode that do not store valid data. The FTL mapping table (Flash Translation Layer Mapping Table) is a mapping data structure from logical addresses to physical addresses maintained by the eMMC controller. Each physical block corresponds to a status record, including metadata such as the block mode flag (TYPE_PSLC or TYPE_TLC), valid page bitmap, and erase count.

[0052] When the partition adjustment decision engine determines to expand the pSLC partition, the Block Role Manager selects a candidate Block from the TLC idle Block pool and performs a mode conversion from TLC Block to pSLC Block. When it determines to shrink the pSLC partition, the Block Role Manager selects the pSLC Block to be converted and performs the reverse conversion. The following details the Block role conversion process using the conversion of a pSLC Block to a TLC Block as an example.

[0053] First, the Block Role Manager marks the Block's status as "in transition" in the FTL mapping table. Blocks in the "in transition" state no longer accept new host write allocations, but read operations on valid data still function normally to ensure host I / O continuity. Next, the Block Role Manager traverses the Block's FTL mapping table entries, identifying all Pages containing valid data. A Page is the smallest read / write unit in NAND Flash, and a Block typically contains hundreds of Pages. For the identified valid data, the Block Role Manager reads it and writes it to other Blocks in pSLC mode, completing the data migration. After the data migration is complete, all Pages of the original Block are marked as invalid in the FTL mapping table.

[0054] Next, the Block Role Manager performs a Block Erase operation on the original Block, which involves sending the ONFI standard command sequence 0x60 to 0xD0 to complete the entire block erasure. Block Erase is a physical operation specific to NAND Flash, with a typical erasure time of 3 to 5 milliseconds. After erasure, the Block Role Manager updates the type flag of the Block in the FTL mapping table, changing TYPE_PSLC to TYPE_TLC, and initializes the metadata structures required for TLC mode, such as the three-layer voltage threshold configuration and page grouping information. Finally, the Block is added to the TLC free Block pool, making it available for subsequent TLC mode write allocation. The process of converting a TLC Block to a pSLC Block is the reverse of the above: after confirming that the TLC data has been migrated, the Block is erased, marked as TYPE_PSLC, and added to the pSLC free Block pool.

[0055] The total time for converting a single block is approximately 1 to 3 milliseconds (based on measured values ​​of an ARM Cortex-R5 processor at 400MHz). Converting 100 blocks in batches takes approximately 100 to 300 milliseconds. These conversion times are within an acceptable range for engineering purposes and will not significantly impact host foreground I / O.

[0056] To further improve block conversion efficiency, this embodiment introduces a collaborative optimization mechanism with the host file system. When the eMMC controller detects a TRIM or DISCARD command issued by the host file system, it prioritizes blocks within the range indicated by the TRIM command as candidate blocks for partition adjustment. Since data within the TRIM range has been marked as invalid by the host, mode conversion can be performed directly without data migration, thereby reducing conversion time by approximately 70%.

[0057] During the Block role conversion process, this embodiment also introduces a data heat assessment mechanism. This data heat assessment refers to analyzing the access frequency of valid data in the pSLC Block that is about to be converted to TLC mode, identifying hot and cold data. Hot data refers to data that has been frequently accessed or written recently, while cold data refers to data that has not been accessed for a long time. The classification results of dual-hot, long-hot, short-hot, and cold data recorded in the per-Block heat statistics table in the first step are directly used as the basis for data heat assessment. For identified hot data, it is preferentially retained in the pSLC area, i.e., moved out to other pSLC Blocks rather than converted to TLC mode with the original Block; for cold data, it is allowed to migrate to the TLC area with the Block conversion. This mechanism ensures that high-value hot data continues to enjoy the high-speed read / write characteristics of pSLC mode, while low-access-frequency cold data is migrated to the high-density TLC area to free up pSLC space.

[0058] At the per-block granularity, this embodiment further establishes a partition adjustment decision table based on dual-window hot-cold crossover. For dual-hot blocks with high write counts in both the short and long windows, they are determined to be stable hot data, and their pSLC mode remains unchanged. For long hot blocks with low write counts in the short window but high write counts in the long window, they are determined to be historical hot data, and their pSLC mode is maintained to preserve access performance. For short hot blocks with high write counts in the short window but low write counts in the long window, they are determined to be recently active data, and their pSLC mode is maintained. For cold blocks with low write counts in both the short and long windows, they are determined to be cold data, and when the partition is shrunk, they are preferentially migrated to the TLC area to achieve cold data degradation.

[0059] To address potential power outages during partition adjustment, this embodiment incorporates a robust power outage protection mechanism. A power outage refers to the sudden loss of power to the eMMC device during Block role transitions or FTL mapping table updates. This embodiment employs a journaling mechanism for the FTL mapping table, writing a log entry before each modification to the table, recording key information such as the operation type, target Block address, and the state before and after the modification. Upon power-up, the controller scans the log area and recovers any incomplete partition adjustment operations based on the logs. For Blocks in the "transitioning" state, the system prioritizes recovery: if data migration is complete, erasure and type update continue; if data migration is incomplete, the transition is rolled back, restoring the Block to its original state. This mechanism ensures that no data loss or Block type inconsistency occurs under any power outage scenario.

[0060] In eMMC devices with a multi-channel NAND architecture, this embodiment also introduces a partitioned load balancing mechanism. The multi-channel architecture refers to the eMMC controller simultaneously managing 2 to 4 independent NAND Flash channels, each with independent read and write bandwidth. To avoid localized overheating or channel bandwidth bottlenecks caused by concentrated partitioning operations on a single channel, the Block Role Manager prioritizes channels with lighter current write loads when allocating Block conversions. The load balancing algorithm employs a random weighted selection strategy, where channel weight is defined as 1 divided by the number of pending operations on the current channel plus 1. Channels with fewer pending operations have higher weights and a greater probability of being selected, thus achieving a uniform distribution of conversion operations across multiple channels.

[0061] S140. When the pSLC area occupancy rate reaches a preset threshold (e.g., 85%), a folding operation is performed to re-encode the pSLC data and move it to the TLC area; wherein, the folding operation adopts an idle-aware scheduling strategy, and the idle-aware scheduling strategy dynamically adjusts the folding execution rate according to the host IO activity status.

[0062] In this embodiment, the idle-aware scheduling strategy includes: executing folding at full speed during host idle periods, executing folding at a limited speed during host IO active periods, and pausing folding when the pSLC occupancy rate exceeds a preset overload threshold.

[0063] Before performing the folding operation, the availability of data in the pSLC area is assessed for its popularity. Hot data is prioritized and retained in the pSLC area, while cold data is moved to the TLC area via the folding operation. Once the pSLC occupancy rate drops below 70%, the folding operation is stopped to avoid unnecessary bandwidth contention between background data migration and foreground data writing.

[0064] In this embodiment, the folding operation refers to a data merging and relocation operation performed by the eMMC controller in the background when valid data already written in the pSLC region needs to be freed up. This operation involves reading pSLC format data, re-encoding it to TLC format, and writing it into the TLC region. The re-encoding refers to remapping 1-bit data originally stored at the SLC voltage threshold to one of eight voltage states according to the TLC's 3-bit encoding rules, and then writing it into the TLC physical page. The folding operation shares NAND channel bandwidth with the foreground host I / O, therefore a scheduling strategy is needed to coordinate resource contention between the two.

[0065] The idle-aware scheduling strategy refers to a scheduling mechanism that dynamically adjusts the folding execution intensity based on the activity status of the host IO queue. Specifically, when the eMMC controller detects that the host IO queue is idle (less than 2 pending commands), the folding scheduler starts full-speed folding to make full use of idle bandwidth for data migration; when the host IO queue is active (2 or more pending commands), the folding scheduler slows down execution, limiting the folding bandwidth to 50% of the maximum rate to prioritize the response performance of the foreground host IO; when the pSLC area occupancy rate exceeds a preset overload threshold (e.g., 80%), the folding scheduler pauses folding operations and uses all bandwidth for foreground writing to avoid a sharp drop in the performance of front-end direct-write TLC due to complete exhaustion of the pSLC area.

[0066] To further ensure system stability, the folding scheduler also integrates a temperature-sensing scheduling mechanism. When the internal temperature sensor of the eMMC detects that the NAND chip temperature exceeds a preset temperature threshold (e.g., 70°C), the folding operation is paused to reduce power consumption and heat generation caused by additional read and write operations; the folding operation automatically resumes after the temperature drops below a preset recovery threshold (e.g., 60°C).

[0067] This embodiment also introduces a folding budgeting system to strictly control the interference of folding on foreground I / O. The folding budgeting system means that within each 100-millisecond scheduling cycle, the folding operation occupies a maximum of 30 milliseconds (i.e., 30% of the cycle time), with the remaining 70 milliseconds guaranteeing the execution time of foreground host I / O. Combined with a write priority queue mechanism, the system performs strict priority scheduling for different types of write requests: the highest priority Q0 is allocated to FTL metadata updates and power-loss protection log writes; the second highest priority Q1 is allocated to host synchronous write requests; the medium priority Q2 is allocated to host ordinary write requests; and the lowest priority Q3 is allocated to folding background writes. Through the synergy of the above budgeting system and priority queue, the P99.9 write latency during partition rebalancing is controlled within 80 milliseconds, significantly better than the tail latency of over 500 milliseconds in uncontrolled scenarios.

[0068] Before performing the folding operation, this embodiment performs a heat assessment on the valid data in the pSLC region, prioritizing the retention of hot data in the pSLC region and migrating cold data to the TLC region through the folding operation. This heat assessment uses the same statistical logic as the data heat assessment during the Block role transition in the third step, ensuring that hot data receives continuous high-speed cache protection in the pSLC region. In continuous write scenarios such as video surveillance DVRs, this embodiment also introduces a write merging and folding time-slice rotation mechanism. The write merging refers to merging multiple small write requests into a single large write before performing folding, reducing the number of folding triggers; the folding time-slice rotation refers to dividing the folding operation into multiple small time slices and distributing them into the gaps between foreground I / O operations, avoiding prolonged channel occupation during folding.

[0069] This embodiment provides a quantitative analysis of the wear impact caused by folding operations. A single folding operation involves approximately 512 pSLC page reads, 512 TLC page programmings, and 1 pSLC block erase, equivalent to approximately 0.3 TLC P / E (Program / Erase) cycles of wear. Assuming 5,000 partition adjustments occur during the device's lifespan, totaling approximately 250,000 folds, the equivalent additional wear is approximately 9.2 TLC P / E cycles. Compared to the total pSLC lifespan (30,000 to 50,000 P / E cycles), this additional wear accounts for less than 0.03%, which is negligible in engineering practice.

[0070] To verify the long-term stability of this embodiment, a 1000-hour aging test was conducted on a 32GB pSLC / TLC hybrid eMMC sample. Approximately 850 partition adjustments were triggered during the test, and all adjustments were successfully completed without data loss or block state anomalies. The increase in total write amplification factor (WAF) caused by partition adjustments was approximately 3%, which is within an acceptable range.

[0071] This embodiment is also applicable to hybrid mode adaptation of QLC NAND (Quad Level Cell). In QLC mode, each storage cell stores 4 bits of data, and its storage density is 4 times that of pSLC, so the capacity gain of dynamic partitioning is more significant. Considering the characteristics of QLC NAND, this embodiment makes the following adaptation modifications: the upper limit ratio of pSLC regions is adjusted from 50% to 40% because the P / E lifetime of QLC blocks is only 3000 to 5000 times, making frequent mode switching unsuitable; the folding budget is adjusted from 30% to 20% because QLC page programming time is approximately 1.5 times that of TLC, requiring a more conservative background scheduling strategy to avoid impacting foreground performance.

[0072] In one embodiment, the above method further includes: When the internal temperature of the eMMC exceeds the preset temperature threshold, the folding operation is paused and resumed after the temperature drops below the preset recovery threshold.

[0073] Through the above specific implementation methods, this embodiment achieves the following technical effects: In terms of capacity utilization, under sparse write scenarios, idle pSLC capacity is automatically released and converted to TLC mode, effectively increasing storage capacity by 15% to 25%. For example, in industrial IoT data logger scenarios, the effective capacity is 24GB when fixed at 25% pSLC partitioning, and the effective capacity can reach 30GB after adopting the dynamic partitioning of this embodiment; during off-peak periods (parking mode) of in-vehicle IVI, the available storage capacity increases by 22%.

[0074] In terms of write performance, the pSLC cache is dynamically expanded in intensive write scenarios to avoid the performance bottleneck of front-end direct writing to TLC, resulting in a 3x improvement in write performance stability. For example, in a scenario with concurrent in-vehicle IVI navigation and dashcam operation, an 8GB pSLC cache with a fixed partition can only buffer for about 16 minutes at a write rate of 53MB / min. After the dynamic partition is expanded to 45% (14.4GB), it can buffer for 271 minutes, completely eliminating the performance drop caused by cache breakdown. In a video surveillance DVR scenario, the P99 write latency for 72 hours of continuous writing is reduced from 45 milliseconds to 18 milliseconds.

[0075] Regarding performance jitter, by using folding idle-aware scheduling and budgeting, tail latency jitter was reduced from ±35% to ±8%. In a 72-hour continuous write test of a video surveillance DVR, write speed jitter was reduced by 77%, and WAF was reduced from 2.8 to 1.9.

[0076] In terms of power consumption, for ultra-low power IoT scenarios, the pSLC ratio is reduced to 5% during idle periods, reducing idle power consumption from 350 microamps to 95 microamps, shortening OTA upgrade time from 120 seconds to 50 seconds, and reducing OTA upgrade energy consumption from 180 millijoules to 75 millijoules.

[0077] In terms of no additional hardware cost, all functions in this embodiment are implemented through the eMMC controller firmware, without the need to add additional storage chips or hardware circuits, which has good cost advantages and versatility.

[0078] In one embodiment, the lower limit of the pSLC region is set to 5% of the total capacity; in another embodiment, for a specific sparse write scenario, the pSLC region can be further reduced to 10% of the total capacity as a normal lower limit, and the absolute lower limit of 5% is only allowed to be reached in an extremely idle state.

[0079] In terms of applicable scenarios, the same firmware can adapt to various write modes such as automotive, monitoring, IoT, and consumer electronics, without the need to customize dedicated firmware versions for different applications. For example, the same 32GB eMMC dynamically allocates 45% pSLC during peak periods in automotive IVI, 20% during mid-peak periods, and 8% during off-peak periods; it maintains 15% to 20% as a write buffer in the stable state of monitoring DVR; and it shrinks to 5% during idle periods in industrial IoT and expands to 40% during OTA, truly achieving full-scenario adaptability.

[0080] The aforementioned hybrid-mode-based dynamic partition switching method monitors host write activity in real time and uses short-term and long-term window statistics to determine the current write mode. Based on the write mode and pSLC region occupancy, a hysteresis control strategy is employed, and the partition adjustment decision engine intelligently decides whether to perform partition adjustments, as well as their direction and magnitude. When expanding or shrinking pSLC partitions, precise data migration, erasure, and FTL mapping table updates ensure data consistency. Upon reaching a preset threshold, a folding operation is performed, re-encoding and moving the pSLC data to the TLC region. Simultaneously, an idle-aware scheduling strategy dynamically adjusts the folding rate to adapt to changes in host I / O activity, thereby achieving block-level fine-grained mode switching and data migration scheduling. This not only overcomes the shortcomings of existing technologies but also significantly improves system flexibility and efficiency. Furthermore, this process considers the impact of temperature on operations, further ensuring data processing reliability and system stability.

[0081] Figure 2 This is a schematic block diagram of a dynamic partition switching device 300 in pSLC / TLC hybrid mode provided in an embodiment of the present invention. Figure 2As shown, corresponding to the above-described dynamic partition switching method for pSLC / TLC hybrid mode, the present invention also provides a dynamic partition switching device 300 for pSLC / TLC hybrid mode. This dynamic partition switching device 300 for pSLC / TLC hybrid mode includes a unit for executing the above-described dynamic partition switching method for pSLC / TLC hybrid mode, and the device can be configured in a server. Specifically, please refer to... Figure 2 The dynamic partition switching device 300 of the pSLC / TLC hybrid mode includes a write heat monitoring unit 301, a partition adjustment decision unit 302, a block role switching unit 303, and a folding scheduling unit 304.

[0082] The write activity monitoring unit 301 monitors the host write activity in real time, determining the current write mode based on dual timescale statistics of short-term and long-term windows. The partition adjustment decision unit 302 determines whether to perform partition adjustment based on the write mode and the current occupancy rate of the pSLC region using a partition adjustment decision engine. When determining whether to perform adjustment, the engine specifies the adjustment direction and magnitude. The partition adjustment decision engine employs a hysteresis control strategy, which includes setting upper and lower limits for the pSLC region and a cooldown period block role conversion unit 303. When the decision is to expand the pSLC partition, the unit selects a block from the TLC idle block pool and converts it to pSLC mode; when the decision is to shrink the pSLC partition, the unit migrates valid data from the pSLC block to be converted to other pSLCs. The Block is erased and the type marker in the FTL mapping table is updated to TLC mode, and added to the TLC idle Block pool; the folding scheduling unit 304 is used to perform folding operation to re-encode pSLC data and move it to the TLC area when the pSLC area occupancy rate reaches a preset threshold, and adopts an idle-aware scheduling strategy to dynamically adjust the folding execution rate according to the host IO activity status.

[0083] In one embodiment, the method further includes: The pause unit is used to pause the folding operation when the internal temperature of the eMMC exceeds a preset temperature threshold, and resume it after the temperature drops below the preset recovery threshold.

[0084] In one embodiment, the method further includes a heat assessment unit, which is used to assess the heat of valid data in the pSLC region before performing the folding operation, so that hot data is preferentially retained in the pSLC region and cold data is moved out to the TLC region through the folding operation.

[0085] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned dynamic partition switching device based on hybrid mode and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0086] The aforementioned dynamic partition switching device based on hybrid mode can be implemented as a computer program, which can, for example... Figure 3 It runs on the computer device shown.

[0087] Please see Figure 3 , Figure 3 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0088] See Figure 3 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0089] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a dynamic partition switching method based on a hybrid mode.

[0090] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0091] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a dynamic partition switching method based on a hybrid mode.

[0092] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0093] The processor 502 is used to run a computer program 5032 stored in the memory to implement all the steps of the hybrid mode-based dynamic partition switching method.

[0094] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0095] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0096] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein when executed by a processor, the computer program causes the processor to perform all the steps of the hybrid-mode-based dynamic partition switching method.

[0097] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0098] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0099] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0100] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0101] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0102] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dynamic partition switching method based on hybrid mode, characterized in that, include: Real-time monitoring of host write activity, based on dual time scale statistics of short-term and long-term windows, to determine the current write mode; Based on the writing mode and the current occupancy rate of the pSLC region, the partition adjustment decision engine determines whether to perform partition adjustment, and determines the adjustment direction and adjustment range when determining to perform. The partition adjustment decision engine adopts a hysteresis control strategy, which includes setting an upper limit ratio, a lower limit ratio and a cooldown period for the pSLC region. When the decision is to expand the pSLC partition, select a block from the TLC free block pool and convert it to pSLC mode; when the decision is to shrink the pSLC partition, move the valid data in the pSLC block to be converted to other pSLC blocks, erase the block and update the type mark in the FTL mapping table to TLC mode, and add it to the TLC free block pool. When the pSLC area occupancy rate reaches a preset threshold, a folding operation is performed to re-encode the pSLC data and move it to the TLC area; The folding operation employs an idle-aware scheduling strategy, which dynamically adjusts the folding execution rate based on the host's I / O activity level.

2. The dynamic partition switching method based on hybrid mode according to claim 1, characterized in that, The current write mode includes one of burst-intensive, continuous-intensive, normal, or sparse; The write heat monitoring uses an exponentially weighted moving average algorithm to calculate a smooth estimate of write throughput.

3. The dynamic partition switching method based on hybrid mode according to claim 1, characterized in that, The duration of the short-term window is shorter than the duration of the long-term window. The short-term window is used to respond to burst writes, and the long-term window is used to determine the steady-state write mode.

4. The dynamic partition switching method based on hybrid mode according to claim 1, characterized in that, The hysteresis control strategy includes: setting an upper limit ratio and a lower limit ratio for the pSLC region, setting a cooling period after the adjustment direction is confirmed, and using hysteresis control to avoid repeated oscillations at the threshold critical point.

5. The dynamic partition switching method based on hybrid mode according to claim 1, characterized in that, The process of converting a Block to or from pSLC mode includes: marking the state during conversion, omitting valid data, erasing the Block, updating the type flag in the FTL mapping table, and adding it to the idle Block pool of the corresponding mode region.

6. The dynamic partition switching method based on hybrid mode according to claim 1, characterized in that, The idle-aware scheduling strategy includes: folding is executed at full speed during host idle periods, folding is executed at a limited speed during host I / O active periods, and folding is paused when the pSLC occupancy rate exceeds a preset overload threshold.

7. The dynamic partition switching method based on hybrid mode according to claim 6, characterized in that, Also includes: When the internal temperature of the eMMC exceeds the preset temperature threshold, the folding operation is paused and resumed after the temperature drops below the preset recovery threshold.

8. The dynamic partition switching method based on hybrid mode according to claim 1, characterized in that, The expansion trigger condition of the hysteresis control strategy is that the current write mode is bursty dense or continuous dense and the pSLC region occupancy rate exceeds the upper limit ratio, and the reduction trigger condition is that the current write mode is sparse and the pSLC region occupancy rate is lower than the lower limit ratio.

9. The dynamic partition switching method based on hybrid mode according to claim 6, characterized in that, Before performing the folding operation, the heat of valid data in the pSLC region is evaluated. Hot data is retained in the pSLC region first, while cold data is moved out to the TLC region through the folding operation.

10. A dynamic partition switching device for pSLC / TLC hybrid mode, characterized in that, include: The write heat monitoring unit is used to monitor the host write heat in real time and determine the current write mode based on dual time scale statistics of short-term and long-term windows. The partition adjustment decision unit is used to determine whether to perform partition adjustment based on the write mode and the current occupancy rate of the pSLC region through the partition adjustment decision engine, and to determine the adjustment direction and adjustment magnitude when determining to perform adjustment. The partition adjustment decision engine adopts a hysteresis control strategy, which includes setting an upper limit ratio, a lower limit ratio, and a cooldown period for the pSLC region. The Block Role Conversion Unit is used to select a Block from the TLC Free Block Pool and convert it to pSLC mode when the decision is to expand the pSLC partition; when the decision is to shrink the pSLC partition, it moves the valid data in the pSLC Block to be converted to other pSLC Blocks, erases the Block and updates the type mark in the FTL mapping table to TLC mode, and adds it to the TLC Free Block Pool. The folding scheduling unit is used to perform folding operations when the pSLC area occupancy rate reaches a preset threshold. This involves re-encoding the pSLC data and moving it to the TLC area. An idle-aware scheduling strategy is used to dynamically adjust the folding execution rate based on the host I / O activity status.

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