Data processing method, device and electronic equipment for branch target buffer

Abstract

Embodiments of the present application provide a data processing method and device of a branch target buffer and electronic equipment, and relate to the technical field of computers. In the method, a first bit segment in an instruction address of a to-be-written branch instruction is used to generate a first row index for the to-be-written branch instruction, and a corresponding row of the first row index in a branch target buffer (BTB) is used as a to-be-written row. A second bit segment in the instruction address is used as a branch table entry label, and a low bit difference part in a destination address that is different from the instruction address is determined. Metadata is generated based on the length of the low bit difference part. The branch table entry label, the metadata, and the low bit difference part are used to form a to-be-written branch table entry. A free slot bit of the to-be-written row is identified based on a vector bit of the to-be-written row, and the to-be-written branch table entry is written based on the free slot bit. In this way, the storage space utilization efficiency of the BTB can be improved while reducing access delay.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a data processing method, apparatus, and electronic device for a branch target buffer. Background Technology

[0002] Because branch instructions affect instruction execution efficiency, the processor sets up a branch target buffer (BTB) to store the destination address of branch instructions for later use.

[0003] In related technologies, the branch table entry representing the destination address is divided into three parts: offset, page, and region. These three parts are stored separately, and the offset part stores pointers to the region and page parts to improve the storage efficiency of BTB. However, this approach results in a high access latency because reading requires first reading the pointer and then using the pointer to read the region and page parts. Summary of the Invention

[0004] This invention provides a data processing method, apparatus, and electronic device for a branch target buffer (BTB), which can improve the storage space utilization efficiency of the BTB while reducing access latency.

[0005] To address the aforementioned problems, this invention discloses a data processing method for a branch target buffer, the method comprising: Based on the first bit segment of the instruction address of the branch instruction to be written, a first row index is generated for the branch instruction to be written, and the corresponding row of the first row index in the branch target buffer BTB is taken as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used. The second bit segment in the instruction address is used as the branch entry label, and the low-order part of the destination address that differs from the instruction address is determined as the low-order difference part; the second bit segment and the first bit segment correspond to the different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps; Metadata is generated for the destination address based on the length of the low-order difference portion; the metadata is used to characterize the length of the low-order difference portion. The branch entry label, the metadata, and the low-order difference portion are combined to form the branch entry to be written. The free slots of the row to be written are identified based on the vector bits of the row to be written, and the branch table entry to be written is written based on the free slots.

[0006] On the other hand, embodiments of the present invention disclose a data processing apparatus for a branch target buffer, the apparatus comprising: The first processing module is used to generate a first row index for the branch instruction to be written based on the first bit segment in the instruction address of the branch instruction to be written, and to take the corresponding row of the first row index in the branch target buffer BTB as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used. The determination module is used to use the second bit segment in the instruction address as a branch entry label, and to determine the low-order part of the destination address that differs from the instruction address as the low-order difference part; the second bit segment and the first bit segment correspond to different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps; The generation module is configured to generate metadata for the destination address based on the length of the low-order difference portion; the metadata is used to characterize the length of the low-order difference portion. A component module is used to assemble the branch entry label, the metadata, and the low-order difference portion into a branch entry to be written. The second processing module is used to identify the free slots of the row to be written based on the vector bits of the row to be written, and to write the branch table entry to be written based on the free slots.

[0007] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to execute the aforementioned method.

[0008] This invention also discloses a machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described above.

[0009] The embodiments of the present invention include the following advantages: The data processing method for the branch target buffer provided by the embodiments of the present invention generates a first row index for the branch instruction to be written based on the first bit segment of the instruction address to be written, and takes the corresponding row in the branch target buffer (BTB) as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used. The second bit segment in the instruction address is used as the branch entry label, and the low-order part of the destination address that differs from the instruction address is determined as the low-order difference part; the second bit segment and the first bit segment correspond to the different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps. Metadata is generated for the destination address based on the length of the low-order difference part; the metadata is used to represent the length of the low-order difference part. The branch entry label, metadata, and low-order difference part are combined to form the branch entry to be written. The free slots of the row to be written are identified based on the vector bits of the row to be written, and the branch entry to be written is written based on the free slots. In this way, branch entries to be written are generated based on the branch entry label, instruction address, and destination address, and stored in free slots in the row to be written. There is no need to split the destination address into multiple parts and store pointers to other parts. Consequently, during reading, there is no need to first read the pointer and then read other parts based on the pointer, thus reducing access latency to some extent. Furthermore, branch instructions with the same first-order segment are mapped to the same row in the BTB, allowing branch entries with the same first-order segment to share the same row in the BTB. This improves the storage space utilization efficiency of the BTB while reducing access latency. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below.

[0011] Figure 1 This is a flowchart of the steps of a data processing method for a branch target buffer provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the composition of a branch table entry provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of an associated group provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a line to be written according to an embodiment of the present invention; Figure 5 This is a block diagram of a data processing device for a branch target buffer provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0013] First, let's describe an application scenario related to this invention. In current computer architectures, microprocessors typically continuously fetch the next instruction after the current instruction until they encounter a branch instruction. Since a branch instruction may change the fetch address of subsequent instructions—for example, if the branch instruction's jump condition is met, it's necessary to jump to the branch instruction's destination address and execute the instruction at that address; if the branch instruction's jump condition is not met, it's necessary to fetch the address of the next instruction after the branch instruction and execute the instruction at that address. Whether a branch instruction actually jumps can only be determined during instruction execution. To reduce branch latency, the processor front-end is typically equipped with a branch prediction unit (BTB). This BTB is used to predict in advance whether a branch instruction will jump, thus pre-fetching the instruction at the next instruction address or the instruction at the destination address. The BTB is configured to cache the destination addresses of branch instructions in the program, providing a reference for branch prediction.

[0014] One related technique leverages the temporal locality of branch instructions: branch instructions that are temporally close are more likely to be located in similar address ranges; that is, multiple destination addresses of multiple branch instructions that are temporally close often share the same high-order bits. The destination address of a branch instruction is divided into three parts from low to high: offset, page, and region. The region portion of the destination address is stored in a Region BTB, and the page portion is stored in a Page BTB. The offset portion and pointers to the corresponding entries in the Region BTB and Page BTB are stored in the BTB-Monitor (BTBM). This storage method requires reading the destination address from the BTB first, then reading the BTBM to obtain the offset portion, the pointer to the Region BTB, and the pointer to the Page BTB. Then, these two pointers are used to read the corresponding entries in the Region BTB and Page BTB respectively to obtain the Region portion and the Page portion. Finally, the read Region portion, Page portion, and Offset portion are concatenated to obtain the destination address. This serial reading process increases BTB access latency, resulting in a high access delay.

[0015] Therefore, this invention provides a data processing method for a branch target buffer, which will be described in detail below.

[0016] Figure 1 This is a flowchart of the steps of a data processing method for a branch target buffer provided in an embodiment of the present invention, as follows: Figure 1 As shown, the method may include the following steps: Step 101: Based on the first bit segment of the instruction address of the branch instruction to be written, generate a first row index for the branch instruction to be written, and take the corresponding row of the first row index in the branch target buffer BTB as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used.

[0017] Step 102: Use the second bit segment in the instruction address as the branch entry label, and determine the low-order part of the destination address that differs from the instruction address as the low-order difference part; the second bit segment and the first bit segment correspond to the different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps.

[0018] Step 103: Generate metadata for the destination address based on the length of the low-order difference portion; the metadata is used to characterize the length of the low-order difference portion.

[0019] Step 104: Combine the branch entry label, the metadata, and the low-order difference portion into a branch entry to be written.

[0020] Step 105: Identify the free slots of the row to be written based on the vector bits of the row to be written, and write the branch table entry to be written based on the free slots.

[0021] In this embodiment of the invention, a row in the BTB corresponds to a storage word (i.e., a row in the RAM) of a random access memory (RAM) unit. For a row in the BTB, the portion between two predefined start positions is a storage slot, and a row may include multiple predefined start positions. When storing a branch entry, one or more consecutive storage slots are occupied according to the actual length of the branch entry. The vector bits of all storage slots in a row form a valid bit vector, that is, each storage slot corresponds to one bit in the valid bit vector. The number of bits in the valid bit vector of each row is the same as the number of storage slots included in each row. One vector bit corresponds to one storage slot in that row. For example, the vector bit corresponding to the i-th storage slot in that row is the i-th vector bit, that is, the i-th vector bit represents the i-th storage slot. Specifically, the vector bit value includes a first value and a second value. In one implementation, the i-th vector bit is specifically used to characterize whether the i-th storage slot is used as the starting storage slot for a branch entry, i.e., whether a branch entry is stored starting from the i-th storage slot. Accordingly, if the value of the vector bit is a first value, it indicates that the storage slot represented by the vector bit is used as the starting storage slot for a branch entry; if the value of the vector bit is a second value, it indicates that the storage slot represented by the vector bit is not used as the starting storage slot for a branch entry. Alternatively, in another implementation, if the value of the vector bit is a first value, it indicates that the storage slot represented by the vector bit has been used to store part or all of a branch entry; if the value of the vector bit is a second value, it indicates that the storage slot represented by the vector bit has not been used to store part or all of a branch entry. The specific values ​​of the first and second values ​​can be predefined by the developer; for example, the first value can be 1 and the second value can be 0. This embodiment of the invention does not impose such limitations.

[0022] The branch instruction to be written can be any branch instruction in the program that needs to write the destination address into the BTB. For example, when a branch instruction in the program jumps, that branch instruction can be used as the branch instruction to be written, so that the branch table entry for that branch instruction can be written into the BTB. The instruction address represents the memory location of the branch instruction itself. The value of the program counter (PC) when the branch instruction is executed can be obtained to get the instruction address of the branch instruction; the instruction address of the branch instruction can also be called the fetch PC of the branch instruction. The address to which the branch instruction jumps when the branch instruction jumps (i.e., when the branch condition of the branch instruction is met) is obtained, thus yielding the destination address of the branch instruction.

[0023] The first segment, also known as the index bit, represents a fixed bit in the instruction address. The specific range of the first segment can be predefined by the developer. The length of the first segment (i.e., the number of bits included in the first segment) can be set based on the total number of lines in the BTB. Assuming the total number of lines in the BTB is 2 to the power of r, the length of the first segment can be r. For example, the first segment can be the lower 8 bits of the instruction address; this embodiment of the invention does not impose any limitations on this. Further, the branch instruction to be written can be mapped to a line in the BTB according to the first segment in the instruction address of the branch instruction to be written. For example, assuming the lower 8 bits of the instruction address of the branch instruction to be written are equal to 50, then the first line index is 50, and the 50th line in the BTB can be used as the line to be written, that is, the branch instruction to be written can be mapped to the 50th line in the BTB. The second bit field corresponds to a different bit in the instruction address as the first bit field. The second bit field is different from the first bit field. The length of the second bit field is the length of the branch table entry label. The specific range of the second bit field can be predefined by the developer. For example, a bit field that differs between different branch instructions can be selected as the second bit field. The second bit field can be m bits in the instruction address. For example, the second bit field can be the 10th to the 34th bit of the instruction address. This embodiment of the invention does not limit this.

[0024] The branch entry to be written to the branch instruction is the branch table entry to be written. The branch table entry includes a branch table entry label and all or part of the destination address. For example, in one implementation, the entire destination address can be used to form the branch table entry, so the complete destination address can be obtained by accessing the BTB. In another implementation, the lower bits of the destination address that differ from the instruction address of the branch instruction to be written can be used to form the branch table entry, thus reducing the length of the branch table entry and saving storage space. Specifically, in this embodiment of the invention, the destination address of the branch instruction to be written can be compared with the instruction address of the branch instruction to be written. Specifically, starting from the most significant bit, the j-th bit in the destination address can be compared with the j-th bit in the instruction address. For example, assuming the address length is 64, that is, both the destination address and the instruction address include bits 0 to 63, then the initial value of j is 63. If the j-th bit in the destination address is the same as the j-th bit in the instruction address, then j is updated to j-1, and the comparison of the j-th bit in the destination address and the j-th bit in the instruction address is performed again. If the j-th bit in the destination address is different from the j-th bit in the instruction address, then bits 0 to j in the destination address are taken as the low-order difference portion. Furthermore, bits 10 to 34 in the instruction address of the branch instruction to be written can be obtained as the branch entry label for that branch instruction.

[0025] The length of the metadata can be a fixed value, denoted by n (i.e., the number of bits included in the metadata). For example, n can be equal to 6. In this embodiment of the invention, the metadata can be used to represent the length of the low-order difference portion. For example, assuming the low-order difference portion includes 30 bits, the metadata can be 011110. Of course, the metadata can also include bits representing other information. For example, n can be 8. The first two bits of the metadata can be used to represent the branch type of the branch instruction, and the last six bits of the metadata are used to represent the length of the low-order difference portion. The branch type of the branch instruction can be a conditional branch, an indirect jump branch, etc. Assuming that the identifiers corresponding to the conditional branch and the indirect jump branch can be 00 and 01 respectively, and the branch type of the branch instruction to be written is a conditional branch, then 8 bits of metadata can be generated: 00011110.

[0026] Furthermore, the branch entry label, metadata, and low-order difference portion of the destination address of the branch instruction can be combined in the order of branch entry label - metadata - low-order difference portion to obtain the branch entry to be written. Figure 2 This is a schematic diagram illustrating the composition of a branch table entry provided in an embodiment of the present invention, such as... Figure 2 As shown, a branch entry consists of a branch entry label, metadata, and a low-order difference portion, arranged sequentially. The branch entry label comprises m bits, and the metadata comprises n bits; both the label and metadata are fixed-length data. However, the length of the low-order difference portion, which differs from the instruction address in the destination address of different branch instructions, may vary. Therefore, the low-order difference portion is variable-length data. Accordingly, the length of branch entries for different branch instructions may differ. This embodiment of the invention can adapt to variable-length branch entries, enabling writing and querying of variable-length branch entries.

[0027] In this embodiment of the invention, the low-order part of the destination address that differs from the instruction address is identified as the low-order difference part. Metadata is generated for the destination address based on the length of the low-order difference part; the metadata is used to characterize the length of the low-order difference part. The branch entry label, metadata, and low-order difference part are combined to form a branch entry to be written. By setting the metadata, it is convenient to determine the specific length of the low-order difference part carried in the branch entry based on the metadata, thereby facilitating the subsequent reading of the low-order difference part. Furthermore, due to the spatial locality of branch instructions, i.e., the destination addresses of many branch instructions in the program are in the same address range as the instruction address of the branch instruction, this implementation only stores the low-order difference part between the instruction address and the destination address, which can reduce the length of the finally generated branch entry to be written, effectively reducing the amount of data to be stored, and thus saving BTB storage space.

[0028] Furthermore, by setting a branch entry label in the branch entry, when querying the branch entry of a certain branch instruction from the BTB, the second bit field of the instruction address of that branch instruction can be matched with the label in each branch entry stored in the BTB, thus facilitating the query.

[0029] In this embodiment of the invention, a branch entry occupies one or more consecutive storage slots in a row of a BTB. In one implementation, the vector bit corresponding to the first storage slot occupied by a branch entry (i.e., the starting storage slot of the branch entry) is set to a first value, and the vector bits corresponding to the remaining occupied storage slots are set to a second value. This facilitates the identification of the starting storage slot and occupied range of the branch entry stored in the row by combining the vector bits. Furthermore, the free slots of the row to be written can be identified based on the vector bits of the row to be written. The branch entry to be written is then written based on the free slots.

[0030] In summary, the data processing method for the branch target buffer provided in this embodiment of the invention generates a first row index for the branch instruction to be written based on the first bit segment of the instruction address to be written, and takes the corresponding row in the branch target buffer (BTB) as the row to be written. The BTB includes multiple rows, each row including multiple storage slots and vector bits indicating whether each storage slot is used. The second bit segment in the instruction address is used as the branch entry label, and the low-order bits in the destination address that differ from the instruction address are determined as the low-order difference part. The second bit segment and the first bit segment correspond to the different bits in the instruction address. The instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps. Metadata is generated for the destination address based on the length of the low-order difference part; the metadata is used to characterize the length of the low-order difference part. The branch entry label, metadata, and low-order difference part are combined to form the branch entry to be written. The free slots of the row to be written are identified based on the vector bits of the row to be written, and the branch entry to be written is written based on the free slots. In this way, the branch table entry to be written is based on the branch table entry label, instruction address, and destination address, and the branch table entry to be written is stored in the free slot in the row to be written. There is no need to split the destination address into multiple parts and store pointers to other parts. Accordingly, when reading, there is no need to read the pointer first and then read other parts based on the pointer, which can reduce access latency to a certain extent.

[0031] Furthermore, with the increasing number of branch hotspots in modern software, the number of branch entries that the Branch Prediction Block (BTB) needs to store is also increasing. However, due to constraints such as chip area and power consumption, the physical capacity of the BTB itself (e.g., the total number of bits in the BTB) is limited. In this embodiment of the invention, the row index of the branch instruction is determined by the first segment of the instruction address to be written to, so that branch instructions with the same first segment are mapped to the same row in the BTB, thereby allowing branch entries of branch instructions with the same first segment to share the same row in the BTB. With a fixed physical capacity, since multiple branch entries can be stored in one row, the storage density of information in the BTB can be increased, that is, the number of branch entries stored in the BTB can be increased. This improves the storage space utilization efficiency of the BTB while reducing access latency, thereby improving the branch prediction performance of the microprocessor.

[0032] For example, in one branch prediction method, the branch prediction unit first queries the BTB for the destination address of the branch instruction. If the destination address of the branch instruction is not found, that is, the BTB has not yet recorded the branch entry for the branch instruction, the branch instruction is predicted not to jump, and the next instruction is prefetched. If the destination address of the branch instruction is found, the branch predictor further predicts whether the branch instruction will jump. Accordingly, if the destination address of the branch instruction is not found, but the branch instruction actually jumps, it will cause a branch misprediction, thereby significantly reducing execution performance. In this embodiment of the invention, a row in the BTB can store multiple branch entries, which can efficiently utilize storage space, thereby increasing the total number of branch entries stored in the BTB, thereby reducing the BTB missing rate, that is, reducing the probability of not finding the destination address of the branch instruction in the BTB, and thus reducing the probability of causing a branch misprediction, avoiding the problem of branch misprediction reducing execution performance.

[0033] Optionally, in this embodiment of the invention, when the vector bit is a first value, it indicates that the storage slot is used as the starting storage slot of a branch table entry. Accordingly, the step of identifying the free slot of the row to be written based on the vector bit of the row to be written may specifically include: Step 1051: Take the slot represented by the last vector bit in the vector bits to be written as the first starting slot.

[0034] Step 1052: Determine the remaining slots after the slot occupied by the branch table entry stored in the first starting slot as the free slots.

[0035] A row in a BTB can be considered an associative group. Branch entries of branch instructions with the same first bit segment share the same associative group; that is, BTB uses a group-associative structure. For any row in a BTB, a branch entry consisting of the branch entry label, metadata, and low-order differences represents one path of data in the associative group, and a row can be shared by multiple paths of data. Figure 3 This is a schematic diagram of an associated group provided in an embodiment of the present invention, such as... Figure 3 As shown, any row in BTB uses Figure 3 The organizational structure shown, i.e., each row in the BTB of this embodiment of the invention, adopts the same structure. In this implementation, the storage slots are divided in an equal-length manner, which can reduce the complexity of the storage slot division. In order from the most significant bit to the least significant bit, the row is arranged sequentially as follows: effective vector bit - 1st storage slot - 2nd storage slot - 3rd storage slot - 4th storage slot.

[0036] Let 's' represent the row number (row index) of the row to be written, and 't' represent the number of storage slots in a single row. The product of 's-1' and the length of a single row can be used as the end position of the row preceding the row to be written. Correspondingly, the position after the end position of this row can be used as the start position of the row to be written. The (t+1)th position starting from the start position of this row is used as the start position of the first storage slot in this row, and the L1th position starting from the start position of the first storage slot is used as the end position of the first storage slot in this row. The (L1+1)th position after the start position of the first storage slot is used as the start position of the second storage slot in this row. Here, L1 represents the length of the first storage slot. By analogy, the start and end positions of each storage slot in a row can be determined, thus revealing the storage range of each slot within that row. Assuming L1=10, the first storage slot in the row is defined as the range from the start position of the first storage slot in the row to the start position of the first storage slot + 10. It should be noted that the storage range corresponding to the last storage slot in each row is the range from the start position of the last storage slot to the end position of the row. Alternatively, in another implementation, the start and end positions of each row in the BTB, as well as the start and end positions of each storage slot within that row, can be pre-recorded. This allows for easy retrieval of the start and end positions of each storage slot within each row, facilitating the writing of branch entries to the row to be written and improving write efficiency.

[0037] It should be noted that the specific organizational structure of BTB Bank can be configured as needed. Figure 3 This is just one example. Specifically, the number of storage slots in a row, the starting position of each storage slot, and the length of each storage slot can all be set as needed. For example, Figure 3The illustration only shows that each storage slot has the same length. In another implementation, the first two storage slots can be designed to have the same length, and the last two storage slots can have the same length. Alternatively, in another implementation, a row can include 6 storage slots, and correspondingly, the first 6 bits in each row are used as vector bits. This embodiment of the invention does not impose any limitations on this.

[0038] Vector bits closer to the start of the row to be written are placed at the beginning. Correspondingly, the vector bit furthest from the start of the row to be written among the vector bits with the first value can be determined as the last vector bit in the row to be set to the first value. The branch entries stored in the first starting slot refer to the branch entries stored starting from the first starting slot. Figure 4 This is a schematic diagram of a line to be written according to an embodiment of the present invention, such as... Figure 4 As shown, there are two vector bits set to the first value. Following the order from most significant bit to least significant bit, the first vector bit is the first one set to the first value, and the third vector bit is the last one set to the first value. Accordingly, the third storage slot in the row to be written can be used as the first starting slot. It can be understood that if the 4-bit vector bit is 100000, then the last vector bit set to the first value is the first vector bit. Next, the slot occupied by the branch entry stored in the first starting slot can be identified, and free slots are determined based on the slots after the branch entry stored in the first starting slot. Assume that the first and second storage slots in the row to be written store branch entry 1, and the third and fourth storage slots store branch entry 2. That is, branch entry 2 (the branch entry stored in the first starting slot) occupies the third and fourth storage slots. This example demonstrates storing two branch entries in an association group, with branch entry 1 and branch entry 2 each occupying two storage slots. This achieves efficient storage of multiple variable-length branch entries within the same association group, improving storage density. Correspondingly, for this example, the subsequent slots (the 5th and 6th storage slots) can be designated as free slots.

[0039] It should be noted that, for Figure 4 In the example where only branch entry 1 is stored, the first vector bit in the valid bit vector is set to a first value, and all other vector bits are set to a second value. Further, in this embodiment of the invention, if there are no vector bits set to the first value in the vector bits of the row to be written, then all storage slots in the row to be written are directly determined as free slots.

[0040] In this embodiment of the invention, a vector bit with a first value is used to identify the storage slot used as the starting storage slot for a branch entry. The slot represented by the last vector bit in the row to be written, which is set to the first value, is designated as the first starting slot. The remaining slots after the slot occupied by the branch entry stored in the first starting slot are designated as free slots. This allows branch entries to be stored continuously in the row, starting from the slot closest to the vector bit region, avoiding the problem of skipping a storage slot and wasting storage resources.

[0041] Optionally, in this embodiment of the invention, the branch entry label in each branch entry includes m bits, and the metadata in each branch entry includes n bits, that is, the fixed-length part of each branch entry is m+n bits. Accordingly, this embodiment of the invention may further include the following steps: Step S21: Read n bits of data starting from the (m+1)th bit of the first starting slot as the first metadata, and based on the first metadata, determine the length of the low-bit difference portion in the branch table entry stored in the first starting slot to obtain the first length p.

[0042] Step S22: Determine the slot occupied by the m+n+p bits of data stored starting from the first starting slot as the slot occupied by the branch table entry stored in the first starting slot.

[0043] Let the u-th vector bit represent the last vector bit in the row to be written that is set to the first value. Then, the corresponding u-th storage slot can be used as the first starting slot. Accordingly, the starting position of the u-th storage slot can be determined, and the (m+1)th to (m+1+n)th bits after the starting position of the u-th storage slot are read as the metadata in the branch table entry stored starting from the first starting slot (hereinafter referred to as the first metadata for convenience). Based on the first metadata, the length of the low-order difference portion stored starting from the first starting slot is determined (hereinafter referred to as the first length, denoted by p for convenience). For example, assuming that the last 6 bits in the first metadata are 011110, then the first length p = 30 can be determined.

[0044] Furthermore, the m+n+p bits of data starting from the beginning position of the u-th storage slot constitute the branch entry stored in the first starting slot. The storage slot into which the beginning position of the u-th storage slot + m+n+p (hereinafter referred to as the end position of the branch entry stored in the first starting slot) falls is designated as the end slot of the branch entry stored in the first starting slot. For example, the end position of the entry can be compared with the beginning and end positions of each storage slot in the row to be written. The storage slot corresponding to the beginning and end positions into which the end position of the entry falls is designated as the end slot of the branch entry stored in the first starting slot. Accordingly, the slots occupied by the branch entries stored in the u-th storage slot and the end slot of the branch entries stored in the first starting slot are the slots occupied by the branch entries stored in the first starting slot. For example, assuming the u-th storage slot is the 3rd storage slot, and the ending slot of the branch entry stored in the first starting slot is the 4th storage slot, then the slots occupied by the branch entry stored in the first starting slot are the 3rd and 4th storage slots. Accordingly, the other slots after the 4th storage slot in the row to be written (e.g., the 5th and 6th storage slots) can be identified as free slots in the row to be written.

[0045] In this embodiment of the invention, the first metadata in the branch entry stored starting from the first starting slot is determined based on the number of bits n of the fixed-length metadata. The length p of the low-order difference portion in the branch entry stored starting from the first starting slot is then determined based on the first metadata. Finally, based on the length m of the fixed-length branch entry label, the length n of the metadata, and the length p of the low-order difference portion in the branch entry stored starting from the first starting slot, the slot occupied by the branch entry stored in the first starting slot can be accurately identified, thereby ensuring the efficiency of identifying idle slots to a certain extent.

[0046] Optionally, the step of writing the branch table entry to be written based on the free slot may specifically include: Step 1053: If the total length of the free slots is not less than the length of the branch table entry to be written, then the free slots are determined as writable slots.

[0047] Step 1054: If the total length of the free slots is less than the length of the branch entry to be written, then determine the target slot from the storage slots located before the free slots and whose corresponding vector bits are the first value, and determine the target slot and the storage slots thereafter as the writable slots; the total length of the target slot and the storage slots thereafter is not less than the length of the branch entry to be written.

[0048] Step 1055: Start writing the branch table entry to be written from the first slot in the writable slots.

[0049] In this embodiment of the invention, when the length of a single slot is equal, the product of the number of free slots and the length of a single slot can be used as the total length of the free slots. Alternatively, the length of each free slot can be summed to obtain the total length of the free slots. The length of the branch entry to be written is equal to m+n+the length of the low-order difference portion of the entry. If the total length is not less than the length of the branch entry to be written, it means that the current free slots are sufficient to store the branch entry to be written. Therefore, the free slots can be directly determined as writable slots. In this embodiment of the invention, the branch entries are stored in a variable-length manner, that is, the branch entries are written starting from the beginning position of a storage slot and occupy one or more consecutive slots. Specifically, the branch entry to be written can start from the beginning position of the first slot in the writable slots. At the same time, the vector bit corresponding to the first slot in the writable slots is set to a first value, and the vector bits corresponding to the storage slots after the first slot in the writable slots are set to a second value. The default value for the vector bit can be the second value. When the storage slot corresponding to the vector bit is used as the starting storage slot for a branch entry, the vector bit is set to the first value. In this embodiment, an empty slot is directly designated as a writable slot only when the total length of the free slots is not less than the length of the branch entry to be written. The branch entry to be written begins from the first writable slot. This avoids the problem of insufficient write space leading to inaccurate writing.

[0050] For example, referring to the previous example, the free slots include the 5th and 6th storage slots. Assuming the total length of the 5th and 6th storage slots is 100, and the length of the branch entry to be written is 80, then writing can begin from the starting position of the 5th storage slot. The branch entry to be written occupies both the 5th and 6th storage slots (in this example, the first 30 bits of the 6th storage slot are occupied). Simultaneously, the vector bit corresponding to the 5th storage slot is set to a first value, and the vector bit corresponding to the 6th storage slot remains at a second value. In another example, assuming the length of the branch entry to be written is 50, then writing can begin from the 5th storage slot, and the branch entry to be written occupies only the 5th storage slot. Simultaneously, the vector bit corresponding to the 5th storage slot is set to a first value, and the vector bit corresponding to the 6th storage slot remains at a second value.

[0051] If the total length is less than the length of the branch entry to be written, it means that the current free slots are insufficient to store the branch entry. Therefore, at least one storage slot previously occupied by the free slot can be released. Specifically, the storage slot preceding the free slot and whose corresponding vector bit is the first value can be selected as a candidate slot. Following the order from closest to furthest from the free slot, the total length of the candidate slot and the storage slots following it is sequentially checked to see if it is not less than the length of the branch entry to be written. If so, the candidate slot is designated as the target slot, and the target slot and the storage slots following it are determined as writable slots. If not, the next candidate slot is checked. In this embodiment of the invention, when the total length of the free slots is less than the length of the branch entry to be written, releasing previously occupied storage slots ensures that the length of the writable slots is sufficient to accommodate the branch entry to be written, thereby avoiding insufficient write space and the problem of inaccurate writing. Meanwhile, determining the target slot from the storage slots preceding the free slots and whose corresponding vector bits are the first values ​​ensures that the storage slots storing complete branch table entries are stored before the free slots are released, thereby ensuring that the branch table entries in the rows to be written are stored continuously and avoiding waste of storage resources.

[0052] For example, referring to the previous example, the free slots include the 5th and 6th storage slots. Assume the total length of the 5th and 6th storage slots is 100, and the length of the branch table entry to be written is 150. Since the total length of the free slots is less than the length of the branch table entry to be written, the storage slots preceding the 5th and 6th storage slots and whose corresponding vector bits are the first value—the 1st and 3rd storage slots—can be selected as candidate slots. Following the order of proximity to the free slots, the 3rd storage slot is evaluated first. The total length of the 3rd storage slot and the subsequent storage slots (slots 4-6) is 200, satisfying the condition that it is not less than the length of the branch table entry to be written. Therefore, slots 3-6 can be selected as writable slots.

[0053] Accordingly, writing can begin from the starting position of the 3rd storage slot, with the branch entry to be written occupying the 3rd, 4th, and 5th storage slots. Simultaneously, the vector bit corresponding to the first writable slot is set to a first value, and the vector bits corresponding to the storage slots after the first writable slot are set to a second value. For example, the vector bit corresponding to the 3rd storage slot is set to the first value, while the vector bits corresponding to the 4th to 6th storage slots remain at the second value. In this example, the branch entry to be written requires 3 storage slots. In this embodiment, the 3rd to 6th storage slots are used as writable slots. After writing the branch entry, the 6th storage slot is free and can be used by subsequent branch entries. If the 4th to 6th storage slots are used as writable slots, after writing the branch entry, the 3rd storage slot cannot be used by other branch entries, wasting storage resources.

[0054] It should be noted that in this embodiment of the invention, each row in the BTB has the same length, and the row length is not less than the maximum length of a branch table entry. This ensures that each row of the BTB can store at least one branch table entry. Furthermore, in one implementation, the row length is not less than the maximum length of at least two branch table entries. This ensures that at least two branch table entries can be stored simultaneously in a single row, avoiding the problem of branch table entries of two branch instructions releasing each other's occupied storage slots. Since only the row length needs to be set to be not less than the maximum length of at least two branch table entries, the required hardware modification is small, and the hardware cost is low.

[0055] In this embodiment of the invention, the more branch entries stored in a row, the greater the correlation of the association group. For example, the correlation can be equal to two branch entries stored in a row. Branch entries are written starting from the first writable slot, and each branch entry is a whole composed of a tag, metadata, and low-order difference portion in the order of branch entry tag - metadata - low-order difference portion. In this way, the branch entry tag, metadata, and low-order difference portion are stored sequentially in a row, that is, the fixed-length portion and the variable-length portion of one data path are stored continuously. This allows the branch entry to be read to be located based on the branch entry tag without dynamic shifting of the read data, and can be read directly in sequence. Therefore, the problem of high access latency can be further avoided, ensuring that branch instructions with the same first segment can share the same row, thereby achieving a high BTB correlation and efficient use of the physical storage space of the BTB.

[0056] Furthermore, in this embodiment of the invention, fixed-length branch entry tags and metadata are used, along with variable-length low-order difference portions, to form branch entries for storage. Storage begins from the first writable slot. This allows for flexibility in handling branch entries of varying lengths, flexibly adapting to the variable lengths of required branch entries while minimizing wasted storage space. Additionally, if there are insufficient unused storage slots, releasing used slots forward prevents insufficient storage space and ensures proper storage.

[0057] Optionally, embodiments of the present invention may further include: Step S31: For any branch instruction to be queried, based on the first segment of the instruction address of the branch instruction to be queried, generate a second row index for the branch instruction to be queried, and take the corresponding row of the second row index in the BTB as the row to be read.

[0058] Step S32: Take the second bit field in the instruction address of the branch instruction to be queried as a reference tag, and based on the reference tag, query the starting storage slot of the branch table entry of the branch instruction to be queried from the line to be read, and take it as the second starting slot.

[0059] Step S33: Starting from the second starting slot, read the branch table entry of the branch instruction to be queried.

[0060] The branch instruction to be queried can be any branch instruction in the program that requires querying the destination address from the BTB. For example, when executing a branch instruction in the program and needing branch prediction, this branch instruction can be used as the branch instruction to be queried, allowing the branch table entry of that branch instruction to be queried in the BTB. For example, assuming the lower 8 bits of the instruction address of the branch instruction to be queried are equal to 51, then the second row index is 51, and row 51 in the BTB can be used as the row to be read, mapping the branch instruction to be queried to row 51 in the BTB. Further, taking the second field as bits 10 to 34 of the instruction address as an example, bits 10 to 34 of the instruction address of the branch instruction to be queried can be obtained to get the branch table entry label (hereinafter referred to as the reference label) of that branch instruction.

[0061] Furthermore, since the label portion of a branch entry includes the second field of the instruction address of the branch instruction corresponding to that branch entry, the starting storage slot (hereinafter referred to as the second starting slot) of the branch entry of the branch instruction to be queried can be determined by matching the reference label with the labels in the branch entries stored in the line to be read. The branch entry of the branch instruction to be queried is then read starting from the second starting slot.

[0062] In this embodiment of the invention, the corresponding row in the first segment index (BTB) of the instruction address of the branch instruction to be queried is used as the row to be read. The starting storage slot of the branch table entry of the branch instruction to be queried is retrieved from the row to be read by tag matching. Reading begins from this starting storage slot, and the branch table entry of the branch instruction to be queried can be obtained. In this way, multiple BTBs do not need to be accessed serially, thus ensuring data access efficiency.

[0063] Optionally, the step of querying the starting storage slot of the branch table entry of the branch instruction to be queried from the row to be read based on the reference tag, as the second starting slot, specifically includes: Step S32a: The storage slots in the row to be read that are consistent with the reference label and whose corresponding vector bits are the first values ​​are determined as the second starting slots.

[0064] In this embodiment of the invention, the row to be read can be read from the BTB. Then, a reference label is compared in parallel with the first m bits of each storage slot in the row to be read. For example, the starting position of each storage slot in the row to be read can be queried, and the content within the range from the starting position of each storage slot to the starting position of each storage slot + m is compared in parallel with the reference label. If the first m bits of a storage slot are the same as the reference label, and the vector bit corresponding to the storage slot with the same first m bits as the reference label has a first value, then that storage slot is determined as the second starting slot. In this way, by directly comparing all storage slots in the row to be read with the reference label in parallel, the circuit implementation can be simplified since no selection is required. Of course, in another implementation, the storage slots in the row to be read whose corresponding vector bit has a first value can be selected first. Then, these storage slots are matched with the first m bits using a label; this embodiment of the invention does not limit this approach.

[0065] In this embodiment of the invention, when writing a branch table entry, the first m bits of the instruction address of the branch instruction are used as the branch table entry label, and each write operation starts from the beginning of a storage slot. Thus, by identifying the storage slot in the row to be read where the first m bits match the reference label and the corresponding vector bit is the first value, the starting storage slot of the branch table entry of the branch instruction to be queried can be conveniently located.

[0066] Optionally, the step of reading the branch table entry of the branch instruction to be queried, starting from the second starting slot, specifically includes: Step S33a: Read n bits of data starting from the (m+1)th bit of the second starting slot as the second metadata, and based on the second metadata, determine the length of the low-bit difference portion in the branch table entry of the branch instruction to be queried, and obtain the second length q.

[0067] Step S33b: Read m+n+q bits of data starting from the second starting slot, as the branch entry of the branch instruction to be queried.

[0068] First, determine the starting position of the second starting slot. Then, read bits (m+1) to (m+1+n) after the starting position of the second starting slot to obtain the metadata (hereinafter referred to as the second metadata) stored in the branch table entry starting from the second starting slot. The value represented by the portion of the second metadata indicating the length of the low-order difference is taken as the second length q. Assuming the last 6 bits of the second metadata are 011110, then the second length q = 30. Further, the m+n+q bits of data starting from the starting position of the second starting slot constitute the branch table entry for the branch instruction to be queried.

[0069] After reading the branch table entry of the branch instruction to be queried, the low-order difference portion of the branch table entry can be concatenated with the high-order portion of the instruction address of the branch instruction to be queried to form the destination address of the branch instruction to be queried. Let M represent the total number of bits in the instruction address; the high-order (Mq) bits of the instruction address of the branch instruction to be queried can be used as the high-order portion of the instruction address of the branch instruction to be queried. Furthermore, the branch type of the branch instruction to be queried can be determined based on the bits used to characterize the branch type in the second metadata, and the corresponding branch predictor can be selected based on the branch type of the branch instruction to be queried for branch prediction.

[0070] In this embodiment of the invention, n bits of data are first read from the (m+1)th bit of the second starting slot as second metadata. Based on the second metadata, the length of the low-order difference portion in the branch entry of the branch instruction to be queried is determined, resulting in a second length q. Then, m+n+q bits of data are read from the second starting slot as the branch entry of the branch instruction to be queried, ensuring that the complete branch entry of the branch instruction to be queried can be accurately obtained.

[0071] Alternatively, only the low-order difference portion of the branch table entry of the branch instruction to be queried can be read. Accordingly, step S33 may include: reading n bits of data starting from the (m+1)th bit of the second starting slot as second metadata, and determining the length of the low-order difference portion of the branch table entry of the branch instruction to be queried based on the second metadata to obtain the second length q. Reading q bits of data starting from the (m+n+1)th bit after the starting position of the second starting slot to obtain the low-order difference portion of the branch table entry of the branch instruction to be queried.

[0072] Optionally, this embodiment of the invention may further include: if there exists a storage slot located after the second starting slot and whose corresponding vector bit is a first value, the slot preceding the storage slot closest to the second starting slot is used as the ending slot of the branch entry of the branch instruction to be queried. Data stored from the second starting slot to the ending slot is read and used as the branch entry of the branch instruction to be queried. If there is no slot located after the second starting slot and whose corresponding vector bit is a first value, the step of reading n bits of data starting from the (m+1)th bit of the second starting slot as the second metadata is performed.

[0073] Since the storage slot with the first value corresponding to the vector bit is the starting storage slot of a branch entry, the storage slots with the first value corresponding to the vector bit after the second starting slot are the starting storage slots of other branch entries. For example, assuming the vector bits corresponding to the 1st to 6th storage slots in the row to be read are 100000, and the second starting slot is the 1st storage slot in the row to be read, then execution begins from step S33a above to read the branch entry of the branch instruction to be queried. For example, assuming the vector bits corresponding to the 1st to 6th storage slots in the row to be read are 101010, and the second starting slot is the 1st storage slot in the row to be read, then the storage slot preceding the storage slot with the first value corresponding to the vector bit (the 3rd storage slot in this example) (the 2nd storage slot in this example) closest to the second starting slot (the 3rd storage slot in this example) can be used as the ending slot of the branch entry of the branch instruction to be queried. By reading the data stored in the first and second storage slots, the branch table entry for the branch instruction to be queried can be obtained. This method improves reading efficiency.

[0074] Reference Figure 5 The diagram shows a block diagram of a data processing apparatus for a branch target buffer provided in an embodiment of the present invention, such as... Figure 5 As shown, the device may specifically include: The first processing module 201 is used to generate a first row index for the branch instruction to be written based on the first bit segment in the instruction address of the branch instruction to be written, and to take the corresponding row of the first row index in the branch target buffer BTB as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used. The determining module 202 is used to use the second bit segment in the instruction address as a branch entry label, and to determine the low-order part of the destination address that differs from the instruction address as the low-order difference part; the second bit segment and the first bit segment correspond to different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps; Generation module 203 is used to generate metadata for the destination address based on the length of the low-order difference portion; the metadata is used to characterize the length of the low-order difference portion; Module 204 is used to assemble the branch entry label, the metadata, and the low-order difference portion into a branch entry to be written. The second processing module 205 is used to identify the free slot of the row to be written based on the vector bits of the row to be written, and to write the branch table entry to be written based on the free slot.

[0075] Optionally, if the vector bit is a first value, it indicates that the storage slot is used as the starting storage slot of a branch table entry; The second processing module 205 is specifically used to: take the slot represented by the last vector bit in the vector bits of the row to be written that is set to the first value as the first starting slot; The slots after the slot occupied by the branch table entry stored in the first starting slot are determined as the free slots.

[0076] Optionally, each branch entry's label includes m bits, and each branch entry's metadata includes n bits; the second processing module 205 is further configured to: Starting from the (m+1)th bit of the first starting slot, n bits of data are read as the first metadata. Based on the first metadata, the length of the low-bit difference portion in the branch table entry stored in the first starting slot is determined to obtain the first length p. The slots occupied by the m+n+p bits of data stored starting from the first starting slot are determined as the slots occupied by the branch entries stored in the first starting slot.

[0077] Optionally, the second processing module 205 is further configured to: If the total length of the free slots is not less than the length of the branch table entry to be written, then the free slots are determined as writable slots. If the total length of the free slots is less than the length of the branch entry to be written, then a target slot is determined from the storage slots located before the free slots and whose corresponding vector bits are the first value, and the target slot and the storage slots thereafter are determined as the writable slots; the total length of the target slot and the storage slots thereafter is not less than the length of the branch entry to be written. The branch entry to be written is written starting from the first slot in the writable slots.

[0078] Optionally, the device further includes: The third processing module is used to generate a second row index for any branch instruction to be queried based on the first segment of the instruction address of the branch instruction to be queried, and to take the corresponding row of the second row index in the BTB as the row to be read. The query module is used to take the second bit field in the instruction address of the branch instruction to be queried as a reference tag, and based on the reference tag, query the starting storage slot of the branch table entry of the branch instruction to be queried from the line to be read, and use it as the second starting slot; The reading module is used to read the branch table entries of the branch instruction to be queried, starting from the second starting slot.

[0079] Optionally, the query module is specifically used for: The storage slots in the row to be read whose first m bits match the reference label and whose corresponding vector bits are the first values ​​are determined as the second starting slots.

[0080] Optionally, the reading module is specifically used for: Starting from the (m+1)th bit of the second starting slot, read n bits of data as the second metadata, and based on the second metadata, determine the length of the low-order difference portion in the branch entry of the branch instruction to be queried, and obtain the second length q; Read m+n+q bits of data starting from the second starting slot, and use them as the branch entry for the branch instruction to be queried.

[0081] In summary, in the data processing apparatus for the branch target buffer provided in this embodiment of the invention, a first row index is generated for the branch instruction to be written based on the first segment of the instruction address to be written, and the corresponding row in the branch target buffer (BTB) is taken as the row to be written. The BTB includes multiple rows, each row including multiple storage slots and vector bits indicating whether each storage slot is used. The second segment of the instruction address is used as the branch entry label, and the low-order part of the destination address that differs from the instruction address is determined as the low-order difference part. The second segment and the first segment correspond to the different bits in the instruction address. The instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps. Metadata is generated for the destination address based on the length of the low-order difference part; the metadata is used to characterize the length of the low-order difference part. The branch entry label, metadata, and low-order difference part are combined to form the branch entry to be written. The free slots of the row to be written are identified based on the vector bits of the row to be written, and the branch entry to be written is written based on the free slots. In this way, branch entries to be written are based on their branch entry tags, instruction addresses, and destination addresses, and these entries are stored in free slots within the row to be written. There's no need to split the destination address into multiple parts and store pointers to those parts. Consequently, during reading, there's no need to first read the pointer and then read the other parts based on it, thus reducing access latency to some extent. Furthermore, branch instructions with the same first-order segment are mapped to the same row in the BTB, allowing branch entries with the same first-order segment to share the same row in the BTB. This improves the storage space utilization efficiency of the BTB while reducing access latency.

[0082] Reference Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. For example... Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus.

[0083] The processor, the memory, and the communication interface communicate with each other via the communication bus; the memory stores at least one executable instruction, which causes the processor to execute the data processing method of the branch target buffer described in the foregoing embodiment. The executable instructions can form a program.

[0084] This invention provides a machine-readable medium storing instructions that, when executed by one or more processors, enable the processors to perform the data processing method for the branch target buffer described in the foregoing embodiments. The machine-readable medium may be one or more.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0086] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0088] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0089] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0090] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1The steps of the function specified in one or more boxes.

[0091] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0092] Finally, it should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0093] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0094] The foregoing has provided a detailed description of a data processing method for a branch target buffer, a data processing device for a branch target buffer, an electronic device, and a readable medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data processing method for a branch target buffer, characterized in that, The method includes: Based on the first bit segment of the instruction address of the branch instruction to be written, a first row index is generated for the branch instruction to be written, and the corresponding row of the first row index in the branch target buffer BTB is taken as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used. The second bit segment in the instruction address is used as the branch entry label, and the low-order part of the destination address that differs from the instruction address is determined as the low-order difference part; the second bit segment and the first bit segment correspond to the different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps; Metadata is generated for the destination address based on the length of the low-order difference portion; the metadata is used to characterize the length of the low-order difference portion. The branch entry label, the metadata, and the low-order difference portion are combined to form the branch entry to be written. The free slots of the row to be written are identified based on the vector bits of the row to be written, and the branch table entry to be written is written based on the free slots.

2. The method according to claim 1, characterized in that, When the vector bit is a first value, it indicates that the storage slot is used as the starting storage slot of a branch table entry; The step of identifying the free slot of the row to be written based on the vector bits of the row to be written includes: taking the slot represented by the last vector bit in the vector bits of the row to be written that is set to a first value as the first starting slot; The slots after the slot occupied by the branch table entry stored in the first starting slot are determined as the free slots.

3. The method according to claim 2, characterized in that, Each branch table entry contains m tags, and each branch table entry contains n metadata bits; the method further includes: Starting from the (m+1)th bit of the first starting slot, n bits of data are read as the first metadata. Based on the first metadata, the length of the low-bit difference portion in the branch table entry stored in the first starting slot is determined to obtain the first length p. The slots occupied by the m+n+p bits of data stored starting from the first starting slot are determined as the slots occupied by the branch entries stored in the first starting slot.

4. The method according to claim 1, characterized in that, The step of writing the branch table entry to be written based on the free slot includes: If the total length of the free slots is not less than the length of the branch table entry to be written, then the free slots are determined as writable slots. If the total length of the free slots is less than the length of the branch entry to be written, then a target slot is determined from the storage slots located before the free slots and whose corresponding vector bits are the first value, and the target slot and the storage slots thereafter are determined as the writable slots; the total length of the target slot and the storage slots thereafter is not less than the length of the branch entry to be written. The branch entry to be written is written starting from the first slot in the writable slots.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: For any branch instruction to be queried, a second row index is generated for the branch instruction based on the first segment of the instruction address of the branch instruction to be queried, and the corresponding row of the second row index in the BTB is taken as the row to be read; The second bit field in the instruction address of the branch instruction to be queried is used as a reference tag, and based on the reference tag, the starting storage slot of the branch table entry of the branch instruction to be queried is queried from the line to be read, and used as the second starting slot. Starting from the second starting slot, read the branch table entry of the branch instruction to be queried.

6. The method according to claim 5, characterized in that, The step of querying the starting storage slot of the branch table entry of the branch instruction to be queried from the row to be read, based on the reference tag, as the second starting slot, includes: The storage slots in the row to be read whose first m bits match the reference label and whose corresponding vector bits are the first values ​​are determined as the second starting slots.

7. The method according to claim 5, characterized in that, The step of reading the branch table entry of the branch instruction to be queried, starting from the second starting slot, includes: Starting from the (m+1)th bit of the second starting slot, read n bits of data as the second metadata, and based on the second metadata, determine the length of the low-order difference portion in the branch entry of the branch instruction to be queried, and obtain the second length q; Read m+n+q bits of data starting from the second starting slot, and use them as the branch entry for the branch instruction to be queried.

8. A data processing apparatus for a branch target buffer, characterized in that, The device includes: The first processing module is used to generate a first row index for the branch instruction to be written based on the first bit segment in the instruction address of the branch instruction to be written, and to take the corresponding row of the first row index in the branch target buffer BTB as the row to be written; the BTB includes multiple rows, each row including multiple storage slots and vector bits representing whether each storage slot is used. The determination module is used to use the second bit segment in the instruction address as a branch entry label, and to determine the low-order part of the destination address that differs from the instruction address as the low-order difference part; the second bit segment and the first bit segment correspond to different bits in the instruction address; the instruction address indicates the storage location of the branch instruction to be written, and the destination address indicates the storage location of the instruction to be executed when the branch instruction to be written jumps; The generation module is configured to generate metadata for the destination address based on the length of the low-order difference portion; the metadata is used to characterize the length of the low-order difference portion. A component module is used to assemble the branch entry label, the metadata, and the low-order difference portion into a branch entry to be written. The second processing module is used to identify the free slots of the row to be written based on the vector bits of the row to be written, and to write the branch table entry to be written based on the free slots.

9. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 7.

10. A machine-readable medium, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 7.

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