Memory management method, memory controller, storage device, and program product

Abstract

The present disclosure provides a memory management method, a memory controller, a storage device and a program product. The buffer memory of the storage device comprises a shared elastic resource pool shared by a plurality of write streams. The memory management method comprises: monitoring the write behavior of a target write stream in the plurality of write streams to determine a plurality of running characteristics of the target write stream; determining a target buffer capacity of the target write stream and a target programming mode corresponding to the target buffer capacity according to the plurality of running characteristics and the available state of the shared elastic resource pool; adjusting the amount of buffer resources allocated to the target write stream from the shared elastic resource pool according to the target buffer capacity; and programming the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode. Thus, the amount of buffer resources obtained by each write stream from the shared elastic resource pool can be adjusted according to its current write behavior.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and more particularly to a control technology that dynamically allocates buffer memory resources and selects the corresponding programming mode according to the writing behavior of each write stream when a storage device receives multiple write streams issued by a host system. It also relates to a memory management method, a memory controller, a storage device, and a program product. Background Technology

[0002] When a host system writes data to a storage device, it typically divides the write operation into multiple concurrent write streams based on the data type and lifecycle. For example, in a zoned universal flash storage architecture, multiple partition write streams and one general logic cell write stream are opened simultaneously. The write data issued by the host system is first temporarily stored in the buffer memory of the memory controller. After accumulating to the amount of data required for a single programming operation of the memory module, the memory controller then programs the data into the memory module. The capacity reserved in the buffer memory for a single write stream determines the planar parallelism and programming mode that the write stream can adopt. To enable each write stream to adopt a programming mode with a high degree of parallelism during concurrent writes, a common practice is to statically configure the buffer memory, that is, to reserve a fixed amount of capacity for each write stream to support the highest degree of parallelism. However, the write behavior of the host system on each write stream varies in time and space. Some write streams only carry fragmented small amounts of writes over long periods of time, while others only experience continuous high-throughput writes during specific periods. Under the above static configuration method, the capacity of the buffer memory is decoupled from the actual needs of the write stream. The on-chip buffer memory is in a low-occupancy state for a long time, which not only increases the chip area and power consumption of the memory controller, but also makes it difficult to adjust the available buffer capacity and programming mode of each write stream according to the load change. Summary of the Invention

[0003] In view of this, the present disclosure provides a memory management method, a memory controller, a storage device, and a program product. The method determines multiple operational characteristics of a target write stream by monitoring its write behavior. Based on these multiple operational characteristics and the availability of a shared elastic resource pool, it determines a target buffer capacity and a target programming mode corresponding to the target buffer capacity. It adjusts the amount of buffer resources allocated from the shared elastic resource pool to the target write stream based on the target buffer capacity, and programs the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode. This ensures that the buffer capacity occupied by each write stream and the programming mode adopted by each write stream are determined by the current write behavior of that write stream, without needing to reserve a fixed capacity for each write stream to support the highest parallelism.

[0004] According to a first aspect of this disclosure, a memory management method is provided, applicable to a storage device including a memory controller, a buffer memory, and a memory module. The storage device receives write commands from multiple write streams issued by a host system via the memory controller. The buffer memory includes a shared elastic resource pool shared by the multiple write streams. The method includes: monitoring the write behavior of a target write stream among the multiple write streams to determine multiple operating characteristics of the target write stream; determining a target buffer capacity and a target programming mode corresponding to the target buffer capacity based on the multiple operating characteristics and the availability status of the shared elastic resource pool; adjusting the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; and programming the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode.

[0005] According to a second aspect of this disclosure, a memory controller is provided, suitable for use in a storage device, the storage device including a memory module and a connection interface circuit for communicating with a host system. The memory controller is used to process multiple write streams issued by the host system. The memory controller includes: a data management circuit electrically connected to the connection interface circuit, used to receive write commands and write data corresponding to the multiple write streams via the connection interface circuit; a memory interface control circuit electrically connected to the memory module; a buffer memory including a shared elastic resource pool shared by the multiple write streams; and a processor electrically connected to the data management circuit, the memory interface control circuit, and the buffer memory, wherein the processor is configured to: monitor the write behavior of a target write stream among the multiple write streams to determine multiple operating characteristics of the target write stream; determine a target buffer capacity of the target write stream and a target programming mode corresponding to the target buffer capacity based on the multiple operating characteristics and the availability status of the shared elastic resource pool; adjust the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; and control the memory interface control circuit to program the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode.

[0006] According to a third aspect of this disclosure, a storage device is provided, comprising: a connection interface circuit for communicating with a host system; a memory module; and a memory controller electrically connected to the connection interface circuit and the memory module for processing multiple write streams issued by the host system. The memory controller includes a buffer memory, which includes a shared elastic resource pool shared by the multiple write streams. The memory controller is configured to: monitor the write behavior of a target write stream among the multiple write streams to determine multiple operating characteristics of the target write stream; determine a target buffer capacity and a target programming mode corresponding to the target buffer capacity based on the multiple operating characteristics and the availability status of the shared elastic resource pool; adjust the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; and program the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode.

[0007] According to a fourth aspect of this disclosure, a computer program product is provided, comprising a computer program adapted to be loaded and executed by a memory controller of a storage device. The storage device includes a buffer memory and a memory module. The storage device is configured to receive write commands from multiple write streams issued by a host system. The buffer memory includes a shared elastic resource pool shared by the multiple write streams. When the computer program is loaded and executed by the memory controller, the memory controller performs the following steps: monitoring the write behavior of a target write stream among the multiple write streams to determine multiple operating characteristics of the target write stream; determining a target buffer capacity of the target write stream and a target programming mode corresponding to the target buffer capacity based on the multiple operating characteristics and the availability status of the shared elastic resource pool; adjusting the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; and programming the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode.

[0008] Based on the above, the memory management method, memory controller, storage device, and program product provided in this disclosure, by monitoring the write behavior of a target write stream and determining multiple operating characteristics of the target write stream, enable the determination of the target buffer capacity and target programming mode to be based on the current write behavior of the target write stream, rather than on a pre-fixed configuration; by using the multiple operating characteristics and the availability status of the shared elastic resource pool as the basis for determination, the determination process simultaneously considers the needs of a single write stream and the current reserve of the shared elastic resource pool; by determining the target buffer capacity and the target programming mode corresponding to the target buffer capacity together, the two maintain a corresponding relationship in the determination results, rather than being selected independently; and by adjusting the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity, the buffer resources can be allocated on demand between the shared elastic resource pool and each write stream. Furthermore, when multiple write streams are not simultaneously at peak demand, the total capacity required for the shared elastic resource pool can be less than the sum of the capacities required to support the highest parallelism for each write stream. This helps reduce the area and power consumption of the on-chip buffer memory of the memory controller, thereby helping to reduce the manufacturing cost of the memory controller. Attached Figure Description

[0009] Figure 1A This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure;

[0010] Figure 1B This is a comparative schematic diagram showing the buffer resource configuration methods according to the embodiments of this disclosure;

[0011] Figure 1C This is a schematic diagram illustrating the functional hierarchy and state feedback of buffer resource scheduling according to embodiments of the present disclosure;

[0012] Figure 2 This is a main flowchart of a memory management method according to embodiments of the present disclosure;

[0013] Figure 3 A flowchart illustrating the steps of statistical context updating and runtime feature determination according to embodiments of this disclosure;

[0014] Figure 4 This is a schematic diagram illustrating the basic guaranteed capacity and shared elastic resource pool structure according to an embodiment of the present disclosure;

[0015] Figure 5 This is a schematic diagram showing the mapping between operating characteristics, capacity levels, and programming modes according to embodiments of this disclosure;

[0016] Figure 6 The following is a flowchart illustrating the branching process of silent timeout termination and capacity return according to an embodiment of this disclosure.

[0017] Figure 7 A branch flowchart of congestion protection shown according to embodiments of this disclosure;

[0018] Figure 8 This is an interactive timing diagram illustrating command reception, statistics, resource adjustment, and programming according to embodiments of the present disclosure. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0020] Figure 1A This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1A The host system 10 is, for example, a mobile phone, tablet computer, laptop computer, personal computer, or server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is electrically connected to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0021] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0022] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130. In this embodiment, the host system 10 divides the write operation into multiple concurrent write streams according to the data type and lifecycle, and sends the write commands and write data of each write stream to the storage device 20 via the data transmission interface circuit 130; the number of write streams can be, for example, seven.

[0023] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via a wired connection or wirelessly communicate with the storage device 20. The storage device 20 can be, for example, an embedded storage device, a solid-state drive (SSD), a USB flash drive, a memory card, or a wireless storage device. The embedded storage device can be, for example, a storage device conforming to the Universal Flash Storage (UFS) specification or a storage device conforming to the embedded MultiMediaCard (eMMC) specification. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via a system bus to various input / output devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, and speakers.

[0024] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol. In another embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with general flash memory specifications or embedded multimedia card specifications, and utilize the communication protocol defined by the corresponding specification for data transmission; in the embodiment compatible with general flash memory specifications, the multiple write streams may, for example, include six open partition write streams and one ordinary logic cell write stream.

[0025] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.

[0026] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0027] The control functions of the memory controller 210 can be implemented by hardware logic circuits, firmware executed by the processor 211, or a combination thereof. The memory controller 210 performs operations such as writing, reading, and erasing data in the memory module 220 according to the instructions of the host system 10, and executes the memory management method provided in this disclosure.

[0028] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is configured with multiple control instructions or program codes, and these control instructions or program codes are executed when the storage device 20 is running to perform operations such as writing, reading, and erasing data.

[0029] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, the processor 211 monitors the write behavior of a target write stream among multiple write streams to determine multiple operating characteristics of the target write stream; based on the multiple operating characteristics and the availability status of the shared elastic resource pool, it determines the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity; based on the target buffer capacity, it adjusts the amount of buffer resources allocated from the shared elastic resource pool to the target write stream; and based on the target programming mode, it controls the memory interface control circuit 213 to program the write data corresponding to the target write stream from the buffer memory 214 to the memory module 220.

[0030] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0031] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. The memory controller 210 is electrically connected to the connection interface circuit 230 and the memory module 220. The processor 211 in the memory controller 210 is electrically connected to the data management circuit 212, the memory interface control circuit 213, and the buffer memory 214. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0032] The data management circuit 212 is electrically connected to the processor 211 and the connection interface circuit 230, and forms an electrical connection path with the memory interface control circuit 213 via the processor 211. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transmission. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data to the host system 10 via the connection interface circuit 230. In one embodiment, the data management circuit 212 receives write commands and write data corresponding to multiple write streams via the connection interface circuit 230. The hardware circuitry used to update the statistical context (also known as statistical information) is provided by the data management circuit 212. The memory controller 210 maintains a corresponding statistical context for each of the multiple write streams. The statistical context includes the cumulative amount of data written, the write command count, and the timestamp of the most recent write command. Each statistical context can be carried, for example, by a dedicated hardware register located in the command parsing path of the data management circuit 212. When the data management circuit 212 receives a write command corresponding to a target write stream, it updates the statistical context corresponding to that target write stream without passing through the processor 211. The processor 211 then reads the statistical context corresponding to the target write stream at predetermined evaluation cycles to determine multiple operational characteristics of the target write stream; the specific content of these operational characteristics and their determination method will be discussed later. Figure 3 The embodiments are further elaborated here.

[0033] In another embodiment, the data transmission portion of the data management circuit 212 may also be integrated into the processor 211, while the update of the statistical context is still performed by the hardware circuitry, and this update does not pass through the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming) operations, read operations, or erase operations on the memory module 220.

[0034] Furthermore, the data to be written to the memory module 220 is converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction code or program code. For example, a read instruction sequence may include information such as the read identifier, memory address, and physical address.

[0035] Furthermore, the memory controller 210 establishes a Logical to Physical Address Mapping Table and a Physical to Logical Address Mapping Table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses of physical units (e.g., physical erase units or physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the Logical to Physical Address Mapping Table (also called the Logical to Physical Mapping Table) to find the physical unit mapped to a logical unit (e.g., finding the physical page mapped to a logical page; finding the physical address mapped to a logical address), and the memory controller 210 can use the Physical to Logical Address Mapping Table (also called the Physical to Logical Mapping Table) to find the logical unit mapped to a physical unit (e.g., finding the logical page mapped to a physical page; finding the logical address mapped to a physical address).

[0036] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. Buffer memory 214 may be, for example, a static random access memory (SRAM) located within memory controller 210, but this disclosure is not limited thereto; buffer memory 214 may also be other suitable memories. In this embodiment, buffer memory 214 includes a shared elastic resource pool shared by multiple write streams, and also includes a basic guarantee capacity configured to each of the multiple write streams. This basic guarantee capacity is not occupied by the needs of other write streams among the multiple write streams. Furthermore, buffer memory 214 is also used to temporarily store write data corresponding to the multiple write streams until the write data is programmed into memory module 220 according to the target programming mode. The current buffer capacity of the target write stream includes the basic guarantee capacity configured to the target write stream and the amount of buffer resources allocated to the target write stream from the shared elastic resource pool. The structural relationship between the shared elastic resource pool and the basic guarantee capacity will be discussed later. Figure 1B and Figure 4 The embodiments are further elaborated here.

[0037] The memory module 220 is electrically connected to the memory controller 210 and is used to store user data sent by the host system 10. The memory interface control circuit 213 in the memory controller 210 is electrically connected to the memory module 220 and provides interface control over the memory module 220. In this disclosure, the memory module 220 is the object programmed from the buffer memory 214 into the target write data corresponding to the target write stream according to the target programming mode. Specifically, the programming modes supported by the memory module 220 include single-level cell single-plane programming, single-level cell multi-plane programming, and three-level cell full-plane programming. Each programming mode requires a different amount of data to perform a single programming operation, and the target buffer capacity corresponds to the amount of data required by the memory module 220 to perform a single programming operation in the target programming mode. The correspondence between the target buffer capacity and the target programming mode will be discussed later. Figure 5 The embodiments are further elaborated here.

[0038] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane includes multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0039] In another embodiment, the hardware circuitry for updating the statistical context may also be a separate hardware circuitry located in the memory controller 210, independent of the data management circuitry 212; this hardware circuitry also updates the corresponding statistical context when a write command corresponding to the target write stream is received, and this update is not transmitted through the processor 211.

[0040] In another embodiment, the storage device 20 is not limited to storage devices conforming to the general flash memory specification. Any storage device that includes a memory controller 210 and a memory module 220, whose buffer memory 214 includes a shared elastic resource pool shared by multiple write streams, whose memory module 220 supports selecting the corresponding programming mode based on the target buffer capacity, and whose host system 10 concurrently issues write commands and write data via multiple write streams, can be used for adjusting the buffer resource amount and selecting the target programming mode. Specifically, the adjustment of the buffer resource amount and the selection of the target programming mode occur within the storage device 20, based on multiple operating characteristics of the target write stream and the availability status of the shared elastic resource pool; the types of parameters used do not change due to different interface specifications between the host system 10 and the storage device 20, and the various judgment thresholds can still be determined as described later. Figure 5 As described in the embodiments, the storage device 20 is configured during initialization according to the specifications of the storage module 220 and the interface speed between the storage device 20 and the host system 10.

[0041] Furthermore, in addition to the general flash memory interface, other interfaces with equivalent transmission control capabilities can also be used between the storage device 20 and the host system 10. This equivalent transmission control capability means that the interface allows the storage device 20 to delay sending handshake information corresponding to the target write stream, causing the host system 10 to postpone transmitting corresponding write data that has not yet received the handshake information, while the storage device 20 still receives the write data that has already received the handshake information and is being transmitted. This will be relevant in subsequent correspondence. Figure 7 In this embodiment, the processor 211 delays sending a Ready To Transfer (RTT) frame to the host system 10, which is the specific form of the handshake information under the general flash memory interface; in embodiments using other interfaces, this limitation is borne by the delayed transmission of the handshake information defined by that interface. It should be noted that interfaces without equivalent transmission control capabilities are not covered by this extension.

[0042] Based on the above Figure 1AThe block diagram of the host system and storage device shown illustrates that the memory controller of the storage device receives write commands and write data from multiple write streams issued by the host system through its data management circuit via the connection interface circuit. Its processor determines the target buffer capacity and the corresponding target programming mode based on the current write behavior of each write stream and the availability status of the shared elastic resource pool. Through its memory interface control circuit, it programs the write data temporarily stored in the buffer memory to the memory module, thereby enabling the buffer memory capacity configuration and the memory module programming mode selection to be coordinated by the same memory controller.

[0043] Figure 1B This is a comparative diagram illustrating buffer resource configuration methods according to embodiments of this disclosure. Please refer to... Figure 1B , Figure 1B Two buffer resource configuration methods are shown side by side in two equal-sized areas. The left area shows the static configuration method of the background technology (hereinafter referred to as the fixed configuration method), and the right area shows the configuration method of this disclosure. There is no causal relationship between the two areas, and they are only used for comparison of configuration results.

[0044] In a fixed configuration, the buffer memory reserves a fixed maximum buffer capacity for each of the multiple write streams to support the highest degree of parallelism, such as... Figure 1B As shown in the left area, the maximum buffer capacity corresponding to each write stream is independent and does not borrow from each other. Specifically, taking a memory module with six planes as an example, if the amount of data required for a single programming operation in a three-level cell full-plane programming is, for example, 288KB, then the maximum buffer capacity required for a single write stream is 288KB. In this configuration, the capacity of the buffer memory used to hold the write data of multiple write streams is the product of the maximum buffer capacity of a single write stream and the number of concurrent write streams:

[0045]

[0046] in This refers to the capacity of the buffer memory used to hold write data from multiple write streams. The maximum buffer capacity that needs to be reserved for a single write stream. This represents the number of concurrent writes to the stream. For example, when... When the size is 288KB and the number of concurrent write streams is seven, It is 2016KB, which is approximately 2MB.

[0047] Reference Figure 1BIn the right-hand region, in the configuration disclosed herein, the multiple write streams 300 issued by the host system 10 include a first write stream 301, a second write stream 302, a third write stream 303, and a fourth write stream 304. Each write stream corresponds to a different data type or lifecycle defined by the host system 10. The buffer memory 214 does not reserve a fixed maximum buffer capacity for each write stream, but rather includes a basic guaranteed capacity 310 configured for each of the multiple write streams 300 and a shared elastic resource pool 320 shared by the multiple write streams 300.

[0048] Specifically, the basic guarantee capacity 310 includes a basic guarantee capacity 311 configured to the first write stream 301, a basic guarantee capacity 312 configured to the second write stream 302, a basic guarantee capacity 313 configured to the third write stream 303, and a basic guarantee capacity 314 configured to the fourth write stream 304. Each basic guarantee capacity is dedicated to its corresponding write stream and is not occupied by the needs of other write streams in the multiple write streams 300; the size of the basic guarantee capacity is, for example, 16KB, so that each write stream still has the capacity to receive a single page write command when the available capacity of the shared elastic resource pool 320 is exhausted.

[0049] Shared elastic resource pool 320 is shared by multiple write streams 300, and its total capacity is, for example, 1MB. Figure 1B As shown in the right-hand area, the allocated portion of the shared elastic resource pool 320 represents a portion of its capacity, while the remaining portion remains idle and available for any of the multiple write streams 300 to request. The current buffer capacity of the target write stream includes the basic guaranteed capacity configured for that target write stream and the amount of buffer resources allocated to that target write stream from the shared elastic resource pool 320. The allocation and return process of the shared elastic resource pool 320 will be discussed later. Figure 4 The embodiments are further elaborated here.

[0050] It should be noted that, Figure 1B The ellipsis at the end of the write stream list in the right-hand area indicates that the number of multiple write streams 300 is not limited to the four shown in the figure. This disclosure does not limit the number of multiple write streams 300. Figure 1B The four write streams shown are an exemplary implementation; Figure 1B The ellipsis at the end of the column in the left area also indicates that the number of write streams is not limited to those shown in the figure.

[0051] Based on the comparison of the two configuration methods above, it can be seen that in the fixed configuration method, the capacity of the buffer memory used to receive written data is fixedly allocated to each write stream; when a write stream is in a low-load state, the buffer capacity reserved but not used by that write stream cannot be obtained by other write streams. In contrast, in the configuration method of this disclosure, each write stream has a basic guaranteed capacity 310, and each write stream can obtain buffer resources from the shared elastic resource pool 320 according to its current writing behavior, and subsequently... Figure 6 In the closing process described in the embodiment, at least a portion of the acquired buffer resources is returned to the shared elastic resource pool 320, so that the capacity of the buffer memory 214 used to receive write data is not permanently divided but fixedly configured among the write streams, allowing it to flow between multiple write streams 300. In this configuration, the capacity of the buffer memory 214 used to receive write data is the sum of the basic guaranteed capacity of each write stream and the capacity of the shared elastic resource pool 320. Accordingly, the capacity of the shared elastic resource pool 320 can be configured according to the concurrent demand of multiple write streams 300: when multiple write streams 300 are not simultaneously at peak demand, the capacity of the shared elastic resource pool 320 can be less than the difference between the sum of the maximum buffer capacity of each write stream and the sum of the basic guaranteed capacity of each write stream. In this case, the capacity of the buffer memory 214 used to receive the written data is less than the corresponding capacity required under the fixed configuration. When multiple write streams 300 may simultaneously be at peak demand, the capacity of the shared elastic resource pool 320 can also be configured to be no less than the difference.

[0052] For example, when there are seven concurrent write streams, each write stream has a base guaranteed capacity of 16KB, each write stream has a maximum buffer capacity of 288KB, and the shared elastic resource pool 320 has a capacity of 1MB (1024KB), the capacity of the buffer memory 214 used to hold the write data is the sum of the base guaranteed capacities of the seven write streams (112KB) and the 1024KB, which is 1136KB, approximately 1.1MB, less than the 2016KB required in the fixed configuration. Under this configuration, the buffer capacity obtainable by a single write stream is not limited by the reduction in this capacity: as will be addressed later. Figure 5As described in the embodiments, the target buffer capacity is selected from multiple capacity levels, with the largest capacity level corresponding to the amount of data required for the memory module 220 to perform one programming operation under three-level unit full-plane programming, which is 288KB in the example of the aforementioned six planes. The buffer resource required for a certain write stream to expand from its basic guaranteed capacity of 16KB to the maximum capacity level is 272KB, which is less than the 1024KB of the shared elastic resource pool 320. Therefore, when the available capacity of the shared elastic resource pool 320 is sufficient to cover the 272KB, the write stream can still obtain a total buffer capacity of 288KB, which is the same as the maximum buffer capacity fixedly reserved for a single write stream under the fixed configuration. As for the situation where multiple write streams 300 are simultaneously under peak demand, and the available capacity of the shared elastic resource pool 320 is insufficient to cover the expansion needs of each write stream, then as will be addressed in the subsequent corresponding... Figure 7 As described in the embodiment, when the local buffer occupancy state of a certain write stream reaches the warning threshold, the data transmission of the host system 10 corresponding to the write stream is restricted, and the data to be programmed in the buffer memory 214 of the write stream is programmed into the memory module 220. The data to be programmed is the data that the write stream has received in the buffer memory 214 but has not yet been programmed into the memory module 220.

[0053] For example, in the case where multiple write streams 300 may simultaneously experience peak demand, the capacity of the shared elastic resource pool 320 can be configured to be the sum of the 272KB of each of the seven write streams, i.e., 1904KB. This makes the sum of the basic guaranteed capacity of the seven write streams (112KB) and the 1904KB of the shared elastic resource pool 320 2016KB, the same as the capacity required under the fixed configuration. Under this configuration, each of the seven write streams can obtain 272KB of buffer resources from the shared elastic resource pool 320, and their current total buffer capacity reaches 288KB. If any write stream is under low load and does not obtain buffer resources from the shared elastic resource pool 320, or according to subsequent corresponding... Figure 6 In this embodiment, when at least a portion of its buffer resources is returned, the returned portion can still be obtained by other write streams among the multiple write streams 300, rather than being reserved for the write stream when it is under low load, as in the fixed configuration. It should be noted that when the capacity of the shared elastic resource pool 320 is not less than the difference, and the amount of buffer resources obtained by each write stream from the shared elastic resource pool 320 is limited to the difference between its target buffer capacity and its basic guaranteed capacity, the expansion needs of each of the multiple write streams 300 can be met by the shared elastic resource pool 320; subsequent corresponding... Figure 7The protection processing described in the embodiments is for situations where the available capacity of the shared elastic resource pool 320 is insufficient to meet the expansion requirements of the target write stream, such as in a configuration where the capacity of the shared elastic resource pool 320 is less than the difference. The above values ​​are examples, and this disclosure does not limit the capacity of the shared elastic resource pool 320.

[0054] It should be noted that, compared with the aforementioned fixed configuration method, the configuration method of this disclosure differs in three aspects. First, in terms of the structure of the buffer resources, the capacity of the buffer memory 214 used to receive written data is not permanently divided and fixedly configured to each write stream, and the unused portion of any write stream can be obtained by other write streams among the multiple write streams 300 through the shared elastic resource pool 320. Secondly, regarding the determination of buffer capacity, the target buffer capacity and the corresponding target programming mode are not predetermined. Instead, they are determined based on multiple operational characteristics of the target write stream and the availability of the shared elastic resource pool 320. These operational characteristics include average write command data volume, write throughput, and write quiescent duration, which respectively characterize the write granularity, total write volume, and write activity of the target write stream. Furthermore, these multiple operational characteristics help distinguish between write streams with small write granularity and high write throughput, write streams with large write granularity and low write throughput, and write streams that experience interruptions during the write process. This prevents these streams from being configured with the same buffer capacity and programming mode simply because they share a single similar operational characteristic. Write streams that experience interruptions during the write process will be further determined based on subsequent corresponding... Figure 6 The embodiment performs final programming and capacity return. Thirdly, regarding the return of buffer resources and the handling of boundary conditions, when the buffer resources acquired by each write stream exceed the timeout threshold for its write silence duration, and it still contains data to be programmed in the buffer memory 214, the subsequent corresponding... Figure 6 In this embodiment, after the data is programmed, at least a portion of it is returned to the shared elastic resource pool 320; and when the available capacity of the shared elastic resource pool 320 is insufficient to meet the expansion requirements of a certain write stream, and the local buffer occupancy status of the write stream reaches a warning threshold, then according to the subsequent corresponding... Figure 7 The embodiment restricts the data transmission of the host system 10 corresponding to the write stream and programs its unprogrammed data to the memory module 220. Accordingly, the target buffer capacity of each write stream is determined according to its current write behavior and the availability of the shared elastic resource pool 320. The unused capacity in the buffer memory 214 can be transferred between multiple write streams 300. Even when the available capacity of the shared elastic resource pool 320 is exhausted and the local buffer occupancy status of a certain write stream reaches the warning threshold, the aforementioned protection process still allows the data received by the write stream to be programmed to the memory module 220, which helps to prevent the buffer memory 214 from overflowing.

[0055] In another embodiment, the buffer resources obtained by one of the multiple write streams 300 from the shared elastic resource pool 320 can make its current buffer capacity twice or other multiples of its target buffer capacity, for example, 576KB in the aforementioned example where the target buffer capacity is 288KB. Specifically, the target buffer capacity of the write stream still corresponds to the amount of data required for the memory module 220 to perform one programming operation in its target programming mode, while its current buffer capacity can accommodate two or more of that amount of write data; while one of the data amounts of write data temporarily stored in the write stream is programmed into the memory module 220 according to its target programming mode, the write stream can still receive subsequent write data issued by the host system 10 through the remaining portion of its current buffer capacity. For this write stream, its receiving of write data and the memory module 220 performing programming operations can overlap in time, without having to wait for the previous programming operation to be completed before receiving subsequent write data. This configuration differs structurally from the aforementioned fixed configuration: in the fixed configuration, the capacity reserved by each write stream is the maximum buffer capacity required for a single write stream; during the period when the write stream performs a programming operation in a programming mode corresponding to this capacity, this capacity is occupied by the write data to be programmed, and the write stream therefore must wait for the programming operation to complete before receiving subsequent write data. In this configuration, the local buffer occupancy status of the write stream depends on subsequent... Figure 7 In this embodiment, the proportion of the data to be programmed in the increased current buffer capacity is used. It should be noted that this configuration increases the amount of buffer resources obtained by the write stream from the shared elastic resource pool 320, causing the available capacity of the shared elastic resource pool 320 to decrease more rapidly. The expansion needs of other write streams in the multiple write streams 300 may not be met by the shared elastic resource pool 320, and will instead enter the subsequent corresponding... Figure 7 The protection process described in the embodiments is applicable when the available capacity of the shared elastic resource pool 320 is sufficient to cover the increase. This disclosure does not limit the ratio between the current buffer capacity and the amount of data required for the single programming operation.

[0056] In another embodiment, the write stream referred to in this disclosure does not correspond to the foregoing. Figure 1AThe open partitions in the embodiments are limited to ordinary logical units. Any concurrent write channel where the host system 10 issues write commands and each channel requires buffer space in the buffer memory 214 to temporarily store write data to be programmed into the memory module 220 can be considered a write stream as described in this disclosure. The memory controller 210 monitors the write behavior of each concurrent write channel, adjusts the amount of buffer resources allocated to the concurrent write channel from the shared elastic resource pool 320, and programs the write data into the memory module 220 according to the determined target programming mode. Specifically, the basic guarantee capacity 310 is configured to each write channel, and the shared elastic resource pool 320 allocates and returns buffer space according to the write behavior of each write channel and its current buffer space requirements, without being limited to the partitioning criteria of the host system 10 for that write channel.

[0057] Furthermore, the number of multiple write streams 300 is not the same as the aforementioned corresponding number. Figure 1A In the embodiment, the number of open partition write streams is limited to six and the number of ordinary logic unit write streams.

[0058] Based on the above Figure 1B The diagram showing the comparison of buffer resource configuration methods illustrates that the buffer memory of the storage device includes a basic guaranteed capacity configured for each write stream and a shared elastic resource pool shared by multiple write streams. This ensures that each write stream has a dedicated capacity that is not occupied by other write streams at any given time. At the same time, the portion exceeding the dedicated capacity can be borrowed from and returned from the shared elastic resource pool according to the current needs of each write stream. This avoids the need to reserve the capacity required to support the highest parallelism for each write stream, or to occupy the capacity required for its peak when the write stream is under low load.

[0059] Figure 1C This is a schematic diagram illustrating the functional hierarchy and state feedback of buffer resource scheduling according to embodiments of this disclosure. Please refer to... Figure 1C As mentioned above Figure 1A According to the embodiments described, the memory controller 210 includes a data management circuit 212, a processor 211, and a buffer memory 214; Figure 1C This section illustrates the roles of each component in the memory management method from a functional perspective, as well as the information transmission paths and status feedback relationships between the components.

[0060] Specifically, write commands and write data from multiple write streams 300 in the host system 10 are transmitted to the data management circuit 212 via arrow A11. The memory controller 210 maintains a corresponding statistical context 390 for each of the multiple write streams 300; the statistical context 390 includes the cumulative amount of written data, write command count, and the timestamp of the most recent write command. In this embodiment, the hardware circuitry for updating the statistical context 390 is the data management circuit 212. Upon receiving a write command corresponding to a target write stream, the data management circuit 212 updates the statistical context 390 corresponding to that target write stream, and this update does not pass through the processor 211. The processor 211 reads the statistical context 390 corresponding to the target write stream via arrow A12 according to a predetermined evaluation cycle to determine multiple operational characteristics of the target write stream; the specific content of the multiple operational characteristics and their determination method will be discussed later. Figure 3 The embodiments are further elaborated here.

[0061] Processor 211 in Figure 1C The method employs two logical modules to represent the decision-making steps in its memory management process. Logic module PR11 determines the target buffer capacity and the corresponding target programming mode for the target write stream based on multiple operational characteristics of the target write stream and the availability status of the shared elastic resource pool 320. Logic module PR12 adjusts the amount of buffer resources allocated from the shared elastic resource pool 320 to the target write stream based on the target buffer capacity. The output of logic module PR11 is transmitted to logic module PR12 via arrow A13, and the output of logic module PR12 is transmitted to buffer memory 214 via arrow A14. Figure 1C As shown by the dashed arrow A16, the availability status of the shared elastic resource pool 320 is fed back to the logic module PR11, ensuring that the determination of the target buffer capacity and target programming mode is based not only on the multiple operational characteristics of the target write stream itself, but also on the current available capacity of the shared elastic resource pool 320. It should be noted that logic modules PR11 and PR12 are drawn with dashed borders within the frame of processor 211, indicating that they are logical steps executed by processor 211 rather than physical components independent of processor 211.

[0062] The buffer memory 214 includes a basic guaranteed capacity 310 configured for multiple write streams 300 and a shared elastic resource pool 320 shared by the multiple write streams 300; the write data corresponding to the target write stream temporarily stored in the buffer memory 214 is programmed into the memory module 220 according to the target programming mode via arrow A15. The structural relationship between the basic guaranteed capacity 310 and the shared elastic resource pool 320 is as described above. Figure 1B Corresponding to the following Figure 4 The embodiments are further elaborated here.

[0063] Based on the above Figure 1C The diagram illustrates the functional hierarchy and status feedback of buffer resource scheduling. The four steps of the memory management method—monitoring write behavior to determine multiple operating characteristics, determining the target buffer capacity and target programming mode, adjusting the amount of buffer resources, and programming the write data to the memory module according to the target programming mode—correspond to the data management circuit's statistics on write behavior and the processor's determination of multiple operating characteristics, the processor's determination of the target buffer capacity and target programming mode, the processor's adjustment of the amount of buffer resources, and the processor's programming of the write data from the buffer memory to the memory module according to the target programming mode. Furthermore, the availability status of the shared elastic resource pool is fed back to the processor to determine the target buffer capacity and target programming mode, forming a closed loop based not only on the write behavior of the target write stream itself but also on the availability status of the shared elastic resource pool.

[0064] Figure 2 This is a main flowchart illustrating a memory management method according to embodiments of the present disclosure. Please refer to... Figure 1A and Figure 2 The memory management method of this embodiment is applicable to storage device 20. Storage device 20 includes memory controller 210, buffer memory 214, and memory module 220. The memory controller 210 receives write commands from multiple write streams issued by host system 10. Buffer memory 214 includes a shared elastic resource pool shared by the multiple write streams. The following steps S210 to S240 are executed by processor 211 in memory controller 210; continuing from the previous text... Figure 1A As explained above, the operations performed by each component of the memory controller 210 can also be regarded as operations performed by the memory controller 210. Therefore, the following steps can also be regarded as being performed by the memory controller 210, or as being performed by the storage device 20 including the memory controller 210.

[0065] In step S210, the processor 211 monitors the write behavior of a target write stream among multiple write streams to determine multiple operational characteristics of the target write stream. Specifically, the multiple write streams can be divided by the host system 10 according to data type and lifecycle, and the target write stream is any write stream currently being evaluated among the multiple write streams. The processor 211 reads the statistical context corresponding to the target write stream according to a predetermined evaluation cycle to determine multiple operational characteristics of the target write stream; the multiple operational characteristics include average write command data volume, write throughput, and write silence duration, and the specific definition and determination method of each operational characteristic will be discussed later. Figure 3 The embodiments are further elaborated here.

[0066] In step S220, the processor 211 determines the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity based on the multiple operating characteristics and the availability status of the shared elastic resource pool. Specifically, the availability status of the shared elastic resource pool refers to the remaining available capacity in the shared elastic resource pool that has not yet been borrowed by any write stream and remains idle. In other words, the processor 211 does not determine the target buffer capacity solely based on the multiple operating characteristics, but incorporates the availability status of the shared elastic resource pool at the time of determination; for example, if the multiple operating characteristics of the target write stream point to a larger target buffer capacity, the availability status also needs to indicate that the shared elastic resource pool has available capacity to meet the expansion requirements of the target write stream. The target buffer capacity corresponds to the amount of data required for the memory module 220 to perform one programming operation in the target programming mode. The correspondence between the target buffer capacity and the target programming mode, and its determination conditions, will be discussed later. Figure 5 The embodiments are further elaborated here.

[0067] In step S230, the processor 211 adjusts the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity. Specifically, the current buffer capacity of the target write stream includes the basic guaranteed capacity configured for the target write stream and the amount of buffer resources allocated from the shared elastic resource pool. The processor 211 adjusts the portion allocated from the shared elastic resource pool in this step. The basic guaranteed capacity configured for the target write stream is dedicated to the target write stream and is not occupied by the needs of other write streams among multiple write streams. When the target buffer capacity is greater than the current buffer capacity of the target write stream, and the availability status indicates that the shared elastic resource pool has available capacity to meet the expansion needs of the target write stream, the processor 211 increases the allocated buffer resources from the shared elastic resource pool for the target write stream. The increased buffer resources can be determined based on the difference between the target buffer capacity and the current buffer capacity of the target write stream. If the available capacity of the shared elastic resource pool is insufficient to meet the expansion needs, the handling will proceed accordingly in subsequent steps. Figure 7 The embodiments are further elaborated here. The structural relationship between the basic guaranteed capacity and the shared elastic resource pool is as described above. Figure 1B The embodiments have been described, and will be followed accordingly. Figure 4 The embodiment further elaborates; the process of performing cleanup according to the write silence duration and returning the buffer resources to the shared elastic resource pool will be addressed in subsequent corresponding steps. Figure 6 The embodiments are further elaborated here.

[0068] In step S240, the processor 211, according to the target programming mode, controls the memory interface control circuit 213 to program the write data corresponding to the target write stream from the buffer memory 214 to the memory module 220. Specifically, the programming modes supported by the memory module 220 include single-level cell single-plane programming, single-level cell multi-plane programming, and three-level cell full-plane programming. Each programming mode requires a different amount of data to perform a programming operation. The write data corresponding to the target write stream is first temporarily stored in the buffer memory 214 until the temporarily stored write data reaches the amount of data required for the target programming mode to perform a programming operation. Then, the memory interface control circuit 213 programs the write data to the memory module 220 according to the target programming mode. As for the programming of data that has not yet reached the required amount when the write silence time of the target write stream exceeds the silence timeout threshold or its local buffer occupancy reaches the warning threshold, the corresponding programming will be handled in subsequent steps. Figure 6 and Figure 7 The embodiments are further elaborated here.

[0069] It should be noted that steps S210 to S240 constitute one round of processing performed by processor 211 for the target write stream. Processor 211 executes steps S210 to S240 for each of the multiple write streams, with each determination targeting the currently evaluated write stream and jointly constrained by the availability status of the shared elastic resource pool. Furthermore, Figure 2 The start and end shown are boundary markers of the process and do not indicate that the memory management method is executed only once. During the operation of the storage device 20, the processor 211 can repeatedly execute steps S210 to S240 according to a predetermined evaluation cycle to periodically update multiple operating characteristics of each write stream and increase the amount of allocated buffer resources when the expansion conditions are met. The return of the buffer resources is performed according to the aforementioned closing process based on the write silence duration.

[0070] Based on the above Figure 2 The illustrated memory management method involves a storage device monitoring the write behavior of a target write stream to determine multiple operational characteristics of that target write stream. Based on these operational characteristics and the availability of a shared elastic resource pool, the device determines a target buffer capacity for the target write stream and a target programming mode corresponding to that target buffer capacity. The device then adjusts the amount of buffer resources allocated from the shared elastic resource pool to the target write stream accordingly. Finally, the device programs the write data corresponding to the target write stream from the buffer memory to the memory module according to the target programming mode. Thus, the target buffer capacity depends on the current write behavior of the target write stream and the availability of the shared elastic resource pool, and corresponds to the amount of data required for the memory module to perform one programming operation in that target programming mode.

[0071] Figure 3This is a flowchart illustrating the steps of statistical context updating and runtime characteristic determination according to embodiments of this disclosure. Please refer to... Figure 1A , Figure 2 and Figure 3 , Figure 3 Steps S310 to S380 shown are as described above. Figure 2 In step S210, the processor 211 monitors the write behavior of the target write stream among multiple write streams to determine the specific implementation of multiple operating characteristics of the target write stream.

[0072] In this embodiment, multiple operational characteristics include average write command data volume, write throughput, and write quiet duration. The average write command data volume characterizes the write granularity of the target write stream, the write throughput characterizes the total write volume of the target write stream, and the write quiet duration characterizes the write activity of the target write stream. In other words, the processor 211 uses three dimensions—write granularity, total write volume, and write activity—to jointly characterize the current write behavior of the same write stream, rather than relying on a single dimension as the basis for judgment.

[0073] In step S310, the memory controller 210 maintains a corresponding statistical context for each of the multiple write streams. Specifically, the statistical context includes the cumulative amount of written data, the write command count, and the most recent write command timestamp; the cumulative amount of written data is the cumulative amount of written data received by the write stream within the current statistical time window, the write command count is the number of write commands received by the write stream within the current statistical time window, and the most recent write command timestamp is the time when the last write command of the write stream arrived. Each statistical context can be carried, for example, by a dedicated hardware register located in the command parsing path of the data management circuit 212. In another embodiment, each dedicated hardware register is configured to a write stream that is currently in the active state among the multiple write streams, and each write stream has its own corresponding statistical context during its active period.

[0074] In step S320, the memory controller 210 receives a write command corresponding to the target write stream via the connection interface circuit 230. In step S330, upon receiving the write command, the hardware circuit updates the cumulative written data volume, write command count, and most recent write command timestamp in the statistical context corresponding to the target write stream, and this update is not performed by the processor 211. Specifically, in this embodiment, the hardware circuit is the data management circuit 212, which identifies the write stream to which the write command belongs in its command parsing path and updates the statistical context corresponding to the write stream. In another embodiment, the hardware circuit may also be a separate hardware circuit independent of the data management circuit 212, which also updates the statistical context corresponding to the target write stream upon receiving the write command, and this update is also not performed by the processor 211.

[0075] The update of the statistical context is performed by the hardware circuit, so that the update can be performed in real time with each write command without occupying the computing resources of the processor 211. The processor 211 does not need to intervene in the recording when each write command arrives, so the observation density of the write behavior and the decision frequency of the processor 211 can be set separately.

[0076] In step S340, the processor 211 reads the statistical context corresponding to the target write stream according to a predetermined evaluation cycle. This evaluation cycle is, for example, 100 milliseconds, meaning the processor 211 reads the statistical context of the target write stream every 100 milliseconds and determines multiple operational characteristics of the target write stream in this evaluation cycle. In this embodiment, the statistical time window is the time interval between two adjacent reads, and its length corresponds to the evaluation cycle. At the end of the statistical time window, the processor 211 reads and saves the current value of the statistical context, and after determining multiple operational characteristics in this round, resets the cumulative written data volume and the write command count to open the next statistical time window. The statistical time window and the evaluation cycle are, for example, both 100 milliseconds, but this disclosure is not limited to this specific duration. The evaluation cycle is, for example, carried by a timer of the memory controller 210, and the processor 211 reads the statistical context during periodic interrupts generated by the timer; this disclosure is not limited to this implementation method.

[0077] In step S350, when the write command count is greater than zero, the processor 211 determines the average write command data volume based on the ratio of the cumulative written data volume to the write command count:

[0078]

[0079] in To average the amount of data written, To accumulate the amount of data written, The write command count is used. For example, when the target write stream receives metadata writes from the file system or log writes from the system background, its average write command data size is, for example, 4KB; when the target write stream receives image data writes from an application, and the total amount of image data is, for example, tens of megabytes, its average write command data size is, for example, 64KB; when the target write stream receives large multimedia file writes, its average write command data size is, for example, 256KB. Furthermore, if the write command count of the target write stream is zero within a certain statistical time window, the processor 211 will not determine the capacity level of the target write stream based on these multiple operating characteristics during this evaluation cycle, but this disclosure is not limited to this; as for the cleanup programming and buffer resource return handling when the write silence duration of the target write stream exceeds the silence timeout threshold, these will be addressed in subsequent corresponding... Figure 6The embodiments are further elaborated here.

[0080] In step S360, the processor 211 determines the write throughput based on the ratio of the cumulative written data volume to the statistical time window:

[0081]

[0082] in For write throughput, This refers to the statistical time window. For example, the write throughput for metadata is 5MB / s, and the write throughput for image data is 80MB / s.

[0083] In step S370, the processor 211 determines the write silence duration based on the time difference between the current time and the timestamp of the most recent write command:

[0084]

[0085] in To write the silence duration, For the current moment, This is the timestamp of the most recent write command. For example, when the target write stream is in a continuous write state, its write silence duration is, for example, 0.5 milliseconds; when the host side of the target write stream has stopped issuing write commands, its write silence duration increases to, for example, 8 milliseconds.

[0086] In step S380, at the end of the statistical time window, the processor 211 resets the cumulative written data volume and the write command count, and retains the timestamp of the most recent write command. Specifically, resetting the cumulative written data volume and the write command count allows the statistical time window to roll, and the average write command data volume and write throughput obtained in each evaluation period correspond to the write behavior within the window; while retaining the timestamp of the most recent write command allows the write silence time to accumulate across the statistical time window, so even if the target write stream does not receive any write commands in multiple consecutive statistical time windows, its write silence time still increases over time.

[0087] It should be noted that the average write command data volume is the average of the data volumes of all write commands within the statistical time window, not the actual data volume of a single write command. When the same statistical time window includes both a large number of write commands with small data volumes and a small number of write commands with large data volumes, the average write command data volume falls between the two. The processor 211 determines the target buffer capacity and target programming mode determination conditions for the target write stream based on these multiple operating characteristics and the availability status of the shared elastic resource pool, and then applies these conditions in subsequent operations. Figure 5 The embodiments are further elaborated here.

[0088] In another embodiment, in step S340, the processor 211 reads the evaluation period on which the statistical context is based, and the statistical time window corresponding to the evaluation period, the duration of which is not limited to the aforementioned 100 milliseconds. Specifically, the duration of the evaluation period is carried by a programmable register of the memory controller 210 and configured during the initialization of the storage device 20. When the duration of the evaluation period is short, the processor 211 reads the statistical context more frequently, and the statistical time window corresponding to each read is shorter; when the duration of the evaluation period is long, the processor 211 reads the statistical context less frequently, and the statistical time window corresponding to each read is longer.

[0089] Furthermore, during the initialization of the storage device 20, the duration of the evaluation cycle can be configured according to at least one of the following: the page programming time (tPROG) of the memory module 220, the interface rate between the storage device 20 and the host system 10, and the computing resources required by the processor 211 to execute steps S340 to S380, and the duration remains unchanged during the operation of the storage device 20.

[0090] Based on the above Figure 3 The illustrated steps for updating the statistical context and determining operational characteristics show that when the storage device receives a write command corresponding to the target write stream, the hardware circuit updates the statistical context of the target write stream in real time. This update does not go through the processor, and the processor reads the statistical context according to a predetermined evaluation cycle to determine the average write command data volume, write throughput, and write silence duration of the target write stream. This allows the current write behavior of the target write stream to be characterized by three dimensions: write granularity, total write volume, and write activity, serving as the basis for subsequently determining the target buffer capacity and target programming mode.

[0091] Figure 4 This is a schematic diagram illustrating the basic guaranteed capacity and shared elastic resource pool structure according to embodiments of this disclosure. Please refer to... Figure 1A , Figure 1B and Figure 4 , Figure 4 The capacity configuration of buffer memory 214 is shown in an expanded view, as well as the correspondence between the current buffer capacity 330 of the target write stream and buffer memory 214.

[0092] like Figure 4 As shown above, the multiple write streams 300 issued by the host system 10 include a first write stream 301, a second write stream 302, a third write stream 303, and a fourth write stream 304. The ellipsis following them indicates that the number of multiple write streams 300 is not limited to the four shown in the figure.

[0093] The buffer memory 214 includes a basic guaranteed capacity 310 configured to multiple write streams 300 and a shared elastic resource pool 320 shared by the multiple write streams 300. The basic guaranteed capacity 310 includes a basic guaranteed capacity 311 configured to the first write stream 301, a basic guaranteed capacity 312 configured to the second write stream 302, a basic guaranteed capacity 313 configured to the third write stream 303, and a basic guaranteed capacity 314 configured to the fourth write stream 304; each basic guaranteed capacity is dedicated to the corresponding write stream and is not occupied by the needs of other write streams among the multiple write streams 300. The shared elastic resource pool 320 is not dedicated to any of the multiple write streams 300, and its capacity can be borrowed according to the current expansion needs of each write stream; in this embodiment, the borrowed capacity is returned after the corresponding write stream stops issuing write commands and completes the final programming.

[0094] The current buffer capacity 330 of the target write stream includes the corresponding basic guaranteed capacity 331 and the buffer resource amount 332 obtained from the shared elastic resource pool 320. The basic guaranteed capacity 331 is the portion of the basic guaranteed capacity 310 allocated to the target write stream, and the buffer resource amount 332 is the portion of the shared elastic resource pool 320 currently allocated to the target write stream. In other words, in this embodiment, the capacity available for the target write stream to receive write data at any given time is the sum of its dedicated basic guaranteed capacity 331 and the buffer resource amount 332 borrowed from the shared elastic resource pool 320; the processor 211 follows the aforementioned correspondence... Figure 2 The adjustment in step S230 is to the amount of buffer resources 332, while the basic guarantee capacity 331 remains unchanged.

[0095] As shown by arrow A41, after determining the target buffer capacity of the target write stream, the processor 211 compares the target buffer capacity with the current buffer capacity 330 of the target write stream; if the target buffer capacity is greater than the current buffer capacity 330, the processor 211 allocates the difference between the two from the shared elastic resource pool 320 to the target write stream, thereby increasing the buffer resource amount 332.

[0096]

[0097] in The increment of buffer resources allocated from the shared elastic resource pool 320 to the target write stream. The target buffer capacity is the target write stream. The current buffer capacity of the target write stream is 330. For example, a write stream originally configured with only 16KB of buffer capacity was used to handle metadata writing to the file system. Subsequently, the host system 10 began to send large multimedia files through the write stream. The processor 211 determined its target buffer capacity to be 288KB based on multiple operating characteristics of the write stream. Then, the processor 211 allocated 272KB of buffer resources from the shared elastic resource pool 320 to the write stream, so that the current buffer capacity 330 of the write stream reached a total of 288KB. The target programming mode of the write stream was switched from single-level unit single-plane programming to three-level unit full-plane programming.

[0098] As shown by arrow A42, in this embodiment, after the write silence duration of the target write stream exceeds the silence timeout threshold, thus determining that it has stopped issuing write commands and completed the finalization programming, the buffer resource 332 is returned to the shared elastic resource pool 320, so that this portion of capacity can be borrowed by other write streams among multiple write streams 300; the finalization programming and return process will be discussed in subsequent corresponding... Figure 6 The embodiments are further elaborated here. Furthermore, the amount of buffer resources returned is limited to those not carrying data to be programmed. If a buffer area carrying unprogrammed data is returned, that data cannot be preserved; therefore, this portion of the capacity can only be returned after the data it carries has been programmed.

[0099] It should be noted that the total amount of buffer resources borrowed by multiple write streams 300 from the shared elastic resource pool 320 does not exceed the capacity of the shared elastic resource pool 320. Therefore, when the processor 211 allocates buffer resources to the shared elastic resource pool 320 according to the target buffer capacity, the availability status of the shared elastic resource pool 320 must indicate that its available capacity is sufficient to cover the difference between the target buffer capacity and the current buffer capacity 330. If the available capacity is insufficient to cover the difference, the difference allocation is not performed, and this embodiment does not further limit the capacity level in this case. As for the situation where the local buffer occupancy status of the target write stream has reached the warning threshold and the available capacity of the shared elastic resource pool 320 is insufficient, its handling will be addressed in subsequent corresponding actions. Figure 7 The embodiments are further elaborated here.

[0100] This disclosure does not limit the allocation order of the shared elastic resource pool 320 when multiple write streams 300 simultaneously request allocation, nor does it limit the specific partitioning method of the shared elastic resource pool 320. Furthermore, after the aforementioned allocation or return is completed, the availability status of the shared elastic resource pool 320 is updated accordingly and used as input for determining the capacity level in subsequent evaluation cycles; the local buffer occupancy status of the target write stream is monitored in real time by hardware, and corresponding processing is triggered immediately when the corresponding triggering conditions are met, without waiting for subsequent evaluation cycles.

[0101] In another embodiment, processor 211 corresponds to the aforementioned Figure 2 The adjustment performed in step S230, in addition to increasing the allocated buffer resource amount 332 from the shared elastic resource pool 320 to the target write stream, also includes returning the difference from the buffer resource amount 332 to the shared elastic resource pool 320 when the target buffer capacity is less than the current buffer capacity 330 of the target write stream, as shown by arrow A42. Specifically, the processor 211 obtains the difference between the target buffer capacity and the current buffer capacity 330, allocates the capacity corresponding to the difference from the shared elastic resource pool 320 when the difference is greater than zero, and returns the capacity corresponding to the difference to the shared elastic resource pool 320 when the difference is less than zero.

[0102] In this other embodiment, the buffer resource amount 332 is adjusted according to changes in the write behavior of the target write stream before it stops issuing write commands, without waiting for the aforementioned closing process based on the write silence duration. This return and the increase in allocation correspond to subsequent actions. Figure 5 The correspondence shown determines the target buffer capacity, the difference being that the determined target buffer capacity is less than the current buffer capacity 330; processor 211 does not use a single operational characteristic as the basis for return. The amount of buffer resources 332 returned is still limited to those not carrying data to be programmed. The relationship between the threshold used for return and the threshold used for increased allocation will be discussed in subsequent correspondences. Figure 5 The embodiments are further elaborated here.

[0103] In another embodiment, if the capacity involved in the aforementioned return carries data to be programmed, the processor 211 has two processing methods. In the first processing method, the processor 211 determines the programming mode to be adopted based on the amount of data in that portion, and controls the memory interface control circuit 213 to program that portion of data into the memory module 220 according to the programming mode. Only after that portion of capacity no longer carries unprogrammed data is it returned to the shared elastic resource pool 320. In the second processing method, the processor 211 only returns the portion of the buffer resource 332 that does not carry unprogrammed data in this instance, and the remaining portion is returned after the data it carries is programmed. This disclosure does not limit the use of any of these methods, nor is it limited to the above processing methods.

[0104] In another embodiment, the minimum accepting unit corresponding to the buffer capacity configured for each write stream has two implementations. In the first implementation, the minimum accepting unit is the amount of data corresponding to one physical page of the memory module 220; when the amount of data corresponding to a write command is greater than the minimum accepting unit, the memory controller 210 writes the write data to the buffer memory 214 in multiple parts according to the minimum accepting unit, and the buffer memory 214 does not need to contain the entire write data corresponding to the write command at once. In the second implementation, the minimum accepting unit is the write data corresponding to a complete write command; the current buffer capacity 330 of the target write stream is not less than its current average write command data size, which helps to accept the write data corresponding to a single write command whose data size is not greater than the average write command data size at once. This disclosure does not limit the use of either of these implementations, nor is it limited to the above-described embodiments.

[0105] In another embodiment, the internal organization and accounting method of the shared elastic resource pool 320 are implemented in the following parallel ways. In the first embodiment, the capacity of the shared elastic resource pool 320 is divided into multiple buffer resource blocks of the same size, and the size of each buffer resource block is the amount of data corresponding to one physical page of the memory module 220; the borrowing and returning of buffer resource amount 332 is based on buffer resource block, and the buffer resource amount 332 allocated to the target write stream is the product of the number of buffer resource blocks allocated to it and the size, while the availability state of the shared elastic resource pool 320 is the product of the number of currently free buffer resource blocks and the size. In this embodiment, since the capacity corresponding to each capacity level is the amount of data required for the memory module 220 to perform one programming operation in the corresponding programming mode, and this amount of data is an integer multiple of the amount of data corresponding to the physical page, the capacity corresponding to each capacity level is an integer multiple of the size of the buffer resource block. When each basic guarantee capacity is configured in units of the buffer resource block, the amount of buffer resources 332 that the target write stream needs to borrow is also the product of the number of buffer resource blocks and the size. In the second embodiment, the shared elastic resource pool 320 uses segment accounting. When borrowing, the processor 211 records the starting position and length of the borrowed segment, and when returning, marks the segment as free and updates the corresponding record. In the third embodiment, the shared elastic resource pool 320 pre-sets corresponding sub-pools for each capacity level that is larger than the basic guaranteed capacity. Each sub-pool uses the difference between its corresponding capacity level and the basic guaranteed capacity as an allocation unit. When one sub-pool has no available allocation units, the processor 211 takes an allocation unit from the sub-pool corresponding to the larger capacity level. The portion equivalent to the allocation unit of the smaller capacity level is allocated to the target write stream, and the remainder is reserved as available capacity for the sub-pool of the smaller capacity level. When the target buffer capacity of the target write stream corresponds to another capacity level, the processor 211 returns the previously acquired allocation unit to the atomic pool and takes an allocation unit from the sub-pool corresponding to the other capacity level. In the fourth embodiment, the shared elastic resource pool 320 is not pre-divided into identifiable parts, but is maintained by the memory controller 210 in a quota accounting manner: the processor 211 records the current available capacity of the shared elastic resource pool 320, and records the amount of buffer resources 332 acquired by each of the multiple write streams 300; when performing allocation, the processor 211 subtracts the capacity allocated in this allocation from the available capacity, and increases the amount of buffer resources 332 recorded by the write stream by the same amount; when performing return, the processor 211 updates the two records in reverse according to the actual returned capacity.In this embodiment, the storage space occupied by the write data of the target write stream in the buffer memory 214 is obtained by the memory controller 210 within the limit defined by the record, and the capacity available for the target write stream to receive write data at any time is still the sum of its basic guaranteed capacity 331 and the amount of buffer resources 332 carried by the record.

[0106] Furthermore, the buffer resource amount 332 allocated to the target write stream in the address space of the buffer memory 214 has the following parallel implementations. In the first implementation, the addresses corresponding to the buffer resource amount 332 are contiguous, which helps to reduce the number of segmentation steps required for the memory interface control circuit 213 to move the write data temporarily stored in the target write stream. In the second implementation, the buffer resource amount 332 includes multiple buffer resource blocks with non-contiguous addresses. The memory controller 210 maintains the correspondence between the target write stream and each of its allocated buffer resource blocks, and the memory interface control circuit 213 moves the write data in stages according to the correspondence. This disclosure does not limit the use of any of these implementations, nor is it limited to the above-described embodiments.

[0107] In another embodiment, when two or more write streams 300 are determined to require increased allocation of buffer resources in the same evaluation cycle, and the available capacity of the shared elastic resource pool 320 is insufficient to meet all requirements, the processor 211 has the following parallel implementations for the allocation order. In the first implementation, the processor 211 allocates resources sequentially according to the order in which it completes the determination of each of the multiple write streams 300, until the available capacity of the shared elastic resource pool 320 is insufficient to cover the subsequent shortfall. In the second implementation, the processor 211 first obtains the shortfall required by each of these write streams, and then allocates resources sequentially from high to low according to the local buffer occupancy status of each write stream. In the third implementation, the processor 211 allocates resources sequentially from small to large according to the shortfall required by each write stream, which helps to ensure that more write streams are allocated in the current evaluation cycle, while those requiring larger shortfalls are left to be determined in subsequent evaluation cycles. In the fourth embodiment, the processor 211 allocates the available capacity of the shared elastic resource pool 320 according to the proportion of the difference required by each write stream, and aligns the sum of the capacity allocated to each write stream and its current buffer capacity 330 downwards to a maximum capacity level not exceeding the sum. The difference between the capacity level and the current buffer capacity 330 is used as the actual allocated buffer resource amount 332 for this time. The write data of the write stream is programmed into the memory module 220 in this time according to the programming mode corresponding to the capacity level. If there is no capacity level not exceeding the sum, or if the capacity level is not greater than the current buffer capacity 330, the write stream does not obtain allocation in this time and is left to be determined in a subsequent evaluation cycle. In the fifth embodiment, a portion of the capacity of the shared elastic resource pool 320 is reserved and does not participate in the allocation of the current evaluation cycle. The reserved portion is not included in the aforementioned available state, which helps the write streams that are determined to increase allocation in subsequent evaluation cycles to obtain the buffer resource amount 332 from the reserved portion.

[0108] Each of the above embodiments may be selected and is not limited to the above embodiments; the fifth embodiment may also be combined with any of the other four.

[0109] Based on the above Figure 4 The schematic diagram of the basic guaranteed capacity and shared elastic resource pool shown indicates that the storage device allows each write stream to maintain its own dedicated and unoccupied basic guaranteed capacity. When the capacity exceeds the dedicated capacity, it is borrowed from the shared elastic resource pool when the expansion conditions are met. The capacity is returned after the corresponding write stream stops issuing write commands and completes the closing programming. This allows the shared buffer capacity to continue to be used by other write streams, without having to reserve the capacity required for the peak of each write stream.

[0110] Figure 5 This is a schematic diagram illustrating the mapping between operating characteristics, capacity levels, and programming modes according to embodiments of this disclosure. Please refer to... Figure 1A , Figure 2 , Figure 3 , Figure 4 and Figure 5 , Figure 5 The processor 211 is shown in the aforementioned correspondence. Figure 2 In step S220, the correspondence between the target buffer capacity and the target programming mode is determined based on multiple operating characteristics and the availability status of the shared elastic resource pool.

[0111] like Figure 5 As shown on the left, the operational characteristics FC include average write command data volume FC1, write throughput FC2, and write silent duration FC3. The definitions and determination methods of these three have been described above. Figure 3 The embodiments are illustrated below. The availability state FC4 of the shared elastic resource pool is used as input for the determination, along with the operating characteristics FC1 to FC3. However, it is not the operating characteristic of the target write stream, but rather the current available capacity state of the shared elastic resource pool.

[0112] like Figure 5 As shown on the right, capacity level 340 includes a first buffer capacity 341, a second buffer capacity 342, and a third buffer capacity 343 that increase sequentially. Programming mode 350 includes single-layer unit single-plane programming 351, single-layer unit multi-plane programming 352, and three-layer unit full-plane programming 353. The target buffer capacity is selected from capacity level 340, and each capacity level corresponds to a different programming mode.

[0113] Condition set CD1 is as follows Figure 5 As shown in the first line, when the average write command data volume is not greater than the first data volume threshold, the write throughput is lower than the first rate threshold, and the write silence duration is less than the silence timeout threshold, as shown by arrow A51, the processor 211 determines the target buffer capacity as the first buffer capacity 341; as shown by arrow A54, the target programming mode corresponding to the first buffer capacity 341 is single-level unit single-plane programming 351. When multiple operating characteristics of the target write stream hit the set of conditions CD1, and the current buffer capacity 330 of the target write stream is its basic guaranteed capacity 331, the current buffer capacity 330 of the target write stream is maintained at the basic guaranteed capacity 331, and the buffer resource amount 332 is not obtained from the shared elastic resource pool 320. This helps to reduce the occupation of the buffer capacity exceeding the basic guaranteed capacity 331 by fragmented small writes, and helps to keep more available capacity in the shared elastic resource pool 320 for other write streams to obtain during expansion.

[0114] Condition set CD2 is as follows Figure 5As shown in the second line, when the average write command data volume is greater than the first data volume threshold but not greater than the second data volume threshold, the write throughput is not lower than the first rate threshold but not higher than the second rate threshold, and the write quiescent duration is not greater than the active interval threshold, as shown by arrow A52, the processor 211 determines the target buffer capacity as the second buffer capacity 342; as shown by arrow A55, the target programming mode corresponding to the second buffer capacity 342 is single-level unit multi-plane programming 352. For example, when host system 10 sends image data of an application via the target write stream, and the total amount of the image data is, for example, tens of megabytes, and the average write command data volume of the target write stream is, for example, 64KB, the write throughput is, for example, 80MB per second, and the write silence duration is, for example, 0.5 milliseconds, which is less than the active interval threshold of, for example, 1 millisecond, processor 211 determines that the target buffer capacity is the second buffer capacity 342, for example, 96KB, and the target programming mode is single-level unit multi-plane programming 352; when the current buffer capacity 330 of the target write stream is its 16KB base guarantee capacity 331, processor 211 performs the corresponding operation as described above. Figure 4 In this embodiment, 80KB of buffer resources 332 are allocated from the shared elastic resource pool 320. When multiple operational characteristics of the target write stream hit the active burst write condition set CD2, and the current buffer capacity 330 of the target write stream is its base guaranteed capacity 331, and the available capacity of the shared elastic resource pool 320 is sufficient to cover the difference between the second buffer capacity 342 and the current buffer capacity 330, its current buffer capacity 330 is increased from the base guaranteed capacity 331 to the second buffer capacity 342. The temporarily stored write data can then be programmed in parallel to multiple planes in a single programming operation using single-level unit multi-plane programming 352. Compared to single-level unit single-plane programming 351, this helps improve the write performance of the target write stream under medium load and the response speed for handling burst write data. Examples of the values ​​for each threshold and capacity level will be explained later.

[0115] Condition set CD3, such as Figure 5As shown in the third line, when the average write command data volume is greater than the second data volume threshold, the write throughput is higher than the second rate threshold, and the availability state FC4 indicates that the shared elastic resource pool has available capacity to meet the expansion requirements of the target write stream, as shown by arrow A53, the processor 211 determines the target buffer capacity as the third buffer capacity 343; as shown by arrow A56, the target programming mode corresponding to the third buffer capacity 343 is three-level unit full-plane programming 353. When the target buffer capacity is the third buffer capacity 343, the write data temporarily stored in the target write stream can be programmed using three-level unit full-plane programming 353, which programs a larger amount of data in one programming operation than the data programs in one programming operation of single-level unit single-plane programming 351 and single-level unit multi-plane programming 352, thus helping to improve the write throughput of the target write stream under continuous large-volume writes.

[0116] It should be noted that the conditions listed in condition sets CD1 to CD3 are the conditions required for the set to be true. Figure 5If a cell is not shown in a certain decision dimension, it indicates that the set is not conditioned on the value of that dimension. Furthermore, each capacity level corresponds to the amount of data required for the memory module 220 to perform one programming operation in the corresponding programming mode. For example, taking a memory module 220 with six planes and a single physical page of 16KB for each plane as an example, the amount of data required for a single-level cell single-plane programming 351 to perform one programming operation is one physical page of one plane, for example, 16KB, so the first buffer capacity 341 is, for example, 16KB; the amount of data required for a single-level cell multi-plane programming 352 to perform one programming operation is the six planes within the scope of a chip enable (CE) signal to complete the programming at once, for example, the product of the number of the six planes and the physical page size, which is 96KB, so the second buffer capacity 342 is, for example, 96KB; the amount of data required for a single-level cell full-plane programming 353 to perform one programming operation is the same as the six planes within the scope of the chip enable signal to complete the programming at once, and each memory cell of the three-level cell stores three bits, so the amount of data required is, for example, the product of the number of the six planes, the physical page size and the number of bits stored in each memory cell, which is 288KB, so the third buffer capacity 343 is, for example, 288KB. The aforementioned number of planes and physical page size are examples, and this disclosure is not limited thereto. In one embodiment, since each capacity level matches its corresponding programming mode, the temporarily stored write data can be programmed as soon as it accumulates to the amount of data required for one programming operation. This helps reduce the number of operations of the memory module 220, thereby helping to reduce write amplification and power consumption, and helping to extend the lifespan of the memory module 220. In one embodiment, when the target programming mode of the target write stream is three-level cell full-plane programming 353, after the write data corresponding to the target write stream accumulates in the buffer memory 214 to the amount of data required for one programming operation of the target programming mode, it is directly programmed from the buffer memory 214 to the memory module 220 according to the three-level cell full-plane programming 353, without going through the intermediate process of writing to the memory module 220 by single-level cell programming.

[0117] The capacity level 340 is configured based on at least one of the following: physical page size, number of planes, cell programming mode, and programming parallelism of the memory module 220. The first data volume threshold, the second data volume threshold, the first rate threshold, the second rate threshold, the active interval threshold, and the silent timeout threshold are carried by the programmable registers of the memory controller 210 and are configured during the initialization of the memory device 20 according to the specifications of the memory module 220 and the interface speed between the storage device 20 and the host system 10.

[0118] The first rate threshold is set according to the upper limit of the write rate of single-level unit single-plane programming, the second rate threshold is set according to a predetermined proportion of the maximum bandwidth supported by single-level unit multi-plane programming, and the active interval threshold is set according to the page programming time of memory module 220. In one embodiment, the first rate threshold is set to be slightly higher than the upper limit of the write rate of single-level unit single-plane programming. When the write quiescent time is not greater than the active interval threshold, it means that the target write stream still has write commands arriving within the time corresponding to the active interval threshold, that is, it is in a write active state; when the host system 10 continuously issues write commands through the target write stream at intervals not greater than the active interval threshold, and the amount of write data issued during this period exceeds the amount of data that memory module 220 can complete programming in the same period, the speed at which it issues write data is faster than the speed at which memory module 220 completes page programming, so the write data corresponding to the target write stream continues to accumulate in the buffer memory 214, and is not programmed every time a write command is received. For example, the first rate threshold is, for instance, 20 MB / s; the predetermined ratio upon which the second rate threshold is based is, for instance, 80%; the second rate threshold is, for instance, 150 MB / s; the active interval threshold is, for instance, 1 to 2 milliseconds; the silent timeout threshold is, for instance, 5 to 10 milliseconds (in this embodiment, it is, for instance, set to 5 milliseconds); the first data volume threshold is, for instance, 16 KB; and the second data volume threshold is, for instance, 96 KB. Each of these thresholds is carried by a programmable register, allowing it to be configured during initialization according to the specifications and interface speed of the associated memory module 220, and not limited to the values ​​described above.

[0119] Figure 5 This is a schematic diagram illustrating the mapping between operating characteristics, capacity levels, and programming modes according to embodiments of this disclosure. Please refer to... Figure 1A , Figure 2 , Figure 3 , Figure 4 and Figure 5 , Figure 5 The processor 211 is shown in the aforementioned correspondence. Figure 2 In step S220, the correspondence between the target buffer capacity and the target programming mode is determined based on multiple operating characteristics and the availability status of the shared elastic resource pool 320.

[0120] like Figure 5 As shown on the left, the operational characteristics FC include average write command data volume FC1, write throughput FC2, and write silent duration FC3. The definitions and determination methods of these three have been described above. Figure 3The embodiments are illustrated below. The availability state FC4 of the shared elastic resource pool 320, along with the average write command data volume FC1, write throughput FC2, and write quiescent duration FC3, serve as the determination inputs. This availability state FC4 is not a characteristic of the target write stream's operation, but rather characterizes the current available buffer capacity of the shared elastic resource pool 320.

[0121] like Figure 5 As shown on the right, capacity levels 340 include a first buffer capacity 341, a second buffer capacity 342, and a third buffer capacity 343, which increase sequentially. Programming modes 350 include single-level unit single-plane programming 351, single-level unit multi-plane programming 352, and three-level unit full-plane programming 353. The target buffer capacity is selected from capacity levels 340, and each capacity level corresponds to one of the programming modes in programming mode 350. Therefore, when the processor 211 hits a set of conditions, it simultaneously determines the target buffer capacity and the target programming mode that belong to the same correspondence, rather than determining them independently.

[0122] Condition set CD1 is as follows Figure 5 As shown in the first line. When the average write command data volume FC1 is not greater than the first data volume threshold, the write throughput FC2 is lower than the first rate threshold, and the write silence duration FC3 is less than the silence timeout threshold, as shown by arrow A51, the processor 211 determines the target buffer capacity as the first buffer capacity 341, and as shown by arrow A54, determines the target programming mode corresponding to the first buffer capacity 341 as single-level unit single-plane programming 351. When the current buffer capacity 330 of the target write stream is the basic guaranteed capacity 331, the processor 211 maintains the basic guaranteed capacity 331 and does not obtain the buffer resource amount 332 from the shared elastic resource pool 320, so that the unused buffer resources in the shared elastic resource pool 320 can be obtained by other write streams. When the current buffer capacity 330 of the target write stream is greater than the first buffer capacity 341, the processor 211 can proceed according to the aforementioned corresponding... Figure 4 The embodiment adjusts the amount of buffer resources by 332. The specific timing and method of returning the buffer resources will be explained in the embodiments below.

[0123] Condition set CD2 is as follows Figure 5As shown in the second line, when the average write command data volume FC1 is greater than the first data volume threshold but not greater than the second data volume threshold, the write throughput FC2 is not lower than the first rate threshold but not higher than the second rate threshold, and the write silence duration FC3 is not greater than the active interval threshold, as shown by arrow A52, the processor 211 determines the target buffer capacity as the second buffer capacity 342, and as shown by arrow A55, determines the target programming mode corresponding to the second buffer capacity 342 as single-level multi-plane programming 352. For example, when the host system 10 sends image data of the application via the target write stream, the total amount of the image data is, for example, tens of megabytes, the average write command data volume FC1 is, for example, 64KB, the write throughput FC2 is, for example, 80MB per second, and the write silence duration FC3 is, for example, 0.5 milliseconds and less than, for example, the active interval threshold of 1 millisecond, the processor 211 determines the target buffer capacity as, for example, the second buffer capacity 342 of 96KB, and determines the target programming mode as single-level multi-plane programming 352. When the current buffer capacity 330 of the target write stream is a base guaranteed capacity 331 of 16KB, and the available capacity of the shared elastic resource pool 320 is sufficient to cover the difference between the second buffer capacity 342 and the current buffer capacity 330, the processor 211 allocates 80KB of buffer resources 332 from the shared elastic resource pool 320 to the target write stream, increasing the current buffer capacity 330 to the second buffer capacity 342. Thus, write data temporarily stored in the buffer memory 214 can be programmed in parallel to multiple planes in a single programming operation, reducing the number of programming operations required for single-plane programming under moderate load.

[0124] Condition set CD3, such as Figure 5 As shown in the third line, when the average write command data volume FC1 is greater than the second data volume threshold, the write throughput FC2 is higher than the second rate threshold, and the availability status FC4 indicates that the shared elastic resource pool 320 has available capacity to meet the expansion requirements of the target write stream, as shown by arrow A53, the processor 211 determines the target buffer capacity as the third buffer capacity 343, and as shown by arrow A56, determines the target programming mode corresponding to the third buffer capacity 343 as three-level unit full-plane programming 353. When the current buffer capacity 330 of the target write stream is less than the third buffer capacity 343, the processor 211 can allocate the difference in capacity between the two from the shared elastic resource pool 320 to the target write stream. The write data temporarily stored in the target write stream can be programmed using three-level unit full-plane programming 353, so that the amount of data processed in one programming operation is greater than the amount of data processed in one programming operation by single-level unit single-plane programming 351 and single-level unit multi-plane programming 352.

[0125] It should be noted that the conditions listed in each of the condition sets CD1 to CD3 are the conditions required for the corresponding condition set to be true. Figure 5If no square is displayed for a certain decision dimension, it means that the corresponding condition set does not require the value of that decision dimension to be true. When the processor 211 hits one of the condition sets CD1 to CD3, it selects the corresponding capacity level and the programming mode that has been pre-established to correspond to that capacity level.

[0126] Each capacity level corresponds to the amount of data required for the memory module 220 to perform a programming operation in the corresponding programming mode. For example, taking a memory module 220 with six planes and a single physical page of one plane having a data size of 16KB, the single-level cell single-plane programming 351 requires the data size of one physical page of one plane when performing a programming operation, so the first buffer capacity 341 is, for example, 16KB. In single-level cell multi-plane programming 352, when performing a programming operation, the programming is completed by passing through all six planes within the scope of a chip enable (CE) signal at once. The required data size is, for example, the product of the number of the six planes and the data size of the physical page, which is 96KB, so the second buffer capacity 342 is, for example, 96KB. When performing a single programming operation, the three-layer cell full-plane programming 353 completes the programming by passing through all six planes within the range of the chip's enable signal at once. The required data volume is, for example, the product of the number of the six planes, the data volume of the physical page, and the number of bits in the three-layer cell, which is 288KB. Therefore, the third buffer capacity 343 is, for example, 288KB. The above-mentioned number of planes, data volume of physical pages, and cell programming mode are merely examples, and this disclosure is not limited thereto.

[0127] Since each capacity level matches the amount of data required for a programming operation in the corresponding programming mode, the write data temporarily stored in the buffer memory 214 can be used to perform the corresponding programming operation when the accumulated data reaches the corresponding amount. In one embodiment, when the target programming mode of the target write stream is three-level cell full-plane programming 353, after the write data corresponding to the target write stream is accumulated in the buffer memory 214 to the amount of data required for a programming operation in three-level cell full-plane programming 353, it is directly programmed from the buffer memory 214 to the memory module 220 using three-level cell full-plane programming 353, without going through the intermediate process of first writing to the memory module 220 using single-level cell programming.

[0128] The capacity level 340 is configured based on at least one of the following: physical page size, number of planes, cell programming mode, and programming parallelism of the memory module 220. The first data volume threshold, the second data volume threshold, the first rate threshold, the second rate threshold, the active interval threshold, and the silent timeout threshold are carried by the programmable registers of the memory controller 210 and are configured during the initialization of the memory device 20 according to the specifications of the memory module 220 and the interface speed between the storage device 20 and the host system 10.

[0129] The first rate threshold is set according to the upper limit of the write rate of single-level unit single-plane programming 351, the second rate threshold is set according to a predetermined proportion of the maximum bandwidth supported by single-level unit multi-plane programming 352, and the active interval threshold is set according to the page programming time of memory module 220. In one embodiment, the first rate threshold is set to be slightly higher than the upper limit of the write rate of single-level unit single-plane programming 351. When the write quiescent duration FC3 is not greater than the active interval threshold, it means that within the time period from the current evaluation point not exceeding the active interval threshold, there are still write commands corresponding to the target write stream arriving. When the write throughput FC2 indicates that the host system 10 issues write data at a rate higher than the memory module 220 can complete programming within the corresponding period, the write data corresponding to the target write stream continues to accumulate in the buffer memory 214, and no programming operation is performed upon receiving a single write command. For example, the first rate threshold is, for instance, 20 MB / s; the predetermined ratio upon which the second rate threshold is based is, for instance, 80%; the second rate threshold is, for instance, 150 MB / s; the active interval threshold is, for instance, 1 to 2 milliseconds; the silent timeout threshold is, for instance, 5 to 10 milliseconds, and in this embodiment, it is, for instance, set to 5 milliseconds; the first data volume threshold is, for instance, 16 KB; and the second data volume threshold is, for instance, 96 KB. Each of the above thresholds can be configured separately according to the specifications and interface speed of the associated memory module 220, and this disclosure is not limited to the above values.

[0130] In one embodiment, when the value obtained by the processor 211 based on multiple operating features and the available state FC4 does not match any of the condition sets CD1 to CD3, and the target write stream does not trigger the closing process executed according to the write silence duration and the protection process executed according to the local buffer occupancy state, the processor 211 maintains the current buffer capacity and the currently used programming mode of the target write stream in the current evaluation cycle, and re-performs the determination based on the multiple operating features and the available state of the shared elastic resource pool 320 obtained at that time in the next evaluation cycle. This avoids performing buffer resource adjustments without corresponding basis when multiple operating features fall within the determination gap between the condition sets CD1 to CD3.

[0131] In one embodiment, the average write command data volume FC1 and the write throughput FC2 can be used as independent decision dimensions. When the average write command data volume FC1 is small and the write throughput FC2 is high, although the amount of data carried in a single write command of the target write stream is small, it can still accumulate to the amount of data required for a programming operation corresponding to a higher capacity level in a short time. Therefore, the processor 211 can mainly determine the higher candidate capacity level and the corresponding higher programming parallelism programming mode based on the write throughput FC2, and verify whether the candidate capacity level meets the predetermined minimum acceptance unit based on the average write command data volume FC1. When the average write command data volume FC1 is large and the write throughput FC2 is low, in one embodiment, using a physical page as the minimum unit of acceptance, the processor 211 can be configured with a lower capacity level corresponding to the lower programming parallelism, and the unprogrammed data is programmed to the memory module 220 by a closing process executed according to the write quiescent duration; in another embodiment, using a complete host write command as the minimum unit of acceptance, the processor 211 can ensure that the target buffer capacity is not lower than the average write command data volume FC1, and select a programming mode with a lower programming parallelism according to the write throughput FC2, and the unprogrammed data is also processed by the same closing process. The above embodiments are applicable in parallel with the determination methods shown in condition sets CD1 to CD3, and do not replace the determination methods shown in condition sets CD1 to CD3.

[0132] In one embodiment, the number of capacity levels included in capacity level 340 is not limited to the first buffer capacity 341, the second buffer capacity 342, and the third buffer capacity 343, and the combination of programming modes included in programming mode 350 is not limited to single-level cell single-plane programming 351, single-level cell multi-plane programming 352, and three-level cell full-plane programming 353. The capacity corresponding to each capacity level and its corresponding programming mode can be configured according to at least one of the following: the number of planes of memory module 220, physical page size, number of bits stored in each memory cell, the range of a chip enable signal, and programming parallelism. When the number of planes, physical page size, cell programming mode, or programming parallelism of memory module 220 changes, the capacity corresponding to each capacity level and the number of capacity levels can change accordingly. This disclosure does not imply... Figure 5 The three sets of correspondences shown are limited.

[0133] In one embodiment, when multiple operational characteristics of the target write stream fluctuate around the thresholds listed in condition sets CD1 to CD3, the target buffer capacity determined by the periodic evaluation may repeatedly change between adjacent capacity levels. In an embodiment where the periodic evaluation is used to perform both expansion and contraction, the processor 211 still determines the target buffer capacity and target programming mode according to condition sets CD1 to CD3. The following embodiments are used to determine the timing of buffer resource return when the target buffer capacity is less than the current buffer capacity 330, without changing the conditions listed in condition sets CD1 to CD3, and without preventing the increase allocation based on the determined target buffer capacity. In a first embodiment, for at least one threshold on which the increase from a lower capacity level to a higher capacity level is based, a fallback threshold is set for the fallback from the higher capacity level to the lower capacity level, and the fallback threshold is lower than the corresponding increase threshold, so as to form a range between the two where buffer resource return is not performed. In a second embodiment, the processor 211 does not perform buffer resource return again for a cooling period after performing a buffer resource return. In a third embodiment, processor 211 performs buffer resource return only when the target buffer capacity determined in multiple consecutive evaluation cycles is less than the current buffer capacity 330. This disclosure does not limit the adoption of any of the above embodiments.

[0134] In one embodiment, the average write command data volume FC1 and write throughput FC2 are determined based on the cumulative values ​​within a statistical time window, thus reducing the impact of instantaneous fluctuations within the statistical time window on the determination result. However, when the values ​​determined in adjacent evaluation cycles are located on both sides of the same threshold, the target buffer capacity may still fluctuate repeatedly between adjacent capacity levels. Increasing the duration of the statistical time window can reduce the sensitivity of the evaluation result to short-term fluctuations, but it may also delay the time when the processor 211 identifies the burst write state. Therefore, the suppression of repeated buffer resource return can be achieved by at least one of the following methods: fallback threshold, cooling time, or confirmation in multiple consecutive evaluation cycles, rather than simply by increasing the duration of the statistical time window.

[0135] Based on the above Figure 5 The mapping relationship between the operating characteristics, capacity levels, and programming modes shown is illustrated. The processor 211 uses the average write command data volume FC1, write throughput FC2, and write quiescent time FC3 to characterize the write behavior of the target write stream, and further considers the availability status FC4 of the shared elastic resource pool 320 when determining the third buffer capacity 343. Based on this, the processor 211 determines the target buffer capacity from multiple capacity levels and simultaneously determines the target programming mode corresponding to the target buffer capacity, so that the buffer capacity allocated to the target write stream matches the amount of data required to perform one programming operation in the corresponding programming mode.

[0136] Figure 6This is a flowchart illustrating the silent timeout termination and capacity restoration process according to embodiments of this disclosure. Please refer to... Figure 1A , Figure 4 and Figure 6 , Figure 6 The process shown is continuously executed by storage device 20 during operation, without relying on... Figure 2 The evaluation period is shown. The hardware circuit updates the timestamp of the most recent write command of the target write stream with each write command, and obtains the write silence duration based on the time difference between the current time and the most recent write command timestamp. When the write silence duration exceeds the silence timeout threshold, the processor 211 can execute... Figure 6 The shown closing process is performed without waiting for the next evaluation cycle. The write silence duration is related to... Figure 3 The write silence duration determined in step S370 is the same physical quantity, but the timing of obtaining the two is different.

[0137] In step S620, the memory controller 210 determines whether the write silence duration of the target write stream exceeds the silence timeout threshold, and whether the target write stream still has data to be programmed in the buffer memory 214. When both conditions are met, the process proceeds to step S630; when either condition is not met, the process ends.

[0138] In step S630, processor 211 determines the finalization programming mode based on the amount of unprogrammed data. When the target write stream enters a silent state, the data remaining in buffer memory 214 may be insufficient to perform a programming operation in the original target programming mode. Therefore, processor 211 selects a different finalization programming mode based on the current amount of remaining data, allowing the remaining data to be programmed without waiting for subsequent write data. The finalization programming mode is only used for this finalization process and temporarily overrides... Figure 5 The determined target programming pattern. For example, the closing programming pattern can be selected from single-layer unit single-plane programming and single-layer unit multi-plane programming.

[0139] In step S640, the processor 211, in accordance with the final programming mode, controls the memory interface control circuit 213 to program the unprogrammed data from the buffer memory 214 to the memory module 220.

[0140] In step S650, after the unprogrammed data is programmed, the processor 211 returns at least a portion of the buffer resources 332 allocated from the shared elastic resource pool 320 to the target write stream to the shared elastic resource pool 320. After the return, the target write stream still retains the basic guaranteed capacity 331.

[0141] For example, the current buffer capacity 330 of the target write stream is 96KB, including a base guarantee capacity of 16KB 331 and a buffer resource of 80KB 332. After the host system 10 stops issuing write commands via the target write stream, the write silence duration increases to 8 milliseconds, exceeding the silence timeout threshold of, for example, 5 milliseconds, and the buffer memory 214 still contains 32KB of unprogrammed data. The processor 211 determines the final programming mode based on the 32KB of data, completes the programming of the 32KB of data, and returns the 80KB buffer resource of 332 to the shared elastic resource pool 320, restoring the current buffer capacity 330 of the target write stream to the base guarantee capacity of 16KB 331. When a new write command arrives subsequently, the processor 211 will then... Figure 2 The evaluation cycle shown redetermines the target buffer capacity and target programming mode.

[0142] Figure 6 The start and end points shown indicate the boundaries of this process. The storage device 20 can repeat the above judgment for each of the multiple write streams during operation. Figure 6 The process shown is used to perform cleanup programming and capacity return after the write stream enters a silent state; Figure 2 The cycle assessment shown is used to determine the capacity level and programming mode, which belong to different processing paths.

[0143] When the periodic assessment determines, based on the statistical results of previous statistical time windows, that the buffer resources for the target write stream should be increased, Figure 6 The process shown simultaneously detects that the target write stream has entered a silent state. Figure 6 The triggered cleanup process can take precedence over the capacity adjustment determined by the periodic assessment. In other words, when the target write stream has stopped writing, the storage device 20 can process the remaining data and return the buffer resources first, instead of expanding the target write stream according to the lagging statistics.

[0144] In one embodiment, when Figure 6When the cleanup process and the capacity adjustment determined by the periodic evaluation are both met simultaneously, the processor 211 may process them in one of the following ways. In a first embodiment, the processor 211 invalidates the capacity adjustment determined for the target write stream in the current evaluation cycle but not yet executed, and re-determines it in a subsequent evaluation cycle. In a second embodiment, the processor 211 first executes the capacity adjustment determined in the current evaluation cycle, and then executes cleanup programming and capacity restoration, so that the cleanup process overrides the result of the capacity adjustment. In a third embodiment, the processor 211 treats the cleanup process and capacity adjustment as different events, and prioritizes the cleanup event; the availability state of the shared elastic resource pool 320 can be maintained through indivisible read and update operations, or the processing of one event can be postponed while processing the other. This disclosure does not limit the adoption of any of the above embodiments.

[0145] In one embodiment, processor 211 can compare the amount of unprogrammed data with the amount of data required to perform one programming operation for each of multiple candidate final programming modes to determine the final programming mode. When the amount of unprogrammed data is not greater than the amount of data required to perform one programming operation for single-level cell single-plane programming, processor 211 can use single-level cell single-plane programming. When the amount of unprogrammed data is large, processor 211 can use single-level cell multi-plane programming, or complete the programming in batches through multiple programming operations. If memory module 220 supports selecting a portion of planes to perform multi-plane programming within the scope of a chip enable signal, processor 211 can also determine the number of planes participating in programming based on the amount of unprogrammed data. For example, when a physical page of a plane is 16KB and the amount of residual data is 32KB, processor 211 can select two planes to perform single-level cell multi-plane programming. If memory module 220 does not support selecting a portion of planes to perform multi-plane programming, processor 211 determines the final programming mode separately based on the programming modes actually supported by memory module 220.

[0146] based on Figure 6 The silent timeout termination and capacity return process shown involves the processor 211 determining the termination programming mode based on the amount of remaining data and completing the data programming when the silent duration of the target write stream exceeds the silent timeout threshold and the buffer memory 214 still contains unprogrammed data. Then, at least a portion of the buffer resource amount 332 obtained by the target write stream from the shared elastic resource pool 320 is returned to the shared elastic resource pool 320. Thus, the write stream that has stopped writing no longer continuously occupies buffer resources exceeding the basic guaranteed capacity 331.

[0147] Figure 7 This is a congestion protection flowchart illustrating an embodiment of this disclosure. Please refer to... Figure 1A , Figure 2 , Figure 4 and Figure 7 , Figure 7 The process shown is continuously executed by storage device 20 during operation, without relying on... Figure 2 The evaluation cycle is shown. When the memory controller 210 detects that the local buffer occupancy status of a certain write stream has reached the warning threshold, the processor 211 takes that write stream as the target write stream and executes... Figure 7 The determination and protection processes are shown.

[0148] In step S720, the memory controller 210 obtains the local buffer occupancy status of the target write stream. The local buffer occupancy status is the proportion of the data to be programmed within the current buffer capacity 330 of the target write stream, which can be expressed as... Where W represents the local buffer occupancy status, and D represents the amount of data to be programmed. The current buffer capacity is 330. The current buffer capacity 330 includes a base guaranteed capacity 331 and buffer resources 332 obtained from the shared elastic resource pool 320. For example, when the current buffer capacity 330 is 96KB, and 80KB of it is unprogrammed data, the local buffer occupancy is approximately 83.3%. The local buffer occupancy can be obtained directly from the hardware or calculated based on the free capacity reported by the hardware.

[0149] In step S730, processor 211 determines whether the local buffer occupancy status has reached the warning threshold and whether the available capacity of the shared elastic resource pool 320 is insufficient to meet the expansion requirements of the target write stream. When both conditions are met, processor 211 proceeds to step S740; when either condition is not met, the current protection process ends. The warning threshold can be carried by a programmable register of memory controller 210 and configured during the initialization of storage device 20, for example, as 80% of the current buffer capacity 330.

[0150] For example, when the target write stream has only a basic guaranteed capacity of 16KB 331 and the amount of unprogrammed data reaches 14KB, its local buffer occupancy is 87.5%. If the processor 211 has determined that the target write stream needs to be expanded to 96KB, then the target write stream still needs 80KB of buffer resources 332. In an embodiment where the capacity of the shared elastic resource pool 320 is 1024KB, if the other three write streams each obtain 272KB and the other two write streams each obtain 80KB, then the total allocated capacity is 976KB, and the remaining available capacity is 48KB, which is less than the 80KB required for the target write stream to expand. In this case, the local buffer occupancy reaches the warning threshold, and the available capacity of the shared elastic resource pool 320 is insufficient to meet the expansion requirements, so step S740 is entered. The available capacity of the shared elastic resource pool 320 being zero is only one case of insufficient available capacity, and this disclosure is not limited to this.

[0151] When the shared elastic resource pool 320 still has sufficient available capacity to meet expansion needs, the processor 211 can proceed according to... Figure 2 Step S230 increases the amount of buffer resources allocated to the target write stream by 332, without proceeding to step S740. On the other hand, when the available capacity of the shared elastic resource pool 320 is insufficient, but the local buffer occupancy status of the target write stream has not yet reached the warning threshold, the memory controller 210 continues to monitor the local buffer occupancy status, and similarly does not proceed to step S740. Therefore, subsequent protection processing is only performed when the target write stream cannot obtain enough additional buffer resources, and its current buffer capacity 330 is close to being filled by unprogrammed data.

[0152] In step S740, processor 211 restricts data transmission of the host system 10 corresponding to the target write stream. In an embodiment where the connection interface circuit 230 employs a general-purpose flash memory interface, processor 211 may control data management circuit 212 to delay sending a transmission ready frame to the host system 10, causing the host system 10 to postpone the transmission of write data for which a transmission ready frame has not yet been obtained. For write data that has already obtained a transmission ready frame or is being transmitted, storage device 20 may still continue to receive. In another embodiment, processor 211 may also postpone receiving or processing subsequent write commands of the target write stream; this disclosure does not limit the specific manner of data transmission restriction.

[0153] In step S750, the processor 211 controls the memory interface control circuit 213 to program the unprogrammed data in the target write stream to the memory module 220 using single-level cell single-plane programming. Under normal operating conditions, the processor 211 can wait for the written data in the buffer memory 214 to accumulate to the amount of data required for one programming operation in the target programming mode before performing programming. In this protection process, the processor 211 does not wait for the data amount to reach the amount required for the target programming mode, but instead uses single-level cell single-plane programming, which requires a smaller amount of data per programming operation. If the amount of unprogrammed data is greater than the amount of data that can be processed by a single single-level cell single-plane programming operation, the processor 211 can complete the data programming through multiple programming operations. The single-level cell single-plane programming used in this protection process is only used for the current protection process and temporarily overrides the original target programming mode of the target write stream.

[0154] In step S760, processor 211 determines whether the local buffer occupancy status has fallen below the warning threshold. If the local buffer occupancy status is still not below the warning threshold, processor 211 returns to step S750 and continues programming; if the local buffer occupancy status falls below the warning threshold, processor 211 proceeds to step S770. Since step S740 has restricted the host system 10 from continuing to transmit data, and step S750 continuously releases the buffer space occupied by the programmed data, the local buffer occupancy status can decrease as the protection process is executed.

[0155] In step S770, processor 211 removes the data transmission restriction on host system 10 and resumes sending the transmission ready frame corresponding to the target write stream to host system 10. When processor 211 suspends receiving or processing subsequent write commands in step S740, processor 211 also resumes receiving and processing the corresponding write commands. For example, when the current buffer capacity 330 of the target write stream is 16KB and the amount of unprogrammed data is 14KB, after processor 211 programs the 14KB of data to memory module 220, the local buffer occupancy state can drop below the 80% warning threshold, and processor 211 can then remove the data transmission restriction.

[0156] Figure 7 The protection process shown can be repeatedly executed for each write stream during the operation of storage device 20. This protection process limits further data entry into buffer memory 214 and releases the buffer space currently occupied by the target write stream through single-level cell single-plane programming, but does not re-determine the capacity level of the target write stream. The target buffer capacity and target programming mode remain as follows: Figure 2 The evaluation period shown and Figure 5 The mapping relationship shown is determined. When the target write stream simultaneously satisfies... Figure 6 When the write quiescent condition is shown, the processor 211 may also return at least a portion of the buffer resource amount 332 allocated from the shared elastic resource pool 320 to the target write stream to the shared elastic resource pool 320 after the unprogrammed data has been programmed.

[0157] based on Figure 7 The congestion protection process shown in the diagram involves the storage device 20 limiting the data transmission of the host system 10 and programming the unprocessed data to create available space in the current buffer capacity 330 of the target write stream, thereby reducing the risk of buffer memory 214 overflowing. When the local buffer occupancy status of the target write stream reaches the warning threshold and the available capacity of the shared elastic resource pool 320 is insufficient to meet the expansion requirements, the storage device 20 reduces the data transmission of the host system 10 and programs the unprocessed data to make available space in the current buffer capacity 330 of the target write stream.

[0158] Figure 8 This is a timing diagram illustrating the interaction of command reception, statistics, resource adjustment, and programming according to embodiments of this disclosure. Please refer to... Figure 1A , Figure 2 , Figure 3 , Figure 5 and Figure 8 , Figure 8 The interaction between the host system 10, data management circuit 212, processor 211, buffer memory 214 and memory module 220 illustrates an execution timing of the memory management method of this disclosure. Figure 8 It includes the command receiving and statistics phase S81, the periodic assessment and resource adjustment phase S82, and the data programming phase S83.

[0159] In stage S81, as shown in step S811, the host system 10 issues a write command and write data corresponding to the target write stream. Figure 8 For simplicity, the connection interface circuit 230 is omitted. Write commands and write data can be transmitted to the data management circuit 212 via the connection interface circuit 230. As shown in step S812, the hardware circuit in the data management circuit 212 identifies the write stream corresponding to the write command and updates the statistical context of the target write stream, and this update does not go through the processor 211. The statistical context includes the cumulative amount of written data, the write command count, and the timestamp of the most recent write command. As shown in step S813, the data management circuit 212 temporarily stores the write data of the target write stream in the buffer memory 214.

[0160] In stage S82, as shown in step S821, processor 211 reads the statistical context of the target write stream according to a predetermined evaluation cycle. As shown in step S822, data management circuit 212 provides processor 211 with the cumulative amount of written data, write command count, and the timestamp of the most recent write command. As shown in step S823, processor 211 determines multiple operating characteristics of the target write stream based on the statistical context, and determines the target buffer capacity and the target programming mode corresponding to the target buffer capacity based on the multiple operating characteristics and the availability status of the shared elastic resource pool 320. As shown in step S824, processor 211 adjusts the amount of buffer resources allocated from the shared elastic resource pool 320 to the target write stream according to the target buffer capacity.

[0161] In stage S83, as shown in step S831, processor 211 issues the target programming mode; as shown in step S832, buffer memory 214 provides write data for the target write stream. Figure 8 For simplicity, the memory interface control circuit 213 is omitted. In actual execution, the processor 211 controls the memory interface control circuit 213 to program the write data from the buffer memory 214 to the memory module 220 according to the target programming mode. As shown in step S833, the memory module 220 performs programming according to the target programming mode; as shown in step S834, the memory module 220 returns a programming completion status to the processor 211 after programming is complete.

[0162] Stages S81, S82, and S83 each have different triggering methods. Stage S81 is executed upon receiving a write command and written data from the host system 10; stage S82 is executed according to the predetermined evaluation cycle of the processor 211; and stage S83 can be executed when the amount of written data temporarily stored in the buffer memory 214 reaches the amount of data required to perform one programming operation in the target programming mode. Therefore, within one evaluation cycle, stages S81 and S83 can be executed zero times, one time, or multiple times. Figure 8 The vertical arrangement in the text only represents a representative processing order, and does not mean that the three stages must each be executed once in sequence.

[0163] When the amount of write data temporarily stored in buffer memory 214 reaches the amount of data required for multiple programming operations, processor 211 can execute multiple programming operations; the remaining data that is insufficient to constitute the amount of data required for a complete programming operation can continue to be temporarily stored in buffer memory 214. At the end of the statistical time window, the cumulative amount of write data and the write command count can be reset, while the timestamp of the most recent write command is retained for subsequent evaluation cycles to determine the write silence duration of the target write stream.

[0164] Figure 8 This demonstrates the normal periodic evaluation and data programming timing. The closing programming and buffer resource return performed when the target write stream enters a write quiescent state, and the congestion protection performed when the local buffer occupancy reaches the warning threshold and the available capacity of the shared elastic resource pool 320 is insufficient, are independent of the evaluation cycle of stage S82, and are respectively performed according to... Figure 6 and Figure 7 The process shown is executed.

[0165] based on Figure 8 The interactive timing shown allows the hardware circuitry to update the statistical context of each write stream with each write command. The processor 211 then reads the statistical context according to a predetermined evaluation cycle, determines the target buffer capacity and the corresponding target programming mode, and adjusts the amount of buffer resources acquired by the target write stream. Write command statistics, resource adjustment, and data programming can be executed according to their respective triggering conditions, thus eliminating the need for the processor 211 to perform a complete capacity and programming mode determination for each write command.

[0166] It should be noted that in the above embodiments, the various values, thresholds, parameter ranges, and condition settings mentioned are all exemplary and do not constitute a limitation on the scope of protection of the claims of this disclosure. Specifically, the number of capacity levels and the capacity corresponding to each capacity level (e.g., 16KB, 96KB, and 288KB), the combination of programming modes corresponding to each capacity level (e.g., single-level cell single-plane programming, single-level cell multi-plane programming, and three-level cell full-plane programming), the number of planes of the memory module (e.g., six) and the amount of data corresponding to one physical page of a single plane (e.g., 16KB), the number of bits stored in each memory cell, the first data volume threshold (e.g., 16KB) and the second data volume threshold (e.g., 96KB), the first rate threshold (e.g., 20MB / s) and the second rate threshold (e.g., 150MB / s) and the predetermined ratio (e.g., 80%) on which they are based, and the active interval threshold (e.g., 1 millisecond) The following parameters can be adjusted according to the application scenario requirements of the host system, the specifications of the memory module, the interface speed between the storage device and the host system, and the operating status of the memory module. These parameters include: the duration of the evaluation period and the duration of the statistical time window (e.g., both 100 milliseconds); the duration of the cooldown time after execution and the number of consecutive evaluation periods on which the execution is based; the basic guaranteed capacity (e.g., 16KB) and the total capacity of the shared elastic resource pool (e.g., 1MB); the number of concurrent write streams (e.g., seven); the warning threshold corresponding to the local buffer occupancy status (e.g., 80% of the current buffer capacity of the write stream); and the candidate range of the tail programming mode.

[0167] In another embodiment, this disclosure also provides a computer program product, which includes a computer program or a non-transitory computer-readable storage medium storing the computer program. The computer program is adapted to be loaded and executed by a memory controller of a storage device. The storage device includes a buffer memory and a memory module. The storage device is used to receive write commands from multiple write streams issued by a host system. The buffer memory includes a shared elastic resource pool shared by the multiple write streams. When the computer program is loaded and executed by the memory controller, the memory controller monitors the write behavior of a target write stream among the multiple write streams to determine multiple operating characteristics of the target write stream. Based on the multiple operating characteristics and the availability status of the shared elastic resource pool, a target buffer capacity for the target write stream and a target programming mode corresponding to the target buffer capacity are determined. Based on the target buffer capacity, the amount of buffer resources allocated from the shared elastic resource pool to the target write stream is adjusted. Based on the target buffer capacity, the write data corresponding to the target write stream is programmed from the buffer memory to the memory module according to the target programming mode. The non-transitory computer-readable storage medium includes, for example, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk. Therefore, the technical solution disclosed herein can be implemented in the form of a computer program product.

[0168] Based on the above, the memory management method, memory controller, storage device, and program product provided in this disclosure, by having the memory controller update the statistics of write behavior in hardware with each write command and the processor read them according to a predetermined evaluation cycle, eliminates the need for the acquisition of operational characteristics to occupy the processor's computing resources when each write command arrives; by making the capacity corresponding to each capacity level correspond to the amount of data required to perform one programming operation in the programming mode corresponding to that capacity level, the temporarily stored write data can be programmed when it accumulates to the amount of data required for one programming operation, which helps to reduce the number of operations of the memory module, thereby achieving... This helps reduce write amplification and power consumption, and helps extend the lifespan of memory modules. By determining the final programming mode based on the amount of data remaining in the buffer memory when the write quiz time exceeds the quiz timeout threshold, and after programming is completed, at least a portion of the buffer resources obtained by the write stream from the shared elastic resource pool is returned, so that the capacity can be borrowed by other write streams in a timely manner. By configuring a basic guaranteed capacity for each write stream that is not occupied by the needs of other write streams, each write stream still has the capacity to receive a single-page write command when the available capacity of the shared elastic resource pool is exhausted.

[0169] Furthermore, by restricting data transmission from the host system corresponding to the write stream when the local buffer occupancy of a certain write stream reaches a warning threshold and the available capacity of the shared elastic resource pool is insufficient to meet the expansion needs of that write stream, and by programming the unprogrammed data to the memory module, buffer overflow is avoided. Moreover, by providing the above mechanism simultaneously as a method, a memory controller, a storage device, and a computer program product, this technical solution can be implemented in different forms. Thus, this disclosure achieves a relative balance between buffer memory capacity utilization, the available buffer capacity for each write stream, and the number of programming operations performed by the memory module.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method applicable to a storage device including a memory controller, a buffer memory, and a memory module, wherein the storage device receives write commands from multiple write streams issued by a host system via the memory controller, and the buffer memory includes a shared elastic resource pool shared by the multiple write streams, characterized in that, The method includes: Monitor the write behavior of the target write stream among the multiple write streams to determine multiple operational characteristics of the target write stream; Based on the aforementioned multiple operational characteristics and the availability status of the shared elastic resource pool, the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity are determined. Adjust the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; and According to the target programming mode, the write data corresponding to the target write stream is programmed from the buffer memory to the memory module.

2. The memory management method according to claim 1, characterized in that, The multiple operational characteristics include average write command data volume, write throughput, and write silent duration; The average write command data volume represents the write granularity of the target write stream, the write throughput represents the total write volume of the target write stream, and the write silence duration represents the write activity of the target write stream.

3. The memory management method according to claim 2, characterized in that, The memory controller maintains a corresponding statistical context for each of the multiple write streams. The statistical context includes the cumulative amount of data written, the write command count, and the timestamp of the most recent write command. The step of monitoring the write behavior of a target write stream among the multiple write streams to determine multiple operational characteristics of the target write stream includes: Upon receiving a write command corresponding to the target write stream, the statistical context corresponding to the target write stream is updated by hardware circuitry, and this update is not transmitted via the processor of the memory controller; and The processor reads the statistical context corresponding to the target write stream at predetermined evaluation cycles to determine the plurality of operational characteristics of the target write stream.

4. The memory management method according to claim 3, characterized in that, The step of having the processor read the statistical context corresponding to the target write stream at predetermined evaluation cycles to determine the plurality of operational characteristics of the target write stream includes: When the write command count is greater than zero, the average write command data volume is determined based on the ratio of the cumulative written data volume to the write command count; The write throughput is determined based on the ratio of the cumulative written data volume to the statistical time window. The write silence duration is determined based on the time difference between the current time and the timestamp of the most recent write command; and At the end of the statistical time window, the cumulative written data volume and the write command count are reset, and the timestamp of the most recent write command is retained.

5. The memory management method according to claim 2, characterized in that, The method further includes: When the write silence duration exceeds the silence timeout threshold and the target write stream still has data to be programmed in the buffer memory, the final programming mode is determined according to the amount of data to be programmed, wherein the data to be programmed is data that has been received to the buffer memory but has not yet been programmed into the memory module; According to the described final programming mode, the data to be programmed is programmed into the memory module; and After the data to be programmed is programmed, at least a portion of the buffer resources allocated from the shared elastic resource pool to the target write stream will be returned to the shared elastic resource pool.

6. The memory management method according to claim 2, characterized in that, The target buffer capacity is selected from multiple capacity levels, each corresponding to a different programming mode. These multiple capacity levels include a first buffer capacity, a second buffer capacity, and a third buffer capacity that increase sequentially. The step of determining the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity based on the multiple operational characteristics and the availability status of the shared elastic resource pool includes: When the average write command data volume is not greater than the first data volume threshold, the write throughput is lower than the first rate threshold, and the write silence duration is less than the silence timeout threshold, the target buffer capacity is determined to be the first buffer capacity and the target programming mode is single-layer unit single-plane programming. When the average write command data volume is greater than the first data volume threshold and not greater than the second data volume threshold, the write throughput is not lower than the first rate threshold and not higher than the second rate threshold, and the write silent duration is not greater than the active interval threshold, the target buffer capacity is determined to be the second buffer capacity and the target programming mode is single-level unit multi-plane programming; and When the average write command data volume is greater than the second data volume threshold, the write throughput is higher than the second rate threshold, and the availability status indicates that the shared elastic resource pool has available capacity to meet the expansion requirements of the target write stream, the target buffer capacity is determined to be the third buffer capacity and the target programming mode is three-layer unit full-plane programming.

7. The memory management method according to claim 6, characterized in that, The multiple capacity levels are configured according to at least one of the following: physical page size, number of planes, unit programming mode, and programming parallelism of the memory module; The first data volume threshold, the second data volume threshold, the first rate threshold, the second rate threshold, the active interval threshold, and the silent timeout threshold are carried by the programmable registers of the memory controller and are configured during the initialization of the memory device according to the specifications of the memory module and the interface rate between the storage device and the host system. The first rate threshold is set according to the upper limit of the write rate of single-layer cell single-plane programming, the second rate threshold is set according to a predetermined proportion of the maximum bandwidth supported by single-layer cell multi-plane programming, and the active interval threshold is set according to the page programming time of the memory module.

8. The memory management method according to claim 1, characterized in that, The target buffer capacity corresponds to the amount of data required for the memory module to perform one programming operation in the target programming mode.

9. The memory management method according to claim 1, characterized in that, The buffer memory also includes a basic guarantee capacity configured to the multiple write streams respectively, and the basic guarantee capacity is not occupied due to the needs of other write streams in the multiple write streams; The current buffer capacity of the target write stream includes: the basic guaranteed capacity configured to the target write stream, and the amount of buffer resources allocated to the target write stream from the shared elastic resource pool.

10. The memory management method according to claim 1, characterized in that, The method further includes: Obtain the local buffer occupancy status of the target write stream. The local buffer occupancy status is the proportion of the data to be programmed in the current buffer capacity of the target write stream. The data to be programmed is the data that has been received to the buffer memory but has not yet been programmed into the memory module.

11. The memory management method according to claim 10, characterized in that, The method further includes: When the local buffer occupancy status reaches a warning threshold, and the availability status indicates that the available capacity of the shared elastic resource pool is insufficient to meet the expansion requirements of the target write stream, the data transmission of the host system corresponding to the target write stream is restricted, and the data to be programmed in the buffer memory of the target write stream is programmed into the memory module; and When the local buffer occupancy status is lower than the warning threshold, the restriction on data transmission to the host system is lifted.

12. The memory management method according to claim 11, characterized in that, The restriction on data transmission of the host system corresponding to the target write stream includes: delaying the sending of a transmission ready frame to the host system; The step of writing the target data to be programmed into the memory module by writing the target data to be programmed into the memory module by writing the target data to be programmed into the memory module by single-layer cell single-plane programming.

13. A memory controller, suitable for use in a storage device, the storage device including a memory module and a connection interface circuit for communicating with a host system, the memory controller being used to process multiple write streams issued by the host system, characterized in that, The memory controller includes: A data management circuit, electrically connected to the connection interface circuit, is used to receive write commands and write data corresponding to the multiple write streams via the connection interface circuit. A memory interface control circuit is used to electrically connect to the memory module; Buffer storage, including a shared elastic resource pool shared by the multiple write streams; and A processor, electrically connected to the data management circuit, the memory interface control circuit, and the buffer memory, wherein the processor is configured to: Monitor the write behavior of the target write stream among the multiple write streams to determine multiple operational characteristics of the target write stream; Based on the aforementioned multiple operational characteristics and the availability status of the shared elastic resource pool, the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity are determined. Adjust the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; and According to the target programming mode, the memory interface control circuit is controlled to program the write data corresponding to the target write stream from the buffer memory to the memory module.

14. The memory controller according to claim 13, characterized in that, The memory controller maintains a corresponding statistical context for each of the multiple write streams. The statistical context includes the cumulative amount of written data, the write command count, and the timestamp of the most recent write command. The statistical context corresponding to the target write stream is updated by hardware circuitry upon receiving a write command corresponding to the target write stream, and the update is not transmitted via the processor; The processor is also configured to read the statistical context corresponding to the target write stream at predetermined evaluation cycles to determine the plurality of operational characteristics of the target write stream.

15. A storage device, characterized in that, include: Connects to the interface circuitry for communication with the host system; Memory module; as well as A memory controller, electrically connected to the connection interface circuit and the memory module, is used to process multiple write streams issued by the host system. The memory controller includes a buffer memory, which includes a shared elastic resource pool shared by the multiple write streams. The memory controller is configured to: Monitor the write behavior of the target write stream among the multiple write streams to determine multiple operational characteristics of the target write stream; Based on the aforementioned multiple operational characteristics and the availability status of the shared elastic resource pool, the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity are determined. Adjust the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; as well as According to the target programming mode, the write data corresponding to the target write stream is programmed from the buffer memory to the memory module.

16. A computer program product, comprising a computer program, characterized in that, The computer program is adapted to be loaded and executed by the memory controller of the storage device, the storage device including a buffer memory and a memory module, the storage device being used to receive write commands from multiple write streams issued by the host system, the buffer memory including a shared elastic resource pool shared by the multiple write streams; When the computer program is loaded and executed by the memory controller, the memory controller performs the following steps: Monitor the write behavior of the target write stream among the multiple write streams to determine multiple operational characteristics of the target write stream; Based on the aforementioned multiple operational characteristics and the availability status of the shared elastic resource pool, the target buffer capacity of the target write stream and the target programming mode corresponding to the target buffer capacity are determined. Adjust the amount of buffer resources allocated from the shared elastic resource pool to the target write stream according to the target buffer capacity; as well as According to the target programming mode, the write data corresponding to the target write stream is programmed from the buffer memory to the memory module.

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