Cache compression control

Abstract

Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus includes a cache including N data storage locations to hold cache lines and M tag storage locations to hold address tags of the cache lines. Each address tag is associated with a data field configured to support at least one of a pointer encoding to indicate one of the N data storage locations into which a corresponding cache line is allocated and a compressed data encoding to represent a predetermined value. A compression control circuit, in response to a determination that a given cache line to be allocated into the cache contains the predetermined value, sets the data field associated with a given address tag corresponding to the given cache line to the compressed data encoding to represent the predetermined value and suppresses storing the given cache line into any of the N data storage locations.

Description

Technical Field

[0001] This disclosure relates to data processing. Specifically, this disclosure relates to allocating cache lines in a cache. Background Technology

[0002] Data processing devices can provide one or more caches for temporarily storing data that has recently been loaded from memory, allowing subsequent accesses to that data to be performed with reduced latency. By storing more data in the cache, it is more likely that data will be requested for subsequent memory accesses. However, increasing the cache capacity incurs some hardware costs, such as increased circuit area and power consumption. Summary of the Invention

[0003] In one example embodiment described herein, an apparatus is provided comprising: a cache including: N data storage locations configured to store cache lines; and M tag storage locations configured to store address tags of cache lines, wherein each address tag is associated with a data field configured to support at least one of: a pointer encoding for indicating one of the N data storage locations, to which a corresponding cache line is allocated; and a compressed data encoding for representing a predetermined value; and compression control circuitry that, in response to a determination that a given cache line to be allocated to the cache contains a predetermined value, sets the data field associated with a given address tag corresponding to the given cache line to the compressed data encoding for representing the predetermined value, and suppresses the storage of the given cache line in any of the N data storage locations.

[0004] In another example embodiment described herein, a system is provided comprising: means as described above implemented in at least one packaged chip; at least one system component; and a board wherein at least one packaged chip and at least one system component are assembled on the board.

[0005] In another example embodiment described herein, a chip-in-chip product including the system described above is provided, wherein the system is assembled on an additional board with at least one other product component.

[0006] In another example implementation described herein, a method is provided comprising: storing cache lines in N data storage locations; storing address tags of the cache lines in M ​​tag storage locations, wherein each address tag is associated with a data field supporting at least one of the following: a pointer encoding for indicating that the corresponding cache line is allocated to one of the N data storage locations; and a compressed data encoding for representing a predetermined value; and in response to determining that a given cache line to be allocated to the cache contains a predetermined value, setting the data field associated with a given address tag corresponding to the given cache line to the compressed data encoding for representing the predetermined value, and suppressing the storage of the given cache line in any of the N data storage locations.

[0007] In another example embodiment described herein, a non-transitory computer-readable medium is provided for storing computer-readable code for manufacturing an apparatus comprising: N data storage locations configured to store cache lines; and M tag storage locations configured to store address tags of cache lines, wherein each address tag is associated with a data field configured to support at least one of the following: a pointer encoding for indicating one of the N data storage locations to which a corresponding cache line is allocated; and a compressed data encoding for representing a predetermined value; and compression control circuitry that, in response to a determination that a given cache line to be allocated to a cache contains a predetermined value, sets the data field associated with a given address tag corresponding to the given cache line to the compressed data encoding for representing the predetermined value, and suppresses the storage of the given cache line in any of the N data storage locations. Attached Figure Description

[0008] The invention will be further described by way of example only, with reference to embodiments illustrated in the accompanying drawings, wherein:

[0009] Figure 1 Examples of data processing apparatus including several caches are illustrated according to some example implementations;

[0010] Figure 2A An apparatus including a cache having a tag storage location and a data storage location is illustrated according to some example implementations;

[0011] Figure 2B Examples of label storage location entries are provided according to some example implementation schemes;

[0012] Figure 3Examples of pointer encoding and compressed data encoding based on some example implementation schemes are illustrated;

[0013] Figure 4 Examples of dynamically correlated tag storage locations and data storage locations are illustrated according to some example implementation schemes;

[0014] Figure 5 Examples illustrate statically associated tag storage locations and data storage locations according to some example implementation schemes;

[0015] Figure 6 The steps for reading data from a cache are illustrated according to some example implementations;

[0016] Figure 7A and Figure 7B The steps for writing compressible and incompressible data to a cache are illustrated according to some example implementations;

[0017] Figure 8 The following is an example of a sequence of steps for evicting an entry from one cache to a lower cache, according to some example implementations;

[0018] Figure 9 Systems and chip-containing products according to some example implementation schemes are illustrated;

[0019] Figure 10 The use of a computer-readable medium for manufacturing apparatus is illustrated according to some example embodiments. Detailed Implementation

[0020] Before discussing the implementation scheme with reference to the accompanying drawings, the following description of the implementation scheme is provided.

[0021] The device may be configured with a cache comprising N data storage locations configured to store cache lines and M tag storage locations configured to store address tags of the cache lines. In the following description, it should be understood that N and M are placeholder values ​​used to represent the arrangement of caches in the hardware. For example, N and M may represent the associativity of a specific cache implementation, where a 4-way set-associative cache may include a particular cache line that can be assigned to one of the four data storage locations (i.e., N=4).

[0022] The size of a cache line can vary across different implementations, and some examples may include cache lines of 64 bytes or more. To reduce the necessary capacity for storing cache lines, some methods achieve data compression by encoding the cache lines into smaller sizes. Various methods are used, which may require complex codecs, access to multiple data storage locations for a single cache line, or reorganization of cache associativity. The problem with such methods is that when accessing the cache, reading and writing data requires complex logic to encode or decode the cache line, resulting in additional latency and power consumption, thereby degrading cache performance.

[0023] According to this technique, an address tag stored in a tag storage location is associated with a data field. The data field is configured to support at least one of the following: a pointer encoding for indicating one of N data storage locations, to which a corresponding cache line is allocated; and a compressed data encoding for representing a predetermined value. In some examples, the data field may support multiple compressed data encodings, each representing a different predetermined value. The number of available compressed data encodings may depend on the size of the data field. It should be understood that by providing encodings for one or more specific predetermined values, it is not necessary to include complex logic for applying codecs to encode / decode the data more generally. Therefore, in the following description, a cache line containing a predetermined value may be described as “compressible,” while a cache line not containing a predetermined value may be described as “incompressible” (i.e., at least for the purposes of this technique—data not containing a predetermined value may be compressible using other cache compression methods).

[0024] The device is also equipped with a compression control circuit that, in response to determination that a given cache line to be allocated to the cache contains a predetermined value, sets the data field associated with a given address tag corresponding to the given cache line to a compressed data encoding for representing the predetermined value, and suppresses the storage of the given cache line in any of the N data storage locations. Therefore, the predetermined value (by storing the encoding representing the value) is effectively stored in the tag storage location instead of in the data storage location. Since the purpose of pointer encoding is not needed when using compressed data encoding (i.e., because the given cache line is not stored in any of the N data storage locations), the data field is provided for a dual purpose depending on whether the corresponding cache line contains the predetermined value. Therefore, this technique enables the tag storage location to use the same data field for two encodings, thereby reducing the total circuit area required to store cache lines in both compressed form (i.e., represented by compressed data encoding) and uncompressed form (i.e., in the data storage location indicated by pointer encoding).

[0025] In some examples, the cache is arranged such that M=N (i.e., there are the same number of data storage locations and tag storage locations). In such examples, setting the data field of the tag storage location to compressed data encoding can make one data storage location unused (i.e., since the tag storage location cannot be used to indicate that data storage location has pointer encoding). This can provide a small power saving because the data storage location is no longer needed.

[0026] In other examples, the cache is arranged such that M > N (i.e., there are more tag storage locations than data storage locations). It should be understood that data storage locations can be configured to have a larger storage capacity than tag storage locations because tag storage locations typically do not need to hold as much data as data storage locations. For example, tag storage locations might be needed to hold address tags, the data fields described above, and some associated metadata, all of which might only amount to a few bytes. On the other hand, data storage locations would be needed to hold an entire cache line, as above, which could be as large as, for example, 64 bytes. Therefore, the hardware cost of including one or more additional tag storage locations is minimal compared to including an additional data storage location. By setting the data fields of the additional tag storage locations to compressed data encoding as described above, tag storage locations can be used to represent data storage locations that hold cache lines containing predetermined values. Thus, at least when holding cache lines containing predetermined values, the cache capacity is effectively increased as if additional data storage locations existed, while only incurring the hardware cost of additional tag storage locations.

[0027] In some examples, the compression control circuitry, in response to a determination that a given cache line does not contain a predetermined value, permits the allocation of the given cache line to a selected data storage location among N data storage locations, and sets the data field of the selected tag storage location to a pointer encoding indicating the selected data storage location among the N data storage locations. Therefore, the cache line that does not contain a predetermined value is stored in the data storage location. By setting the data field of the selected tag storage location to a pointer encoding indicating that data storage location, the data storage location where the given cache line is stored can be easily located when a lookup is performed in the tag storage location.

[0028] In some examples, the apparatus is provided with read circuitry configured to receive read requests for target data at memory addresses from which read requests are made. The read requests may originate from an architectural source (e.g., a load / store unit after a load instruction is executed by a data processing device) or a microarchitectural source (e.g., a prefetcher that predicts future memory accesses will target the requested memory address). The read circuitry may perform a lookup in M ​​tag storage locations to identify a hit address tag corresponding to the requested memory address. In response to the fact that the data field identifying the hit address tag and associated with the hit address tag contains compressed data encoding, the read circuitry is configured to provide a predetermined value as a response to the read request.

[0029] In some examples, the read circuitry is configured to provide a predetermined value without accessing N data storage locations. For instance, the read circuitry can inject a predetermined value directly into the data path in response to a read request. This reduces both power consumption and latency.

[0030] In some examples, in response to a data field associated with a hit address tag containing pointer encoding, the read circuitry is configured to retrieve target data from one of N data storage locations indicated by the pointer encoding. This allows the read circuitry to retrieve data whose values ​​are not predetermined.

[0031] In some examples, the device is equipped with write circuitry configured to receive write requests to write target data to a specified memory address. As mentioned above, write requests can also originate from an architectural or microarchitecture source. The write circuitry can perform a lookup in M ​​tag storage locations to identify the target address tag corresponding to the specified memory address. The functionality of writing data to the cache can then depend on whether the target address tag is associated with a data field containing compressed data encoding or pointer encoding, and whether the target data to be written is a predetermined value. Specifically, if the target address tag is associated with a data field containing compressed data encoding and the target data to be written is not a predetermined value, the cache line can be "decompressed" to allow the target data to be stored. Decompression involves setting the data field to a pointer encoding indicating an available data storage location among the N data storage locations, and then allocating the target data to one of the available data storage locations among the N data storage locations.

[0032] It should be understood that data storage locations can be available, for example, when the cache is still warming up after the system is powered on or after some previously cached data has been invalidated. However, in some examples, if it is determined that no available data storage location exists, the write circuitry can evict existing cache lines from one of the N data storage locations. Various eviction strategies can be employed for this eviction, such as Least Recently Used (LRU), First-In-First-Out (FIFO), or Rereference Interval Prediction (RRIP). Once the data location is made available, the write target data can be allocated as described above.

[0033] In some examples, such as when the target data to be written is a predetermined value, the write circuitry is configured to set the data field associated with the target address label to a compressed data encoding. It should be understood that in specific implementations that provide multiple compressed data encodings for representing multiple predetermined values, the target data to be written may contain different predetermined values ​​among those already represented. Therefore, setting a compressed data encoding may include verifying that the correct compressed data encoding has been set, or setting a different compressed data encoding.

[0034] It should also be understood that if the write circuit does not identify the target address label, then as described above, the write target data can be allocated to the cache as a new cache line under the control of the compression control circuit.

[0035] In some examples, the apparatus is provided with an eviction circuit configured to select an eviction victim to be evicted from the cache in response to a given cache line being allocated to the cache. According to this technique, the eviction circuit can select the eviction victim based on whether the given cache line to be allocated contains a predetermined value. This criterion can be included as part of any other eviction strategy, such as those mentioned above.

[0036] In some examples, the cache is also provided with a priority metadata store configured to store eviction victim priority metadata associated with each of the M tag storage locations. The priority metadata store may include M priority metadata storage locations, each corresponding to a different tag storage location among the M tag storage locations. In some examples, the M priority metadata storage locations may be additional metadata fields included in the M tag storage locations. Alternatively, a single storage location may be provided with the ability to track metadata for each of the M tag storage locations. The eviction circuitry can then select an eviction victim based on the eviction victim priority metadata. In this way, eviction priority is tracked relative to the M tag storage locations (i.e., not N data storage locations). In the specific example where M>N, this allows all cache entries (including both compressed and uncompressed entries) to be tracked for eviction purposes.

[0037] In some examples, the eviction circuitry, in response to a given cache line containing a predetermined value, prioritizes the address tag associated with the compressed data encoding for selecting the eviction victim. This allows the cache to retain cache lines that do not contain the predetermined value, where possible, thus allowing for more efficient use of the N data storage locations. It should be understood that if no address tag associated with the compressed data encoding exists, the address tag associated with the pointer encoding can be evicted instead. This, in turn, renders the data location indicated by the pointer encoding unusable.

[0038] On the other hand, the eviction circuitry can, in response to a given cache line not containing a predetermined value, prioritize the cache line at the address tag associated with the pointer encoding and the data location indicated by that pointer encoding for selecting the eviction victim. This allows the cache to retain cache lines containing predetermined values ​​where possible.

[0039] Based on these examples above, the eviction circuit can prioritize replacing compressible data with compressible data and replacing incompressible data with incompressible data.

[0040] In some examples, this technique can be applied to multiple caches in the same system. For example, the apparatus can be configured with a second cache to store entries evicted from (the first) cache (e.g., L1 and L2 caches). The second cache includes at least one second tag storage location configured to store an address tag associated with a second data field, which is configured to at least support compressed data encoding. In some examples, the second cache can be arranged in the same manner as the first cache, but with larger N and M values ​​to accommodate more cached data. In response to the cache evicting an entry including an address tag associated with compressed data encoding from one of the M tag storage locations, the second cache can store the entry in at least one second tag storage location and set the second data field to compressed data encoding. Therefore, when compressible data is evicted from the first cache and allocated to the second cache, the data does not need to be uncompressed. Therefore, it is not necessary to send complete cache lines containing predetermined values ​​between caches, thereby reducing bandwidth in the memory system.

[0041] In the examples above, the predetermined value can be any value selected within a specific implementation. For example, a value that occurs particularly frequently in a given workload can be chosen as the predetermined value to be represented by the compressed data encoding. In some examples, the predetermined value can be all zeros or all one. As mentioned above, multiple compressed data encodings can be provided to store both; for example, one encoding for all zeros and one encoding for all one.

[0042] In some examples, at least one of the M tag storage locations contains a data field configured specifically to support compressed data encoding. In other words, at least one of the M tag storage locations does not support pointer encoding. Therefore, at least one of the M tag storage locations can be used as a dedicated storage location for compressible data, while the other tag storage locations can be used to store incompressible data using pointer encoding.

[0043] In some examples, the compression control circuitry is configured to suppress the setting of data fields to compressed data encoding in response to a given machine state. It should be understood that data already stored as compressed data encoding can be retained and read (e.g., based on the example of the read circuitry described above). However, newly allocated cache lines can be prevented from being stored as compressed data encoding, even if they contain predetermined values.

[0044] In some examples, a given machine state is determined based on values ​​stored in system registers. These system registers can be modified only by supervisory processes with elevated privilege levels (e.g., the operating system or hypervisor). Therefore, these processes can have the ability to disable compression functionality if needed.

[0045] In some examples, compression control circuitry is configured to suppress setting data fields to compressed data encoding in response to a given cache line containing data of a predetermined type. Such predetermined type of data may be data that is known to rarely or never contain predetermined values ​​(e.g., memory protection tags or prefetcher metadata). Furthermore, data contained in other caches (i.e., duplicate data stored in multiple caches) may preferably remain in uncompressed form.

[0046] The specific implementation scheme will now be described with reference to the accompanying drawings.

[0047] Figure 1 An example of a data processing apparatus 2 is illustrated schematically. The data processing apparatus has a processing pipeline 4 comprising multiple pipeline stages. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; a release stage 12 for checking whether the operands required for the micro-operation are available in a register file 14, and releasing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 for performing the data processing operation corresponding to the micro-operation by processing the operands read from the register file 14 to generate a result value; and a write-back stage 18 for writing the processed result back to the register file 14. It should be understood that this is merely one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, an additional register renaming level may be included to map the architecture registers specified by program instructions or micro-operations to physical register specifiers in the identifier register file 14. In some examples, a one-to-one relationship may exist between program instructions decoded by the decoding stage 10 and their corresponding micro-operations processed by the execution stage. It is also possible that a one-to-many or many-to-one relationship exists between program instructions and micro-operations, such that, for example, a single program instruction can be split into two or more micro-operations, or two or more program instructions can be merged to be processed as a single micro-operation.

[0048] Execution phase 16 includes multiple processing units for performing different types of processing operations. For example, the execution units may include: an arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations; a floating-point unit 22 for performing operations on floating-point values; a branching unit 24 for evaluating the results of branching operations and adjusting the program counter representing the current execution point accordingly; and a load / store unit 28 for performing load / store operations to access data in memory systems 8, 30, 32, and 34. In this example, the memory system includes a Level 1 data cache 30, a Level 1 instruction cache 8, a shared Level 2 cache 32, and main system memory 34. It should be understood that this technology relates to cache arrangement as a whole and can therefore be applied to any one or more of caches 8, 30, and 32. Therefore, although for the sake of brevity the following description will primarily refer to cache 30, it should be understood that the same features may also exist in instruction cache 8, L2 cache 32, or L3 cache (not shown).

[0049] It should also be understood that this is merely one example of a possible memory hierarchy, and other cache arrangements may also be provided. The specific type of processing units 20 to 28 shown in execution phase 16 is only one example, and other specific implementations may have different sets of processing units or may include multiple instances of the same type of processing units, enabling parallel processing of multiple micro-operations of the same type. It should be understood that... Figure 1 This is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not illustrated for the sake of brevity, such as branch prediction mechanisms, address translation, or memory management mechanisms.

[0050] Figure 2A An example arrangement of a device including cache 30 according to the present technology is illustrated. Cache 30 includes a set-associative arrangement having eight groups 38 for storing cached data. For a cache with associativity A, this means that the number of entries (each holding a cache line) in a group 38 is A. Such a cache can be described as an "[A]-way" set-associative cache, and entries can also be considered logically grouped into "ways," such as data ways 40, where each group 38 includes one entry from each data way 40. In this example, cache 30 includes four data ways 40, so cache 30 is 4-way set-associative for data. In addition to data ways 40, cache 30 also includes tag ways 42. As shown, the number of tag ways can be greater than the number of data ways. In this example, cache 30 includes five tag ways 42, so cache 30 is 5-way set-associative for address tags.

[0051] The set-associative placement strategy used for this type of cache means that when data with a given address needs to be allocated to the cache, it is placed in an entry within a specific set of 38 selected based on an index value calculated based on the given address. In some cases, the index can simply be a portion of bits extracted from the given address, while in other examples, the index can be based on a more complex function of the given address (e.g., applying a hash function to the given address to obtain the index value). Therefore, data associated with a given address cannot be stored in an entry outside of set 38 that corresponds to the set selected based on the given address. This is useful because it reduces the number of cache entries that must be checked to determine if the cache stores data associated with a specified destination address. However, compared to direct-mapped caching, where data for a given address can only be allocated to a single entry selected based on address, the set-associative placement scheme improves performance because of the flexibility to allocate data for a given address to two or more locations. This reduces the likelihood of thrashing, as it means that two or more different addresses mapped to the same set can each be cached simultaneously. Each entry can specify a data value, which is the information of interest stored in the cache entry. The data value can be data or instructions, or it can be address mapping information cached, for example, in a translation back buffer. According to this example, four entries in a given group 38 of data path 40 can correspond to N data storage locations (i.e., N=4) as defined in the appended claims.

[0052] Each entry stored in the cache can correspond to an address tag, which is stored in group 38 of one of the tag paths in tag path 42 (which can also be determined based on an index as described above). Therefore, five entries in a given group 38 of tag path 42 can correspond to M tag storage locations as defined in the appended claims (i.e., M=5). An example of tag entry 44 is shown in... Figure 2BThe image shows and includes an address tag 46, which corresponds to a portion of the memory address not used to generate the index and is stored in an entry in group 38 of tag path 42. Tag entry 44 also includes an encoded data field 48 capable of supporting one or both of a pointer encoding for identifying a data path in data path 40 where the data corresponding to address tag 46 resides, or a compressed data encoding for representing a predetermined value. Specific examples of such encoding will be described later. Tag entry 44 may also declare other metadata 50 associated with the memory address, such as a validity indicator indicating whether the corresponding data is valid, consistency status information (e.g., a dirty bit indicating whether the corresponding data has been modified compared to the corresponding data value in a lower-level cache (e.g., L2 or L3 cache) or memory), or eviction priority information for selecting a victim cache entry when it needs to be evicted from the cache. It should be understood that tag entry 44 may consist of only a few bytes, depending on how much of the memory address is used to define address tag 46 and how much other metadata 50 is required. Therefore, the hardware cost of each tag path in tag path 42 is lower than that of each data path in data path 40.

[0053] Return to Figure 2A Cache 30 is coupled to cache controller 36, which includes several functional units for controlling access to cache 30 and the allocation of data to cache. In this example, cache controller 36 includes compression control circuitry 52, read / write circuitry 54, and evict circuitry 56. Compression control circuitry 52 responds to a determination of whether a given cache line to be allocated to the cache contains a predetermined value. The predetermined value can be any value, for which there exists a compressed data encoding supported by data field 48 to represent the value. Therefore, the content identified by compression control circuitry 52 as a predetermined value can vary between implementations and even between caches in a given memory system. In response to the determination that a given cache line contains a predetermined value, compression control circuitry 52 controls the allocation of address tag 46 corresponding to the given cache line to tag entry 40 in tag path 42. Compression control circuitry 52 then sets data field 48 to the compressed data encoding representing the predetermined value. Since tag entry 44 now effectively holds a given cache line (or its representation), it is not necessary to store the given cache line in data path 40. Therefore, compression control circuitry 52 inhibits the storage of a given cache line in data path 40.

[0054] According to the above technique, cache lines that may be as large as 64 bytes can be compressed to be stored in tag entries 44, compared to tag entries that may only be a few bytes. Therefore, by providing an additional tag path 42, cache 30 can efficiently store an additional path equivalent to a cache line containing a predetermined value. It should be understood that the capacity value of the additional path depends on the difference between the number of tag paths 42 (M) and the number of data paths 40 (N). A specific implementation is for... Figure 2A The given value is M = 1.25 × N; however, other specific implementations are also possible.

[0055] On the other hand, if a given cache line to be allocated to the cache does not contain a predetermined value, the compression control circuit 52 sets data field 48 to pointer encoding instead of compressed data encoding. The pointer encoding indicates a data path in data path 40 where the given cache line is stored. It should be understood that the pointer encoding does not necessarily also specify group 38, as this can be identified by an index as described above. Therefore, this provides cache functionality for any data that is not a predetermined value.

[0056] Figure 3 Examples of encodings that can be supported by data field 48 are illustrated. In this example, data field 48 comprises a nibble (i.e., 4 bits). The first bit identifies the encoding type, with 1 indicating pointer encoding and 0 indicating compressed data encoding. For pointer encoding, the remaining 3 bits represent pointer bits identifying one of the data paths in data path 40. For compressed data encoding, the remaining 3 bits are used to represent a predetermined value. In this example, encodings for all zeros and all ones are present. This example also provides several “reserved” encodings, which can be implementation-specific. For example, if a particular value is particularly frequent in a given workload, that value can be assigned one of the reserved compressed data encodings (i.e., the value becomes a “predetermined value”). Thus, the value can be compressed to utilize the increased effective capacity of cache 30 more frequently.

[0057] It should be understood that, due to Figure 3 Four bits are provided for data field 48, so the pointer encoding can point to up to eight different data paths (i.e., because three bits are provided for the pointer bits). Figure 2AIn the cache 30, the data field 48 can be reduced to only 3 bits, allowing 2 pointer bits to point to any of the 4 data paths 40. Furthermore, for caches with more data paths, the data field 48 can be larger to accommodate more pointer bits. Since these pointer bits serve a dual purpose as value bits for compressed data encoding, there are also more possible compressed data encodings that can be supported. Therefore, a larger cache with more paths can also support compression of a larger number of predetermined values.

[0058] By using the pointer encoding described above, it is possible to dynamically associate each tag path with different data paths. Figure 4 Another example of a cache including 10 tag paths 60 and 8 data paths 62 is illustrated. As shown, each tag path in the tag paths 60 can be associated with any data path in the data paths 62. This arrangement allows for the flexibility to use any given tag path 60 to point to a data path 62 or to store a predetermined value based on compressed data encoding. However, not all tag paths in the cache need to support both pointer encoding and compressed data encoding. Figure 5 Another example is illustrated, where the tag path includes a statically associated tag path 64 and an additional tag path 66. The statically associated tag path can be fixed to provide a pointer for a specific data path 62. In some examples, the static tag path 64 may not explicitly define a pointer, but rather implicitly use, for example, the address tag in tag path 3 to correspond to a cache line stored in data path 3, implicitly use tag path 4 to correspond to a cache line stored in data path 4, and so on. The additional tag path 66 is not associated with any data path and can therefore be used with the data field 48 specifically to support compressed data encoding (i.e., and does not support pointer encoding). Therefore, the additional tag path 66 provides a dedicated tag storage location where predetermined values ​​can be represented by compressed data encoding.

[0059] It should be understood that Figure 4 and Figure 5 The examples provided are just two examples, and other possible implementations are possible. In fact, some examples can combine these two implementations to create combinations such as... Figure 4 The examples shown are some tag paths that can be dynamically associated with data paths, and such as... Figure 5 The at least one tag path shown cannot be associated with a data path used for dedicated storage of compressed data (i.e., at least one tag path with a data field specifically supporting compressed data encoding). Therefore, it should be understood that there are many different possible implementations of tag paths to provide different levels of flexibility for storing compressed or uncompressed data according to this technology.

[0060] return Figure 2A The cache controller is also provided with read / write circuitry 54, which is configured to receive read requests and / or write requests and then process the requested access to data in the cache. Such requests may be received from load / store unit 28 or may be line-fill requests from another level of cache. Read / write requests may specify a target address from which read / write circuitry 54 derives an index value as described above to select group 38 of tag path 42. Each address tag 46 in the entries of the selected group 38 is then compared with the tag portion of the target address. If any address tag 46 matches the tag portion of the target address, it is determined that the data targeted by the request is stored in the cache (i.e., in data path 40 or as compressed data encoded in tag path 42). This is referred to as a cache hit. On the other hand, if no address tag 46 in the selected group 38 matches the tag portion of the target address, a cache miss occurs. In this case, the information associated with the target address may need to be retrieved from another data repository, such as another level of cache 32 or main memory 34.

[0061] When a cache hit occurs, the address tag can be identified as either the hit address tag or the target address tag corresponding to the requested address. Subsequently, the read / write request is handled differently depending on whether the hit address tag is associated with a data field 48 containing pointer encoding or compressed data encoding.

[0062] For a read request, the read / write circuit 54, in response to a hit address tag 46 associated with a data field 48 containing pointer encoding, accesses the pointed-to data path 40 at the same set 38 (i.e., using the same derived index to look up tag path 42), thereby retrieving the requested cache line and returning the cache line as a response to the read request. On the other hand, if a hit address tag 46 is associated with a data field 48 containing compressed data encoding, the read / write circuit 54 is configured to generate a predetermined value as a response to the read request without accessing any data path in data path 40. For example, in a specific example where the read / write circuit 54 is used for the L1 data cache 30 and is responding to a read request from load / store unit 28, the predetermined value can be directly injected into the data line between load / store unit 28 and cache 30. Therefore, the read / write circuit 54 may include hardware logic for generating a predetermined value in response to compressed data encoding. Thus, it should be understood that reading compressed data from tag path 42 does not require access to data path 40, which provides a power saving for performing each read request.

[0063] Figure 6 A series of steps for the read / write circuit 54 in response to a read request are illustrated. At step 70, a read request is received. As described above, the read request specifies the requested memory address where the target data to be read is located. At step 72, a lookup is performed to determine if a hit exists in the address tag. If not, at step 74, the read request is forwarded to memory 34 or a lower-level cache. If a hit exists in the address tag, at step 76, it is determined whether the data field associated with the hit address tag contains pointer encoding or compressed data encoding. If the data field contains pointer encoding, at step 78, the read / write circuit 54 retrieves the target data from the data storage location indicated by the pointer encoding and returns that data value in response to the read request. If the data field contains compressed data encoding, at step 80, the read / write circuit 54 provides a predetermined value as a response to the read request, for example, by directly injecting a predetermined value into the data row.

[0064] For write requests, the way read / write circuitry 54 handles the request further depends on whether the write data itself is compressible (i.e., contains a predetermined value). If the write data is compressible, it can be written by setting the data field 48 associated with the hit address tag to compressed data encoding. Thus, if data field 48 previously pointed to data path 40, that data path 40 is "released" so that it can be used to be pointed to by a different tag path 42. If there is a miss in tag path 42 (i.e., no address tag exists), compressed data encoding is set in an available tag path 42 associated with a new address tag corresponding to the address specified in the write request. If no tag path 42 is available, read / write circuitry 54 can trigger eviction circuitry 56 to select an entry in tag path 42 as the eviction victim. Since the incoming data to be allocated to the cache is compressible, eviction circuitry 56 can preferentially evict address tags associated with compressed data encoding, so that the data currently held in data path 40 remains undisturbed.

[0065] Figure 7AA series of steps for the read / write circuit 54 in response to a write request specifying compressible writeable data are illustrated. At step 90, a write request is received. As described above, the write request specifies the memory address to which the target data is to be written. At step 92, a lookup is performed to determine if a hit exists in the address tag. If the hit address tag is located in a compressed entry (i.e., an address tag associated with a compressed data code), the compressed data code is reset at step 94. It should be understood that in examples where multiple predetermined values ​​exist and therefore multiple compressed data codes exist, step 94 may include setting the same compressed data code or a different compressed data code compared to an already set compressed data code. If the hit address tag is located in an uncompressed entry (i.e., an address tag with a pointer code), the pointer code is overwritten by the compressed data code, thereby freeing the indicated data storage location, for example, to be pointed to by a data field stored at a different tag location.

[0066] If step 92 results in a miss, then at step 98 it is determined whether any available tag storage locations exist. If not, the eviction process begins. Specifically, at step 100, eviction victims are selected from the tag storage locations, prioritizing those with compressed data encoding. Although not illustrated, it should be understood that if no tag storage location with compressed data encoding exists, an eviction victim will be selected from the tag storage locations with pointer encoding. Thus, the tag storage location is made available, and at step 102, for example under the control of compression control circuitry 52, a new address tag (corresponding to the memory address specified in the write request) is assigned, and the associated data field 48 is set to compressed data encoding.

[0067] Alternatively, if the data to be written is incompressible, it is written to data path 40. If the hit address tag is a compressed entry (i.e., associated with compressed data encoding), the entry may have to be decompressed to write the incompressible data. Therefore, when writing data to an available data path, data field 48 is set to pointer encoding to point to that data path. If no available data path 40 exists, read / write circuitry 54 can trigger eviction circuitry 56 to select an entry from data path 40 as the eviction victim. Since the incoming data to be allocated to the cache is incompressible, eviction circuitry 56 can preferentially evict the address tag associated with the pointer encoding in tag path 42 and the corresponding cache line in data path 40. Therefore, the data currently represented as compressed data encoding in tag path 42 remains undisturbed.

[0068] Figure 7BA series of steps for the read / write circuit 54 in response to a write request specifying incompressible write data are illustrated. At step 110, a write request is received. As described above, the write request specifies the memory address to which the target write data is to be written. At step 112, a lookup is performed to determine if a match exists in the address tag. If the match address tag is located in a compressed entry (i.e., the address tag associated with the compressed data encoding), the compressed entry can be decompressed to allow allocation of the incompressible data. Therefore, at step 114, it is determined whether the data storage location is available. If not, the eviction process begins. Specifically, at step 116, an eviction victim is selected from the data storage locations. This also implicitly selects the corresponding tag storage location as the eviction victim, which is associated with a pointer encoding identifying the selected data storage location. Therefore, the data storage location is made available, and at step 118, the write data is allocated to the data storage location, and the data field 48 of the corresponding tag entry is set to the pointer encoding indicating the allocated data storage location.

[0069] If, at step 112, the hit address tag is located in an uncompressed entry (i.e., the address tag associated with the pointer encoding), then it is not necessary to decompress the compressed entry. Instead, at step 120, the data location currently pointed to by the pointer encoding is overwritten by the written data.

[0070] If step 112 results in a miss, step 122 determines whether any available data storage location exists. If not, an eviction process similar to that in step 116 is performed at step 124. Specifically, an eviction victim is selected from the data storage locations and evictd to make the data storage location (and its corresponding tag storage location) available. At step 126, a new address tag (corresponding to the memory address specified in the write request) is assigned, and the associated data field 48 is set to a pointer encoding indicating an available data storage location. The written data is also assigned to that data storage location.

[0071] The general functionality of the eviction circuit 56 has already been described with reference to the previous example. The eviction circuit 56 can select an eviction victim based on eviction victim priority metadata stored in association with the tag path 42. As described above, this can be contained within the metadata field 50 of the tag entry 44. Alternatively, the eviction victim priority metadata can be stored in a separate victim path equal in number to the tag path 42. Therefore, a cache can track the eviction victim priority metadata at a higher level of association than the data path 40. Further alternatively, a single storage structure capable of tracking information for each tag path can be provided. For example, in the case of M tag paths, the priority metadata storage device can include log2(M) bits, where the resulting binary value identifies the tag path to be evicted next.

[0072] Furthermore, if the evicted data is allocated to a lower-level cache by the evicting circuit 56, the evicted compressed entries (i.e., tagged entries with compressed data encoding) can retain their compressed form if the lower-level cache also supports compressed data encoding. As described above, although the first-level data cache 30 is described... Figure 2A However, the same arrangement of data paths 40 and tag paths 42 can be implemented in the L2 cache 32. It should be understood that the L2 cache 32 can include a larger number of data paths 40 and cache paths 42, and / or can include different indexing schemes to allow a larger number of groups 38 in each path. Therefore, when a tag entry with compressed data encoding is evicted from the L1 data cache 30, the tag entry can be allocated to the L2 cache 32 without decompressing the data. In other words, the compressed data encoding can be passed between caches instead of passing a complete cache line containing predetermined values. This reduces traffic between caches and allows for more efficient use of memory system bandwidth.

[0073] Figure 8The sequence of steps for eviction circuit 56 to evict entries to a lower-level cache is illustrated. At step 130, an eviction victim is selected from the Level 1 data cache 30. As described above, this selection can be performed based on the eviction victim's priority metadata and whether the incoming cache line to be allocated contains a predetermined value. At step 132, it is determined whether the eviction victim has an address tag associated with compressed data encoding. If not (i.e., the cache line for the eviction victim is stored in the data storage location), then at step 134, the evicted address tag is allocated to a tag storage location, and the evicted data is allocated to the data storage location of the Level 2 cache 32. The associated data field 48 of the tag storage location is set to a pointer encoding for pointing to the data storage location. If the eviction victim does have an address tag associated with compressed data encoding, then at step 136, the evicted address tag is allocated to a tag storage location in the Level 2 cache, and the associated data field 48 of the tag storage location is set to compressed data encoding. The L2 cache 32 can also be equipped with a compression control circuit similar to the compression control circuit 52 described above. Therefore, when an address tag is assigned to a tag storage location in the L2 cache at step 136, any data storage location that would store data in the data storage location is suppressed. Thus, the aforementioned advantage of increasing the effective capacity of the cache with relatively low hardware cost also applies to the L2 cache 32. It should be understood that the above process can also be achieved when the tag address is evicted from the L2 cache 32 to the L3 cache.

[0074] In some examples, it may be desirable to disable the compression functionality of this technology. For example, when secure data is being processed, it may be preferable to restore normal use of the cache by storing the data in a data storage location to avoid giving potential hints about the content of the data. For example, if the data is stored as compressed data encoded in a tag storage location, the overall cache usage may not change (e.g., because no data must be evicted from the data storage location). This could give an attacker a hint that the secure data contains predetermined values, thus compromising security. Therefore, when secure data is being processed by a secure process, the data processing device 2 can switch to machine state (e.g., by writing machine state data to a system register). The compression control circuit 52 can then suppress the setting of data field 48 to compressed data encoding in response to this machine state. In other words, data field 48 is only set to pointer encoding, and the data is allocated to the data storage location. When the compression functionality is disabled, reading compressed data, as referenced... Figure 6 As described.

[0075] In some examples, compression control circuitry 52 can be configured not to apply this technique to specific data types. Specifically, microarchitectural metadata (such as memory protection tags, prefetcher metadata, etc.) may rarely be predetermined values ​​and / or may be timing-sensitive (e.g., the storage and retrieval of data in the cache must meet certain timing requirements, where compression may interfere with these requirements). Therefore, compression control circuitry 52 can, in response to determination that a cache line to be allocated to the cache contains the data, set the associated data field 48 to pointer encoding and allocate the cache line to the data storage location.

[0076] The concepts described herein can be specifically embodied in a system comprising at least one packaged chip. The previously described apparatus is implemented in this at least one packaged chip (either in a specific chip of the system or distributed across more than one packaged chip). The at least one packaged chip is assembled on a board along with at least one system component. Chip-containing products may include systems assembled on another board having at least one other product component. The system or chip-containing product may be assembled into a housing or onto a structural support (such as a frame or blade).

[0077] like Figure 9 As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the devices described above are implemented on a single chip or distributed across two or more chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package, which includes a protective housing (e.g., made of metal, plastic, glass, or ceramic) housing the semiconductor device implementing the aforementioned devices, and connectors such as pads, solder balls, or pins for connecting the semiconductor device to an external environment. Where more than one chip 400 is provided, these chips may be provided as individual integrated circuits (provided as separate packages), or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., using interpolators, or by using three-dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0078] In some examples, a collection of chiplets (i.e., small modular chips with specific functionalities) may be referred to as a chip in itself. Chipslets may be individually packaged in semiconductor packages and / or packaged together with other chiplets in multi-chiplet semiconductor packages (e.g., using interpolators, or by using three-dimensional integration to provide multi-layer chiplet products comprising two or more vertically stacked integrated circuit layers).

[0079] One or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or flexible substrate materials such as paper, plastic, or textile materials. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include any one or more of the following: another packaged chip (e.g., supplied by a different manufacturer or manufactured at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0080] A chip-containing product 416 is manufactured, comprising a system 406 (including a board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product components 412 include one or more additional components that are not part of system 406. As an example, in a non-exhaustive list, one or more product components 412 may include user input / output devices such as keyboards, touchscreens, microphones, speakers, displays, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on an additional board 414.

[0081] Plate 402 or another plate 414 may be disposed on or within the equipment housing or other structural support (e.g., frame or blade) to provide a product that can be disposed of by a user and / or intended for operational use by personnel or company.

[0082] System 406 or chip-containing product 416 can be at least one of the following: end-user product, machine, medical device, computing or telecommunications infrastructure product, or automated control system. For example, as a non-exhaustive list, a chip-containing product can be any of the following: telecommunications equipment, mobile phone, tablet computer, laptop computer, computer, server (e.g., rack server or blade server), infrastructure equipment, networking equipment, vehicle or other automotive product, industrial machine, consumer device, smart card, credit card, smart glasses, avionics equipment, robotic equipment, camera, television, smart TV, DVD player, set-top box, wearable device, home appliance, smart meter, medical device, heating / lighting control equipment, sensor, and / or control system for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0083] Figure 10Examples of the concepts described herein are illustrated in computer-readable code 202 for manufacturing a device 204 embodying the described concepts. For example, the computer-readable code 202 may be used at one or more levels of the semiconductor design and manufacturing process, including the electronic design automation (EDA) level, to manufacture an integrated circuit including the device 204 embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the device 204 embodying the concepts described herein to be defined, modeled, simulated, verified, and / or tested.

[0084] For example, computer-readable code 202 used to manufacture device 204 embodying the concepts described herein can be embodied in code that defines the hardware description language (HDL) representation of these concepts. For example, code 202 can define register-transfer level (RTL) abstractions of one or more logic circuits for defining device 204 embodying these concepts. Code 202 can define HDL representations of one or more logic circuits embodying device 204 in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code 202 can provide definitions of concepts or other behavioral representations of concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0085] Additionally or alternatively, computer-readable code 202 may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis procedures to the RTL representation to generate a definition for manufacturing a device embodying the present invention. Alternatively or additionally, one or more logic synthesis procedures may generate a bitstream from computer-readable code 202 to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0086] Computer-readable code 202 may include a mixture of code representations for manufacturing apparatus 204 (or virtually any component of apparatus 204), such as including one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus 204 embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus 204 and computer-readable code 202 defining instructions that will be executed by the defined apparatus once manufactured.

[0087] Such computer-readable code can be set in any known transient computer-readable medium 200 (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium 200 such as semiconductors, magnetic disks, or optical disks. Integrated circuits manufactured using computer-readable code 202 may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0088] In a brief general overview, apparatus, systems, methods, computer-readable media, and computer code are disclosed. The apparatus includes a cache comprising N data storage locations for storing cache lines and M tag storage locations for storing address tags of the cache lines. Each address tag is associated with a data field configured to support at least one of the following: a pointer encoding indicating one of the N data storage locations to which a corresponding cache line is allocated; and a compressed data encoding representing a predetermined value. In response to a determination that a given cache line to be allocated to the cache contains a predetermined value, compression control circuitry sets the data field associated with a given address tag corresponding to the given cache line to the compressed data encoding representing the predetermined value, and suppresses the storage of the given cache line in any of the N data storage locations.

[0089] In this application, the phrase "configured as..." is used to mean that the elements of the device are configured to perform the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0090] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, features of the dependent claims can be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus, the apparatus comprising: The cache includes: N data storage locations, configured to store cache lines; and M tag storage locations are configured to store address tags for cache lines, wherein each address tag is associated with a data field configured to support at least one of the following: A pointer encoding used to indicate one of the N data storage locations, corresponding to a cache line allocated to that data storage location; and Compressed data encoding used to represent predetermined values; and A compression control circuit, in response to a determination that a given cache line to be allocated to the cache contains the predetermined value, sets the data field associated with a given address label corresponding to the given cache line to the compressed data encoding for representing the predetermined value, and suppresses the storage of the given cache line in any of the N data storage locations.

2. The apparatus according to claim 1, wherein M>N.

3. The apparatus of claim 1 or claim 2, wherein the compression control circuit, in response to a determination that the given cache line does not contain the predetermined value, permits the given cache line to be allocated to a selected data storage location among the N data storage locations, and sets the data field of the selected tag storage location to the pointer encoding for indicating the selected data storage location among the N data storage locations.

4. The apparatus according to any of the preceding claims, wherein the apparatus comprises: A read circuit, configured to receive a read request for target data at a memory address from which a read request is made. In response to a hit address tag identifying a memory address corresponding to the request and the data field associated with the hit address tag containing the compressed data encoding, the read circuit is configured to provide the predetermined value as a response to the read request.

5. The apparatus of claim 4, wherein the read circuit is configured to provide the predetermined value without accessing the N data storage locations.

6. The apparatus of claim 4 or 5, wherein in response to the data field associated with the hit address tag containing the pointer encoding, the read circuitry is configured to retrieve the target data from one of the N data storage locations indicated by the pointer encoding.

7. The apparatus according to any preceding claim, wherein the apparatus comprises: A write circuit configured to receive a write request to write target data to a specified memory address. The write circuitry, in response to identifying a target address tag corresponding to the specified memory address and associated with the data field containing the compressed data encoding, is configured to: If the target data is not the predetermined value, the data field associated with the target address label is set to the pointer encoding indicating the available data storage location among the N data storage locations, and is used to allocate the written target data to the available data storage location among the N data storage locations.

8. The apparatus of claim 7, wherein the write circuitry, in response to a determination that no available data storage location exists, is configured to evict an existing cache line from one of the N data storage locations.

9. The apparatus according to claim 7 or claim 8, wherein the target data to be written is the predetermined value: The write circuit is configured to set the data field associated with the target address label to the compressed data encoding.

10. The apparatus according to any preceding claim, wherein the apparatus comprises: An eviction circuit, configured to select an eviction victim to be evicted from the cache in response to a given cache line being allocated to the cache. The eviction circuitry is configured to select the eviction victim based on whether the given cache line to be allocated contains the predetermined value.

11. The apparatus according to claim 10, wherein, The cache includes a priority metadata storage device configured to store eviction victim priority metadata in association with each of the M tag storage locations. The eviction circuit is configured to select the eviction victim based on the eviction victim priority metadata.

12. The apparatus of claim 10 or claim 11, wherein in response to the given cache line containing the predetermined value, the eviction circuit is configured to prioritize the address tag associated with the compressed data encoding for selecting the eviction victim.

13. The apparatus of any one of claims 10 to 12, wherein in response to the given cache line not containing the predetermined value, the eviction circuit is configured to prioritize the address tag associated with the pointer encoding for selecting the eviction victim.

14. The apparatus according to any preceding claim, wherein the apparatus comprises: A second cache, configured to store entries evicted from the cache, includes at least one second tag storage location configured to store address tags associated with a second data field, the second data field being configured to at least support the compressed data encoding. In response to the cache evicting an entry containing an address tag associated with the compressed data encoding from one of the M tag storage locations, the second cache is configured to store the entry in the at least one second tag storage location and set the second data field to the compressed data encoding.

15. The apparatus according to any preceding claim, wherein the predetermined value is one of the following: All zeros; and All one.

16. The apparatus according to any of the preceding claims, wherein, In at least one of the M tag storage locations, the data field is configured to specifically support the compressed data encoding.

17. The apparatus according to any of the preceding claims, wherein the compression control circuitry is configured to suppress setting the data field to the compressed data encoding in response to a given machine state.

18. The apparatus of claim 17, wherein the given machine state is determined based on a value stored in a system register.

19. The apparatus according to any of the preceding claims, wherein the compression control circuitry is configured to suppress setting the data field to the compressed data encoding in response to the given cache line containing data of a predetermined type.

20. The apparatus of claim 19, wherein the predetermined type of data is one of the following: Memory protection tags; Prefetcher metadata; The data is already stored in at least one other cache.

21. A system comprising: The apparatus according to any of the preceding claims is implemented in at least one packaged chip; At least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

22. A chip-containing product, the chip-containing product comprising the system of claim 21, wherein the system is assembled on an additional board together with at least one other product component.

23. A method, the method comprising: Store cache lines in N data storage locations; The address tags of cache lines are stored in M ​​tag storage locations, where each address tag is associated with a data field that supports at least one of the following: A pointer encoding used to indicate one of the N data storage locations corresponds to a cache line being allocated to that data storage location; and Compressed data encoding used to represent predetermined values; as well as In response to determining that a given cache line to be allocated to the cache contains the predetermined value, the data field associated with a given address label corresponding to the given cache line is set to the compressed data encoding for representing the predetermined value, and the storage of the given cache line in any of the N data storage locations is suppressed.

24. A non-transitory computer-readable medium storing computer-readable code for manufacturing an apparatus, the apparatus comprising: The cache includes: N data storage locations, configured to store cache lines; and M tag storage locations are configured to store address tags for cache lines, wherein each address tag is associated with a data field configured to support at least one of the following: A pointer encoding used to indicate one of the N data storage locations, corresponding to a cache line allocated to that data storage location; and Compressed data encoding used to represent predetermined values; and A compression control circuit, in response to a determination that a given cache line to be allocated to the cache contains the predetermined value, sets the data field associated with a given address label corresponding to the given cache line to the compressed data encoding for representing the predetermined value, and suppresses the storage of the given cache line in any of the N data storage locations.

Images