An eDRAM multi-level cache system and method for low temperature processors

Abstract

The application discloses a kind of eDRAM multistage cache systems and methods for low temperature processor, by utilizing the characteristics of eDRAM storage unit leakage reduction, data retention time extension under low temperature environment, eDRAM is applied to L1 cache, L2 cache and L3 cache of low temperature processor, and according to the difference of different cache hierarchy in access frequency, capacity demand, reliability demand, area efficiency demand and access delay demand, the mapping relationship between cache hierarchy demand and eDRAM storage unit characteristics is established, so that the cache reliability of low temperature processor is guaranteed while improving on-chip cache density, reducing refresh overhead, access conflict and system power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an eDRAM multilevel cache system and method for low-temperature processors. Background Technology

[0002] With the development of applications such as cryogenic high-performance computing and quantum computing control, cryogenic electronic systems have gradually become an important research direction for integrated circuits and processor architectures. In some application scenarios, processors need to operate in cryogenic environments, such as in liquid nitrogen temperature zones, deep cryogenic refrigeration environments, or system environments adjacent to cryogenic memories, cryogenic sensors, and quantum chips, performing control, scheduling, data preprocessing, or general computing tasks. For such cryogenic processor systems, the capacity, access latency, power consumption, and area efficiency of the on-chip cache directly affect the overall performance of the processor and the system energy efficiency.

[0003] Current processors typically use SRAM for on-chip cache. SRAM offers advantages such as fast access speed, no need for refresh, and good process compatibility, making it widely used in L1, L2, and L3 caches. However, SRAM cells usually consist of six or more transistors, resulting in a relatively large area per bit. As cache capacity increases, the SRAM array occupies a significant amount of chip area and incurs substantial dynamic and static power consumption. Especially in multi-level cache architectures, large-capacity last-level caches often become a major component of chip area and static power consumption, limiting further improvements in area efficiency and energy efficiency for low-temperature processors.

[0004] Embedded dynamic random access memory (eDRAM) offers higher storage density than SRAM, such as 1T1C eDRAM and gain-cell-based eDRAM. In particular, gain-cell-based eDRAM can be implemented using fewer transistor cells (2T, 3T, 4T, etc.), offering advantages such as better logic process compatibility, higher storage capacity per unit area, and lower dynamic power consumption. Therefore, eDRAM has the potential to replace or partially replace SRAM as on-chip cache. However, under normal temperature conditions, eDRAM relies on the charge of storage nodes to maintain data, and is affected by transistor leakage, charge leakage, and read / write disturbances, requiring very frequent periodic refreshes. Refresh operations introduce additional power consumption, access conflicts, and performance penalties, thus limiting the application of eDRAM in high-performance processor caches.

[0005] In low-temperature environments, transistor subthreshold leakage current, junction leakage current, and storage node charge leakage are typically significantly reduced, resulting in a corresponding extension of data retention time in eDRAM memory cells. When the processor operates at temperatures of 77K and below, the required refresh frequency for eDRAM can be significantly reduced, along with refresh power consumption and performance loss caused by refresh. This characteristic gives eDRAM a distinct application value in on-chip caches for low-temperature processors compared to room-temperature scenarios: on the one hand, eDRAM can achieve higher storage density with fewer transistors, thus providing a larger cache capacity within the same chip area; on the other hand, the low-temperature environment reduces the refresh burden on eDRAM, largely avoiding access conflicts and reducing system power consumption, making it more suitable to replace traditional SRAM in building multi-level cache systems for low-temperature processors.

[0006] However, most existing processor cache systems still primarily use SRAM, failing to fully utilize the reduced leakage current and extended retention time of eDRAM under low-temperature conditions. Existing eDRAM cache solutions are typically designed for room-temperature processors or general-purpose on-chip cache scenarios, focusing on compensating for insufficient data retention in eDRAM through refresh strategies, without establishing dedicated cache architectures, memory cell selection mechanisms, and low-temperature-aware refresh control methods for 77K and below low-temperature processors. Furthermore, different cache levels differ significantly in access frequency, access latency, reliability, capacity, and area efficiency. For example, L1 cache prioritizes low latency and high reliability, L2 cache requires a trade-off between capacity and access performance, and L3 or last-level cache prioritizes high density and large capacity. Simply replacing all cache levels with a single type of eDRAM memory cell makes it difficult to simultaneously meet the comprehensive requirements of performance, reliability, area, and power consumption for multi-level caches in low-temperature processors. Summary of the Invention

[0007] The present invention aims to at least partially solve one of the technical problems in the related art.

[0008] The main objective of this invention is to provide an eDRAM multilevel cache system for low-temperature processors.

[0009] Another objective of this invention is to propose an eDRAM multi-level cache method for low-temperature processors.

[0010] To achieve the above objectives, a first aspect of the present invention provides an eDRAM multi-level cache system for low-temperature processors, comprising: a processor, an L1 cache, an L2 cache, and an L3 cache connected to the processor core, a cache management controller, and a refresh controller; wherein:

[0011] The L1 cache, L2 cache, and L3 cache are all constructed using eDRAM memory cells; The cache management controller is used to configure the appropriate eDRAM memory cell type for the corresponding cache level according to the reliability requirements, access frequency, capacity requirements, access latency requirements and area efficiency requirements of different cache levels. The refresh controller is used to perform differentiated refresh control for different cache levels based on the data retention time of the eDRAM storage unit; The processor operates in a low-temperature environment, which extends the data retention time of the eDRAM storage cells, thereby reducing the refresh frequency and refresh power consumption.

[0012] In one embodiment of the present invention, the cache management controller matches various eDRAM memory cells according to the reliability requirements, access frequency, capacity requirements, access latency requirements and area efficiency requirements corresponding to the cache level, and determines the type of eDRAM memory cell used in each cache level based on the matching results.

[0013] In one embodiment of the present invention, the L1 cache uses a high-speed, high-reliability eDRAM memory cell, the L2 cache uses an eDRAM memory cell that balances access performance and area efficiency, and the L3 cache uses a high-density eDRAM memory cell.

[0014] In one embodiment of the present invention, the high-speed, high-reliability eDRAM memory cell is a 4T gain cell eDRAM, the eDRAM memory cell that balances access performance and area efficiency is a 3T gain cell eDRAM, and the high-density eDRAM memory cell is a 2T gain cell eDRAM or a 1T1C eDRAM.

[0015] In one embodiment of the present invention, the refresh controller includes a refresh scheduler, a refresh counter, a retention time manager, and a temperature monitoring unit; The refresh scheduler generates the refresh cycle for each cache level based on the data retention time of the corresponding eDRAM storage unit.

[0016] In one embodiment of the present invention, the refresh controller employs a hierarchical refresh strategy, including: L1 cache uses a low-frequency refresh method; L2 cache uses a periodic refresh method; The L3 cache uses a block-interleaved refresh method.

[0017] In one embodiment of the present invention, the refresh controller dynamically adjusts the refresh cycle of the corresponding cache level based on the operating temperature, cache access frequency and error detection results obtained by the temperature monitoring unit.

[0018] In one embodiment of the present invention, when the processor operates at a low temperature of 77 K or below, the refresh controller extends the refresh cycle of the corresponding cache level according to the difference in data retention time of the eDRAM storage cells used in each cache level.

[0019] To achieve the above objectives, a second aspect of the present invention provides a method for eDRAM multi-level caching for low-temperature processors, comprising: Obtain cache requirement information for each cache level of the processor; Based on the cache requirement information of each cache level, configure the appropriate eDRAM storage unit for the corresponding cache level; Obtain the data retention time of the eDRAM memory unit corresponding to each cache level, and generate the basic refresh cycle of the corresponding cache level based on the data retention time; The processor operating temperature, cache access frequency, and error detection results are obtained, and the refresh cycle of the corresponding cache level is dynamically adjusted based on the operating temperature, cache access frequency, and error detection results. Perform refresh operations for the corresponding cache level based on the adjusted refresh cycle.

[0020] In one embodiment of the present invention, dynamically adjusting the refresh cycle of the corresponding cache level based on the operating temperature, cache access frequency, and error detection results includes: Extend the refresh cycle when the operating temperature decreases, reduce the additional refresh frequency when the cache access frequency increases, and shorten the refresh cycle of the corresponding cache level when error detection results indicate an increase in the error rate.

[0021] The embodiments of the present invention have the following beneficial effects: (1) Improve cache area utilization. By establishing a mapping relationship between the cache hierarchy requirements of low-temperature processors and the characteristics of eDRAM storage units, and by adopting differentiated eDRAM structures for L1 cache, L2 cache and L3 cache, the storage capacity per unit area can be increased compared with the traditional SRAM cache system. Larger capacity cache can be configured under the same chip area, or more layout resources can be released for integrating processor core, on-chip interconnect and other functional modules.

[0022] (2) Reduce cache power consumption. eDRAM memory cells have fewer transistors than traditional SRAM cells, which can reduce the area of ​​the cache array and access power consumption; at the same time, in low temperature environments, eDRAM memory node leakage current is reduced and data retention time is extended, which can further reduce refresh power consumption and overall power consumption of the cache system.

[0023] (3) Reduce refresh overhead. Under low-temperature operating conditions of 77K and below, the data retention time of eDRAM memory cells is significantly extended, and the required refresh frequency is reduced. Through the low-temperature-aware refresh control mechanism, unnecessary refresh operations can be reduced, refresh power consumption can be reduced, and the blocking of normal cache access during the refresh process can be reduced.

[0024] (4) Improve overall system performance. By using high-density eDRAM to build a multi-level cache for low-temperature processors, the cache capacity can be increased within the same chip area, the cache hit rate can be improved, the number of accesses to external memory can be reduced, thereby reducing memory access latency and improving processor execution efficiency.

[0025] (5) Improve the adaptability of different cache levels. In order to meet the requirements of low latency and high reliability of L1 cache, performance and capacity balance of L2 cache, and high density and large capacity of L3 cache, 4T, 3T and 2T gain units eDRAM are used respectively in the preferred embodiment, so that different cache levels can achieve a more reasonable trade-off between reliability, area efficiency, access performance and power consumption.

[0026] (6) Improved process compatibility. The gain unit eDRAM structure adopted can be implemented based on standard CMOS logic process without the need for additional dedicated memory process modules, additional mask steps or special manufacturing processes, which facilitates integration and implementation in low-temperature processor chips.

[0027] (7) Enhanced adaptability to low-temperature environments. This invention fully utilizes the characteristics of reduced leakage current and extended retention time of eDRAM under low-temperature environments. It dynamically adjusts the refresh cycle through temperature sensing, access heat sensing, and error rate feedback mechanisms, enabling the cache system to adapt to the low-temperature processor operating environment and improve system energy efficiency. Attached Figure Description

[0028] The above-described and additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 A schematic diagram of the framework of an eDRAM multi-level cache system for low-temperature processors provided in an embodiment of the present invention; Figure 2 A mapping diagram of eDRAM memory cells based on cache requirement characteristics provided in an embodiment of the present invention; Figure 3 The cell structure diagrams for three different eDRAMs provided in embodiments of the present invention; Figure 4 This is a schematic diagram of a hierarchical refresh control mechanism provided in an embodiment of the present invention; Figure 5 This is a flowchart of the dynamic adaptive refresh control provided in an embodiment of the present invention; Figure 6This is a flowchart illustrating an eDRAM multi-level cache method for low-temperature processors, provided as an embodiment of the present invention. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] The following description, with reference to the accompanying drawings, describes an eDRAM multilevel cache system and method for low-temperature processors according to embodiments of the present invention.

[0032] Example 1 This embodiment provides an eDRAM multi-level cache system for cryogenic processors. By leveraging the characteristics of reduced leakage current and extended data retention time of eDRAM memory cells in cryogenic environments, eDRAM is applied to the L1, L2, and L3 caches of cryogenic processors. Based on the differences in access frequency, capacity requirements, reliability requirements, area efficiency requirements, and access latency requirements of different cache levels, a mapping relationship between cache level requirements and eDRAM memory cell characteristics is established. This ensures the reliability of the cryogenic processor cache while increasing on-chip cache density and reducing refresh overhead, access conflicts, and system power consumption.

[0033] In this embodiment, the caching system includes multiple cache regions with different performance targets. Different cache regions are constructed using eDRAM memory cells with different performance characteristics based on their reliability requirements, access frequency, capacity requirements, access latency requirements, and area efficiency requirements. Specifically, the high-speed, high-reliability cache region preferentially uses eDRAM memory cells with high read / write stability, large read / write margin, and low access disturbance; the balanced cache region preferentially uses eDRAM memory cells that balance access performance, data retention capability, and area efficiency; and the large-capacity cache region preferentially uses eDRAM memory cells with high storage density and area utilization to increase the capacity of the last-level cache. In a preferred embodiment, the high-speed, high-reliability cache region corresponds to the processor's L1 cache, the balanced cache region corresponds to the processor's L2 cache, and the large-capacity cache region corresponds to the processor's L3 cache. It should be noted that this invention is not limited to a three-level cache structure; for processors with other cache hierarchy organization forms, the corresponding type of eDRAM memory cells can also be selected based on the performance requirements of each cache level.

[0034] like Figure 1 As shown, the caching system in this embodiment includes a processor (i.e., a computing core), L1 cache, L2 cache, and L3 cache (different cache regions) connected to the processor, a cache management controller, and a refresh controller. The processor can be a low-temperature CPU, a low-temperature GPU, an NPU, an LPU, or other processors suitable for low-temperature environments; this application does not impose specific limitations on this. Preferably, the processor operates at a low temperature of 77 K or below. Under this operating condition, the leakage current of the eDRAM memory cells is significantly reduced, and the data retention time of the memory nodes is extended, thereby reducing the refresh frequency required by the caching system and minimizing the power consumption and performance loss caused by refresh operations.

[0035] In this embodiment, the L1, L2, and L3 caches are all constructed using eDRAM memory cells. Different types of eDRAM memory cells are used for different cache levels to meet the different performance targets of each cache level. Specifically, the L1 cache mainly handles high-frequency instruction and data access near the processor core, requiring high access latency and reliability; the L2 cache mainly handles cache expansion and data buffering functions, needing to balance access performance, cache capacity, and area efficiency; and the L3 cache, as a shared cache or last-level cache, is primarily used to provide a large cache capacity, therefore prioritizing storage density and area utilization.

[0036] The cache management controller is used to manage the configuration between cache tiers and eDRAM memory cells. Specifically, the cache management controller obtains the reliability requirements, access frequency, capacity requirements, access latency requirements, and area efficiency requirements corresponding to each cache tier, and configures matching eDRAM memory cell types for different cache tiers based on the performance characteristics of various eDRAM memory cells, thereby forming a heterogeneous eDRAM cache architecture based on cache requirement awareness. By using different types of eDRAM memory cells to construct different cache tiers, each cache tier can achieve comprehensive optimization in terms of access performance, storage capacity, reliability, and chip area.

[0037] The refresh controller manages the refresh operations of each level of eDRAM cache. Since different types of eDRAM memory cells have different data retention times, the refresh controller generates corresponding refresh strategies based on the data retention times of the eDRAM memory cells used in each cache level, and performs differentiated refresh control on each cache level according to the generated refresh strategies. Because the processor operates in a low-temperature environment, the data retention time of the eDRAM memory cells is significantly longer than under normal temperature conditions. Therefore, the refresh controller can appropriately extend the refresh cycle of each cache level, reduce the number of refreshes, reduce refresh power consumption, and minimize the impact of refresh operations on normal cache access, thereby improving the overall operating efficiency of the cache system.

[0038] This embodiment achieves a reasonable match between cache level requirements and eDRAM storage unit performance through the coordinated work of the cache management controller and refresh controller. In addition, taking into account the extended data retention time of eDRAM in low-temperature environments, differentiated refresh management is implemented for different cache levels, enabling the low-temperature processor cache system to achieve better overall performance in terms of cache capacity, access performance, data reliability, chip area and system power consumption.

[0039] Example 2 This embodiment further illustrates the different types of eDRAM memory cells used in the heterogeneous eDRAM cache system described in Embodiment 1 and their application in each cache level. Based on the differences in access frequency, reliability requirements, capacity requirements, access latency requirements, and area efficiency requirements among different cache levels of the low-temperature processor, this embodiment employs a cache requirement-aware design approach to select eDRAM memory cells with different performance characteristics for different cache levels, thereby optimizing the overall performance of the cache system.

[0040] like Figure 2As shown, this embodiment establishes the correspondence between cache hierarchy requirements and eDRAM memory unit performance. Based on the functional positioning and performance targets of L1, L2, and L3 caches, different types of eDRAM memory units are used for construction. In a preferred embodiment, the L1 cache is implemented using 4T gain unit eDRAM, the L2 cache using 3T gain unit eDRAM, and the L3 cache using 2T gain unit eDRAM. The above-described eDRAM memory units are only described as preferred embodiments. In other embodiments, other eDRAM memory units with corresponding performance characteristics can also be used, such as 1T1C eDRAM or other gain unit eDRAM structures. The preferred structures of various eDRAM memory units are as follows: Figure 3 As shown.

[0041] For the L1 cache, since it is located near the processor core, it is the cache level with the highest processor access frequency and the highest requirements for access latency and data reliability. It usually undertakes instruction fetching, critical data caching, and high-frequency read and write operations. Therefore, the storage unit is required to have high read and write stability, large read and write margin, and low access disturbance. Based on the above requirements, this embodiment preferably uses high-speed, high-reliability 4T gain unit eDRAM to construct the L1 cache.

[0042] In a preferred embodiment, the 4T gain unit eDRAM includes three write-related transistors, one read-related transistor, and a storage node, utilizing the parasitic capacitance of the storage node to store charge information. During a write operation, the write-related transistor is turned on via the write word line to write the data to be written to the storage node. A feedback structure is used to improve write stability, suppress write access crosstalk, and shorten write setup time. During a read operation, the read-related transistor is turned on via the read word line to transfer the data stored in the storage node to the read bit line, where a sensing circuit completes the data reading. To further improve the access speed and reliability of the L1 cache, the L1 cache can also be configured with a high-speed sensitive amplifier, an adjustable bit line precharge circuit, and a level conversion circuit to shorten read / write setup time and improve cache access stability in low-temperature environments.

[0043] Because the leakage current of the 4T gain-cell eDRAM is significantly reduced at low temperatures, its data retention capability is further improved, thus enabling a reduction in refresh rate while maintaining high read / write reliability. Furthermore, compared to traditional 6T SRAM memory cells, the 4T gain-cell eDRAM has a higher storage density, thereby reducing chip area footprint while maintaining L1 cache performance.

[0044] The L2 cache mainly serves as a data buffer and cache expansion function between the L1 cache and the last-level cache. It needs to balance access performance, cache capacity, area efficiency and implementation cost. Therefore, this embodiment preferably uses a balanced eDRAM memory cell that balances performance and area efficiency to build the L2 cache.

[0045] In a preferred embodiment, the balanced eDRAM memory cell adopts a 3T gain unit eDRAM structure. The 3T gain unit eDRAM includes a write path, a read path, and a hold structure. The write path is used to write data to the memory node, the read path is used to couple the memory node voltage to the read bit line, and the hold structure is used to improve the data retention capability of the memory node, thereby balancing access performance and data retention capability. The L2 cache is further configured with a sensing amplifier circuit, preferably an inverter-based sensing amplifier, to detect and recover voltage changes on the read bit line, improving data read speed and reducing the probability of false alarms.

[0046] Because the low-temperature environment significantly extends the data retention time of the 3T gain unit eDRAM, the L2 cache refresh rate can be further reduced compared to the room-temperature environment. By using 3T gain unit eDRAM to construct the L2 cache, the storage capacity per unit area can be increased while ensuring access performance, achieving a balance optimization between cache capacity, access latency, and chip area.

[0047] For L3 cache, which is mainly used as a processor shared cache or last-level cache, a large cache capacity is required. Therefore, storage density and area utilization become the main design goals. For this type of cache region, this embodiment prioritizes the use of high-density eDRAM memory cells to achieve a large-capacity cache. While ensuring data reliability, the access performance requirements are appropriately reduced to improve the overall cache capacity.

[0048] In a preferred embodiment, the high-density eDRAM memory cell employs a 2T gain cell eDRAM structure. In other embodiments, a 1T1C eDRAM or other eDRAM memory structures with higher storage density may also be used.

[0049] The 2T gain unit eDRAM includes write transistors, read transistors, and storage nodes, utilizing the parasitic capacitance of the storage nodes to store charge information. Write operations are performed by controlling the write transistors via write word lines to write data; read operations are performed by controlling the read transistors via read word lines to sense data. Because the 2T gain unit eDRAM has a simple structure and a small number of transistors, it can effectively improve the storage density per unit area, making it suitable for constructing large-capacity last-level caches.

[0050] To further improve the data reliability of the L3 cache, the L3 cache in this embodiment is also equipped with an ECC error correction module to detect and correct data errors caused by charge leakage or other factors; at the same time, a block refresh control unit is configured to divide the cache array into multiple refresh blocks to support the block refresh control strategy described in subsequent embodiments, thereby reducing the impact on normal cache access during the refresh process.

[0051] Because low-temperature environments significantly reduce leakage current in 2T gain-unit eDRAM memory nodes, extending data retention time considerably, the L3 cache can operate stably at lower refresh rates, significantly reducing refresh power consumption and refresh access conflicts. Furthermore, compared to SRAM cache, using 2T gain-unit eDRAM to build the L3 cache allows for the integration of a larger cache capacity within the same chip area, improving processor cache hit rate and reducing the number of processor accesses to external memory, thereby further enhancing the overall performance and system energy efficiency of the low-temperature processor.

[0052] In summary, this embodiment constructs L1 cache, L2 cache, and L3 cache using three types of eDRAM memory units: high-speed and high-reliability, balanced, and high-density, based on the functional positioning and performance requirements of different cache levels. This allows the performance advantages of different types of eDRAM memory units to be fully utilized. Furthermore, by combining the extended data retention time of eDRAM under low-temperature conditions, it achieves comprehensive optimization of cache capacity, access performance, data reliability, chip area, and system power consumption.

[0053] Example 3 This embodiment further explains the refresh controller and its hierarchical refresh control mechanism described in Embodiment 1. Because different types of eDRAM memory cells have different storage structures, data retention times, and reliability requirements, the refresh strategies corresponding to different cache levels also differ. To fully utilize the extended data retention time of eDRAM memory cells in low-temperature environments, this embodiment proposes a hierarchical refresh control mechanism suitable for low-temperature processors. Based on the type of eDRAM memory cell used in different cache levels and its data retention characteristics, different refresh strategies are executed for each cache level, ensuring cache data reliability while reducing refresh power consumption and the impact of refresh operations on normal cache access.

[0054] like Figure 4 As shown, the refresh controller in this embodiment includes a refresh counter, a refresh scheduler, a retention time manager, and a refresh counter that is not in use. Figure 4The temperature monitoring unit is shown. The retention time manager records the data retention time parameters of eDRAM memory cells corresponding to different cache levels and establishes corresponding refresh cycles based on the data retention capabilities of different types of eDRAM memory cells. The refresh counter records the refresh count information of each cache level and determines whether the refresh conditions for the corresponding cache level have been met. The refresh scheduler generates a refresh scheduling strategy based on the information provided by the refresh counter and retention time manager, and controls each cache level to complete the refresh operation according to the corresponding refresh mode. The temperature monitoring unit acquires the operating temperature of the processor chip or cache array in real time, providing a basis for adjusting the refresh cycle.

[0055] In this embodiment, different refresh modes are used for different cache levels.

[0056] For the L1 cache, since it uses high-speed, high-reliability eDRAM memory cells, preferably 4T gain-cell eDRAM, its data retention capability is strong. Furthermore, the L1 cache handles the most frequent data access tasks near the processor core; therefore, the refresh controller employs a low-frequency, high-reliability refresh mode. The retention time manager establishes a refresh cycle based on the data retention time of the corresponding eDRAM memory cell in the L1 cache. The refresh counter continuously records the refresh time. When the preset retention time is reached or the preset reliability condition is met, the refresh scheduler triggers the corresponding cache area to perform a refresh operation. Because low-temperature environments can significantly extend the data retention time of the 4T gain-cell eDRAM, the L1 cache does not require high-frequency refresh, thereby reducing the impact of refresh operations on L1 cache access performance while ensuring the reliability of cached data.

[0057] For L2 cache, since it uses eDRAM memory cells that balance access performance and area efficiency, 3T gain unit eDRAM is preferred. Its data retention capability and access performance are between those of L1 and L3 cache, so the refresh controller adopts a periodic refresh mode. The retention time manager generates a basic refresh cycle based on the data retention time parameters corresponding to the 3T gain unit eDRAM, and the refresh scheduler periodically triggers refresh operations according to the preset refresh cycle. To reduce the impact of refresh on normal cache access, L2 cache further adopts a bank-level interleaved refresh mechanism, dividing the cache array into multiple independent banks. Only one bank is refreshed at a time, while the remaining banks maintain normal read and write access, thereby reducing refresh conflicts and improving cache access efficiency.

[0058] For the L3 cache, since it is mainly used as a shared cache or last-level cache, a high-density 2T gain-cell eDRAM or other high-density eDRAM memory structure is preferred to increase cache capacity. Therefore, the refresh controller adopts a block refresh mode. Specifically, the refresh controller first divides the L3 cache array into multiple storage banks, and each storage bank is further divided into multiple refresh blocks. Each refresh block corresponds to an independent refresh status and refresh count information. The refresh scheduler performs refresh operations only on refresh blocks that meet the refresh conditions according to the refresh cycle provided by the retention time manager, while refresh blocks that do not meet the refresh conditions continue to maintain normal operation, thereby reducing peak refresh power consumption and minimizing the impact of the refresh process on cache access. Furthermore, to avoid a decrease in shared cache access bandwidth caused by multiple banks performing refreshes simultaneously, the refresh scheduler adopts a time-interleaved refresh strategy to stagger the peak times of different banks and different refresh blocks. Specifically, when a Bank enters the refresh state, the other Banks continue to maintain normal cache access. The refresh scheduler arranges each refresh block to complete the refresh in sequence according to the current refresh state, refresh count value and refresh priority of each Bank, so that the refresh operations between multiple Banks are interleaved in time, thereby avoiding access conflicts and performance degradation caused by multiple storage Banks being refreshed at the same time.

[0059] In this embodiment, the refresh mode adopted by each cache level is uniformly managed by the refresh scheduler. Different cache levels establish corresponding refresh cycles based on the data retention time of their eDRAM memory cells, and select low-frequency high-reliability refresh, periodic refresh, or block refresh strategies according to the characteristics of the cache level to achieve hierarchical management of the cache refresh process. Since the leakage current of eDRAM memory cells is reduced and the data retention time is extended in low-temperature environments, the above-mentioned hierarchical refresh control mechanism can effectively reduce the number of refreshes, reduce refresh power consumption, reduce refresh access conflicts, improve cache access efficiency, and further improve the overall performance and energy efficiency of the low-temperature processor cache system.

[0060] Example 4 This embodiment further illustrates the dynamic adaptive refresh control mechanism of the refresh controller described in Embodiment 3. Based on the hierarchical refresh control mechanism described in Embodiment 3, to further reduce refresh power consumption, minimize the impact of refresh operations on normal cache access, and ensure cache data reliability, this embodiment proposes a dynamic adaptive refresh control method suitable for low-temperature processors. This method can adjust the refresh cycle of different cache levels in real time according to the processor's operating state, further optimizing refresh control from fixed-cycle refresh to adaptive refresh.

[0061] like Figure 5As shown, in this embodiment, the refresh controller, based on the hierarchical refresh control, further acquires processor operating status information and dynamically adjusts the refresh cycle of each cache level according to the operating status. The operating status information includes the processor or cache array's operating temperature, cache access frequency, cache data access frequency, cache error detection results, and data retention time prediction results. These various types of status information can be used individually as the basis for refresh cycle adjustment, or they can be used collectively for refresh decisions.

[0062] In this embodiment, the temperature monitoring unit continuously monitors the real-time operating temperature of the processor chip or cache array and sends the detection results to the refresh scheduler. The refresh scheduler adjusts the basic refresh cycle based on the current operating temperature. When a decrease in processor operating temperature is detected, the data retention time is further extended due to the further reduction in leakage current of the eDRAM storage node under low-temperature conditions. Therefore, the refresh scheduler appropriately extends the refresh cycle of the corresponding cache level, reducing the number of refreshes. When an increase in processor operating temperature is detected, the refresh scheduler shortens the refresh cycle accordingly to ensure that the cached data is refreshed within the specified retention time, thereby ensuring the reliability of the cached data.

[0063] The access frequency statistics unit is used to count the number of times each cache block is accessed within a preset time window, and obtains the access frequency information of the cache block based on the statistical results. The refresh scheduler dynamically adjusts the refresh strategy according to the access frequency of the cache block. For cache blocks with high access frequency, since frequent read and write operations can indirectly reduce the risk of long-term data retention, the refresh scheduler appropriately reduces the additional refresh frequency to reduce unnecessary refresh operations; for cache blocks with low access frequency or that have not been accessed for a long time, the refresh is performed according to the data retention time of the corresponding eDRAM storage unit to ensure the reliability of long-term cache data retention.

[0064] In this embodiment, the caching system is further configured with an ECC error detection module to continuously monitor data errors at each cache level. The ECC module calculates the error rate of each cache region in real time and sends the detection results to the refresh scheduler. When the error rate of a certain cache region is detected to be higher than a preset threshold, the refresh scheduler considers that the data retention capability of that cache region has decreased, and accordingly increases the refresh frequency of that cache region and shortens the refresh cycle to reduce the risk of further data errors. When the error rate of a cache region is detected to remain at a low level, the refresh cycle of the corresponding cache region is appropriately extended to further reduce refresh power consumption.

[0065] To further improve refresh control accuracy, the retention time manager in this embodiment can also predict the data retention time of eDRAM memory cells corresponding to different cache levels based on the current operating temperature, eDRAM memory cell type, and historical operating status, and use the prediction results as one of the bases for refreshing cycle adjustment. The refresh scheduler dynamically corrects the basic refresh cycle of each cache level based on the retention time prediction results, making the refresh control more adaptable to the actual operating status of the processor and improving the accuracy of refresh control.

[0066] When the processor operates at a low temperature of 77 K or below, the refresh controller enters a low-temperature refresh mode. Since the low temperature significantly reduces leakage current in eDRAM memory nodes, the data retention time of different types of eDRAM memory cells is extended to varying degrees. Therefore, the refresh scheduler adjusts the refresh cycle for each cache level based on the differences in data retention time of the eDRAM memory cells used in different cache levels in Example 2. Specifically, the refresh cycle of the L1 cache, which uses high-speed, high-reliability eDRAM memory cells, is appropriately extended; the refresh cycle of the L2 cache, which uses balanced eDRAM memory cells, is further extended; and the refresh frequency of the L3 cache, which uses high-density eDRAM memory cells, is appropriately reduced while ensuring reliability. This is combined with the block refresh strategy described in Example 3 to perform refresh operations, thereby further reducing refresh power consumption, minimizing refresh access conflicts, and improving the overall operating efficiency of the cache system.

[0067] In this embodiment, the dynamic adaptive refresh control mechanism is built upon the hierarchical refresh control mechanism described in Embodiment 3, and the two work together. The hierarchical refresh control mechanism determines the basic refresh strategy for each cache level based on different cache levels and different types of eDRAM memory cells; the dynamic adaptive refresh control mechanism dynamically modifies the basic refresh strategy based on the processor's real-time operating state, enabling the refresh control to adjust in real time according to changes in the processor's operating state. Through this control method, the refresh controller can adaptively generate corresponding refresh strategies based on different cache levels, different eDRAM memory cell characteristics, and different operating environments, achieving a reasonable allocation of cache refresh resources.

[0068] In summary, this embodiment, through the coordinated operation of a heterogeneous eDRAM cache architecture, a hierarchical refresh control mechanism, and a dynamic adaptive refresh control mechanism, fully leverages the characteristics of reduced leakage current, extended data retention time, and high storage density of eDRAM memory cells under low-temperature conditions. While ensuring cache access performance and data reliability, it effectively reduces cache refresh power consumption and refresh access conflicts, improves cache capacity utilization and system energy efficiency, and achieves comprehensive optimization of the low-temperature processor cache system in terms of area, power consumption, capacity, performance, and reliability.

[0069] Example 5 This embodiment is a specific application example based on embodiments 1 to 4, used to illustrate the specific implementation of the present invention in a low-temperature high-performance processor.

[0070] This embodiment applies to high-performance processor chips that operate at low temperatures. For example... Figure 1 As shown, the processor chip includes multiple processor cores, an on-chip interconnect network, L1 cache, L2 cache, L3 cache, a cache management controller, and a refresh controller. The processor operates at a low temperature of 77 K and below. Under these low-temperature operating conditions, the leakage current of the eDRAM memory cell storage nodes is significantly reduced, and the data retention time is extended. Therefore, a multi-level cache system for the processor can be constructed using a heterogeneous eDRAM cache architecture based on cache demand awareness.

[0071] In this embodiment, the cache management controller configures different types of eDRAM memory units according to the access frequency, access latency requirements, reliability requirements, capacity requirements, and area efficiency requirements of each cache level. The L1 cache, located near the processor core, caches frequently accessed instructions and critical data, and has the highest requirements for access latency and data reliability; therefore, it is implemented using 4T gain unit eDRAM. The L2 cache mainly serves as a data buffer and cache expansion function between the L1 cache and the last-level cache, and needs to balance cache capacity, access performance, and area efficiency; therefore, it is implemented using 3T gain unit eDRAM. The L3 cache, as the last-level cache shared by multiple processor cores, mainly provides a large cache space; therefore, it is implemented using 2T gain unit eDRAM, and further configured with an ECC error detection and correction module to improve the data reliability of the shared cache. The mapping relationship between the above cache levels and different types of eDRAM memory units is as follows: Figure 2 As shown, various preferred eDRAM memory cell structures are as follows: Figure 3 As shown.

[0072] The refresh controller in this embodiment includes a refresh counter, a retention time manager, a refresh scheduler, a temperature monitoring unit, and an access frequency statistics unit. The retention time manager establishes a basic refresh cycle based on the data retention time of the corresponding eDRAM memory units of L1 cache, L2 cache, and L3 cache; the refresh counter records the current refresh status of each cache level; and the refresh scheduler generates a refresh strategy corresponding to each cache level based on the retention time management results and the system operating status.

[0073] Because the processor operates in a low-temperature environment for extended periods, the data retention time of the eDRAM memory cells is significantly longer than under normal temperature conditions. Therefore, the refresh controller enters a low-temperature refresh mode and employs different refresh strategies for different cache levels. Specifically, the L1 cache uses a low-frequency, high-reliability refresh mode, performing refresh only when the preset retention time is reached or reliability conditions are met, to reduce the impact of refresh operations on L1 cache access performance. The L2 cache uses a periodic refresh mode combined with a bank-level interleaved refresh mechanism, allowing different banks to alternate refresh operations, thereby reducing cache access conflicts during refresh. The L3 cache uses a block refresh mode, dividing the cache array into multiple refresh blocks, refreshing only the blocks that meet the refresh conditions each time, and using time-interleaving to schedule refresh between different refresh blocks, reducing peak refresh power consumption and refresh access congestion. Its refresh control method is as follows: Figure 4 As shown.

[0074] During processor operation, the temperature monitoring unit acquires the real-time operating temperature of the processor chip and cache array, the access frequency statistics unit continuously counts the number of cache block accesses, and the ECC module monitors the cache error rate in real time. This operational status information is then sent to the refresh scheduler. The refresh scheduler dynamically adjusts the refresh cycle of each cache level by considering the current operating temperature, cache access frequency, ECC error detection results, and the data retention time provided by the retention time manager. When a decrease in operating temperature or a low cache error rate is detected, the refresh scheduler appropriately extends the refresh cycle of each cache level; conversely, when an increase in operating temperature or a rise in cache error rate is detected, the refresh cycle of the corresponding cache level is appropriately shortened to ensure cache data reliability. Its dynamic adaptive refresh control process is as follows: Figure 5 As shown.

[0075] In this embodiment, a 4T gain unit eDRAM is used to construct the L1 cache, a 3T gain unit eDRAM is used to construct the L2 cache, and a 2T gain unit eDRAM is used to construct the L3 cache in the low-temperature high-performance processor. Combined with a hierarchical refresh control mechanism and a dynamic adaptive refresh mechanism, comprehensive optimization is achieved between cache capacity, access performance, data reliability, refresh power consumption and chip area, thereby improving the overall operating efficiency and system energy efficiency of the low-temperature high-performance processor.

[0076] Example 6 This embodiment is another specific application example based on embodiments 1 to 4, used to illustrate the specific implementation of the present invention in a low-temperature multi-core processor.

[0077] This embodiment applies to multi-core processor chips operating at low temperatures. For example... Figure 1As shown, the processor includes multiple processor cores, an on-chip interconnect network, multiple private L1 caches, multiple private or semi-shared L2 caches, a shared L3 cache, a cache management controller, and a refresh controller. The processor operates at a low temperature of 77 K and below, and each cache level is constructed using the cache demand-aware heterogeneous eDRAM cache architecture described in Example 1.

[0078] In this embodiment, each processor core is configured with a private L1 cache to cache frequently accessed data and instructions from the local core. This L1 cache is implemented using 4TB gain-unit eDRAM. Each processor core or multiple adjacent processor cores are configured with a private or semi-shared L2 cache to achieve a balance between cache capacity and access performance. This L2 cache is implemented using 3TB gain-unit eDRAM. Multiple processor cores share a common L3 cache, which is implemented using 2TB gain-unit eDRAM to create a large-capacity shared cache space, reducing the number of times the processor accesses external memory. The mapping relationship between the above cache levels and the corresponding eDRAM memory units is as follows: Figure 2 As shown, the preferred eDRAM memory cell structures are as follows: Figure 3 As shown.

[0079] Because the shared L3 cache has a large capacity, to further reduce the impact of refresh operations on shared memory access requests of multi-core processors, this embodiment divides the shared L3 cache into multiple storage banks, and each storage bank is further divided into multiple refresh blocks. The refresh controller configures the L3 cache with an ECC error detection and correction module, a block refresh control unit, and a refresh scheduler. The ECC module is responsible for detecting cache data errors and performing error correction; the refresh scheduler establishes refresh status based on the data retention time of each refresh block and manages the refresh process of each refresh block uniformly.

[0080] After the processor enters normal operation, the low temperature environment reduces the leakage current of the 2T gain unit eDRAM memory node and extends the data retention time, causing the refresh controller to enter a low-temperature refresh mode. For the L1 cache, a low-frequency, high-reliability refresh method is used to ensure the reliability of cache access near the core. For the L2 cache, a periodic refresh method is used, with the refresh cycle dynamically adjusted based on cache access frequency statistics. For the L3 cache, a block refresh method is used, with the refresh scheduler interleaving refreshes of different banks and refresh blocks according to a preset refresh order. This ensures that refresh operations between different banks are executed at off-peak times, avoiding a decrease in shared cache access bandwidth caused by simultaneous refreshes of multiple banks. The refresh control process is as follows: Figure 4 As shown.

[0081] During processor operation, the temperature monitoring unit continuously acquires the operating temperature of the processor chip and cache array, the access frequency statistics unit calculates the access frequency of each cache block in real time, the ECC module continuously monitors the cache error rate, and the refresh scheduler dynamically adjusts the refresh cycle of each cache level based on the above information. When the processor operates stably in a low-temperature environment and the cache error rate remains low, the refresh scheduler appropriately extends the refresh cycle of the L2 and L3 caches to further reduce refresh power consumption. When an increase in the operating temperature or cache error rate of a certain cache region is detected, the refresh cycle of the corresponding cache region is shortened, and the refresh frequency is increased to ensure the reliability of cached data. Its dynamic adaptive refresh control process is as follows: Figure 5 As shown.

[0082] In this embodiment, multiple processor cores can share a large-capacity L3 cache built from high-density 2T gain unit eDRAM. At the same time, a high-reliability L1 cache is built from 4T gain unit eDRAM, and a balanced L2 cache is built from 3T gain unit eDRAM. With the help of a hierarchical refresh control mechanism and a dynamic adaptive refresh control mechanism, the shared cache capacity and cache hit rate are effectively improved, the number of times the processor accesses external memory is reduced, refresh power consumption and refresh access conflicts are reduced, and the overall operating performance, cache access efficiency and system energy efficiency of the low-temperature multi-core processor are improved.

[0083] Example 7 This invention also provides an eDRAM cache control method for low-temperature processors, which is applied to the eDRAM multi-level cache system for low-temperature processors described in any one of embodiments 1 to 6. This method combines a cache demand-aware heterogeneous eDRAM cache architecture, a hierarchical refresh control mechanism, and a dynamic adaptive refresh mechanism to achieve configuration management and refresh control of each level of cache in low-temperature environments. This reduces refresh power consumption and improves the overall operating efficiency of the cache system while ensuring cache access performance and data reliability.

[0084] like Figure 6 As shown, the eDRAM cache control method includes the following steps.

[0085] Step S1: Obtain cache requirement information for each cache level of the processor.

[0086] Specifically, the cache management controller obtains the performance requirement information corresponding to each cache level of the processor. The cache requirement information includes parameters such as reliability requirements, access frequency, capacity requirements, access latency requirements, and area efficiency requirements. Based on the performance targets of different cache levels, the controller establishes corresponding cache requirement information to provide a basis for the subsequent configuration of eDRAM memory units.

[0087] Step S2: Configure the appropriate eDRAM storage unit for the corresponding cache level according to the cache requirement information of each cache level.

[0088] Based on the cache requirement information obtained in step S1, the cache management controller matches the performance characteristics of different types of eDRAM memory cells and selects the corresponding eDRAM memory cell type for each cache level. Specifically, high-speed, high-reliability cache regions are configured with high-speed, high-reliability eDRAM memory cells; balanced cache regions are configured with eDRAM memory cells that balance access performance and area efficiency; and large-capacity cache regions are configured with high-density eDRAM memory cells. In a preferred embodiment, the L1 cache is implemented using 4T gain unit eDRAM, the L2 cache uses 3T gain unit eDRAM, and the L3 cache uses 2T gain unit eDRAM.

[0089] Step S3: Obtain the data retention time of the eDRAM storage unit corresponding to each cache level, and generate the basic refresh cycle of the corresponding cache level based on the data retention time.

[0090] The retention time manager establishes retention time parameters based on the data retention capability of the eDRAM memory cells used in each cache level, and calculates the basic refresh cycle for each cache level based on the corresponding retention time. Since different types of eDRAM memory cells have different data retention times, different cache levels correspond to different basic refresh cycles, providing basic parameters for subsequent dynamic refresh control.

[0091] Step S4: Obtain processor running status information and dynamically adjust the refresh cycle of the corresponding cache level according to the processor running status.

[0092] The processor operating status information includes processor operating temperature, cache access frequency, cache error detection results, and data retention time prediction results. The refresh controller integrates the above operating status information and dynamically adjusts the basic refresh cycle generated in step S3 to adapt the refresh cycle to the actual operating state of the processor.

[0093] Preferably, dynamically adjusting the refresh cycle based on the processor's operating state includes the following process: The temperature monitoring unit acquires the operating temperature of the processor chip or cache array in real time. When the operating temperature is detected to be decreasing, the refresh controller appropriately extends the refresh cycle of the corresponding cache level because the data retention time of the eDRAM storage unit is extended. When the operating temperature is detected to be increasing, the refresh controller shortens the refresh cycle of the corresponding cache level to ensure the reliability of cached data.

[0094] The access frequency statistics unit continuously monitors the access frequency of cache blocks and adjusts the refresh strategy based on the access frequency. When the access frequency of a cache block is high, the refresh controller reduces the additional refresh frequency due to frequent updates of cached data; when the access frequency of a cache block is low or it has not been accessed for a long time, the refresh is performed according to the corresponding data retention time to ensure that the cached data remains reliable in the long term.

[0095] The ECC error detection module continuously monitors the data error rate of each cache level. When the error rate of a certain cache region is detected to be higher than a preset threshold, the refresh controller increases the refresh frequency of the corresponding cache region and shortens the refresh cycle; when the error rate of a cache region is detected to remain at a low level, the refresh cycle of the corresponding cache region is appropriately extended to further reduce refresh power consumption.

[0096] The retention time manager can also predict the data retention time of each cache level based on the current operating temperature, eDRAM memory cell type and historical operating status, and further adjust the refresh cycle based on the prediction results to improve the accuracy of refresh control.

[0097] Step S5: Perform a refresh operation for the corresponding cache level according to the adjusted refresh cycle.

[0098] The refresh scheduler executes corresponding refresh strategies for different cache levels based on the refresh cycle generated in step S4. Specifically, the L1 cache uses a low-frequency, high-reliability refresh method; the L2 cache uses a periodic refresh method combined with a Bank-level interleaved refresh strategy; and the L3 cache uses a block refresh method, performing time-interleaved refresh on different Banks and refresh blocks according to a preset scheduling order to reduce access conflicts and peak refresh power consumption during the refresh period.

[0099] In a preferred embodiment, when the processor operates at a low temperature of 77 K or below, the refresh controller enters a low-temperature refresh mode. Because the leakage current of the eDRAM storage nodes decreases and the data retention time is extended in a low-temperature environment, the refresh controller extends the corresponding refresh cycle for each cache level based on the differences in data retention time between the 4T, 3T, and 2T gain units used in the L1, L2, and L3 caches, respectively. This is combined with a tiered refresh control mechanism to perform refresh operations, thereby further reducing cache refresh power consumption, minimizing refresh access conflicts, and improving the overall energy efficiency of the cache system.

[0100] The method described in this embodiment achieves intelligent refresh management of the low-temperature processor cache system by combining cache demand-aware cache configuration, data retention time management for different types of eDRAM memory cells, hierarchical refresh control, and dynamic adaptive refresh control. By dynamically adjusting the refresh strategy according to the characteristics of the cache hierarchy and the real-time operating status of the processor, it can fully leverage the advantages of long data retention time and high storage density of eDRAM memory cells in low-temperature environments. While ensuring the reliability of cached data, it effectively reduces the number of refreshes, refresh power consumption, and cache access conflicts, thereby improving the overall operating performance of the low-temperature processor.

[0101] It should be noted that the specific execution process of each step and the implementation of related modules in the above method embodiments have been described in detail in embodiments 1 to 6. Each step can be combined, adjusted or appropriately omitted according to actual application needs. Without departing from the technical concept of the present invention, all steps should fall within the protection scope of the present invention.

[0102] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. An eDRAM multi-level cache system for low-temperature processors, characterized in that, include: The processor, the L1 cache, the L2 cache and the L3 cache connected to the processor core, the cache management controller, and the refresh controller; wherein: The L1 cache, L2 cache, and L3 cache are all constructed using eDRAM memory cells; The cache management controller is used to configure the appropriate eDRAM memory cell type for the corresponding cache level according to the reliability requirements, access frequency, capacity requirements, access latency requirements and area efficiency requirements of different cache levels. The refresh controller is used to perform differentiated refresh control for different cache levels based on the data retention time of the eDRAM storage unit; The processor operates in a low-temperature environment, which extends the data retention time of the eDRAM storage cells, thereby reducing the refresh frequency and refresh power consumption.

2. The system according to claim 1, characterized in that, The cache management controller matches various eDRAM memory cells according to the reliability requirements, access frequency, capacity requirements, access latency requirements, and area efficiency requirements corresponding to the cache level, and determines the type of eDRAM memory cell used for each cache level based on the matching results.

3. The system according to claim 2, characterized in that, The L1 cache uses high-speed, high-reliability eDRAM memory cells, the L2 cache uses eDRAM memory cells that balance access performance and area efficiency, and the L3 cache uses high-density eDRAM memory cells.

4. The system according to claim 3, characterized in that, The high-speed, high-reliability eDRAM memory cell is a 4T gain unit eDRAM, the eDRAM memory cell that balances access performance and area efficiency is a 3T gain unit eDRAM, and the high-density eDRAM memory cell is a 2T gain unit eDRAM or a 1T1C eDRAM.

5. The system according to claim 1, characterized in that, The refresh controller includes a refresh scheduler, a refresh counter, a retention time manager, and a temperature monitoring unit; The refresh scheduler generates the refresh cycle for each cache level based on the data retention time of the corresponding eDRAM storage unit.

6. The system according to claim 5, characterized in that, The refresh controller employs a tiered refresh strategy, including: L1 cache uses a low-frequency refresh method; L2 cache uses a periodic refresh method; The L3 cache uses a block-interleaved refresh method.

7. The system according to claim 6, characterized in that, The refresh controller dynamically adjusts the refresh cycle of the corresponding cache level based on the operating temperature, cache access frequency, and error detection results obtained by the temperature monitoring unit.

8. The system according to claim 7, characterized in that, When the processor operates at a low temperature of 77 K or below, the refresh controller extends the refresh cycle of the corresponding cache level according to the difference in data retention time of the eDRAM storage cells used in each cache level.

9. A method for controlling eDRAM cache for low-temperature processors, applied to the eDRAM multi-level cache system according to any one of claims 1 to 8, characterized in that, include: Obtain cache requirement information for each cache level of the processor; Based on the cache requirement information of each cache level, configure the appropriate eDRAM storage unit for the corresponding cache level; Obtain the data retention time of the eDRAM memory unit corresponding to each cache level, and generate the basic refresh cycle of the corresponding cache level based on the data retention time; The processor operating temperature, cache access frequency, and error detection results are obtained, and the refresh cycle of the corresponding cache level is dynamically adjusted based on the operating temperature, cache access frequency, and error detection results. Perform refresh operations for the corresponding cache level based on the adjusted refresh cycle.

10. The method according to claim 9, characterized in that, The refresh cycle of the corresponding cache level is dynamically adjusted based on the operating temperature, cache access frequency, and error detection results, including: Extend the refresh cycle when the operating temperature decreases, reduce the additional refresh frequency when the cache access frequency increases, and shorten the refresh cycle of the corresponding cache level when error detection results indicate an increase in the error rate.

Images