Multi-pass page table walker and method of operation

Abstract

The embodiment of the present disclosure provides a multi-channel page table walker and a working method, and belongs to the technical field of data processing. Specifically, the embodiment comprises: a multi-level page directory entry cache module, which is used for simultaneously querying each level of cache and adopting a high-level hit priority strategy to skip the cached page table level; a crossbar distribution module, which is used for distributing the traversal request to a plurality of table traversal units according to a two-level scheduling strategy of idle priority and rotation pointer; a plurality of table traversal units, each unit internally comprising a multi-level pipeline for alternately arranging the permission check level and the data verification level of each level of page table traversal; and a missing buffer, which is used for decoupling the calculation logic of the table traversal unit from the memory access delay through a plurality of buffer entries. Through the scheme of the present disclosure, the page table traversal performance in the TLB missing scenario is significantly improved through the optimization of four dimensions of multi-channel parallel processing, multi-level cache acceleration, fine pipeline and intelligent scheduling.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and in particular to a multi-channel page table traverser and its working method. Background Technology

[0002] Currently, the SV39 virtual address mode is a widely adopted address translation scheme in the RISC-V architecture. SV39 uses a 39-bit virtual address space and implements the mapping from virtual addresses to physical addresses through a three-level page table structure.

[0003] The virtual address consists of three segments of virtual page numbers VPN[2], VPN[1], and VPN[0] (each 9 bits) and a 12-bit page offset, supporting a total virtual address space of 512GB. Each level of Page Directory Entry (PDE) or Page Table Entry (PTE) is 64 bits wide and includes control flags such as validity bit (V), read / write / execute permission bit (R / W / X), user mode bit (U), global bit (G), access bit (A), dirty bit (D), and physical page number (PPN). SV39 supports three page sizes: 4KB standard page, 2MB megapage, and 1GB gigapage. Each page table traversal requires searching through three levels of page tables sequentially. Each search requires accessing main memory to read the page table data. Therefore, a complete page table traversal requires a maximum of three memory accesses. In a typical DDR4 main memory system, each access latency is approximately 50-100 clock cycles. Thus, page table traversal can generate a latency of hundreds of cycles, significantly impacting processor performance.

[0004] It is evident that there is an urgent need for a multi-channel page table traverser that can improve page table traversal performance in TLB missing scenarios, reduce average page table traversal latency, and improve the overall operating efficiency of the processor. Summary of the Invention

[0005] In view of this, the present disclosure provides a multi-channel page table traverser and its working method, which at least partially solves some of the problems existing in the prior art.

[0006] In a first aspect, embodiments of this disclosure provide a multi-channel page table traverser, including: The multi-level page directory entry caching module is configured to store at least two levels of page directory entry data and respond to the received page table traversal request by querying the cache at each level simultaneously using the virtual page number. When a higher-level cache hits, the hit results of the lower-level cache are masked to skip the cached page table level. The cross switch distribution module is a pure combinational logic device configured to distribute the traversal requests output by the multi-level page directory entry cache module to one of multiple table traversal units according to a two-level scheduling strategy of idle priority and round-robin pointer. When all table traversal units are unable to receive new requests, the transmission of upstream requests is suspended by a backpressure signal. Multiple table traversal units, each containing a multi-level pipeline, are used to break down the traversal process of each level of page table into alternating permission check and data verification levels according to the target multi-level page table structure. The permission check level is used to generate physical addresses and perform physical memory protection permission verification, while the data verification level is used to verify the validity of the returned page table data and determine whether it is a leaf table entry. The missing buffer, containing multiple buffer entries, is used to decouple the computation logic of the table traversal unit from memory access latency. The missing buffer is configured to write the request to a free entry and send a memory access request to the storage unit after the permission check passes, and to match the returned data with the corresponding entry and return it to the corresponding table traversal unit after the storage unit returns the data.

[0007] According to a specific implementation of an embodiment of this disclosure, the multi-level page directory entry caching module includes two levels of caching, which are used to cache first-level and second-level page directory entry data, respectively. The cache module does not store the address space identifier and page table base address fields, and implicitly assumes that the current page table base address is the root base address of the page table structure by clearing all caches when the page table base address register value changes. Each level of cache is configured with an independent pseudo least recently used replacement algorithm.

[0008] According to a specific implementation of an embodiment of this disclosure, the two-level scheduling strategy of the cross switch distribution module is as follows: The first-level scheduler prioritizes allocating requests to table traversal units that are in an idle state based on the idle status signal of each table traversal unit. The second-level scheduler starts a round-robin pointer when all table traversal units are busy, and begins a cyclic scan starting from the next channel after the last selected channel, allocating the request to the first unmasked channel.

[0009] According to a specific implementation of this disclosure, the method by which the permission check level generates physical addresses during each level of page table traversal is as follows: For the first-level page table, it is generated by concatenating the high-order segment of the physical page number and the virtual page number in the page table base address register; For subsequent page tables at each level, they are generated by concatenating the physical page number and the corresponding virtual page number field from the page table data returned by the previous level.

[0010] According to a specific implementation of this disclosure, the validity check performed by the data verification level on the received page table data includes: The system checks whether the valid bit is set, whether the permission bit combination is valid, and whether the big page address is aligned. Furthermore, the data verification level determines whether the current table entry is a leaf table entry by judging whether at least one of the read, write, and execute permission bits is set.

[0011] According to a specific implementation of this disclosure, each stage of the pipeline within each table traversal unit is configured with advancement conditions and waiting mechanisms, including: When multiple requests compete for arbitration resources or buffer writes are not authorized, the corresponding pipeline level is configured to remain in a valid state to wait for authorization. When the pipeline is waiting for data to return from memory, it is configured to enter a paused state and automatically resumes progress after the data is returned.

[0012] According to one specific implementation of this disclosure, the missing buffer sends a memory access request to the storage unit through an arbitrator, and the arbitrator adopts a round-robin priority arbitration strategy.

[0013] According to a specific implementation of this disclosure, a backfill arbitrator is further included, which is used to write back the mapping information obtained from the leaf table entry to the first-level instruction translation backup buffer, the first-level data translation backup buffer, and the second-level translation backup buffer after the data verification level detects the leaf table entry, using a round-robin priority strategy.

[0014] According to a specific implementation of an embodiment of this disclosure, the page table traverser is further configured to detect page errors during traversal, the page errors including replayable page errors and non-replayable page errors; wherein, the replayable page errors include: page not loaded, access bit error, and dirty bit error; the non-replayable page errors include: permission violation, privilege level violation, big page address misalignment, illegal page table entry format, and abnormal permission bits of intermediate page table entries.

[0015] Secondly, embodiments of this disclosure provide a method for operating a multi-channel page table traverser, applied to a multi-channel page table traverser, including: Step 1: Receive the page table traversal request from the translation back buffer and obtain the virtual page number, request type and request identifier from the request; Step 2: Use virtual page numbers to query multi-level page directory entry caches simultaneously, and determine the starting level of page table traversal based on the hit results; Step 3: Using the crossbar switch distribution module, the request is distributed to a selected table traversal unit according to a two-level scheduling strategy of idle priority and round-robin pointer. Step 4: In the current level of permission check of the table traversal unit, generate a physical address and send it to the physical memory protection module for permission verification; Step 5: After the permission verification is successful, the request is written into the free entry of the missing buffer, and the missing buffer sends a memory access request to the storage unit. Step 6: Receive the page table data returned by the storage unit, and in the data verification level of the table traversal unit, perform validity verification on the page table data and judgment on the leaf table entries; Step 7: If the current entry is a leaf entry, the mapping information is written to the translation backup buffers at each level through the backfill arbiter to complete the page table traversal; if it is not a leaf entry, return to step 4 to traverse the next level page table.

[0016] The multi-channel page table traverser in this embodiment includes: a multi-level page directory entry cache module configured to store at least two levels of page directory entry data, and in response to a received page table traversal request, simultaneously querying each level of cache using virtual page numbers, wherein when a higher-level cache hit occurs, the hit result of a lower-level cache is masked to skip the cached page table level; a crossbar switch distribution module, a pure combinational logic device, configured to distribute the traversal request output by the multi-level page directory entry cache module to one of multiple table traversal units according to a two-level scheduling strategy of idle priority and round-robin pointer, and when all table traversal units cannot receive new requests, suspending the transmission of upstream requests through a backpressure signal; and multiple table traversal units, each containing... The system includes a multi-stage pipeline. Following the target multi-level page table structure, the pipeline breaks down the traversal process of each page table level into alternating permission check and data verification levels. The permission check level generates physical addresses and performs physical memory protection permission verification, while the data verification level verifies the validity of the returned page table data and determines whether it is a leaf table entry. A missing buffer, containing multiple buffer entries, decouples the computational logic of the table traversal unit from memory access latency. The missing buffer is configured to write the request to a free entry and issue a memory access request to the storage unit after the permission check passes, and to match the returned data with the corresponding entry and return it to the corresponding table traversal unit after the storage unit returns data.

[0017] The beneficial effects of the embodiments of this disclosure are as follows: Through the solution of this disclosure, by optimizing four dimensions such as multi-channel parallel processing, multi-level caching acceleration, refined pipeline design and intelligent request scheduling, the page table traversal performance in the TLB missing scenario is significantly improved, the average page table traversal latency is reduced, and the overall operating efficiency of the processor is improved. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a multi-channel page table traverser provided in an embodiment of the present disclosure; Figure 2 An overall architecture block diagram of a multi-channel page table traverser provided in this disclosure embodiment; Figure 3 This is a schematic diagram of a PLRU tree-structured replacement algorithm provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of the scheduling logic of a 1-to-4 Xbar crossbar switch distribution module provided in this embodiment of the disclosure; Figure 5 A schematic diagram of a six-stage pipeline structure inside a single TWU provided in this embodiment of the disclosure; Figure 6 A schematic diagram of the interaction structure between a missing buffer (MBUF) and a storage unit provided in an embodiment of this disclosure; Figure 7 This is a complete workflow diagram of normal backfilling of a 1G large page provided in an embodiment of this disclosure.

[0020] Summary of attached image labels: Multi-channel page table traverser 100, multi-level page directory entry cache module 110, cross switch dispatch module 120, table traversal unit 130, and missing buffer 140. Detailed Implementation

[0021] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0022] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0025] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0026] This disclosure provides a multi-channel page table traverser, which can be applied to the page table traversal process in a processor during data processing scenarios.

[0027] The current implementation scheme is the single-channel PTW design used in the open-source RISC-V processor C910. The main features of this design are as follows: (1) A single page table traversal channel is used and it is a serial working mode, which can only process one TLB missing request at a time. When a new request arrives, it must wait for the current request to complete the entire traversal process before it can be received and the next request can be processed. Multiple missing requests can only be queued one by one.

[0028] (2) The pipeline structure is relatively simplified. In each page table traversal, physical address generation, permission checking and data verification are concentrated in a few pipeline stages, resulting in a long timing path for a single pipeline, which makes it difficult to work stably at high frequencies.

[0029] (3) It does not have a dedicated page directory entry caching mechanism. Each page table traversal requires accessing the main memory level by level starting from the first-level page table. It cannot reuse the page directory entry data that has been searched, resulting in a large amount of redundant memory access overhead for scenarios that continuously access the same virtual address range.

[0030] The existing C910 single-channel PTW design has the following main drawbacks: (1) Throughput bottleneck: In single-channel serial processing mode, when multiple TLB missing requests are generated at the same time, subsequent requests must queue up and wait for the previous requests to complete, resulting in a large number of requests accumulating and significant page table traversal delay.

[0031] (2) Memory access redundancy: The lack of a page directory entry (PDE) caching mechanism means that even if multiple consecutive missing requests access adjacent virtual address spaces (sharing high-level page directory entries), each time it is still necessary to traverse from the first-level page table again, resulting in a large number of unnecessary memory accesses.

[0032] (3) Low pipeline utilization: The pipeline advancement mechanism is relatively simple. When waiting for memory data to return, the entire pipeline stops, and hardware resources are idle.

[0033] (4) Inflexible request scheduling: It lacks intelligent request distribution strategies and cannot dynamically allocate processing resources according to the busy status of the processing channel.

[0034] The purpose of this invention is to provide a high-performance multi-channel page table traverser (PTW) architecture for RISC-V processors. Through optimizations in four dimensions—multi-channel parallel processing, multi-level cache acceleration, refined pipeline design, and intelligent request scheduling—it significantly improves page table traversal performance in TLB-miss scenarios, reduces average page table traversal latency, and enhances the overall operating efficiency of the processor.

[0035] See Figure 1 This is a schematic diagram of the structure of a multi-channel page table traverser provided in an embodiment of this disclosure. Figure 1 As shown, the multi-channel page table traverser mainly includes: The multi-level page directory entry caching module 110 is configured to store at least two levels of page directory entry data and, in response to a received page table traversal request, simultaneously query each level of cache using virtual page numbers. When a higher-level cache hits, the hit results of lower-level caches are masked to skip the cached page table level. The cross switch distribution module 120 is a pure combinational logic device, configured to distribute the traversal request output by the multi-level page directory entry cache module 110 to one of the multiple table traversal units 130 according to a two-level scheduling strategy of idle priority and round-robin pointer, and to suspend the transmission of upstream requests through a back pressure signal when all table traversal units 130 are unable to receive new requests. Multiple table traversal units 130, each containing a multi-level pipeline, the multi-level pipeline, according to the target multi-level page table structure, divides the traversal process of each level of page table into alternating permission check level and data verification level. The permission check level is used to generate physical addresses and perform physical memory protection permission verification, and the data verification level is used to verify the validity of the returned page table data and determine whether it is a leaf table entry. The missing buffer 140 contains multiple buffer entries and is used to decouple the calculation logic of the table traversal unit 130 from the memory access latency. The missing buffer 140 is configured to write the request into the free entry and send a memory access request to the storage unit after the permission check is passed, and to return the returned data to the corresponding table traversal unit 130 after the storage unit returns the data and matches it with the corresponding entry.

[0036] The multi-channel page table walker 100 of this disclosure can be applied to the Memory Management Unit (MMU) in a high-performance processor chip based on the RISC-V instruction set architecture. In modern processors, the MMU is responsible for translating virtual addresses into physical addresses to support the operating system's virtual memory management. When a Translation Lookaside Buffer (TLB) misses, a Page Table Walker (PTW) is needed to access the multi-level page table structure in main memory to obtain the mapping relationship between virtual and physical addresses. The performance of the PTW directly affects the overall performance of the processor in memory-intensive applications (such as virtualization, big data processing, and artificial intelligence training).

[0037] In practice, the multi-channel page table traverser 100 is deployed in the Memory Management Unit (MMU) of the RISC-V processor, located between the L2 TLB (Level 2 Translation Lookaside Buffer) and the LSU (Load Memory Unit). When an L2 TLB is missing, a traversal request containing the virtual page number, request type, and request identifier is sent to the page table traverser PTW.

[0038] like Figure 2 As shown, the overall architecture of the page table traverser PTW includes the following core components from top to bottom: PDE Cache (Multi-level Page Directory Entry Cache), 1-to-4 Xbar (Cross Switch Distribution Module 120), 4 TWUs (Table Traversal Units 130), PMP Arbiter (Physical Memory Protection Arbiter), MBUF Arbiter (Missing Buffer 140 Arbiter), PTW MBUF (Page Table Traversal Missing Buffer 140), and Backfill Arbiter.

[0039] The request from L2 TLB missing buffer 140 first goes through the PDE Cache for lookup. Based on the cache hit status, the starting level for traversal is determined, and then the request is distributed to an idle TWU for processing via Xbar. During the traversal, the TWU initiates a memory access request to the LSU via MBUF, and finally writes the obtained page table mapping information back to each level of TLB through the backfill arbitrator.

[0040] Specifically, the structure and processing flow of the multi-level page directory entry caching module 110PDE are as follows: The PDE Cache internally employs a two-level cache, caching page directory entries for the first and second levels respectively. Each level of cache is configured with multiple cache entries (typically 8-16 entries), with each entry storing a 64-bit page directory entry and its corresponding tag. Each level of cache contains three functional units: tag lookup, tag comparison, and data selection, as well as a separate pseudo-least recently used (PLRU) replacement algorithm module.

[0041] When a TLB miss request arrives, the PTW module simultaneously queries both levels of the PDE cache using the corresponding field in the virtual page number. The query employs a high-priority strategy: if a level 2 cache hit occurs, the level 1 hit signal is masked, and only the data in the level 2 cache is returned. This skips the cached first two levels of page tables and directly traverses from the third level, reducing the number of memory accesses from three to one. If only the level 1 cache hits, the data in the level 1 cache is returned, and traversal begins from the second level, reducing the number of memory accesses by one.

[0042] The PDE Cache does not store the Address Space Identifier (ASID) and page table base address (satp.ppn) fields. When the value of the system page table base address register (satp register) changes, all cache contents are cleared. This design implicitly assumes that the current page table base address is the root base address of the page table structure, simplifying hardware comparison logic while ensuring correctness. Each cache level is configured with an independent PLRU replacement algorithm for cache entry eviction.

[0043] like Figure 3As shown, the pseudo-LRU replacement algorithm is implemented using a binary tree structure. Taking 8 cached entries as an example, a complete binary tree with 7 internal decision nodes and 8 leaf nodes is constructed. Each decision node stores a 1-bit direction flag, requiring a total of 7 bits of storage space. When a cache hit occurs (i.e., an entry is accessed), the flags of all decision nodes on the path from the root node to the corresponding leaf node of that entry are flipped to the direction away from that entry, making subsequent replacement operations tend to select the least recently used entry. When an entry needs to be replaced, starting from the root node, the algorithm traverses downwards level by level along the direction indicated by the current flag of each decision node, and the reached leaf node is the cached entry to be replaced. This algorithm approximates the effect of the LRU replacement strategy with extremely low hardware overhead (requiring only N-1 bits of storage and simple tree traversal logic).

[0044] The structure and processing flow of the cross switch distribution module 120 are as follows: like Figure 4 As shown, the 1-to-4 Xbar is a request dispatcher implemented with pure combinational logic, distributing requests from the PDE Cache to one of the four TWUs. The Xbar has no register-level latency, and distribution is completed within a single clock cycle. The distribution algorithm employs a two-level scheduling strategy: The first level prioritizes idle TWUs: it checks the idle status signals TWU_idle[3:0] of each TWU and assigns the request to an idle TWU. When there are multiple idle TWUs, it selects the idle TWU with the smallest number.

[0045] The second level is the round-robin pointer selection: when all TWUs are busy (TWU_idle[3:0] is all zero), the round-robin pointer TWU_req_point[3:0] starts from the next TWU after the last selected position and finds the first TWU that is not masked (without mask signal) for allocation.

[0046] When all four TWUs show a mask signal (meaning that all channels are unable to receive new requests), the PTW pulls the ready signal back to the L2TLB low, notifying the upstream to suspend sending new requests, thus achieving backpressure control.

[0047] The structure and processing flow of the table traversal unit 130TWU are as follows: like Figure 5 As shown, the PTW module contains four independent TWUs, each processing page table traversal requests in parallel. Each TWU contains a six-level pipeline, with each traversal level divided into two pipeline levels according to the SV39 three-level page table structure: permission check level (PMP level) and data verification level (CHK level), for a total of six pipeline levels.

[0048] Permission check level: In each level of page table traversal, the physical address to be queried is generated based on the current level and the page table entry data of the parent level. The physical address of the first level page table is generated by concatenating the physical page number (satp.ppn) in the page table base address register (satp register) with the high-order segment of the virtual page number (VPN[2]); the physical addresses of subsequent levels of page tables are generated by concatenating the physical page number in the page table data returned by the parent level with the corresponding virtual page number field. The generated physical address is sent to the PMP (Physical Memory Protection) module for verification of read, write, and execute permissions. When the permission check passes, a buffer write request is issued.

[0049] Data Validation Level: Receives page table data returned from storage units or cache and performs validity checks on it. Checks include: whether the validity bit (V bit) is set, whether the permission bit combination (R / W / X) is valid, and whether the large page address is aligned. It also determines whether the current entry is a leaf entry (a leaf entry is defined as at least one of the R, W, or X bits being 1). If it is a leaf entry, a backfill request is issued to complete the page table traversal; if it is not a leaf entry, the data is passed to the next level of the permission check pipeline to continue traversal.

[0050] Each stage of the pipeline is designed with precise advance conditions and waiting mechanisms. When multiple requests compete for arbitration resources (such as PMP arbitration or MBUF arbitration), the corresponding pipeline stage remains in an active state, waiting for authorization to avoid data loss. The pipeline pauses while waiting for memory data to return, and automatically resumes execution after the data returns.

[0051] The interaction between the missing buffer 140 (MBUF) and memory is as follows: like Figure 6 As shown, the PTW MBUF has 8 buffer entries that work in conjunction with the MBUF arbitrator. Each buffer entry records information such as the source TWU number, traversal level, and target physical address. When the permission check level of a TWU passes PMP verification, the request is written into the MBUF's free entry, and the MBUF sends a memory access request to the LSU through the arbitrator. The arbitrator uses round-robin arbitration to ensure that memory access requests from each TWU have a fair chance to be sent.

[0052] After the LSU returns page table data, it matches the request identifier information with the corresponding MBUF entry, releases the entry, and returns the data to the corresponding TWU for further pipeline processing. When all eight MBUF entries are occupied, new write requests will be blocked, and the corresponding TWU pipeline stage will enter a waiting state until an entry is released. This design decouples the TWU's computation logic (address generation, permission checking, data verification) from storage access latency, allowing other pipeline stages or other TWUs to continue running while the TWU waits for a memory stage to return, thus improving hardware resource utilization.

[0053] Once the data verification level detects a leaf table entry, it sends backfill data to each level of TLB (L1 ITLB, L1 DTLB, L2 TLB) via the backfill arbitrator to complete the address mapping update. The backfill arbitrator also employs a round-robin priority strategy to prevent a single TWU from occupying the backfill channel for an extended period. The backfill data includes the virtual page number, physical page number, page attributes (cache attributes, shared attributes, permission bits, etc.), and page size information (4KB / 2MB / 1GB).

[0054] During the traversal, the PTW is also responsible for detecting various page fault conditions, including: (1) Replayable Page Faults: Page not loaded (PTE valid bit is 0), Accessed bit error (Accessed bit is 0), Dirty bit error (Dirty bit is 0 and it is a write operation). These errors can be handled by the operating system and the memory access instruction can be re-executed.

[0055] (2) Non-Replayable Page Faults: Permission Fault, Privilege Violation, Misaligned Big Page Address, Illegal Page Table Entry Format, Abnormal Permission Bits of Intermediate Page Table Entries, etc.

[0056] The multi-channel page table traverser provided in this embodiment supports a parallel architecture design for multiple page table traversal requests by setting up multiple independent table traversal units (TWUs) and crossbar dispatchers (Xbars). It employs a two-level page directory entry cache, simultaneously querying and prioritizing higher-level cache hits to mask lower-level hits, thus skipping cached page table levels and reducing memory access frequency. A two-level request scheduling strategy with idle priority and round-robin pointers is used: the crossbar dispatcher prioritizes idle channels, while during busy periods, round-robin pointers distribute requests evenly, and a backpressure mechanism ensures system stability. A six-level pipeline design alternates between permission checks and data verification: each page table traversal level is divided into independent permission check and data verification levels, each with precise advancement conditions and waiting mechanisms. A decoupled design using a missing buffer (MBUF) decouples the computational logic of the table traversal units (TWUs) from memory access latency, improving hardware resource utilization.

[0057] Corresponding to the above embodiments, see [link to relevant documentation]. Figure 7 This disclosure also provides a method for operating a multi-channel page table traverser, including: Step 1: Receive the page table traversal request from the translation back buffer and obtain the virtual page number, request type and request identifier from the request; Step 2: Use virtual page numbers to query multi-level page directory entry caches simultaneously, and determine the starting level of page table traversal based on the hit results; Step 3: Using the crossbar switch distribution module, the request is distributed to a selected table traversal unit according to a two-level scheduling strategy of idle priority and round-robin pointer. Step 4: In the current level of permission check of the table traversal unit, generate a physical address and send it to the physical memory protection module for permission verification; Step 5: After the permission verification is successful, the request is written into the free entry of the missing buffer, and the missing buffer sends a memory access request to the storage unit. Step 6: Receive the page table data returned by the storage unit, and in the data verification level of the table traversal unit, perform validity verification on the page table data and judgment on the leaf table entries; Step 7: If the current entry is a leaf entry, the mapping information is written to the translation backup buffers at each level through the backfill arbiter to complete the page table traversal; if it is not a leaf entry, return to step 4 to traverse the next level page table.

[0058] For example, taking the normal backfilling process of a 1G large page (where the first level is the leaf table entry) as an example, the complete working timing of the multi-channel page table traverser is illustrated: Step S1: After the L2 TLB detects a missing page, it sends a traversal request to the PTW module. The request includes the virtual page number (VPN), the request type (read / write / execute), and the request ID.

[0059] Step S2: The PTW module uses virtual page numbers to query both levels of the PDE Cache simultaneously, and distributes requests to idle TWUs via 1-to-4 Xbars. It also determines the starting level for traversal based on cache hit rates.

[0060] Step S3: Request access to the first-level permission check pipeline of TWU. The physical address of the first-level page table is generated by concatenating satp.ppn and VPN[2], and this address is sent to the PMP module for permission verification. After successful verification, an MBUF write request is issued.

[0061] Step S4: The request is written into the free entry of MBUF, and at the same time, the MBUF arbitrator sends a memory read request to LSU.

[0062] Step S5: Wait for the LSU to return the memory data. After the LSU returns the data, it matches it with the corresponding MBUF entry and passes the data to the corresponding TWU.

[0063] Step S6: Data enters the first-level data validation pipeline of TWU, which checks the PTE validity and permission bit combination. Since it is a 1G large page, a set bit is detected in the R / W / X permission bits (leaf table entry), and it is determined to be a leaf table entry.

[0064] Step S7: Issue a backfill request and write the mapping information (the correspondence between VPN and PPN and page attributes) into the TLB at each level through the backfill arbiter. The page table traversal is completed.

[0065] Compared with the existing C910 single-channel PTW design, the present invention has the following advantages: (1) Multi-channel pipelined parallel processing capability: Four independent TWUs are set up, and each TWU adopts a pipelined design, which can receive a new traversal request every clock cycle. In contrast, the original C910 design only has one serial TWU, which can only receive the next request after the entire traversal process of the current request is completed. Therefore, the theoretical throughput of this invention is more than 4 times that of the original design - not only is the number of channels increased to 4, but the pipelined structure inside each channel also realizes the reception of requests cycle by cycle, fundamentally eliminating the serial waiting bottleneck and significantly reducing the request queuing delay in multi-TLB missing scenarios.

[0066] (2) Multi-level cache acceleration: Two-level PDE cache caches accessed page directory entries. By utilizing the spatial locality of page tables, one or two levels of memory access can be skipped when the cache is hit, reducing the worst case of three memory accesses to one.

[0067] (3) Refined pipeline design: Each level of page table traversal is split into two independent pipeline stages: permission check and data validation, avoiding the blocking propagation of a single-stage long pipeline. Each pipeline stage is designed with precise advancement conditions and waiting mechanisms to minimize performance loss when resource conflicts occur.

[0068] (4) Intelligent request scheduling: The two-level scheduling strategy of idle priority plus round-robin pointer maximizes the use of idle resources while ensuring load balance, and the back pressure signal mechanism ensures the stable operation of the system under high load.

[0069] (5) Decoupled buffer architecture: The 8-entry missing buffer (MBUF) can accommodate multiple pending requests at the same time, allowing TWU to continue processing other operations without waiting for memory to return, thus avoiding memory access bottlenecks.

[0070] It should be understood that the various parts of this disclosure can be implemented in hardware, software, firmware, or a combination thereof.

[0071] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A multi-channel page table traverser, deployed in the processor's memory management unit, characterized in that, include: The multi-level page directory entry caching module is configured to store at least two levels of page directory entry data and respond to the received page table traversal request by querying the cache at each level simultaneously using the virtual page number. When a higher-level cache hits, the hit results of the lower-level cache are masked to skip the cached page table level. The cross switch distribution module is a pure combinational logic device configured to distribute the traversal requests output by the multi-level page directory entry cache module to one of multiple table traversal units according to a two-level scheduling strategy of idle priority and round-robin pointer. When all table traversal units are unable to receive new requests, the transmission of upstream requests is suspended by a backpressure signal. Multiple table traversal units, each containing a multi-level pipeline, are used to break down the traversal process of each level of page table into alternating permission check and data verification levels according to the target multi-level page table structure. The permission check level is used to generate physical addresses and perform physical memory protection permission verification, while the data verification level is used to verify the validity of the returned page table data and determine whether it is a leaf table entry. The missing buffer, containing multiple buffer entries, is used to decouple the computation logic of the table traversal unit from memory access latency. The missing buffer is configured to write the request to a free entry and send a memory access request to the storage unit after the permission check passes, and to match the returned data with the corresponding entry and return it to the corresponding table traversal unit after the storage unit returns the data.

2. The multi-channel page table traverser according to claim 1, characterized in that, The multi-level page directory entry caching module includes two levels of caching, which are used to cache first-level and second-level page directory entry data, respectively. The cache module does not store the address space identifier and page table base address fields, and implicitly assumes that the current page table base address is the root base address of the page table structure by clearing all caches when the page table base address register value changes. Each level of cache is configured with an independent pseudo least recently used replacement algorithm.

3. The multi-channel page table traverser according to claim 1, characterized in that, The two-level scheduling strategy of the cross switch distribution module is as follows: The first-level scheduler prioritizes allocating requests to table traversal units that are in an idle state based on the idle status signal of each table traversal unit. The second-level scheduler starts a round-robin pointer when all table traversal units are busy, and begins a cyclic scan starting from the next channel after the last selected channel, allocating the request to the first unmasked channel.

4. The multi-channel page table traverser according to claim 1, characterized in that, The method by which the permission check level generates physical addresses during each page table traversal is as follows: For the first-level page table, it is generated by concatenating the high-order segment of the physical page number and the virtual page number in the page table base address register; For subsequent page tables at each level, they are generated by concatenating the physical page number and the corresponding virtual page number field from the page table data returned by the previous level.

5. The multi-channel page table traverser according to claim 1, characterized in that, The data validation level performs the following validity checks on the received page table data: The system checks whether the valid bit is set, whether the permission bit combination is valid, and whether the big page address is aligned. Furthermore, the data verification level determines whether the current table entry is a leaf table entry by judging whether at least one of the read, write, and execute permission bits is set.

6. The multi-channel page table traverser according to claim 1, characterized in that, Each stage of the pipeline within each table traversal unit is configured with advancement conditions and waiting mechanisms, including: When multiple requests compete for arbitration resources or buffer writes are not authorized, the corresponding pipeline level is configured to remain in a valid state to wait for authorization. When the pipeline is waiting for data to return from memory, it is configured to enter a paused state and automatically resumes progress after the data is returned.

7. The multi-channel page table traverser according to claim 1, characterized in that, The missing buffer sends a memory access request to the storage unit through an arbitrator, which adopts a round-robin priority arbitration strategy.

8. The multi-channel page table traverser according to claim 1, characterized in that, It also includes a backfill arbitrator, which, when the data verification level detects a leaf entry, uses a round-robin priority strategy to write back the mapping information obtained from the leaf entry to the first-level instruction translation backup buffer, the first-level data translation backup buffer, and the second-level translation backup buffer.

9. The multi-channel page table traverser according to claim 1, characterized in that, The page table traverser is also configured to detect page errors during traversal, including replayable page errors and non-replayable page errors; wherein, the replayable page errors include: page not loaded, access bit error, and dirty bit error; the non-replayable page errors include: permission violation, privilege level violation, big page address misalignment, illegal page table entry format, and abnormal permission bits of intermediate page table entries.

10. A method for operating a multi-channel page table traverser, applied to the multi-channel page table traverser according to any one of claims 1 to 9, characterized in that, The method includes: Step 1: Receive the page table traversal request from the translation back buffer and obtain the virtual page number, request type and request identifier from the request; Step 2: Use virtual page numbers to query multi-level page directory entries cache simultaneously, and determine the starting level of page table traversal based on the hit results; Step 3: Using the crossbar switch distribution module, the request is distributed to a selected table traversal unit according to the two-level scheduling strategy of idle priority and round-robin pointer. Step 4: In the current level of permission check of the table traversal unit, generate a physical address and send it to the physical memory protection module for permission verification; Step 5: After the permission verification is successful, the request is written into the free entry of the missing buffer, and the missing buffer sends a memory access request to the storage unit. Step 6: Receive the page table data returned by the storage unit, and in the data verification level of the table traversal unit, perform validity verification on the page table data and judgment on the leaf table entries; Step 7: If the current entry is a leaf entry, the mapping information is written to the translation backup buffers at each level through the backfill arbiter to complete the page table traversal; if it is not a leaf entry, return to step 4 to traverse the next level page table.

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