A broadband voltage current signal dynamic processing method and system

Abstract

The application discloses a kind of broadband voltage current signal dynamic processing method and system, overcome the data acquisition processing system in prior art cannot effectively realize the synchronism, real-time problem in the transmission and storage process of data, method includes: to broadband voltage current signal is pretreated, to the signal after pretreatment is carried out multi-channel high-speed synchronous sampling;Sampling data is pretreated, establishes the storage control logic between FPGA internal FIFO resource and memory, converts into AXI bus format request with burst read-write request;FPGA receives the sampling data after pretreatment and generates synchronization signal, triggers the SRIO of DSP, controls the transmission of sampling data after pretreatment to DSP;Sampling data is measured to broadband, to the measured data is carried out empirical mode decomposition and hilbert transform, identifies disturbance.The efficient capture of broadband oscillation phenomenon is realized, signal processing speed and stability are improved, and FIFO buffering mechanism is used to prevent data loss.

Description

Technical Field

[0001] This invention relates to the field of power systems and automation technology, and in particular to a method and system for dynamic processing of wideband voltage and current signals. Background Technology

[0002] Signal processing is widely used in power grids, especially in future smart grids. Wideband voltage / current signals, as important state variables characterizing transient fault information, make the research on sensing technologies and the application analysis of sensing data crucial for building smart grids. In many signal sampling systems, especially those dealing with low sampling rates and small data bandwidths, the acquired signals are typically sent directly to a host computer for storage and computation. However, this design is limited by the host computer's hard drive capacity, impacting effective storage space. For wideband voltage and current signals, the large sampling data bandwidth coupled with the relatively slow data transmission speed between the acquisition system and the host computer presents a challenge for real-time data transmission.

[0003] For example, the Chinese Patent Office published patent CN111679117A on September 18, 2020, which describes a wideband 35kV voltage measurement device and method, measures voltage using the principle of resistive voltage division. It features a wide sampling bandwidth, insulation between the primary and secondary sides, high measurement reliability and accuracy, and converts analog voltage signals into digital and optical voltage signals, allowing direct connection to a microcomputer and adapting to the automation and digitalization of power systems. Similarly, the acquired signals are directly sent to a host computer for storage and computation. However, as acquisition speed and resolution increase, storing, processing, and handling large volumes of sampled data becomes more complex. Therefore, a high-performance digital processing system is another key factor restricting the development of high-speed signal acquisition. Summary of the Invention

[0004] The purpose of this invention is to address the problem that existing data acquisition and processing systems cannot effectively achieve synchronization and real-time performance during data transmission and storage. It provides a method and system for dynamic processing of wideband voltage and current signals, achieving efficient capture of wideband oscillation phenomena, improving signal processing speed and stability, enabling rapid response in massive data acquisition and storage, and achieving efficient signal processing and data export. Simultaneously, a FIFO buffer mechanism is employed to prevent data loss, ultimately achieving seamless data transmission between the real-time processing system and external storage and the host computer, meeting the requirements of high bandwidth and real-time performance.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A method for dynamic processing of wideband voltage and current signals includes the following steps: The wideband voltage and current signals are preprocessed, and the preprocessed signals are then sampled synchronously at high speed through multiple channels. The sampled data is preprocessed, and the storage control logic between the FPGA's internal FIFO resources and memory is established to convert burst read and write requests into AXI bus format requests. After receiving the preprocessed sampled data, the FPGA generates a synchronization signal, which triggers the DSP's SRIO to control the transmission of the preprocessed sampled data to the DSP. Broadband measurements are performed on the sampled data, and empirical mode decomposition and Hilbert transform are applied to the measured data to identify disturbances.

[0006] This invention achieves efficient capture of wideband oscillation phenomena, improves signal processing speed and stability, enables rapid response in massive data acquisition and storage, and achieves efficient signal processing and data export. Simultaneously, a FIFO buffer mechanism is employed to prevent data loss, ultimately achieving seamless data transmission between the real-time processing system and external storage and the host computer, meeting the requirements of high bandwidth and real-time performance.

[0007] As a preferred approach, a data exchange network is generated through the mapping relationship between physical ports and virtual ports. After the sampled data is accessed, the corresponding routing switching algorithm is established by switching or updating numerous routing mapping exchange tables in the data exchange network, and the upper and lower layer communication links are reconstructed in real time to complete the dynamic pointing and interaction between data and analysis type virtual ports.

[0008] Preferably, the storage control logic includes, during data transmission, writing input FIFO data to external memory upon receiving a write request, and its state machine transitions include: S_WR_IDLE: This initial idle state is triggered when a low-level active reset signal is input to the state machine. It waits for a write data request to be received and then pulls the signal high to enter the next state S_WR_ACK. S_WR_ACK: If the write request is revoked, it enters the next state S_CHECK_WFIFO; S_CHECK_WFIFO: Detects the size of the input FIFO space. It determines whether to enable burst write operation by checking whether the amount of data used at the input FIFO read end meets the storage space size BURST_SIZE required for a burst write in the subsequent AXI bus protocol. S_WR_BURST: When a burst write completion flag is received, the system jumps sequentially to the S_WR_BURST_END state and then to the S_WR_END state to complete one data write operation.

[0009] Preferably, the storage control logic includes, during data transmission, upon receiving a read request, outputting a FIFO to read data from external memory, and its state machine transitions include: S_WR_IDLE: This initial idle state is triggered when a low-level active reset signal is input to the state machine. It waits for a read data request to be pulled high to enter the next state S_WR_ACK. S_WR_ACK: If the read request is withdrawn, it enters the next state S_CHECK_WFIFO; S_CHECK_WFIFO: If the unused space of the output FIFO is sufficient to accommodate a burst read data transfer, the burst read operation begins; otherwise, it continues to loop and wait in the original state. S_WR_BURST: When the burst read completion flag is received, the system jumps sequentially to the S_WR_BURST_END state and then to the S_WR_END state to complete one data write operation.

[0010] Preferably, the preprocessing of the sampled data includes: packaging the collected multi-channel data, splicing the collected multi-channel data during the packaging process, adding a data header identifier at the beginning of the data, adding a data tail identifier at the end of the data pulse, and establishing a data transmission protocol.

[0011] Preferably, a corresponding access terminal is set in each acquisition channel. Each acquisition channel's access terminal can independently receive and process the corresponding signal, and perform serial-to-parallel conversion on the high-speed sampled data from multiple channels.

[0012] A wideband voltage and current signal dynamic processing system, comprising: The front-end signal conditioning module preprocesses the voltage / current signals; The analog-to-digital conversion module uses equivalent sampling and time-alternating sampling techniques to acquire data at a high sampling rate when the ADC sampling rate is low. The time-alternating sampling involves multiple ADCs sampling the same signal simultaneously, with each ADC's sampling clock driving the corresponding ADC with a fixed phase difference. The sampled data is then combined in chronological order in the back-end receiving device. The clock synchronization module receives GPS and BDS signals. When the GPS / BDS module receives the synchronization clock signal, it sends the second pulse signal to the FPGA to realize real-time synchronization processing of the sampling. At the same time, it decodes the synchronization signal to obtain accurate year, month, day, hour, minute, second information and geographical location information, and performs synchronization processing on the DSP measurement data.

[0013] Preferably, the signal measurement and analysis module includes: The peripheral and physical interface driver layer sends data to the corresponding logical storage unit according to the port required by the external device. The real-time operating system layer mimics the model of a PC computer operating system. The platform middleware layer generates a data exchange network through the mapping relationship between physical ports and virtual ports. After data access, it establishes corresponding routing switching algorithms by switching or updating numerous routing mapping exchange tables in the data exchange network, constructs real-time reconstruction of upper and lower layer communication links, completes dynamic pointing and interaction between data and analysis type virtual ports, and sends standardized format data to the communication application layer for analysis. The communication application layer controls the devices throughout the platform via the system communication link.

[0014] Preferably, the high-speed data acquisition module includes: The front-end signal conditioning module preprocesses the voltage / current signals; The analog-to-digital conversion module uses equivalent sampling and time-alternating sampling techniques to acquire data at a high sampling rate when the ADC sampling rate is low. The time-alternating sampling involves multiple ADCs sampling the same signal simultaneously, with each ADC's sampling clock driving the corresponding ADC with a fixed phase difference. The sampled data is then combined in chronological order in the back-end receiving device. The clock synchronization module receives GPS and BDS signals. When the GPS / BDS module receives the synchronization clock signal, it sends the second pulse signal to the FPGA to realize real-time synchronization processing of the sampling. At the same time, it decodes the synchronization signal to obtain accurate year, month, day, hour, minute, second information and geographical location information, and performs synchronization processing on the DSP measurement data.

[0015] Preferably, the system includes an edge computing module, which performs preliminary processing and compression of data near the collection point, and performs fault prediction and real-time scheduling optimization based on the preliminary processing results.

[0016] Therefore, the present invention has the following beneficial effects: 1. The system adopts a transmission method that uses an FPGA control chip to read data during conversion, enabling the system to achieve a high sampling rate.

[0017] 2. By making reasonable use of the internal resources of the FPGA, a data buffer transmission method is implemented, thereby completing the real-time data transmission and real-time Flash storage functions, enhancing the reliability, effectiveness and stability of data transmission and storage, and greatly leveraging the high-speed data parallel processing capability and timing constraint capability of the FPGA. Attached Figure Description

[0018] Figure 1 This is a flowchart of the steps in the broadband voltage and current signal dynamic processing method in Example 1.

[0019] Figure 2 This is a schematic diagram of the input FIFO state transition in Example 1.

[0020] Figure 3 This is a schematic diagram of the output FIFO state transition in Example 1.

[0021] Figure 4 This is a schematic diagram of the state transition during a write operation in Example 1.

[0022] Figure 5 This is a schematic diagram of the read operation state transition in Example 1.

[0023] Figure 6 This is a schematic diagram of the time-alternating sampling structure in Example 2.

[0024] Figure 7 This is a schematic diagram of data transmission and export in Example 2.

[0025] Figure 8 This is a schematic diagram of the FIFO data transmission process in Example 2.

[0026] Figure 9 This is a schematic diagram of FPGA and dynamic signal flow processing in Example 2.

[0027] Figure 10 This is a schematic diagram of the FPGA and dynamic signal processing circuit in Example 2.

[0028] Figure 11 This is a schematic diagram of the DSP and SDRAM circuits in Example 2.

[0029] Figure 12 This is a schematic diagram of the data export circuit in Example 2. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Example 1: This embodiment provides a method for dynamic processing of wideband voltage and current signals, such as... Figure 1 As shown, the operation process is as follows: Step 1, preprocess the wideband voltage and current signals, and perform multi-channel high-speed synchronous sampling on the preprocessed signals; Step 2, preprocess the sampled data, establish the storage control logic between the FPGA's internal FIFO resources and memory, and convert burst read / write requests into AXI bus format requests; Step 3, after receiving the preprocessed sampled data, the FPGA generates a synchronization signal, triggers the DSP's SRIO, and controls the transmission of the preprocessed sampled data to the DSP; Step 4, perform wideband measurement on the sampled data, perform empirical mode decomposition and Hilbert transform on the measurement data, and identify disturbances.

[0031] The wideband voltage and current signal dynamic processing method provided in this embodiment successfully captures wideband oscillation phenomena efficiently through high-precision ADC and FPGA technology. By employing multi-channel synchronous acquisition and optimized data transmission paths, it significantly improves signal processing speed and stability, achieving rapid response in massive data acquisition and storage, and effectively supporting the data management needs of smart grids.

[0032] The following examples and specific application scenarios further illustrate the technical solution and effects of the present invention. The following examples are explanations of the present invention, but the present invention is not limited to the following examples.

[0033] Specifically, such as Figure 1 As shown, a method for dynamic processing of wideband voltage and current signals specifically includes the following steps: Step 1: Preprocess the wideband voltage and current signals, and then perform multi-channel high-speed synchronous sampling on the preprocessed signals.

[0034] During data acquisition, a corresponding access terminal is set in each acquisition channel. Each access terminal of the acquisition channel can independently receive and process the corresponding signal, and perform serial-to-parallel conversion on the high-speed sampled data from multiple channels to suit parallel transmission and processing.

[0035] The second step is to preprocess the sampled data, establish the storage control logic between the FPGA's internal FIFO resources and memory, and convert burst read / write requests into AXI bus format requests.

[0036] The FPGA receives multiple signals acquired by the ADC and performs data preprocessing.

[0037] The main task of preprocessing the sampled data is data packaging to facilitate subsequent storage and transmission. The specific process includes: packaging the acquired multi-channel data; during packaging, the acquired multi-channel data (multi-channel signals) are spliced ​​together, a data header identifier is added at the beginning of the data, and a data tail identifier is added at the end of the data pulse, establishing a data transmission protocol. After preprocessing, the FPGA stores the data by connecting to external memory, and simultaneously establishes storage control logic between the FPGA's internal FIFO resources and memory to ensure stable transmission of the high-speed sampling sequence within the signal processing board and to correctly send the data to the output port.

[0038] During data transmission, FIFO can effectively buffer the data flow between input and output, avoiding data loss or overflow caused by the mismatch between the input data rate and the output data rate when the sampling data bandwidth is large.

[0039] The storage control logic includes: (1) Input FIFO control logic.

[0040] The input FIFO buffer control is mainly used to complete the function of writing input FIFO data to the external memory after receiving a write request, and its state machine transition diagram is shown in Figure 2 , which implements the jump process between a total of six states. In the data transmission process, after receiving the write request, the input FIFO data is written to the external memory, which specifically includes: S_WR_IDLE: The initial idle state of this state machine. When a low-level active reset signal is input to the state machine, this initial idle state is triggered, and it waits for the write data request to be pulled high to enter the next state S_WR_ACK; S_WR_ACK: If the write request is revoked, it enters the next state S_CHECK_WFIFO; S_CHECK_WFIFO: Detect the space size of the input FIFO, and judge whether to start the burst write operation by checking whether the usage amount of data at the read end of the input FIFO meets the storage space size BURST_SIZE required for one burst write in the subsequent AXI bus protocol; S_WR_BURST: When the burst write completion flag is received, it sequentially jumps to the S_WR_BURST_END state and the S_WR_END state to complete one data write.

[0041] (2) Output FIFO control logic.

[0042] The output FIFO buffer control is mainly used to complete the operation of the output FIFO reading data from the external memory after receiving a read request. Its state machine transition diagram is shown in Figure 3 . This state machine is also composed of six states, and its control logic is basically consistent with that of the input FIFO. The difference is that the trigger signal is changed to the read request read_req; at the same time, the burst read condition in the FIFO space detection state is changed: when the expression wrusedw<FIFO_DEPTH-BURST_SIZE is satisfied, that is, it is proved that the unused space of the output FIFO is sufficient to accommodate one burst read data transmission, the burst read operation will start, otherwise it will keep looping and waiting in the original state.

[0043] That is, in the data transmission process, after receiving the read request, the output FIFO reads data from the external memory, and its state machine transition specifically includes: S_WR_IDLE: When a low-level active reset signal is input to the state machine, this initial idle state is triggered, and it waits for the read data request to be pulled high to enter the next state S_WR_ACK; S_WR_ACK: If the read request is revoked, it enters the next state S_CHECK_WFIFO; S_CHECK_WFIFO: If the unused space in the output FIFO is sufficient to accommodate a burst read data transfer, the burst read operation begins; otherwise, it continues to loop and wait in the original state. S_WR_BURST: When the burst read completion flag is received, the system jumps sequentially to the S_WR_BURST_END state and then to the S_WR_END state to complete one data write operation.

[0044] When converting burst read / write requests into AXI bus format requests, the AXI interface conversion program converts the burst read / write request signal into an AXI bus format request that the controller can receive. The AXI bus interface conversion module includes two parts: AXI write and AXI read.

[0045] (1) Write operation state transition.

[0046] like Figure 4 As shown, it specifically includes: S_WR_IDLE: Initial idle state. The state machine enters this state when the reset signal is valid. Initial values ​​are assigned to the write address base address and burst length. When the input FIFO control sends a burst write request signal (wr_burst_req=1), the state machine enters the next state, S_WA_WAIT.

[0047] S_WA_WAIT: In this state, the state machine waits for the write address to be set. Once the condition is met, it jumps to the S_WA_START state. S_WA_START: This state enables the write address burst transmission channel. When the write address signal is valid (reg_awvalid=1), the relevant control signal configuration for the write address channel is completed, and it unconditionally enters the S_WD_WAIT state.

[0048] S_WD_WAIT: This state is the write data waiting state. When the write address readiness signal (M_AXI_AWREADY=1) is valid, the state machine jumps to the S_WD_PROC state. S_WD_PROC: In this state, the write data burst transmission channel is opened, and the channel control signal assignment operation is completed. When the write data readiness signal M_AXI_WREADY is set to 1, the state machine enters the S_WR_WAIT state.

[0049] S_WR_WAIT: This state is used to determine whether the data burst transmission has ended. When the write response signal is valid (M_AXI_BVALID=1) and the last data has been transmitted (reg_w_last=1), the state machine transitions to the last state.

[0050] S_WR_DONE: This state indicates the completion of an AXI burst write operation, and the entire write process ends.

[0051] Through these state transitions, the state machine can efficiently manage data write operations on the AXI bus, transmitting data from the input FIFO to the controller.

[0052] (2) Read operation state transition.

[0053] Read operation state transition such as Figure 5 As shown, the design concept is basically the same as the write operation state transition, except that the read response process is no longer needed.

[0054] Step 3: After receiving the preprocessed sampled data, the FPGA generates a synchronization signal, which triggers the DSP's SRIO to control the transmission of the preprocessed sampled data to the DSP.

[0055] The sampling data preprocessing also generates a synchronization signal and triggers the DSP's SRIO, controlling the transmission of the spliced ​​sampling data to the DSP for real-time processing. To improve the system's real-time performance, only 16 lines of data are transmitted continuously at a time, and processing can begin immediately after the data is transmitted.

[0056] In this embodiment, the SRIO communication interface is used when designing the system for transmitting FIFO output data in the FPGA. This enables an efficient data processing flow, leveraging the high bandwidth and low latency characteristics of SRIO to ensure fast and stable data transmission between different components.

[0057] During data transmission, the FPGA and DSP use PING / PONG operations to solve the communication problem across clock domains. This design ensures both efficient data transmission and processing speed and accuracy.

[0058] In the DSP, an SRIO receiver module is configured to receive data from the FPGA, enabling high-speed data transmission via the SRIO interface. The EDMA is then configured as the control unit for SRIO data transmission, handling the reception of one concatenated signal through a dedicated channel. The EDMA's automatic linking mechanism allows for rapid response to new data reception requests after receiving 16 lines of data. Specifically, when the FPGA receives 16 lines of concatenated data, it generates a synchronization signal, triggering the DSP's SRIO interface to begin data transmission. This design enables efficient and real-time data transmission between the FPGA and DSP.

[0059] Step 4: Perform broadband measurements on the sampled data, and perform empirical mode decomposition and Hilbert transform on the measured data to identify disturbances.

[0060] In this embodiment, data processing is based on a DSP. Broadband measurement is performed on the sampled data. The measurement results include electrical parameters such as amplitude, phase, and harmonics. Empirical mode decomposition and Hilbert transform are performed on the measurement data to identify disturbances.

[0061] Meanwhile, this embodiment uses an ARM microprocessor-based communication and display control module, which is responsible for uploading the measurement and analysis results to the cloud center through the communication interface, and presenting the results to the user through the local display interface.

[0062] During data processing, a data exchange network is generated through the mapping relationship between physical ports and virtual ports. After the sampled data is accessed, the corresponding routing switching algorithm is established by switching or updating numerous routing mapping exchange tables in the data exchange network, and the upper and lower layer communication links are reconstructed in real time to complete the dynamic pointing and interaction between data and analysis type virtual ports.

[0063] The beneficial effects of using the wideband voltage and current signal dynamic processing method provided in this embodiment are as follows: 1. The AXI bus ensures rapid data interaction and efficient processing capabilities. Simultaneously, a FIFO buffer mechanism prevents data loss, ultimately achieving seamless data transmission between the real-time processing system and external storage and the host computer, meeting the requirements of high bandwidth and real-time performance.

[0064] 2. During data transmission, a reliable data transmission channel is constructed at the hardware level through the combination of a FIFO buffer mechanism and an SRIO communication interface, enabling high-speed and stable transmission of massive amounts of sampled data. This design ensures data integrity while providing reliable data channel support for rapid transient process analysis and real-time fault identification in power systems.

[0065] Example 2: This embodiment provides a wideband voltage and current signal dynamic processing system for implementing the wideband voltage and current signal dynamic processing method in Embodiment 1.

[0066] In new power systems, the widespread application of grid-connected converters from renewable energy sources and the promotion of hybrid AC / DC transmission have significantly weakened the traditional AC coupling characteristics between power grids. This weakening brings new challenges: the interaction between power electronic equipment and traditional equipment such as synchronous generators and transmission networks is more complex, easily inducing novel electromagnetic oscillation phenomena. Compared with electromagnetic oscillations in traditional power systems, these oscillations have a wider frequency distribution, extending from low frequencies of several hertz to high frequencies of several kilohertz, exhibiting typical broadband characteristics. This novel broadband electromagnetic oscillation may lead to serious consequences such as system instability and equipment damage, posing a significant threat to the safe and stable operation of the power system.

[0067] Faced with the challenges posed by novel electromagnetic broadband oscillations, traditional narrowband monitoring techniques are no longer sufficient. Traditional technologies have significant limitations in sampling frequency and signal bandwidth, making it impossible to effectively capture and analyze transient signals covering such a wide frequency range. To accurately monitor and analyze these complex oscillation phenomena, it is urgent to introduce advanced broadband high-speed acquisition and real-time processing technologies. Therefore, this embodiment studies a high-performance broadband voltage / current signal acquisition device and a real-time processing system, providing a broadband voltage and current signal dynamic processing system to achieve rapid identification, accurate location, and effective suppression of broadband oscillations, thereby ensuring the safe and stable operation of the new power system.

[0068] A wideband voltage and current signal dynamic processing system mainly includes a high-speed data acquisition module, a FIFO data transmission module, a signal dynamic processing and transmission module, and a signal measurement and analysis module. The high-speed data acquisition module is connected to the FIFO data transmission module and the signal dynamic processing and transmission module, and the signal measurement and analysis module is also connected to the FIFO data transmission module and the signal dynamic processing and transmission module. The high-speed data acquisition module is a wideband signal acquisition device. It covers the complete process from signal acquisition, conditioning, processing, storage to transmission, which not only improves the safety and stability of power grid operation but also provides a solid technical foundation for the development of smart grids. By accurately acquiring and processing voltage and current signals in the power system, it ensures real-time monitoring and stability of power grid operation.

[0069] To ensure the high efficiency and reliability of the wideband voltage / current signal acquisition device, this embodiment analyzes and determines the design scheme of the high-speed data acquisition module based on the requirements of high-speed data acquisition indicators. Based on this analysis, a high-speed, large-capacity data storage scheme is given, based on the data storage requirements and storage speed requirements. The overall design scheme of the high-speed signal acquisition module is completed, and the selection of logic devices is given based on the comprehensive acquisition and AXIe interface requirements.

[0070] The system employs a DSP as the core algorithm implementation unit and ARM and FPGA as the high-speed sampling control unit for data processing. A 16-bit high-precision analog-to-digital converter chip is used for high-precision sampling. A dual-time synchronization module with GPS and BDS, offering enhanced reliability, is used to achieve the hardware design and implementation of a wideband phasor high-precision measurement device. The entire hardware structure mainly includes: voltage / current signal input terminals, input signal conditioning circuits, a multi-channel analog-to-digital converter (AD) sampling module, a high-speed sampling control unit with FPGA as its core, a wideband phasor high-precision measurement unit with DSP as its core, real-time storage, and a data communication and display control module with an ARM microprocessor as its core. The overall process of high-speed signal sampling involves the voltage / current signal of the power system being input to the sampling unit through the terminal block, and then sequentially passing through the conditioning circuit, the high-precision AD sampling unit, and the high-speed sampling control unit FPGA to complete the sampling.

[0071] Specifically, the wideband voltage and current signal dynamic processing system provided in this embodiment mainly includes two parts: data acquisition and processing, and data transmission and export. The data acquisition and processing includes a high-speed data acquisition module and a signal measurement and analysis module, while the data transmission and export includes a FIFO data transmission module and a signal measurement and analysis module.

[0072] I. Data Acquisition and Processing.

[0073] To address the limitations of traditional data acquisition and processing systems in effectively achieving synchronization and real-time performance during data transmission and storage, this research designs a 16-channel high-precision synchronous real-time high-speed acquisition system based on FPGA. This system employs a transmission method where the FPGA control chip reads data during conversion, enabling a high sampling rate. By rationally utilizing the internal resources of the FPGA and implementing a data buffering transmission method, real-time data transmission and real-time Flash storage are achieved, enhancing the reliability, efficiency, and stability of data transmission and storage. This significantly leverages the high-speed parallel data processing capabilities and timing constraints of the FPGA.

[0074] Specifically, it includes: (1) High-speed data acquisition module.

[0075] The high-speed data acquisition module includes: Front-end signal conditioning module: This is the front-end circuit section for signal acquisition. The front-end signal conditioning channel is responsible for preprocessing voltage / current signals to facilitate subsequent analog-to-digital conversion and data processing. The core objective of the conditioning module design is to perform appropriate gain adjustment, filtering, and interference suppression on the input signal.

[0076] The front-end signal conditioning module's workflow includes multi-channel signal conditioning: voltage / current signals enter the input signal conditioning circuit through access terminals. Each channel is designed with corresponding access terminals to allow voltage / current signals from different channels to be input into the conditioning circuit. Each channel's access terminal can independently receive and process its corresponding signal. The conditioning circuit performs preprocessing such as filtering and amplification on the input signal. A multi-channel high-speed ADC performs high-speed sampling on the conditioned analog signal. The data acquired by the ADC undergoes serial-to-parallel conversion to suit parallel transmission and processing. The relationship between the signal and the sampling rate should satisfy the Nyquist sampling theorem or the bandpass sampling theorem. The sampled data is stored in real-time in the local storage module. Once the data storage is complete, it can be exported to an external host via Gigabit Ethernet.

[0077] Analog-to-Digital Conversion Module: The high-speed data acquisition module must first digitize the analog signal before it can be buffered, filtered, and transmitted. The analog-to-digital converter (ADC) is a key component of the data acquisition module, and its performance directly impacts the overall performance. When the ADC sampling rate is low, equivalent sampling and time-alternating sampling techniques can be used to achieve high sampling rates. Equivalent sampling is primarily for repetitive periodic signals and has limitations; time-alternating sampling, on the other hand, has no limitations on the signal type and is more widely applicable. The time-alternating sampling structure is as follows: Figure 6 As shown, multiple ADCs sample the same signal simultaneously. The sampling clocks of each ADC drive the corresponding ADC with a fixed phase difference, and the sampled data are combined in chronological order in the back-end receiving device. By alternating sampling, the sampling rate of the acquisition system can be increased to the sum of the sampling rates of the multiple ADCs.

[0078] In this embodiment, two AD chips are used to form a 16-channel data acquisition circuit. By directly connecting the parallel / serial interface selection input to the level, and then shorting the chip pins together and applying the same conversion signal, multiple channels can be converted simultaneously.

[0079] The acquisition device receives low-voltage / current signals from the secondary side of the instrument transformer, which need to be processed by a conditioning circuit. The input signal to the conditioning circuit is a 0-100V voltage signal or a 0-5A current signal from the secondary side of the power system instrument transformer. After passing through a conditioning unit composed of a precision instrument transformer, an RLC low-pass filter circuit, and a Zener diode, the signal undergoes low-pass filtering to ensure that the signal input to the AD module satisfies the Nyquist sampling theorem. The passband cutoff frequency is designed to be 5000Hz. Simultaneously, the Zener diode also stabilizes the output voltage and protects the circuit. The output signal of the conditioning circuit uses a differential form, improving the circuit's immunity to ground loop interference and common-mode interference.

[0080] Clock synchronization module: Receives GPS and BDS signals. When the GPS / BDS module receives the synchronization clock signal, it sends the second pulse signal to the FPGA module to achieve real-time synchronization processing of the samples. Simultaneously, the ARM chip decodes the synchronization signal to obtain precise year, month, day, hour, minute, second information and geographical location information, and performs synchronization processing on the DSP measurement data.

[0081] (2) Signal measurement and analysis module.

[0082] The signal measurement and analysis module includes a phasor measurement unit with a DSP as its core, which performs broadband measurements on the sampled data. The measurement results include electrical parameters such as amplitude, phase, and harmonics. The module also performs empirical mode decomposition and Hilbert transform on the measurement data to identify disturbances.

[0083] The signal measurement and analysis module mainly consists of four parts: peripheral and physical interface driver layer, real-time operating system layer, platform middleware layer, and communication application layer.

[0084] Dynamic signal processing is a key factor limiting high-speed signal acquisition, primarily responsible for preprocessing, information processing, and data export of wideband voltage and current signals. To achieve efficient wideband signal processing, project personnel need to prioritize addressing the following issues before integrating the hardware architecture of the dynamic signal processing system: (a) In terms of design, most are concentrated on a single motherboard. Adding different functions requires hardware modifications before software changes can be made, resulting in significant differences between the hardware and software of the devices. (b) Under normal circumstances, the processors in real-time processing systems are tightly coupled, requiring appropriate interface design to reduce coupling and address issues such as poor maintainability and insufficient scalability of current processing systems. (c) Current communication signal processing has high real-time requirements, and the system should be capable of processing multi-target, high-frequency data.

[0085] Based on this, in this embodiment, the signal measurement and analysis module adopts a PC-like communication signal dynamic processing system, which includes a hardware platform and a software layer.

[0086] The hardware platform employs an 8-core processor with an FPGA for expansion, a 1GHz clock speed, supports SMP and AMP, has 8GB of memory, and provides high-speed and low-speed interfaces such as RS232, Ethernet, JTAG, SRIO, LVDS, RS485, and CAN. The logic layer design is embedded in the core processor as algorithm code and comprises four parts: a peripheral and physical interface driver layer, a real-time operating system layer, a platform middleware layer, and a communication application layer.

[0087] Peripheral and Physical Interface Driver Layer: This layer comprises two parts. One part consists of the peripheral interface drivers built into the main DSP chip, such as Ethernet, EMIF, SRIO, I2C, SPI, GPIO, and UART. The other part consists of interface drivers obtained through FPGA expansion due to the limited interfaces of the main chip, such as Ethernet, UART, SPI, GTX, and SDIO. These drivers send data to the corresponding logical memory units based on the port requirements of the external device.

[0088] Real-time operating system layer: The real-time operating system layer mainly mimics the model of a PC computer operating system. The operating system primarily includes a device management module, a file system module, a network service module, a shell module, a dynamic loading module, and a parallel processing module.

[0089] The device management module provides a unified POSIX interface driver, which encapsulates various interface drivers in the peripheral and physical interface driver layers. Data can be read from the corresponding storage into the system simply by calling a unified function. The file system module primarily uses file handling methods similar to those in a computer operating system, managing and storing file data by dividing it into directories, subdirectories, and filenames, utilizing data organization methods on storage devices. The network module controls data transmission over a network. The shell module is similar to a computer's CMD serial port, allowing manual input of programs for command-line operation and information display. The dynamic loading module addresses situations with limited hardware resources, where only a portion of the system's processing algorithms can run simultaneously. Through code scheduling, when other algorithms need to be executed, the original algorithm is automatically unloaded online without a system restart, and the new algorithm is loaded and continues running. The parallel processing module utilizes multi-core CPU parallel algorithms to accelerate the processing of programs in parallel.

[0090] Platform Middleware Layer: The platform middleware generates a data exchange network through the mapping relationship between physical ports and virtual ports. The physical ports support access from different physical devices and are scalable. After data access, by switching or updating numerous routing mapping exchange tables in the data exchange network, corresponding routing exchange algorithms are established, and the communication links between upper and lower layers are reconstructed in real time. This completes the dynamic pointing and interaction between data and analysis type virtual ports, sending standardized format data to application layer software for analysis, and shielding the impact of changes between lower-layer physical devices and upper-layer application software.

[0091] Communication Application Layer: The communication application layer mainly includes control and management software, health management software, and signal processing software. The control and management software primarily manages the devices across the platform through software interaction via the system communication link, including overall device control, parameter control, communication mode selection, communication parameter association, and signal software access management. The health management software is responsible for managing the health status of the devices, performing controls such as power-on self-test management, periodic self-test management, proactive reporting management, and anomaly detection management. The signal processing software can connect to various analysis software, mainly performing specific communication information analysis on the received data; it is typically a pre-built, fixed software package.

[0092] The data acquisition section also includes an edge computing module. This module can perform preliminary processing and compression of data near the acquisition point, reducing the data processing pressure on the central system and improving overall response speed. Furthermore, edge computing can also achieve intelligent analysis functions, such as fault prediction and real-time scheduling optimization, further enhancing the system's intelligence level.

[0093] II. Data Transfer and Export.

[0094] like Figure 7As shown, the overall data transmission and export system consists of a DSP, an FPGA, and signal acquisition components. The data transmission workflow is as follows: The FPGA receives four signals acquired by the ADC and performs data preprocessing. The main task of preprocessing is data packaging to facilitate subsequent storage and transmission. During packaging, the FPGA concatenates the four-channel data, adds a data header identifier at the beginning of the data, and adds a data tail identifier at the end of the data pulse, thus forming a simple transmission protocol. After preprocessing, the FPGA stores the data by connecting to an external DDR3 memory. Simultaneously, it establishes storage control logic between the FPGA's internal FIFO resources and the DDR3 memory to ensure stable transmission of the high-speed sampling sequence within the signal processing board and correctly sends the data to the output port.

[0095] In addition, data preprocessing generates a synchronization signal and triggers the DSP's SRIO, controlling the transmission of the spliced ​​data to the DSP for real-time processing. To improve system real-time performance, only 16 lines of data are transmitted continuously at a time, and processing can begin immediately after transmission.

[0096] Specifically: (1) FIFO data transmission module.

[0097] During data transmission, a FIFO can effectively buffer the data flow between input and output, preventing data loss or overflow caused by a mismatch between the input and output data rates when the sampling data bandwidth is large. The FIFO data transmission circuit design block diagram is shown below. Figure 8 As shown.

[0098] The input FIFO buffer control is mainly used to write data from the input FIFO to external memory upon receiving a write request. This state machine implements six state transition processes, specifically including: S_WR_IDLE: This is the initial idle state of the state machine, triggered when a low-level active reset signal is input. It waits for a write data request (write_req) to go high before entering the next state, S_WR_ACK.

[0099] S_WR_ACK: This state is the response state for the write data request. It is used to complete the write request response, FIFO reset, address latching, and data length latching operations. Once the write request is cancelled, it enters the next state S_CHECK_WFIFO.

[0100] S_CHECK_WFIFO: This state is used to detect the space size of the input FIFO, and it is determined whether to start the burst write operation by judging whether the usage amount rdusedw[15:0] of the data at the read end of the input FIFO meets the storage space size BURST_SIZE required for one burst write operation in the subsequent AXI bus protocol. If the expression rdusedw>= BURST_SIZE is satisfied, it will jump to the next state S_WRITE_BURST, otherwise it will keep waiting for a trigger in this state.

[0101] S_WR_BURST: This state is the burst write state from the input FIFO to the external memory. When the burst write completion flag wr_burst_finish=1 is received, it sequentially jumps to the S_WR_BURST_END state and the S_WR_END state to complete one data writing process.

[0102] The output FIFO cache control is mainly used to complete the operation of the output FIFO reading data from the external memory after receiving a read request. This state machine is also composed of six states, and its control logic is basically the same as that of the input FIFO. The difference lies in that the trigger signal is changed to the read request read_req; at the same time, the burst read condition in the FIFO space detection state is changed: when the expression wrusedw<FIFO_DEPTH-BURST_SIZE is satisfied, that is, it is proved that the unused space of the output FIFO is sufficient to accommodate one burst read data transmission, the burst read operation will start, otherwise it will keep looping and waiting in the original state.

[0103] Through the AXI interface conversion program, the burst read and write request signals are converted into AXI bus format requests that can be received by the controller. The AXI bus interface conversion module includes two parts: AXI write and AXI read.

[0104] The state transition of the AXI write operation is as follows: S_WR_IDLE: Initial idle state. The state machine enters this state when the reset signal is valid. Initial values ​​are assigned to the write address base address and burst length. When the input FIFO control sends a burst write request signal (wr_burst_req=1), the state machine enters the next state, S_WA_WAIT. S_WA_WAIT: In this state, the state machine waits for the write address to be set. Once the condition is met, it jumps to the S_WA_START state. S_WA_START: This state opens the write address burst transmission channel. When the write address signal is valid (reg_awvalid=1), the relevant control signals for the write address channel are configured, and the state machine unconditionally enters the S_WD_WAIT state. S_WD_WAIT: This state is the write data waiting state. When the write address prepare signal (M_AXI_AWREADY=1) is valid, the state machine jumps to the S_WD_PROC state. S_WD_PROC: In this state, the write data burst transmission channel is opened, and the channel control signals are assigned values. When the write readiness signal M_AXI_WREADY is set to 1, the state machine enters the S_WR_WAIT state. S_WR_WAIT: This state is used to determine whether the data burst transmission has ended. When the write response signal is valid (M_AXI_BVALID=1) and the last data has been transmitted (reg_w_last=1), the state machine transitions to the last state. S_WR_DONE: This state marks the completion of an AXI burst write operation, and the entire write process ends.

[0105] Through these state transitions, the state machine can efficiently manage data write operations on the AXI bus, transmitting data from the input FIFO to the controller. Similarly, the design process for the AXI read operation state machine can be derived; the design concept is basically the same as the write process, except that a read response process is no longer needed.

[0106] (2) Data transmission and export module: FPGA to signal dynamic processing transmission process.

[0107] When designing a system in an FPGA for transmitting FIFO output data, an SRIO communication interface is used. This enables an efficient data processing flow, leveraging SRIO's high bandwidth and low latency to ensure fast and stable data transmission between different components.

[0108] During data transmission, the FPGA and DSP use PING / PONG operations to address communication issues across clock domains. This operating mode allows data to be continuously transferred between the two modules without interruption, enabling smooth pipelined data processing. When input data latency exists, PING / PONG operations can also effectively eliminate the latency, ensuring seamless data processing and buffering within the pipelined algorithm. Through this design, the system can maintain efficient data transmission while ensuring processing speed and accuracy.

[0109] First, design a pair of PING / PONG caches, each cache being large enough to store 16 lines of concatenated data, such as... Figure 9 As shown. This design allows the FPGA to prepare the next round of data while receiving the previous data, improving data processing efficiency. To ensure data transmission synchronization, a synchronization control module is created. This module generates a synchronization signal based on the frame field synchronization and line count of the spliced ​​signal and connects it to the DSP's GPIO5 to trigger data transmission.

[0110] In the DSP, an SRIO receiver module is configured to receive data from the FPGA, achieving high-speed data transmission via the SRIO interface. The EDMA is configured as the control unit for SRIO data transmission, handling the reception of one concatenated signal through a dedicated channel. The EDMA's automatic linking mechanism allows the system to quickly respond to the need for new data after receiving 16 lines of data. Specifically, when the FPGA receives 16 lines of concatenated data, it generates a synchronization signal, triggering the DSP's SRIO interface to begin data transmission. This design enables efficient and real-time data transmission between the FPGA and DSP. The specific circuit diagram is shown below. Figure 10 As shown.

[0111] The DSP and FPGA provide the following control and status signals: four-channel transmit enable signal / ENTX

[03] , which transmits when low; four-channel transmit stop signal / TXT

[03] , which stops transmitting when low; receive data arrival signal / RER

[03] , which informs the DSP to prepare to receive data that has arrived from a certain channel; transmit data ready signal / TXR

[03] , which informs whether there is any untransmitted data temporarily stored in the FIFO in each transmit channel, with a low level indicating no data; transmit channel FIFO full signal FUL

[03] , which indicates that the FIFO is full when high; GLOBCLRN signal, which is used to globally clear the internal structure of the FPGA during initialization; TESTREQ signal, which is used for self-testing of the entire system. The DSP in the dynamic processing system provides I / O operation signal / IS, read / write selection signal R / W, read enable signal / RD, write enable signal / WE, and the lower four address bits A0, A1, A2, and A3. These control logic signals can distinguish the four channels and the high and low words of each channel.

[0112] Data storage process in dynamic processing systems: The DSP seamlessly connects to SDRAM via an external memory interface (EMIF) to store processed signals, ensuring data temporary storage and high-speed processing. After completing real-time processing of the input signal, the DSP efficiently moves the processed data to SDRAM using an EDMA mechanism, avoiding CPU resource consumption. The DSP is connected to a 2GB SDRAM. The DSP communicates with the SDRAM via chip select (CEO), byte enable signals (BE0, BE1), and a synchronization clock signal (CLKMEM). Row strobe signals ( / SDRAS), column strobe signals ( / SDCAS), and write enable signals ( / SDWE) correspond to row selection, column selection, and write operations of the SDRAM, respectively. The DSP's address and data lines are directly connected to the SDRAM for data storage and retrieval. This connection method ensures that the data processed by the DSP can be stored and accessed quickly, making it particularly suitable for real-time processing and high-bandwidth applications. The block diagram of the DSP and SDRAM circuit design is shown below. Figure 11 As shown.

[0113] The DSP can transmit data stored in DDR via a network using its built-in network function module. During data transmission, the DSP first encapsulates the data according to a specific network protocol (such as TCP / IP) through its built-in EMAC interface, and then completes the physical transmission of the data through an external network transceiver chip (such as the DP83640). This network function module consists of an EMAC control module, an EMAC module, and an MDIO module, conforming to the IEEE 802.3 protocol, and can easily implement Ethernet communication. The data export circuit block diagram is shown below. Figure 12 As shown.

[0114] The network transceiver chip connects directly to the DSP's EMAC interface via the MII interface, which comprises both receiving and transmitting sections. In the receiving section, the RXD data line transmits received data, RX_ER indicates a receiving error, RX_DV indicates valid data, and RX_CLK provides a synchronization clock signal. The clock frequency varies depending on the network speed (2.5 MHz for 10 Mb / s, 25 MHz for 100 Mb / s). In the transmitting section, the TXD data line transmits transmitted data, TX_EN serves as the transmit enable signal, and TX_CLK provides the transmit clock signal. Similarly, the frequency of TX_CLK also depends on the network speed. Furthermore, the MII interface includes a collision detection signal (COL) to detect transmission and reception collisions in half-duplex mode. Finally, data is transmitted via an RJ45 interface to Ethernet. The DSP can efficiently transfer the processed data from DDR to the host computer, enabling data export functionality.

[0115] The wideband voltage and current signal dynamic processing system provided in this embodiment successfully captures wideband oscillation phenomena efficiently by combining a wideband signal acquisition device with high-precision ADC and FPGA technology. Through multi-channel synchronous acquisition and optimized data transmission paths, signal processing speed and stability are significantly improved. This system achieves rapid response in massive data acquisition and storage, effectively supporting the data management needs of smart grids. Interfaces such as the AXI bus and Gigabit Ethernet ensure rapid data interaction and efficient processing capabilities. Simultaneously, a FIFO caching mechanism prevents data loss, ultimately achieving seamless data transmission between the real-time processing system and external memory and the host computer, meeting the requirements of high bandwidth and real-time performance.

[0116] By introducing edge computing into the data acquisition unit, the system can perform preliminary data processing near the acquisition point, thereby reducing the load on the central processor and improving response speed and data processing efficiency. This innovation significantly enhances the intelligence level and adaptability of the acquisition system. (3) During data transmission, a reliable data transmission channel is built at the hardware level through the combination of FIFO buffering mechanism and SRIO communication interface, realizing high-speed and stable transmission of massive sampling data. This design provides reliable data channel support for rapid transient process analysis and real-time fault identification in the power system while ensuring data integrity.

[0117] Example 3: This embodiment provides a wideband voltage and current signal dynamic processing system. Based on embodiment two, multi-channel synchronous acquisition is adopted during data acquisition.

[0118] This embodiment employs multi-channel synchronous signal acquisition. The overall architecture of multi-channel synchronous signal acquisition includes four parts: data pre-acquisition front-end processing, data storage system, gating switch control system, and FPGA core control system. The front-end processing mainly filters and controls the amplitude of the analog signals input to the measurement system to ensure greater stability of the analog signals input to the acquisition chip. The FPGA core control system uses an FPGA as the core controller to implement functions such as synchronous data processing, real-time acquisition, data caching, timing constraints, port control, data interpretation, and data storage. The data storage system stores the interpreted data in real-time into Flash memory. The gating switch control system utilizes a 1-to-8 multiplexer and solid-state relays to select the input signals of the device under test and control the power supply, enabling the device under test to safely and quickly enter the monitoring state. This embodiment requires synchronous real-time cyclic measurement and control of eight devices under test, and recording, interpreting, transmitting, and storing the measurement data. This mainly includes functions such as power supply management and control, real-time monitoring of DC voltage and current, analog signal channel switching, radio frequency signal switching, and data storage.

[0119] Its working principle is as follows: After the system is powered on, it waits for the FPGA to complete initialization and enters a connection-waiting state. When relevant command parameters are input externally, the FPGA receives and parses the command. First, it controls the internal selection switch of the system to operate, connecting the selected device signal to the acquisition system. Then, it sends control information to the device under test, while the acquisition system monitors the power supply status of the device under test in real time. Subsequently, the acquired data is buffered in the FPGA's internal Random Access Memory (RAM) for processing. Finally, the acquired data is transmitted back to the external monitor for real-time display through the FPGA's on-chip First-Input First-Out (FIFO) queue. The data is then judged and stored according to corresponding rules to form a test data report.

[0120] The hardware circuitry of the multi-channel synchronous acquisition circuit includes: (1) Signal conditioning circuit.

[0121] The signal conditioning circuit filters and controls the amplitude of the analog signal input to the system. It employs a programmable amplifier to design a second-order active Butterworth low-pass filter with a relatively flat passband to filter the front-end input analog voltage signal. Subsequently, the analog current signal is converted into an analog voltage signal using a chip. Then, a high-precision resistor network voltage divider is used to proportionally reduce the measured analog voltage, followed by analog voltage conditioning via a high-performance operational amplifier. Finally, the signal is sent to an analog-to-digital converter (ADC) for sampling. This hardware conditioning ensures that the analog voltage signal input to the acquisition chip has smooth and stable characteristics.

[0122] (2) A / D conversion circuit.

[0123] The analog-to-digital converter (A / D converter) is the core component of data acquisition, affecting the sampling accuracy, sampling rate, and data throughput of the entire system. This embodiment uses two A / D chips to construct a 16-channel data acquisition circuit. By directly connecting the parallel / serial interface selection input to a voltage level, shorting the chip pins together, and applying the same conversion signal, multiple channels can be converted simultaneously.

[0124] 3. Storage circuit.

[0125] After data acquisition is complete, the sampled data from the corresponding channel is sent to the monitor for real-time display and stored in the Flash memory, awaiting a read command from the external controller. The storage circuit establishes communication with the external controller via the SPI interface.

[0126] The FPGA-based high-speed sampling control unit is responsible for controlling and synchronizing the ADC. The relationship between the signal and the sampling rate should satisfy the Nyquist sampling theorem or the bandpass sampling theorem. Sampled data is stored in local storage in real time. Once data storage is complete, it can be exported to an external host via Gigabit Ethernet. After data acquisition, the sampled data from the corresponding channel is sent to a monitor for real-time display and stored in Flash memory, awaiting read commands from the external controller. This chip communicates with the external controller via an SPI interface. The design is simple, the stored data is stable, and it has wide applicability.

[0127] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Other variations and modifications are possible without departing from the technical solutions described in the claims.

Claims

1. A method for dynamic processing of wideband voltage and current signals, characterized in that, include: The wideband voltage and current signals are preprocessed, and the preprocessed signals are then sampled synchronously at high speed through multiple channels. The sampled data is preprocessed, and the storage control logic between the FPGA's internal FIFO resources and memory is established to convert burst read and write requests into AXI bus format requests. After receiving the preprocessed sampled data, the FPGA generates a synchronization signal, which triggers the DSP's SRIO to control the transmission of the preprocessed sampled data to the DSP. Broadband measurements are performed on the sampled data, and empirical mode decomposition and Hilbert transform are applied to the measured data to identify disturbances.

2. The method for dynamic processing of wideband voltage and current signals according to claim 1, characterized in that, A data exchange network is generated by mapping physical ports and virtual ports. After the sampled data is accessed, the corresponding routing switching algorithm is established by switching or updating the numerous routing mapping exchange tables in the data exchange network, and the upper and lower layer communication links are reconstructed in real time to complete the dynamic pointing and interaction between data and analysis type virtual ports.

3. The broadband voltage and current signal dynamic processing method according to claim 1, characterized in that, The storage control logic includes, during data transmission, writing input FIFO data to external memory upon receiving a write request, and its state machine transitions include: S_WR_IDLE: This initial idle state is triggered when a low-level active reset signal is input to the state machine. It waits for a write data request to be received and then pulls the signal high to enter the next state S_WR_ACK. S_WR_ACK: If the write request is revoked, it enters the next state S_CHECK_WFIFO; S_CHECK_WFIFO: Detects the size of the input FIFO space. It determines whether to enable burst write operation by checking whether the amount of data used at the input FIFO read end meets the storage space size BURST_SIZE required for a burst write in the subsequent AXI bus protocol. S_WR_BURST: When the burst write completion flag is received, the system jumps sequentially to the S_WR_BURST_END state and then to the S_WR_END state to complete one data write operation.

4. A method for dynamic processing of wideband voltage and current signals according to claim 1 or 3, characterized in that, The storage control logic includes, during data transmission, upon receiving a read request, outputting a FIFO to read data from external memory, and its state machine transitions include: S_WR_IDLE: This initial idle state is triggered when a low-level active reset signal is input to the state machine. It waits for a read data request to be pulled high to enter the next state S_WR_ACK. S_WR_ACK: If the read request is withdrawn, it enters the next state S_CHECK_WFIFO; S_CHECK_WFIFO: If the unused space in the output FIFO is sufficient to accommodate a burst read data transfer, the burst read operation begins; otherwise, it continues to loop and wait in the original state. S_WR_BURST: When the burst read completion flag is received, the system jumps sequentially to the S_WR_BURST_END state and then to the S_WR_END state to complete one data write operation.

5. A method for dynamic processing of wideband voltage and current signals according to claim 1, 2, or 3, characterized in that, The preprocessing of the sampled data includes: packaging the collected multi-channel data; during the packaging process, splicing the collected multi-channel data; adding a data header identifier at the beginning of the data; adding a data tail identifier at the end of the data pulse; and establishing a data transmission protocol.

6. A method for dynamic processing of wideband voltage and current signals according to claim 1, 2, or 3, characterized in that, Each acquisition channel is equipped with a corresponding access terminal, and each acquisition channel's access terminal can independently receive and process the corresponding signal, performing serial-to-parallel conversion on the high-speed sampled data from multiple channels.

7. A wideband voltage and current signal dynamic processing system, characterized in that, include: The high-speed data acquisition module preprocesses wideband voltage and current signals and performs multi-channel high-speed synchronous sampling on the preprocessed signals. The FIFO data transmission module preprocesses the sampled data, establishes the storage control logic between the FPGA's internal FIFO resources and memory, and converts burst read / write requests into AXI bus format requests. The signal dynamic processing and transmission module: after the FPGA receives the preprocessed sampled data, it generates a synchronization signal to trigger the DSP's SRIO and control the transmission of the preprocessed sampled data to the DSP. The signal measurement and analysis module performs broadband measurements on the sampled data, performs empirical mode decomposition and Hilbert transform on the measured data, and identifies disturbances.

8. The wideband voltage and current signal dynamic processing system according to claim 7, characterized in that, The high-speed data acquisition module includes: The front-end signal conditioning module preprocesses the voltage / current signals; The analog-to-digital conversion module uses equivalent sampling and time-alternating sampling techniques to acquire data at a high sampling rate when the ADC sampling rate is low. The time-alternating sampling involves multiple ADCs sampling the same signal simultaneously, with each ADC's sampling clock driving the corresponding ADC with a fixed phase difference. The sampled data is then combined in chronological order in the back-end receiving device. The clock synchronization module receives GPS and BDS signals. When the GPS / BDS module receives the synchronization clock signal, it sends the second pulse signal to the FPGA to realize real-time synchronization processing of the sampling. At the same time, it decodes the synchronization signal to obtain accurate time and geographical location information, and performs synchronization processing on the DSP measurement data.

9. A wideband voltage and current signal dynamic processing system according to claim 7 or 8, characterized in that, The signal measurement and analysis module includes: The peripheral and physical interface driver layer sends data to the corresponding logical storage unit according to the port required by the external device. The real-time operating system layer mimics the model of a PC computer operating system. The platform middleware layer generates a data exchange network through the mapping relationship between physical ports and virtual ports. After data access, it establishes corresponding routing switching algorithms by switching or updating numerous routing mapping exchange tables in the data exchange network, constructs real-time reconstruction of upper and lower layer communication links, completes dynamic pointing and interaction between data and analysis type virtual ports, and sends standardized format data to the communication application layer for analysis. The communication application layer controls the devices throughout the platform via the system communication link.

10. A wideband voltage and current signal dynamic processing system according to claim 7 or 8, characterized in that, The system includes an edge computing module, which performs preliminary processing and compression of data near the collection point, and performs fault prediction and real-time scheduling optimization based on the preliminary processing results.

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