Memory system and operating method thereof, system

Abstract

The present disclosure provides a memory system and an operating method thereof, the memory system comprising a PCIe interface, a first controller and a second controller; the first controller and the second controller are coupled with the PCIe interface; the first controller is configured to: in response to a configuration command, configure a first flag bit in the first controller to an enabled state; in response to the first flag bit being in the enabled state, generate a first data packet and send the first data packet through the PCIe interface; the second controller is configured to: generate a second data packet and send the second data packet through the PCIe interface; the packaging format of the second data packet is different from the packaging format of the first data packet.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operation method and system. Background Technology

[0002] Devices with PCIe (Peripheral Component Interconnect Express) interfaces, such as PCIe solid-state drives (SSDs), can connect to and interact with the host via the PCIe interface and PCIe bus. Currently, PCIe SSDs supporting the NVMe (Non-Volatile Memory Express) protocol only support the transmission of data packets with the NVMe over PCIe protocol format, which limits the application scenarios of SSDs. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory system and its operation method and system.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, this disclosure provides a memory system including a PCIe interface, a first controller, and a second controller; both the first controller and the second controller are coupled to the PCIe interface;

[0006] The first controller is configured to: in response to a configuration command, configure a first flag bit in the first controller to an enabled state; in response to the first flag bit being in the enabled state, generate a first data packet and send the first data packet through the PCIe interface;

[0007] The second controller is configured to generate a second data packet and send the second data packet through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

[0008] In one optional implementation, the first data packet includes a first header and a first payload; the first header is encapsulated according to the PCIe protocol format, and the first payload includes a first data unit encapsulated according to another protocol format different from the PCIe protocol format.

[0009] The second data packet includes a second header and a second payload; both the second header and the second payload are encapsulated according to the PCIe protocol format.

[0010] In one alternative implementation, the first controller includes a first category code register; the second controller includes a second category code register; the first category code register is configured to store a first category code, and the second category code register is configured to store a second category code different from the first category code; the first category code indicates that the first controller supports sending the first data packet.

[0011] In an alternative implementation, the first controller is further configured to:

[0012] Before sending the first data packet through the PCIe interface, a third data packet is received through the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the third data packet includes a second data unit encapsulated according to the other protocol format, and the second data unit includes a connection request; the first data unit includes response information for the connection request.

[0013] In one alternative implementation, the first controller includes a first register group; the first register group includes the first flag bit; the first register group is further configured to store an identifier of the peer device; the first controller is further configured to:

[0014] The identifier of the peer device is obtained from the first register group, and the identifier of the peer device is encapsulated in the first data packet; and

[0015] The first data packet is sent to the peer device through the PCIe interface.

[0016] In one alternative implementation, the first controller further includes a second register set; the first controller is further configured to:

[0017] The connection status between the first controller and the peer device is stored in the second register group.

[0018] In one alternative implementation, the memory system further includes at least one third controller; the third controller is coupled to the PCIe interface; the first controller further includes a third register group; the third register group includes a second flag bit; the first controller is further configured to:

[0019] Configure the value of the second flag bit to indicate that the first controller is in a discover controller state; and

[0020] The number of the third controllers included in the memory system and the port information of the third controllers are stored in the third register group.

[0021] In one alternative implementation, the third controller includes a third category code register configured to store the first category code.

[0022] In one alternative implementation, the third controller is configured to:

[0023] A fourth data packet is sent through the PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to the other protocol format.

[0024] In one alternative embodiment, the memory system further includes a memory device; both the second controller and the third controller are coupled to the memory device.

[0025] The third controller is further configured to: acquire first data information from the memory device; encapsulate the first data information in the third data unit; and encapsulate the third data unit in the third payload.

[0026] The second controller is further configured to: obtain second data information from the memory device; and encapsulate the second data information in the second payload.

[0027] In one alternative implementation, the other protocol format includes the format of protocol data units defined by the Non-Volatile Memory Fast Channel / Transmission Control Protocol.

[0028] In one alternative implementation, the memory system includes a solid-state drive having the PCIe interface; the solid-state drive includes the first controller and the second controller.

[0029] In a second aspect, this disclosure provides a system including a host and a memory system; the memory system includes a PCIe interface, a first controller, and a second controller; the memory system is coupled to the host via the PCIe interface; both the first controller and the second controller are coupled to the PCIe interface;

[0030] The host is configured to: send a configuration command; the configuration command instructs to configure a first flag bit in the first controller to an enabled state;

[0031] The first controller is configured to: in response to the configuration command, configure the first flag bit to the enabled state; in response to the first flag bit being in the enabled state, generate a first data packet and send the first data packet through the PCIe interface;

[0032] The second controller is configured to generate a second data packet and send the second data packet through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

[0033] In one optional implementation, the first data packet includes a first header and a first payload; the first header is encapsulated according to the PCIe protocol format, and the first payload includes a first data unit encapsulated according to another protocol format different from the PCIe protocol format.

[0034] The second data packet includes a second header and a second payload; both the second header and the second payload are encapsulated according to the PCIe protocol format.

[0035] In one optional implementation, the first controller includes a first category code register; the second controller includes a second category code register; the first category code register is configured to store a first category code, and the second category code register is configured to store a second category code different from the first category code; the first category code indicates that the first controller supports sending the first data packet; the host is further configured to:

[0036] Query the values ​​stored in the first category code register and the second category code register; and

[0037] The configuration command is generated based on the value stored in the first category code register, which is the first category code.

[0038] In an alternative implementation, the first controller is further configured to:

[0039] Before sending the first data packet through the PCIe interface, a third data packet is received through the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the third data packet includes a second data unit generated according to the other protocol format, and the second data unit includes a connection request; the first data unit includes response information for the connection request.

[0040] In an alternative implementation, the system further includes at least one peer device; the memory system is coupled to the peer device via the PCIe interface; the first controller includes a first register set; the first register set includes the first flag bit; the first register set is further configured to store an identifier of the peer device; the first controller is further configured to:

[0041] The identifier of the peer device is obtained from the first register group, and the identifier of the peer device is encapsulated in the first data packet; and

[0042] The first data packet is sent to the peer device through the PCIe interface.

[0043] In one alternative implementation, the first controller further includes a second register set;

[0044] The first controller is also configured to store the connection status between the first controller and the peer device in the second register group;

[0045] The host is also configured to query the second register group to obtain the connection status between the first controller and the peer device.

[0046] In one alternative implementation, the system includes a first non-volatile memory subsystem and a second non-volatile memory subsystem; the first non-volatile memory subsystem includes the memory system; and the second non-volatile memory subsystem includes the peer device.

[0047] In one alternative implementation, the memory system further includes at least one third controller; the third controller is coupled to the PCIe interface; the first controller further includes a third register group; the third register group includes a second flag bit;

[0048] The first controller is further configured to: configure the value of the second flag bit to indicate that the first controller is in the state of a discovery controller; and store the number of the third controllers included in the memory system and the port information of the third controllers in the third register group;

[0049] The host is also configured to query the third register group to obtain the number of the third controllers and the port information of the third controllers.

[0050] In one alternative implementation, the third controller includes a third category code register configured to store the first category code.

[0051] In one alternative implementation, the third controller is configured to:

[0052] A fourth data packet is sent through the PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to the other protocol format.

[0053] In one alternative embodiment, the memory system further includes a memory device; both the second controller and the third controller are coupled to the memory device.

[0054] The third controller is further configured to: acquire first data information from the memory device; encapsulate the first data information in the third data unit; and encapsulate the third data unit in the third payload.

[0055] The second controller is further configured to: obtain second data information from the memory device; and encapsulate the second data information in the second payload.

[0056] In one alternative implementation, the other protocol format includes the format of protocol data units defined by the Non-Volatile Memory Fast Channel / Transmission Control Protocol.

[0057] Thirdly, this disclosure provides a method for operating a memory system, including:

[0058] In response to the configuration command, the first flag bit in the first controller is configured to be enabled;

[0059] In response to the first flag being in the enabled state, a first data packet is generated and sent through the PCIe interface; and

[0060] A second data packet is generated and sent through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

[0061] In one optional implementation, the operation method further includes:

[0062] Before sending the first data packet through the PCIe interface, a third data packet is received through the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the first data packet includes a first data unit encapsulated according to a different protocol format than the PCIe protocol format; the third data packet includes a second data unit encapsulated according to the other protocol format; the second data unit includes a connection request; the first data unit includes response information for the connection request.

[0063] In one optional implementation, the operation method further includes:

[0064] The identifier of the peer device is obtained from the first register group of the first controller, and the identifier of the peer device is encapsulated in the first data packet; and

[0065] The first data packet is sent to the peer device through the PCIe interface.

[0066] In one optional implementation, the operation method further includes:

[0067] The connection status between the first controller and the peer device is stored in the second register group of the first controller.

[0068] In one optional implementation, the operation method further includes:

[0069] Configure the value of the second flag bit in the third register group of the first controller to indicate that the first controller is in the state of a discovered controller; and

[0070] The number of third controllers and the port information of the third controllers are stored in the third register group.

[0071] In one optional implementation, the operation method further includes:

[0072] A fourth data packet is sent through the PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to the other protocol format.

[0073] In one optional implementation, the operation method further includes:

[0074] Obtain first data information from a memory device; encapsulate the first data information in the third data unit, and encapsulate the third data unit in the third payload; and

[0075] The second data information is obtained from the memory device; the second data information is encapsulated in the second payload of the second data packet. Attached Figure Description

[0076] Figure 1 A schematic diagram of an electronic device including a memory system provided for an embodiment of this disclosure;

[0077] Figure 2 A schematic diagram of a solid-state drive provided in an embodiment of this disclosure;

[0078] Figure 3 Schematic diagram of a memory device provided for embodiments of this disclosure Figure 1 ;

[0079] Figure 4 Schematic diagram of a memory device provided for embodiments of this disclosure Figure 2 ;

[0080] Figure 5 Schematic diagram of a memory system provided in an embodiment of this disclosure Figure 1 ;

[0081] Figure 6 Schematic diagram of a memory system provided in an embodiment of this disclosure Figure 2 ;

[0082] Figure 7 A schematic diagram of the registers in the first controller provided in an embodiment of this disclosure;

[0083] Figure 8 A schematic diagram of the protocol stack supported by the first controller and the PCIe interface in the memory system provided in this embodiment of the disclosure;

[0084] Figure 9 A schematic diagram of the first data packet provided in an embodiment of this disclosure;

[0085] Figure 10 A schematic diagram of the fourth data packet provided in an embodiment of this disclosure;

[0086] Figure 11 A schematic diagram of the system provided in the embodiments of this disclosure;

[0087] Figure 12 A schematic diagram illustrating the connection between the memory system and the host and peer devices in a system provided as a specific example of this disclosure;

[0088] Figure 13 This is a flowchart illustrating the operation method of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0089] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0090] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0091] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0092] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0093] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0094] Figure 1 This is a schematic diagram of an electronic device with a memory system provided in an embodiment of this disclosure. In this embodiment, the electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory. Figure 1 As shown, electronic device 100 may include a host 101 and a memory system 102. Memory system 102 may include one or more memory devices 103 and a memory controller 104. Host 101 may include a processor of electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). Host 101 may be configured to send data to memory system 102 or receive data from memory system 102.

[0095] In some embodiments, memory controller 104 is coupled to memory device 103 and host 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host 101. In some embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives.

[0096] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0097] In some embodiments, refer to Figure 2 The memory controller 104 and multiple memory devices 103 can be integrated into the solid-state drive 203. The solid-state drive 203 may also include a connection between the solid-state drive 203 and a host computer (e.g., ...). Figure 1 Solid-state drive connector 204 coupled to host 101.

[0098] Figure 3 Schematic diagram of a memory device provided for embodiments of this disclosure Figure 1 The memory device 300 may be Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0099] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first threshold voltage distribution, and a second memory state "1" may correspond to a second threshold voltage distribution. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0100] like Figure 3As shown, each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations.

[0101] In some embodiments, the memory array 301 includes multiple memory blocks 303, and the sources of memory strings 304 within the same memory block 303 can be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, a top selection transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, allowing data to be read from or written to the bit line 311 via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0102] In some implementations, each memory block 303 is the basic data unit for an erase operation, meaning that all memory cells 305 on the same memory block 303 are erased simultaneously. To erase a memory cell 305 in a selected memory block, an erase voltage bias can be used to couple a common-source line 310 to the selected memory block and an unselected memory block on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0103] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0104] Figure 4 Schematic diagram of a memory device provided for embodiments of this disclosure Figure 2 Combined with reference Figure 3 and Figure 4 The peripheral circuitry 302 may include a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, the peripheral circuitry may also include... Figure 4 Additional circuitry not shown.

[0105] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory strings by applying a bit line voltage generated from voltage generator 404.

[0106] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0107] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and send it to or receive and buffer data from memory array 301.

[0108] In some embodiments, Figure 5 This is a schematic diagram of a memory system provided in an embodiment of the present disclosure. The memory system 500 includes a memory device 502 and a memory controller 501 coupled to the memory device 502. The memory device 502 includes a three-dimensional NAND type memory. Specifically, the memory device 502 includes a memory array 504 and peripheral circuitry 503 coupled to the memory array 504. The memory array 504 can be the memory array 301 including NAND memory cells provided in the above embodiment.

[0109] In some embodiments, the memory controller 501 may include a processor 5011 and a PCIe interface 5012, a memory interface 5013, and a cache 5014 coupled to the processor 5011 via a bus 5010. The memory controller 501 can be coupled to the memory device 502 via the memory interface 5013. During data writing, the memory controller 501 can receive write commands, write data, and the logical address of the write data via the PCIe interface 5012, and can temporarily store the write data in the cache 5014. It can also establish a logical address to physical address (L2P) mapping relationship for the write data. The memory controller 501 can send programming commands to the memory device 502 via the memory interface 5013. The memory device 502 can receive the programming commands and, in response to the programming commands, receive the write data and the physical address of the write data, and store the write data in the memory array 504 at the location corresponding to the physical address of the write data.

[0110] In some specific examples, processor 5011 may further include a front-end controller and a back-end controller, wherein the front-end controller is coupled to PCIe interface 5012, and the back-end controller is coupled to memory interface 5013. Taking the memory system 500 supporting the NVMe over PCIe (NVMe / PCIe) protocol as an example, the front-end controller can implement the functions of the NVMe protocol. For example, the front-end controller can encapsulate NVMe commands and / or data into data packets and send the data packets to external devices (e.g., hosts) through PCIe interface 5012. It can also receive data packets encapsulated with NVMe commands and / or data from external devices through PCIe interface 5012, parse the data packets, and convert the parsed NVMe commands into a protocol format supported by the back-end controller (e.g., ONFI protocol, Toggle protocol, etc.). The back-end controller can receive commands and / or data from the front-end controller. The back-end controller can be coupled to the memory device 502 via the memory interface 5013 and generate control commands in response to commands from the front-end controller. These control commands and / or data are then sent to the memory device 502 via the memory interface 5013 to achieve flash memory management. Here, the data packet encapsulating NVMe commands and / or data is a Transaction Layer Packet (TLP) defined in the PCIe protocol format. In this embodiment, this type of data packet is referred to as NVMe / PCIe TLP.

[0111] In some embodiments, a system including a memory system may also include a peer device. Both the memory system and the peer device are coupled to the host, and the memory system and the peer device may belong to different non-volatile memory subsystems (NVM subsystems). For a system including multiple non-volatile memory subsystems, different non-volatile memory subsystems can directly interact with each other. However, this requires that all non-volatile memory subsystems support the same protocol. When data needs to be transferred between a non-volatile memory subsystem supporting the NVMe-oF (NVMe over Fabrics) protocol and a non-volatile memory subsystem supporting the NVMe / PCIe protocol, the host operating system (OS) is still required as a memory manager to allocate, schedule, and reclaim memory resources, and manage the entire process of protocol conversion and data transmission. This will occupy the operating system's resources and is not conducive to the expansion and improvement of system performance.

[0112] The present disclosure provides the following implementation methods.

[0113] This disclosure provides a memory system, Figure 6 This is a schematic diagram of a memory system provided in an embodiment of the present disclosure. The memory system 500 includes a PCIe interface 5012, a first controller 601, and a second controller 602. Both the first controller 601 and the second controller 602 are coupled to the PCIe interface 5012. The first controller 601 is configured to: in response to a configuration command, configure a first flag bit in the first controller 601 to an enabled state; in response to the first flag bit being enabled, generate a first data packet and send the first data packet through the PCIe interface 5012; the second controller 602 is configured to: generate a second data packet and send the second data packet through the PCIe interface 5012; the encapsulation format of the second data packet is different from the encapsulation format of the first data packet.

[0114] In this embodiment of the present disclosure, the first controller 601 and the second controller 602 may both belong to the memory controller 501 in the memory system 500, and both the first controller 601 and the second controller 602 are coupled to the PCIe interface 5012 in the memory controller 501. When the first flag bit is enabled, the first controller 601 can generate and send a first data packet through the PCIe interface 5012, and the second controller 602 can generate and send a second data packet through the PCIe interface 5012. The encapsulation format of the first data packet is different from that of the second data packet, thereby enabling the memory system 500 to be compatible with two different protocols.

[0115] In this embodiment of the disclosure, reference is made to Figure 6 The first controller 601 and the second controller 602 can be controllers supporting different PCIe Physical Functions (PF). Specifically, the first controller 601 can be a controller supporting PCIe PF1, and the second controller 602 can be a controller supporting PCIe PF0. The first controller 601 and the second controller 602 can have different class codes, support different protocol stacks, and can receive and send data packets with different encapsulation formats. The class codes, protocol stacks, and data packet encapsulation formats of the first controller 601 and the second controller 602 will be described below.

[0116] Figure 7 A schematic diagram of the registers in the first controller provided in an embodiment of this disclosure, with reference to... Figure 7 The first controller 601 may include a first class code register 6011, which can be configured to store a first class code. The first class code can be configured to indicate that the first controller 601 is a PCIe PF1 supported controller and that the first controller 601 supports sending a first data packet.

[0117] In some specific examples, the class code in the first category code can be 01h, the subclass code can be 08h, and the programming interface code can be 04h.

[0118] Figure 8 This is a schematic diagram of the protocol stack supported by the first controller and the PCIe interface in the memory system provided in this embodiment of the disclosure. (Refer to...) Figure 8The protocol stack may include a first layer 611, a second layer 612, a third layer 613, and a fourth layer 614, and its functions can be implemented through the first controller 601 and the PCIe interface 5012. The first layer 611 can be the application layer defined by the NVMe protocol, and can generate NVMe commands and data; the second layer 612 can be the transport layer defined by the Non-Volatile Memory Express over Transmission Control Protocol (NVMe / TCP), and can generate Protocol Data Units (PDUs) encapsulating NVMe commands and / or data, i.e., NVMe / TCP PDUs; the third layer 613 can generate VDM_NVME TLPs (Transaction Layer Packets), which can be data packets encapsulated in a vendor-defined message (VDM) format based on the PCIe protocol and containing NVMe / TCP PDUs; the fourth layer 614 can be the physical layer and data link layer defined by the PCIe protocol, and can receive or send VDM_NVME TLPs. In the above embodiment, the first data packet generated by the first controller 601 can be a VDM_NVME TLP.

[0119] Figure 9 This is a schematic diagram of a first data packet provided in an embodiment of the present disclosure. The first data packet 700 may include a first message header 701 and a first payload 702. The first message header 701 is encapsulated according to the PCIe protocol format, including a message TLP header of three double words (DW) and a custom header (NVMe over VDM HDR) of one double word. The first payload 702 includes a first data unit encapsulated according to another protocol format. Here, the other protocol format is the PDU format defined by the NVMe / TCP protocol, and the first data unit can be an NVMe / TCP PDU.

[0120] In some specific examples, the value of the Fmt field in the first message header 701 can be configured to "011", indicating that the first message header 701 includes four double words and that the first payload 702 of the first data packet 700 encapsulates data (i.e., NVMe / TCP PDU); the value of the Type field in the first message header 701 can be configured to indicate that the first data packet 700 is sent using identifier-based routing; the value of the VDM type field in the first message header 701 can be configured to "01111111", indicating that the first data packet 700 belongs to VDM Type 1; the value of the Vendor ID field in the first message header 701 can be configured to indicate that the first data packet 700 is a data packet compatible with both NVMe / PCIe and NVMe / TCP protocols; the Destination Port field in the first message header 701 conforms to the definition of the NVMe / TCP protocol, and its value can be configured to indicate the port number of the device receiving the first data packet 700; the Source field in the first message header 701... The Port field conforms to the definition of the NVMe / TCP protocol, and its value can be configured to indicate the port number of the storage system 500; the value of the LLEN field in the first message header 701 can be configured to indicate the length of the valid information in the last double word in the first payload 702.

[0121] It should be noted that the first message header 701 also includes fields not mentioned in the above embodiments. The definitions and functions of these fields conform to the PCIe protocol specifications, and will not be elaborated here.

[0122] In some embodiments, the second controller 602 includes a second category code register, which is configured to store a second category code that is different from the first category code.

[0123] In some specific examples, the class code in the second category code can be 01h, the subclass code can be 08h, and the programming interface code can be 02h, indicating that the second controller 602 is a PCIe PF0 supported input / output controller (I / O controller), and that the second controller 602 supports receiving and sending NVMe / PCIe TLPs. Here, the NVMe / PCIe TLP is a transaction layer data packet encapsulated according to the PCIe protocol format and containing NVMe commands and / or data. The second data packet generated and sent by the second controller 602 can be an NVMe / PCIe TLP.

[0124] In this embodiment, the second controller 602 and the PCIe interface 5012 can implement the NVMe over PCIe protocol stack. The specific layer division of the protocol stack conforms to the NVMe over PCIe protocol specification, which will not be described in detail here.

[0125] In some specific examples, the second data packet may include a second header and a second payload, both of which are encapsulated in accordance with the PCIe protocol format. The specific format conforms to the PCIe protocol specification and will not be elaborated here.

[0126] In some specific examples, the encapsulation format of the second data packet differs from that of the first data packet mainly in that the first payload portion of the first data packet is a first data unit encapsulated in the NVMe / TCP PDU format, while the second payload portion of the second data packet is data and / or command information encapsulated in the PCIe protocol format.

[0127] In this embodiment, the memory system includes a first controller and a second controller. The first controller can receive and send VDM_NVME TLP via a PCIe interface, and the second controller can receive and send NVMe / PCIe TLP via a PCIe interface. This enables compatibility with NVMe / PCIe and NVMe / TCP protocols, allowing the memory system with a PCIe interface to support the NVMe-oF protocol. This allows it to directly establish communication connections with other non-volatile memory subsystems that support the NVMe-oF protocol, reducing the consumption of operating system resources and facilitating the expansion and improvement of system performance.

[0128] In this embodiment, for controllers supported by PCIe PF0 (e.g., the second controller 602) and controllers supported by PCIe PF1 (e.g., the first controller 601), in addition to differences in class codes, supported protocol stacks, and supported packet encapsulation formats, different base address registers (BARs) need to be configured to support different physical functions. The BAR in the PCIe PF0 supported controller conforms to the NVMe over PCIe protocol specification, which will not be elaborated here. Below, taking the first controller 601 as an example, the specific configuration of the BAR in the PCIe PF1 supported controller and the specific functions that the PCIe PF1 supported controller can achieve based on the BAR configuration will be described.

[0129] Return to reference Figure 7The BAR in the first controller 601 may include a first register group 6012, a second register group 6013 and a third register group 6014, wherein the first register group 6012 may be a control register, the second register group 6013 may be a status register and the third register group 6014 may be a capability register.

[0130] In some embodiments, the first register group 6012 includes a first flag bit in the above embodiments. The first controller 601 can configure the first flag bit to an enabled state in response to a configuration command, and receive or send VDM_NVME TLP when the first flag bit is in an enabled state.

[0131] In some specific examples, the length of the first flag bit can be 1 bit. When the first flag bit is set to either "1" or "0", the first flag bit is in an enabled state, and the first controller 601 can receive or send VDM_NVMETLP; when the first flag bit is set to either "1" or "0", the first flag bit is in an disabled state, and the first controller 601 cannot receive or send VDM_NVME TLP.

[0132] In this embodiment of the disclosure, the function of the first controller 601 to receive or send VDM_NVME TLP can be enabled or disabled, thereby allowing the memory system 500 to be flexible in its compatibility with the NVMe-oF protocol.

[0133] In some embodiments, when the first flag bit of the first controller 601 is enabled, the memory system 500 can establish a connection with the host or a peer device via VDM_NVME TLP. Here, the peer device may belong to another non-volatile memory subsystem and include a PCIe interface. The memory system 500 and the host, as well as the memory system and the peer device, can be connected via the PCIe bus.

[0134] In some embodiments, before sending the first data packet through the PCIe interface 5012, the first controller 601 is further configured to: receive a third data packet through the PCIe interface 5012; the encapsulation format of the third data packet is the same as that of the first data packet; the third data packet includes a second data unit encapsulated in the format of NVMe / TCP PDU, and the second data unit includes a connection request; the first data unit includes response information for the connection request.

[0135] In some specific examples, the third data packet can be a VDM_NVME TLP sent by the host or peer device to the memory system 500, and the first controller 601 can receive the third data packet through the PCIe interface 5012. The second data unit in the third data packet can be an NVMe-TCP Initialization Connection Request Protocol Data Unit (NVMe-TCP ICReq PDU) or an NVMe-oF Connection Request Protocol Data Unit (NVMe-oF connect Req PDU). When the second data unit is an NVMe-TCP ICReq PDU, the first data unit can be an NVMe-TCP Initialization Connection Response Protocol Data Unit (NVMe-TCPICResp PDU), which includes response information for the NVMe-TCP initialization connection request. Through the interaction of a first data packet including the first data unit and a second data packet including the second data unit, the first controller 601 can complete the NVMe-TCP initialization connection with the host or peer device. When the second data unit is an NVMe-oF connect Req PDU, the first data unit can be an NVMe-oF connection response protocol data unit (NVMe-oF connect Resp PDU), which includes response information for the NVMe-oF connection request. Through the interaction of a first data packet including the first data unit and a second data packet including the second data unit, the first controller 601 can establish an NVMe-oF connection with the host or peer device.

[0136] In some embodiments, the first register group 6012 is further configured to store the identifier of the peer device; the first controller 601 is further configured to: obtain the identifier of the peer device from the first register group 6012 and encapsulate the identifier of the peer device in a first data packet; and send the first data packet to the peer device through the PCIe interface 5012.

[0137] In some specific examples, the first register group 6012 can store a BDF list, which includes identifiers of multiple peer devices that can establish a connection with the memory system 500 via VDM_NVME TLP. The identifiers of the peer devices can include the peer device's bus number, device number, and function number. (See reference...) Figure 9 The first controller 601 can configure the value of the Destination ID field in the first data packet 700 as the identifier of the peer device, and can configure the value of the Requester ID field as the identifier of the memory system 500.

[0138] In this embodiment of the disclosure, the controller supported by PCIe PF1 can send the first data packet using an identifier-based routing method. The first data packet can be encapsulated with the identifier of the memory system and the identifier of the peer device receiving the first data packet. This enables the memory system and the peer device to correctly transmit NVMe commands and / or data, satisfying the reliability and ordering requirements of the NVMe / TCP protocol for message interaction.

[0139] In some embodiments, the first controller 601 is further configured to store the connection status between the first controller 601 and the peer device in the second register group 6013. Here, the connection status between the first controller 601 and the peer device may include, but is not limited to, whether the first controller 601 is connected to the peer device and information about the peer device connected to the first controller 601.

[0140] In some embodiments, in conjunction with reference Figure 6 and Figure 7 The memory system 500 also includes at least one third controller 603, and the third register group 6014 in the first controller 601 includes a second flag bit; the first controller 601 is also configured to: configure the value of the second flag bit to indicate that the first controller 601 is in the state of a discovery controller; and store the number of third controllers 603 included in the memory system 500 and the port information of the third controllers 603 in the third register group 6014.

[0141] In some embodiments, the third controller 603 includes a third category code register configured to store a first category code. Here, the category code stored in the third category code register of the third controller 603 is the same as the category code stored in the first category code register of the first controller 601, and the third controller 603 can be an I / O controller supported by PCIe PF1.

[0142] It should be noted that the third controller 603 may include the same register configuration as the first controller 601, that is, the third controller 603 also includes a controller register, a status register, and a capability register. However, the values ​​stored in the registers of the third controller 603 may differ from the values ​​stored in the registers of the first controller 601. For example, the capability register of the third controller 603 may also include a second flag bit, and the value of the second flag bit in the third controller 603 may differ from the value of the second flag bit in the first controller 601. The value of the second flag bit in the third controller 603 can be configured to indicate that the third controller 603 is not in a discoverer state. Thus, functional differentiation between the first controller 601 and the third controller 603 can be achieved.

[0143] In this embodiment, the PCIe PF1 can support a discovery controller (first controller 601) and an I / O controller (third controller 603). The interaction phase between the controllers supported by the PCIe PF1 and the host can include a discovery phase and an I / O operation phase. Specifically, in the discovery phase, the host can obtain relevant information about the third controller 603 stored in the third register group 6014 of the first controller 601, and the host can connect to the third controller 603 based on this information. In the I / O operation phase, the host can perform actual I / O operations through the third controller 603, and the third controller 603 can respond to commands from the host and perform data transmission. Similarly, when the memory system 500 directly establishes a connection with a peer device, the peer device can also obtain relevant information about the third controller 603 from the first controller 601 and establish a connection with the third controller 603, enabling data to be transmitted between the third controller 603 and the peer device.

[0144] In some embodiments, the third controller 603 is configured to: send a fourth data packet via the PCIe interface 5012; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated in the format of NVMe / TCP PDU.

[0145] In some specific examples, Figure 10 This is a schematic diagram of the fourth data packet provided in an embodiment of the present disclosure. The encapsulation format of the fourth data packet 800 is the same as that of the first data packet 700. The fourth data packet 800 includes a third message header 801 and a third payload 802. The third payload 802 includes a third data unit encapsulated according to the NVMe / TCP PDU format. Here, the third data unit may include header information CH, header information checksum HDGST, data information PDATA, and data information checksum DDGST.

[0146] In some embodiments, in conjunction with reference Figure 10 and Figure 6The memory system 500 also includes a memory device 502, and a second controller 602 and a third controller 603 are both coupled to the memory device 502. The third controller 603 is further configured to: obtain first data information from the memory device 502; encapsulate the first data information in a third data unit; and encapsulate the third data unit in the third payload 802 of the fourth data packet 800. The second controller 602 is further configured to: obtain second data information from the memory device 502; and encapsulate the second data information in the second payload of the second data packet. Here, the first data information can be encapsulated in the data information PDATA portion of the third data unit.

[0147] In this embodiment of the disclosure, I / O controllers that support different PCIe physical functions in the memory system 500 can share the storage resources in the memory system 500. Specifically, the second controller 602 and the third controller 603 can both be coupled to the memory device 502 and obtain data from the memory device 502 or store data in the memory device 502.

[0148] In some specific examples, the second controller 602 and the third controller 603 are both front-end controllers in the memory controller. In this case, the second controller 602 and the third controller 603 can share a back-end controller and interact with the memory device 502 through the back-end controller.

[0149] In some specific examples, both the second controller 602 and the third controller 603 have the functions of a front-end controller and a back-end controller, so both the second controller 602 and the third controller 603 can directly interact with the memory device 502.

[0150] In some embodiments, refer to Figure 6 PCIe PF0 can also support Virtual Functions (VF). Specifically, the memory system 500 can also include a fourth controller, which can be an I / O controller supported by PCIe VF0. The fourth controller can share the storage resources in the memory system 500 with the second controller 602 and the third controller 603, and can receive and send NVMe / PCIe TLP through the PCIe interface 5012 to establish a communication connection with the virtual machine.

[0151] It should be noted that, Figure 6 The number of controllers supported by PCIe PF0 and PCIe PF1 are merely examples, and this disclosure does not impose any specific limitations on them.

[0152] In some embodiments, the memory system 500 includes a solid-state drive with a PCIe interface 5012, and the solid-state drive includes a first controller 601 and a second controller 602.

[0153] In this embodiment, the memory system includes a first controller and a second controller coupled to a PCIe interface. The first controller is configured to generate and send a first data packet via the PCIe interface. The first data packet can be VDM_NVME TLP, which may include a first data unit encapsulated in the format of NVMe / TCP PDU. The second controller can generate and send a second data packet via the PCIe interface. The second data packet can be NVMe / PCIe TLP. This enables compatibility with NVMe / PCIe and NVMe / TCP protocols, allowing the memory system with a PCIe interface to support the NVMe-oF protocol, thereby expanding the application scenarios of the memory system.

[0154] Based on a concept similar to the memory system described above, this disclosure also provides a system. Figure 11 A schematic diagram of a system provided according to an embodiment of this disclosure. (See reference 1) Figure 6 and Figure 10 System 90 includes a host 900 and a memory system 500. The memory system 500 includes a PCIe interface 5012, a first controller 601, and a second controller 602. The memory system 500 is coupled to the host 900 via the PCIe interface 5012. Both the first controller 601 and the second controller 602 are coupled to the PCIe interface 5012. The host 900 is configured to send a configuration command. The configuration command instructs the first flag bit in the first controller 601 to be configured to be enabled. The first controller 601 is configured to: in response to the configuration command, configure the first flag bit to be enabled; in response to the first flag bit being enabled, generate a first data packet and send the first data packet via the PCIe interface 5012. The second controller 602 is configured to: generate a second data packet and send the second data packet via the PCIe interface 5012. The encapsulation format of the second data packet is different from that of the first data packet. Here, the memory system 500 can be any of the memory systems 500 provided in the above embodiments.

[0155] In some embodiments, refer to Figure 9The first data packet 700 includes a first header 701 and a first payload 702; the first header 701 is encapsulated according to the PCIe protocol format, and the first payload 702 includes a first data unit encapsulated according to a different protocol format than the PCIe protocol format; the second data packet includes a second header and a second payload; both the second header and the second payload are encapsulated according to the PCIe protocol format. Here, the other protocol format is the PDU format defined by the NVMe / TCP protocol, and the first data unit can be an NVMe / TCP PDU.

[0156] In some embodiments, the first controller 601 includes a first category code register; the second controller 602 includes a second category code register; the first category code register is configured to store a first category code, and the second category code register is configured to store a second category code different from the first category code; the first category code indicates that the first controller supports sending a first data packet; the host 900 is also configured to: query the value stored in the first category code register and the value stored in the second category code register; and generate a configuration command based on the value stored in the first category code register as the first category code.

[0157] In some embodiments, in conjunction with reference Figure 6 and Figure 7 The memory system 500 also includes at least one third controller 603; the third controller 603 is coupled to the PCIe interface 5012.

[0158] In some embodiments, the third controller 603 includes a third category code register; the third category code register is configured to store a first category code.

[0159] Figure 12 This is a schematic diagram illustrating the connection between a memory system, a host, and a peer device in a system provided as a specific example of this disclosure. (Refer to...) Figure 7 , Figure 11 and Figure 12In step 1001 of the initialization phase, the host 900 can obtain the values ​​stored in the class code registers of multiple controllers in the memory system 500, such as the value stored in the first class code register of the first controller 601, the value stored in the second class code register of the second controller 602, and the value stored in the third class code register of the third controller 603. Based on the values ​​stored in the first and third class code registers, the host 900 determines that the first controller 601 and the third controller 603 are PCIe PF1 supported controllers, and that the first controller 601 and the third controller 603 support receiving and transmitting VDM_NVME TLP. In step 1002 of the initialization phase, the host 900 can configure the I / O controllers. Specifically, the host 900 can configure the I / O controllers supported by PCIe PF0 (e.g., the second controller 602) and the I / O controllers supported by PCIe PF0 (e.g., the third controller 603). In step 1003 of the initialization phase, host 900 can enable the transmission and reception of VDM_NVME TLP. Specifically, host 900 can generate and send a configuration command that indicates that the first flag bit in the first controller 601 is configured to the enabled state. In response to the configuration command, the first controller 601 can configure the value of the first flag bit to the enabled state.

[0160] In some embodiments, the first controller 601 is further configured to receive a third data packet via the PCIe interface 5012 before sending the first data packet via the PCIe interface 5012; the encapsulation format of the third data packet is the same as that of the first data packet; the third data packet includes a second data unit encapsulated in the format of NVMe / TCP PDU, and the second data unit includes a connection request; the first data unit includes response information for the connection request.

[0161] In some embodiments, refer to Figure 11 The system 90 also includes at least one peer device 910; the memory system 500 is coupled to the peer device 910 via a PCIe interface 5012. Here, the peer device 910 may include a PCIe interface 911, and the PCIe interface 911 of the peer device 910 may be coupled to the PCIe interface 5012 of the memory system 500 via a PCIe bus.

[0162] In some specific examples, in conjunction with reference Figure 11 and Figure 12During the VDM_NVME connection phase, the memory system 500 can establish a VDM_NVME connection with the host 900 or the peer device 910. Specifically, the third data packet can be the VDM_NVME TLP including the NVMe-TCP ICReq PDU sent by the host 900 or the peer device 910 to the memory system 500 in step 1004. In this case, the first data packet can be the VDM_NVME TLP including the NVMe-TCP ICResp PDU. Through the interaction of the first data packet and the second data packet, the first controller 601 can complete the NVMe-TCP initial connection with the host 900 or the peer device 910. Alternatively, the third data packet can be the VDM_NVME TLP including the NVMe-oF connect Req PDU sent by the host 900 or the peer device 910 to the memory system 500 in step 1005. In this case, the first data packet can be the VDM_NVME TLP including the NVMe-oF connect Resp PDU. Through the interaction of the first data packet and the second data packet, the first controller 601 can establish an NVMe-oF connection with the host 900 or the peer device 910.

[0163] In some embodiments, system 90 may include a first non-volatile memory subsystem (NVM Subsystem A) and a second non-volatile memory subsystem (NVM Subsystem B); the first non-volatile memory subsystem includes memory system 500, and the second non-volatile memory subsystem includes peer device 910.

[0164] In this embodiment of the disclosure, different non-volatile memory subsystems in the system can establish a communication connection through VDM_NVMETLP, so data can be directly transmitted between the non-volatile memory subsystems, thereby reducing the resource consumption of the host operating system and facilitating the expansion and improvement of system performance.

[0165] In some embodiments, in conjunction with reference Figure 7 and Figure 11 The first controller 601 includes a first register group 6012; the first register group 6012 includes a first flag bit; the first register group 6012 is also configured to store the identifier of the peer device 910; the first controller 601 is also configured to: obtain the identifier of the peer device 910 from the first register group 6012, and encapsulate the identifier of the peer device 910 in a first data packet.

[0166] In some embodiments, in conjunction with reference Figure 7 and Figure 11The first controller 601 includes a second register group 6013. The first controller 601 is also configured to store the connection status between the first controller 601 and the peer device 910 in the second register group 6013. The host 900 is also configured to query the second register group 6013 to obtain the connection status between the first controller 601 and the peer device 910.

[0167] In some embodiments, in conjunction with reference Figure 6 and Figure 7 The first controller 601 also includes a third register group 6014; the third register group 6014 includes a second flag bit; the first controller 601 is further configured to: configure the value of the second flag bit to indicate that the first controller 601 is in the state of discovering the controller; and store the number of third controllers 603 included in the memory system 500 and the port information of the third controllers 603 in the third register group 6014; the host 900 is further configured to: query the third register group 6014 to obtain the number of third controllers 603 and the port information of the third controllers 603.

[0168] In this embodiment of the disclosure, the controller supported by PCIe PF1 can provide a management window for the host 900. Specifically, taking the first controller 601 as an example, the first controller 601 includes a first register group 6012, a second register group 6013, and a third register group 6014. The first register group 6012 includes a first flag bit. The host can control the enable state of receiving or sending VDM_NVME TLP function by configuring the value of the first flag bit. In addition, the first controller 601 can act as a discovery controller for the host 900. The host 900 can obtain the connection status between the first controller 601 and the peer device by querying the second register group 6013. It can also obtain relevant information of the third controller 603 by querying the third register group 6014, and can establish a connection with the third controller 603 based on the relevant information of the third controller 603.

[0169] In some embodiments, the third controller 603 is configured to send a fourth data packet via the PCIe interface 5012; the encapsulation format of the fourth data packet is the same as that of the first data packet. (Refer to...) Figure 10 The fourth data packet 800 includes a third header 801 and a third payload 802; the third payload 802 includes a third data unit encapsulated in the format of NVMe / TCP PDU.

[0170] In some embodiments, in conjunction with reference Figure 6 and Figure 10The memory system 500 also includes a memory device 502; the second controller 602 and the third controller 603 are both coupled to the memory device 502; the third controller 603 is further configured to: obtain first data information from the memory device 502; encapsulate the first data information in a third data unit; encapsulate the third data unit in a third payload 802; the second controller 602 is further configured to: obtain second data information from the memory device 502; encapsulate the second data information in a second payload.

[0171] In this embodiment, the memory system includes a first controller and a second controller coupled to a PCIe interface. The first controller, configured by the host, can generate and send a first data packet via the PCIe interface. The first data packet can be VDM_NVME TLP, which may include a first data unit encapsulated in the NVMe / TCP PDU format. The second controller can generate and send a second data packet via the PCIe interface. The second data packet can be NVMe / PCIe TLP. This enables the memory system with a PCIe interface to be compatible with the NVMe-oF protocol and to directly establish connections with other non-volatile memory subsystems in the system that support the NVMe-oF protocol, reducing the occupation of operating system resources and facilitating the expansion and improvement of system performance.

[0172] Based on a concept similar to the memory system described above, this disclosure also provides a method for operating a memory system. Figure 13 This is a flowchart illustrating an operation method of a memory system provided in an embodiment of this disclosure. The operation method of the memory system includes the following steps:

[0173] Step S10: In response to the configuration command, configure the first flag bit in the first controller to the enabled state;

[0174] Step S20: In response to the first flag being enabled, generate the first data packet and send the first data packet through the PCIe interface;

[0175] Step S30: Generate a second data packet and send the second data packet through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

[0176] In some embodiments, the method of operating the memory system further includes: receiving a third data packet via the PCIe interface before sending the first data packet via the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the first data packet includes a first data unit encapsulated according to a different protocol format than the PCIe protocol format; the third data packet includes a second data unit encapsulated according to another protocol format; the second data unit includes a connection request; and the first data unit includes response information for the connection request.

[0177] In some embodiments, the method of operating the memory system further includes: obtaining the identifier of the peer device from the first register group of the first controller and encapsulating the identifier of the peer device in a first data packet; and sending the first data packet to the peer device through the PCIe interface.

[0178] In some embodiments, the method of operating the memory system further includes storing the connection state between the first controller and the peer device in a second register group of the first controller.

[0179] In some embodiments, the method of operating the memory system further includes: configuring the value of a second flag bit in the third register group of the first controller to indicate that the first controller is in the state of a discovery controller; and storing the number of third controllers and port information of the third controllers in the third register group.

[0180] In some embodiments, the method of operating the memory system further includes: sending a fourth data packet via a PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to another protocol format.

[0181] In some embodiments, the method of operating the memory system further includes: obtaining first data information from a memory device; encapsulating the first data information in a third data unit and encapsulating the third data unit in a third payload; and obtaining second data information from a memory device; and encapsulating the second data information in a second payload of a second data packet.

[0182] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0183] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0184] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory system, characterized in that, It includes a PCIe interface, a first controller, and a second controller; both the first controller and the second controller are coupled to the PCIe interface; The first controller is configured to: in response to a configuration command, configure a first flag bit in the first controller to an enabled state; In response to the first flag being in the enabled state, a first data packet is generated and sent through the PCIe interface; The second controller is configured to generate a second data packet and send the second data packet through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

2. The memory system according to claim 1, characterized in that, The first data packet includes a first message header and a first payload; the first message header is encapsulated according to the PCIe protocol format, and the first payload includes a first data unit encapsulated according to another protocol format different from the PCIe protocol format; The second data packet includes a second header and a second payload; both the second header and the second payload are encapsulated according to the PCIe protocol format.

3. The memory system according to claim 2, characterized in that, The first controller includes a first category code register; the second controller includes a second category code register; the first category code register is configured to store a first category code, and the second category code register is configured to store a second category code that is different from the first category code; The first category code indicates that the first controller supports sending the first data packet.

4. The memory system according to claim 2, characterized in that, The first controller is also configured to: Before sending the first data packet through the PCIe interface, a third data packet is received through the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the third data packet includes a second data unit encapsulated according to the other protocol format, and the second data unit includes a connection request; the first data unit includes response information for the connection request.

5. The memory system according to claim 1, characterized in that, The first controller includes a first register group; the first register group includes the first flag bit; the first register group is further configured to store an identifier of the peer device; the first controller is further configured to: The identifier of the peer device is obtained from the first register group, and the identifier of the peer device is encapsulated in the first data packet; and The first data packet is sent to the peer device through the PCIe interface.

6. The memory system according to claim 5, characterized in that, The first controller further includes a second register group; the first controller is also configured to: The connection status between the first controller and the peer device is stored in the second register group.

7. The memory system according to claim 3, characterized in that, The memory system further includes at least one third controller; the third controller is coupled to the PCIe interface; the first controller further includes a third register group; the third register group includes a second flag bit; the first controller is further configured to: Configure the value of the second flag bit to indicate that the first controller is in a discover controller state; and The number of the third controllers included in the memory system and the port information of the third controllers are stored in the third register group.

8. The memory system according to claim 7, characterized in that, The third controller includes a third category code register; the third category code register is configured to store the first category code.

9. The memory system according to claim 7, characterized in that, The third controller is configured as follows: A fourth data packet is sent through the PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to the other protocol format.

10. The memory system according to claim 9, characterized in that, The memory system further includes a memory device; both the second controller and the third controller are coupled to the memory device; The third controller is further configured to: acquire first data information from the memory device; encapsulate the first data information in the third data unit; and encapsulate the third data unit in the third payload. The second controller is further configured to: obtain second data information from the memory device; and encapsulate the second data information in the second payload.

11. The memory system according to claim 2, characterized in that, The other protocol format includes the format of the protocol data unit defined by the Non-Volatile Memory Fast Channel / Transmission Control Protocol.

12. The memory system according to claim 1, characterized in that, The memory system includes a solid-state drive with the PCIe interface; the solid-state drive includes the first controller and the second controller.

13. A system, characterized in that, It includes a host and a memory system; the memory system includes a PCIe interface, a first controller, and a second controller; the memory system is coupled to the host through the PCIe interface; both the first controller and the second controller are coupled to the PCIe interface; The host is configured to send configuration commands; The configuration command instructs the first flag bit in the first controller to be configured to the enabled state; The first controller is configured to: in response to the configuration command, configure the first flag bit to the enabled state; In response to the first flag being in the enabled state, a first data packet is generated and sent through the PCIe interface; The second controller is configured to generate a second data packet and send the second data packet through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

14. The system according to claim 13, characterized in that, The first data packet includes a first message header and a first payload; the first message header is encapsulated according to the PCIe protocol format, and the first payload includes a first data unit encapsulated according to another protocol format different from the PCIe protocol format; The second data packet includes a second header and a second payload; both the second header and the second payload are encapsulated according to the PCIe protocol format.

15. The system according to claim 14, characterized in that, The first controller includes a first category code register; the second controller includes a second category code register; the first category code register is configured to store a first category code, and the second category code register is configured to store a second category code different from the first category code; the first category code indicates that the first controller supports sending the first data packet; the host is further configured to: Query the values ​​stored in the first category code register and the second category code register; as well as The configuration command is generated based on the value stored in the first category code register, which is the first category code.

16. The system according to claim 14, characterized in that, The first controller is also configured to: Before sending the first data packet through the PCIe interface, a third data packet is received through the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the third data packet includes a second data unit generated according to the other protocol format, and the second data unit includes a connection request; the first data unit includes response information for the connection request.

17. The system according to claim 13, characterized in that, The system further includes at least one peer device; the memory system is coupled to the peer device via the PCIe interface; the first controller includes a first register group; the first register group includes a first flag bit; the first register group is further configured to store an identifier of the peer device; the first controller is further configured to: The identifier of the peer device is obtained from the first register group, and the identifier of the peer device is encapsulated in the first data packet; and The first data packet is sent to the peer device through the PCIe interface.

18. The system according to claim 17, characterized in that, The first controller also includes a second register group; The first controller is also configured to store the connection status between the first controller and the peer device in the second register group; The host is also configured to query the second register group to obtain the connection status between the first controller and the peer device.

19. The system according to claim 17, characterized in that, The system includes a first non-volatile memory subsystem and a second non-volatile memory subsystem; the first non-volatile memory subsystem includes the memory system; the second non-volatile memory subsystem includes the peer device.

20. The system according to claim 15, characterized in that, The memory system further includes at least one third controller; the third controller is coupled to the PCIe interface; the first controller further includes a third register group; the third register group includes a second flag bit; The first controller is further configured to: configure the value of the second flag bit to indicate that the first controller is in the state of a discovery controller; and store the number of the third controllers included in the memory system and the port information of the third controllers in the third register group; The host is also configured to query the third register group to obtain the number of the third controllers and the port information of the third controllers.

21. The system according to claim 20, characterized in that, The third controller includes a third category code register; the third category code register is configured to store the first category code.

22. The system according to claim 20, characterized in that, The third controller is configured as follows: A fourth data packet is sent through the PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to the other protocol format.

23. The system according to claim 22, characterized in that, The memory system further includes a memory device; both the second controller and the third controller are coupled to the memory device; The third controller is further configured to: acquire first data information from the memory device; encapsulate the first data information in the third data unit; and encapsulate the third data unit in the third payload. The second controller is further configured to: obtain second data information from the memory device; and encapsulate the second data information in the second payload.

24. The system according to claim 14, characterized in that, The other protocol format includes the format of the protocol data unit defined by the Non-Volatile Memory Fast Channel / Transmission Control Protocol.

25. A method for operating a memory system, characterized in that, include: In response to the configuration command, the first flag bit in the first controller is configured to be enabled; In response to the first flag being in the enabled state, a first data packet is generated and sent through the PCIe interface; as well as A second data packet is generated and sent through the PCIe interface; the encapsulation format of the second data packet is different from that of the first data packet.

26. The method of operating the memory system according to claim 25, characterized in that, The operation method further includes: Before sending the first data packet through the PCIe interface, a third data packet is received through the PCIe interface; the encapsulation format of the third data packet is the same as that of the first data packet; the first data packet includes a first data unit encapsulated according to a different protocol format than the PCIe protocol format; the third data packet includes a second data unit encapsulated according to the other protocol format; the second data unit includes a connection request; the first data unit includes response information for the connection request.

27. The method of operating the memory system according to claim 25, characterized in that, The operation method further includes: The identifier of the peer device is obtained from the first register group of the first controller, and the identifier of the peer device is encapsulated in the first data packet; and The first data packet is sent to the peer device through the PCIe interface.

28. The method of operating the memory system according to claim 27, characterized in that, The operation method further includes: The connection status between the first controller and the peer device is stored in the second register group of the first controller.

29. The method of operating a memory system according to claim 26, characterized in that, The operation method further includes: Configure the value of the second flag bit in the third register group of the first controller to indicate that the first controller is in the state of a discovered controller; and The number of third controllers and the port information of the third controllers are stored in the third register group.

30. The method of operating the memory system according to claim 29, characterized in that, The operation method further includes: A fourth data packet is sent through the PCIe interface; the encapsulation format of the fourth data packet is the same as that of the first data packet; the fourth data packet includes a third header and a third payload; the third payload includes a third data unit encapsulated according to the other protocol format.

31. The method of operating the memory system according to claim 30, characterized in that, The operation method further includes: Obtain first data information from a memory device; encapsulate the first data information in the third data unit, and encapsulate the third data unit in the third payload; and The second data information is obtained from the memory device; the second data information is encapsulated in the second payload of the second data packet.

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