A double-stage buffer-based cross-clock-domain data transmission method and system

Abstract

The application relates to the technical field of digital communication and integrated circuit design, and discloses a cross-clock-domain data transmission method and system based on double-stage buffering. The cross-clock-domain data transmission method based on double-stage buffering comprises the following steps: in a first clock domain, data source data and corresponding protocol fields are assembled word by word and sequentially written into a first-stage buffer to form a complete protocol frame; the complete protocol frame is moved as a whole to a second-stage buffer, the second-stage buffer stores only one complete protocol frame at any time, after the moving of the complete protocol frame as a whole is completed, a frame ready signal is sent to a second clock domain to trigger the sending of the complete protocol frame by the second clock domain; and according to a sending completion signal of the second clock domain, the storage space occupied by the moved frame in the first-stage buffer is released. The application can improve the frame integrity of cross-clock-domain data transmission and enhance the transmission reliability of the system.

Description

Technical Field

[0001] This invention relates to the fields of digital communication and integrated circuit design technology, and in particular to a method and system for cross-clock domain data transmission based on a two-level buffer. Background Technology

[0002] In embedded systems and high-speed data acquisition devices, clock domain differences are common between the data source (such as UART, SPI, or parallel interface) and the high-speed serial link (such as LVDS). Their operating clocks often have different frequencies and are independent of each other. When data is transmitted across clock boundaries, without a reliable frame-level synchronization mechanism, the transmitting end cannot accurately convey the timing information indicating that the frame data is fully ready to the receiving clock domain. The receiving end may initiate reading before the frame structure is fully formed, resulting in incomplete acquisition of frame data and making transmission reliability difficult to guarantee.

[0003] In application scenarios requiring protocol encapsulation of data, the sending end must sequentially add frame header fields, status word fields, user data fields, and length fields to the original data to form a complete protocol frame before subsequent processing can proceed. The assembly process of the protocol frame is continuous, and the integrity of the frame structure is a fundamental prerequisite for the receiving end to correctly parse the data. If the buffer allows reading across clock domains before the frame structure is fully written, the receiving end will obtain an incomplete frame, leading to protocol parsing failure.

[0004] Existing solutions typically employ a single-level asynchronous FIFO to achieve cross-clock domain transmission. A single-level asynchronous FIFO performs read and write operations on a word-by-word basis and lacks frame integrity awareness, failing to guarantee that cross-clock domain read operations are performed at the granularity of complete protocol frames. In scenarios where both protocol assembly and clock domain isolation must be satisfied simultaneously, a single buffer structure struggles to address both, posing a risk of incomplete frame data reading.

[0005] Therefore, there is an urgent need to propose a cross-clock domain data transmission method and system based on two-level buffering to solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to propose a method and system for cross-clock domain data transmission based on two-level buffering, which can improve the frame integrity of cross-clock domain data transmission and enhance the system transmission reliability.

[0007] To address the aforementioned technical problems, this invention provides a method for cross-clock domain data transmission based on a two-level buffer, comprising the following: Within the first clock domain, the data source data is assembled word by word with the corresponding protocol fields and written sequentially into the first-level buffer to form a complete protocol frame; The complete protocol frame is moved to the second-level buffer. The second-level buffer stores only one complete protocol frame at any given time. After the entire frame is moved, a frame ready signal is sent to the second clock domain to trigger the second clock domain to send the complete protocol frame. Based on the completion signal of the second clock domain, release the storage space occupied by the moved frames in the first-level buffer.

[0008] Furthermore, the step of assembling the data source data and the corresponding protocol fields word by word and writing them sequentially into the first-level buffer within the first clock domain specifically includes: the data source includes multiple data sources; within the first clock domain, each data source is polled sequentially according to a preset polling scheduling strategy, and the data from each data source is assembled word by word with the corresponding protocol fields and written sequentially into the first-level buffer.

[0009] Furthermore, before assembling the data source data and the corresponding protocol fields word by word and writing them sequentially into the first-level buffer, the process includes: detecting whether the remaining storage space in the first-level buffer is not less than the maximum length of a single frame; if the space is insufficient, pausing polling and writing until the space condition is met and then continuing.

[0010] Furthermore, the step of sending the frame ready signal to the second clock domain includes: transmitting the frame ready signal to the second clock domain after synchronization through at least two levels of serial registers, so as to eliminate cross-clock domain metastability.

[0011] Furthermore, the step of releasing the storage space occupied by the moved frame in the first-level buffer according to the transmission completion signal of the second clock domain specifically includes: synchronizing the transmission completion signal to the first clock domain through at least two levels of serial registers, and performing rising edge detection on the synchronized signal to trigger the release operation based on the rising edge detection result.

[0012] Furthermore, the second-level buffer includes a dual-port memory with a write port and a read port; the write port operates in the first clock domain, and the read port operates in the second clock domain; the whole frame shift is completed through the write port, and the transmission of the complete protocol frame is completed through the read port.

[0013] Furthermore, the complete protocol frame includes a frame header field, a status word field, a user data field, and a length field; the word-by-word assembly step writes the frame header field, status word field, user data field, and length field sequentially into the first-level buffer.

[0014] Furthermore, this invention proposes a cross-clock domain data transmission system based on a two-level buffer to implement the cross-clock domain data transmission method based on a two-level buffer as described above, including a first-level buffer, an assembly and writing module, a second-level buffer, a transfer control module, a sending module, and a space release module; The first-level buffer is located in the first clock domain and is used to cache protocol frame data during assembly and to be moved. The assembly and writing module is used to assemble the data source data with the corresponding protocol fields word by word and write them sequentially into the first-level buffer to form a complete protocol frame. The second-level buffer is used to store only one complete protocol frame at any given time; The transfer control module is used to transfer the complete protocol frame to the second-level buffer in its entirety, and send a frame ready signal to the second clock domain after the transfer is completed; The sending module is used to respond to the frame ready signal, send the complete protocol frame in the second-level buffer, and send a sending completion signal to the first clock domain after the sending is completed; The space release module is used to release the storage space occupied by the moved frames in the first-level buffer according to the transmission completion signal.

[0015] Furthermore, it also includes a signal synchronization module, which includes at least two levels of serial registers; the frame ready signal is transmitted to the second clock domain after being synchronized by the signal synchronization module; the transmission completion signal is synchronized to the first clock domain by the signal synchronization module, and after rising edge detection, it triggers the space release module to perform a release operation.

[0016] Furthermore, the second-level buffer includes a dual-port memory with a write port and a read port; the write port operates in the first clock domain, and the shift control module completes the shifting of the entire frame through the write port; the read port operates in the second clock domain, and the sending module completes the transmission of the complete protocol frame through the read port.

[0017] Through the above technical solution, the present invention has the following beneficial effects: By introducing a first-level buffer within the first clock domain to complete the word-by-word assembly of the protocol frame, and then moving the entire frame to the second-level buffer before issuing the frame ready signal, a two-level buffering mechanism is used to completely separate the protocol assembly process from the cross-clock domain transmission process. This fundamentally avoids the second clock domain from initiating a read before the frame data is complete, effectively improving the integrity of the protocol frame transmission. At the same time, the cross-clock domain handshake mechanism formed by the frame ready signal and the transmission completion signal, combined with the constraint that the second-level buffer stores only one frame at any given time, can enhance the timing controllability of cross-clock domain data transmission and improve the overall transmission reliability of the system. Attached Figure Description

[0018] Figure 1 This is a flowchart of a cross-clock domain data transmission method based on a two-level buffer in one embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the specific process of a cross-clock domain data transmission method based on a two-level buffer in one embodiment of the present invention; Figure 3 This is a block diagram of a cross-clock domain data transmission system based on a two-level buffer in one embodiment of the present invention. Detailed Implementation

[0019] Based on the teachings of this specification, those skilled in the art can form new technical solutions through cross-combination of different implementation methods without creating technical contradictions. Such variations should all be considered to fall within the protection scope of this invention.

[0020] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0021] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0022] like Figures 1-2 As shown in the figure, this invention proposes a method for cross-clock domain data transmission based on a two-level buffer, comprising the following steps: S1. Within the first clock domain, the data source data and the corresponding protocol fields are assembled word by word and written sequentially into the first-level buffer to form a complete protocol frame. S2. Move the complete protocol frame to the second-level buffer. The second-level buffer stores only one complete protocol frame at any given time. After the frame is moved, send a frame ready signal to the second clock domain to trigger the second clock domain to send the complete protocol frame. S3. Based on the transmission completion signal of the second clock domain, release the storage space occupied by the moved frames in the first-level buffer.

[0023] The first clock domain and the second clock domain are independent of each other, and their operating clock frequencies can be different.

[0024] In step S1, the specific steps include: the data source includes multiple data sources; within the first clock domain, each data source is polled sequentially according to a preset polling scheduling strategy, and the data from each data source is assembled word by word with the corresponding protocol fields and written sequentially into the first-level buffer.

[0025] Specifically, the polling scheduling strategy includes various methods such as fixed priority polling, equal weight polling, and weighted polling. Fixed priority polling is suitable for scenarios where there are significant differences in the priorities of each data source, equal weight polling is suitable for scenarios where the data rates of each data source are similar, and weighted polling can flexibly allocate scheduling weights according to the bandwidth ratio of each data source.

[0026] In this embodiment, before assembling the data source data and the corresponding protocol fields word by word and writing them sequentially into the first-level buffer, the process includes: detecting whether the remaining storage space in the first-level buffer is not less than the maximum length of a single frame; if the space is insufficient, pausing polling and writing until the space condition is met.

[0027] Specifically, before each new frame assembly and writing begins, the system reads the current free address range of the first-level buffer. When the available space is less than the maximum length of a single frame, scheduling is paused and the system enters a waiting state until the space release module completes the release of the storage space moved from the previous frame, at which point polling writing resumes.

[0028] In a specific example, the first-level buffer operates in the first clock domain (Uart_CLKx) and is implemented using dual-port Block RAM (BRAM4KB_S32R32). Both the write and read ports operate in Uart_CLKx. The write address is WrTifoAdr, the write enable is WrTifoEna, the write data is WrTifoDat, the read address is RdTifoAdr, and the read data output is RdTifoDat. The first-level buffer has a depth of 1024 words (4KB) and stores protocol frame data with a 32-bit data width. It can buffer up to four maximum-length protocol frames (MAX_T_LEN = 1024 bytes, i.e., 256×32bit) simultaneously.

[0029] The first-level buffer handles three functions: multi-channel data aggregation, protocol frame assembly, and slow-domain traffic shaping. The system supports concurrent input from 15 independent data sources (such as UART channels) with a SRC_COUNT value of 15. Each data source carries the data length ExPackLen, address offset ExPackOff, and a validity flag ExPackTag. The MoveState state machine uses MoveIndex as the current polling index to check if ExPackTag[MoveIndex] is valid. If valid, it enters the MOVE_DAT1 state to start reading data and assembling frames for that channel. If invalid and MoveIndex has not reached SRC_COUNT-1, it increments MoveIndex to continue polling. During frame assembly, the MoveState state machine writes the frame header field, status word field, user data field, and length field to the BRAM word by word in that order. The final result is a complete binary frame conforming to the LVDS receiver's parsing rules, with frame types including ASK frames, DATA frames, and STU frames.

[0030] Before each new frame assembly, the system calculates the difference between the read / write pointers RdTifoPtr and WrTifoPtr using the FREE_FIFO function to obtain the remaining space. Only when the remaining space is greater than B2D(MAX_T_LEN) can the MoveState state machine enter the MOVE_IDL2 state to begin frame assembly; otherwise, it remains in the MOVE_IDL1 idle waiting state, forming a natural backpressure control mechanism. Because the arrival of data from multiple data sources is bursty and aperiodic, the first-level buffer uses the above mechanism to smoothly shape the bursty data stream into an aligned frame stream, ensuring that downstream processing modules always face complete protocol frames.

[0031] In step S2, the step of sending the frame ready signal to the second clock domain includes: transmitting the frame ready signal to the second clock domain after synchronization through at least two levels of serial registers, so as to eliminate cross-clock domain metastability.

[0032] Specifically, the at least two cascaded registers constitute a multi-level synchronization chain. After the frame ready signal is generated in the first clock domain, it is sampled and latched sequentially by each level of the multi-level synchronization chain registers, and finally presented in a stable state in the second clock domain.

[0033] In a specific example, the frame ready signal is ExTbufSig, which is a single-cycle high-level pulse generated by the TifoState state machine in the first clock domain (Uart_CLKx) at the end of the FIFO_DATA state after completing the whole frame shift; in the second clock domain (Lvds_CLK1), two-level serial registers are used to synchronize ExTbufSig: the first-level register RdTbufSig[0] samples ExTbufSig at the rising edge of the Lvds_CLK1 clock to complete the fast domain primary sampling; the second-level register RdTbufSig[1] samples RdTbufSig[0] at the rising edge of the Lvds_CLK1 clock to eliminate metastability; after the LvdsTxFsm state machine detects that RdTbufSig[1] is valid, it triggers the high-speed transmission engine to start the reading and sending process of the second-level buffer data. As those skilled in the art will know, the number of stages in the series register can be set according to the system's tolerance for metastability failures, and the number of stages also includes other embodiments besides this one, such as using three-stage or four-stage series registers to further reduce the probability of metastability. Synchronizing the frame ready signal through a multi-stage register chain can effectively suppress the risk of metastability in cross-clock domain signal transmission, helping to improve the transmission stability of the frame ready signal at clock boundaries.

[0034] Step S3 specifically includes: synchronizing the transmission completion signal to the first clock domain via at least two levels of serial registers, and performing rising edge detection on the synchronized signal to trigger the release operation based on the rising edge detection result.

[0035] Specifically, the rising edge detection determines the signal transition by comparing the logic state of the synchronized signal within two consecutive first clock domain clock cycles. When a rising edge transitioning from low to high is detected, a single-cycle pulse signal is generated, which triggers the first-level buffer to perform the release operation of the corresponding moved frame storage space.

[0036] In a specific example, the transmission completion signal is ExTbufFin, which is a single-cycle high-level pulse generated by the LvdsTxFsm state machine in the second clock domain (Lvds_CLK1) at the end of the LVDS_DONE state; in the first clock domain (Uart_CLKx), two-level registers are used to synchronize ExTbufFin: the first-level register RdTbufFin[0] samples ExTbufFin at the rising edge of the Uart_CLKx clock to complete the primary sampling of the fast domain signal from the slow domain; the second-level register RdTbufFin[1] samples RdTbufFin[0] at the rising edge of the Uart_CLKx clock to eliminate metastability; and then through combinational logic ~RdTbufFin[1] & RdTbufFin[0] detects the rising edge and generates a single-cycle enable signal RdTbufFin[2]. RdTbufFin[2] triggers the first-level buffer to update the read pointer RdTifoPtr, completing the release of the storage space of the moved frame and providing available storage resources for the assembly and writing of subsequent frames. The sending completion signal triggers the space release after multi-level synchronization and rising edge detection, which can avoid false triggering caused by signal glitches or metastability, and helps to improve the accuracy of the first-level buffer storage space management.

[0037] In this embodiment, the second-level buffer includes a dual-port memory with a write port and a read port; the write port operates in the first clock domain, and the read port operates in the second clock domain; the whole frame shift is completed through the write port, and the transmission of the complete protocol frame is completed through the read port.

[0038] In a specific example, the second-level buffer is implemented using a dual-port Block RAM (BRAM1KB_S32R32). The write port (CKA) is driven by Uart_CLKx, with a write address of WrTbufAdr, write enable of WrTbufEna, and write data as WrTbufDat. The read port (CKB) is driven by the high-speed transmit clock domain Lvds_CLK1, with a read address of RdTbufAdr, read data output as RdTbufDat, and read enable ENB always active. The second-level buffer has a depth of 256 words (1KB) and stores only one complete protocol frame to be transmitted at any given time.

[0039] The two ports belong to two completely asynchronous clock domains, and direct shared access would lead to setup / hold timing violations. This invention solves this problem by using a "full frame write only + pulse handshake" approach: the TifoState state machine writes the assembled protocol frame from the first-level buffer to the second-level buffer before sending a frame ready signal to the second clock domain; the first clock domain does not write new data to the second-level buffer until the second clock domain completes the read and sends back a transmit completion signal. This ensures that there is no time conflict in accessing the second-level buffer from the two clock domains, and data consistency is guaranteed by frame boundary synchronization signals, rather than byte-by-byte synchronization.

[0040] Furthermore, the time T1 required for the slow domain to pack a frame (approximately 100 μs) is much longer than the time T2 required for the fast domain to send the same frame (approximately 20 μs). Without a second-level buffer, the high-speed transmission engine must wait for the slow domain to complete packing the next frame after completing the current frame, resulting in a link utilization rate of less than 20%. With the introduction of a second-level buffer, the slow domain can simultaneously assemble the next frame in the first-level buffer while the fast domain is sending the current frame, achieving pipelined scheduling and improving link utilization.

[0041] In this embodiment, the complete protocol frame includes a frame header field, a status word field, a user data field, and a length field; the word-by-word assembly step writes the frame header field, status word field, user data field, and length field sequentially into the first-level buffer in the order of the first-level buffer. After the writing is completed, it can be regarded as the complete assembly of a protocol frame.

[0042] In one specific embodiment, this embodiment will be illustrated with Verilog code: I. First-level buffer: BRAM4KB_S32R32 BRAM4K0_S32R32 ( .CKA(Uart_CLKx), .ARA(WrTifoAdr), .WEA(WrTifoEna), .DIA(WrTifoDat), .CKB(Uart_CLKx), .ARB(RdTifoAdr), .ENB(1'b1), .DOB(RdTifoDat) ); The first-level buffer is a key module for realizing the fusion of multi-source heterogeneous data, frame structure standardization, and decoupling of transmission scheduling.

[0043] 1. Multi-channel data aggregation and polling scheduling The system supports SRC_COUNT = 15 independent data sources (such as UART channels); The first-level buffer implements polling arbitration through the MoveState state machine: if (ExPackTag[MoveIndex]) MoveState <= MOVE_DAT1; else if (MoveIndex != SRC_COUNT-1) MoveIndex++; Each data stream carries ExPackLen (length), ExPackOff (address offset), and ExPackTag (validity flag). Effect: It unifies scattered multi-source data into a single FIFO structure, simplifying subsequent processing.

[0044] 2. Dynamic assembly of complete frame structure The first-level buffer not only stores the raw data, but also actively constructs communication protocol frames (ASK frames, DATA frames, STU frames, etc.). These fields are concatenated word by word by the MoveState state machine before being written to BRAM; Finally, the complete binary frame that conforms to the parsing rules of the LVDS receiver is written into the first-level buffer.

[0045] 3. Variable-length frame buffer and depth guarantee The maximum frame length can reach MAX_T_LEN = 1024 bytes (256×32bit); The first-level buffer depth is 1024 words = 4KB, which can buffer 4 maximum frames at the same time; Use FREE_FIFO(RdTifoPtr, WrTifoPtr) to check the remaining space and avoid overflow: if (FREE_FIFO(...) > B2D(MAX_T_LEN)) MoveState <= MOVE_IDL2; 4. Slow-speed domain flow shaping and back pressure control UART data arrivals are bursty and non-periodic; The first-level buffer smooths it into a continuous, aligned frame stream; When the FIFO space is insufficient, polling is automatically paused (remaining in MOVE_IDL1), forming a natural backpressure mechanism.

[0046] II. Second-level buffer BRAM1KB_S32R32 BRAM1KB_S32R32 ( .CKA(Uart_CLKx), .ARA(WrTbufAdr), .WEA(WrTbufEna), .DIA(WrTbufDat), .CKB(Lvds_CLK1), .ARB(RdTbufAdr), .ENB(1'b1), .DOB(RdTbufDat) ); The second-level buffer undertakes four key functions: cross-clock domain security isolation, rate matching, transmission flow control, and hardware decoupling. 1. Cross-clock domain security isolation (CDC Safety) The second-level buffer is a two-port Block RAM (BRAM): Write port: Controlled by Uart_CLKx (slow clock); Read port: Controlled by Lvds_CLK1 (fast clock).

[0047] Because the two clocks are completely asynchronous, directly sharing memory will result in a setup / hold violation.

[0048] This embodiment uses a method that allows only whole-frame writing and pulse handshakes to ensure that during fast-domain reading, the slow-domain will not modify the current frame content, and data consistency is guaranteed by the frame boundary synchronization signal rather than byte-by-byte synchronization.

[0049] 2. Frame Atomicity The first-level buffer (4KB) may contain multiple frames; The second-level buffer (1KB) only buffers the current frame to be sent; Once the writing is complete, the frame content remains locked until the transmission is finished.

[0050] 3. Rate Matching and Traffic Shaping Packing one frame in the slow domain requires time T1 (e.g., 100μs); A fast domain can send a frame in just T2 (e.g., 20μs); Without a second-level buffer, the fast domain must wait for the slow domain to complete the next frame → link utilization < 20%.

[0051] 4. Logical decoupling and modular design Slow-domain logic (MoveState / TifoState): Frame format splicing; Multi-channel polling; FIFO management.

[0052] Fast domain logic (LvdsTxFsm): B / 5B encoding; CRC calculation; Sign-shifted output.

[0053] III. Handshake Synchronization / / Slow → Fast: ExTbufSig Synchronization / / 'Uart_CLKx' clock field -> 'Lvds_CLK1' clock field always @(posedge Lvds_CLK1) begin RdTbufSig[0] <= ExTbufSig; / / First-level register (fast domain sampling) RdTbufSig[1] <= RdTbufSig[0]; / / Second-level register (eliminates metastability) End ExTbufSig is a single-cycle high-level pulse generated by the Uart_CLKx field at the end of the FIFO_DATA state; In the Lvds_CLK1 domain, synchronization is performed using two-level triggers (RdTbufSig[0], RdTbufSig[1]); / / Fast → Slow: ExTbufFin Rising Edge Detection / / 'Lvds_CLK1' clock field -> 'Uart_CLKx' clock field always @(posedge Uart_CLKx) begin RdTbufFin[0] <= ExTbufFin; / / First level (slow domain sampling of fast domain signal) RdTbufFin[1] <= RdTbufFin[0]; / / Second stage (eliminating metastability) RdTbufFin[2] <= ~RdTbufFin[1] & RdTbufFin[0]; / / Rising edge detection End ExTbufFin is a single-cycle pulse generated by the Lvds_CLK1 field in the LVDS_DONE state; In the Uart_CLKx domain, first use two-level register synchronization (RdTbufFin[0], RdTbufFin[1]); Then, use combinational logic ~RdTbufFin[1] & RdTbufFin[0] to detect the rising edge and generate a single-cycle enable signal RdTbufFin[2].

[0054] IV. High-speed transmission LvdsTxFsm reads data from RdTbufDat and performs operations such as 4B / 5B encoding, CRC, and IDLE alternation.

[0055] In addition, such as Figure 3 As shown, this embodiment also proposes a cross-clock domain data transmission system based on a two-level buffer to implement the cross-clock domain data transmission method based on a two-level buffer as described above, including a first-level buffer, an assembly and writing module, a second-level buffer, a transfer control module, a sending module, and a space release module.

[0056] Specifically, the first-level buffer is located in the first clock domain and is used to cache protocol frame data being assembled and to be moved; the assembly and writing module is used to assemble the data source data and corresponding protocol fields word by word and write them sequentially into the first-level buffer to form a complete protocol frame; the second-level buffer is used to store only one complete protocol frame at any given time; the moving control module is used to move the complete protocol frame to the second-level buffer in its entirety and send a frame ready signal to the second clock domain after the moving is completed; the sending module is used to respond to the frame ready signal, send the complete protocol frame in the second-level buffer, and send a sending completion signal to the first clock domain after the sending is completed; the space release module is used to release the storage space occupied by the moved frames in the first-level buffer according to the sending completion signal.

[0057] Furthermore, this embodiment also includes a signal synchronization module, which includes at least two levels of serial registers; the frame ready signal is transmitted to the second clock domain after being synchronized by the signal synchronization module; the transmission completion signal is synchronized to the first clock domain by the signal synchronization module, and after rising edge detection, it triggers the space release module to perform a release operation.

[0058] In this embodiment, the second-level buffer includes a dual-port memory with a write port and a read port; the write port operates in the first clock domain, and the shift control module completes the shift of the entire frame through the write port; the read port operates in the second clock domain, and the sending module completes the transmission of the complete protocol frame through the read port.

[0059] In this embodiment, the processing flow is as follows: Phase 1: Data aggregation and encapsulation (Level 1 buffer) 1. Location: Connect to upstream (sensor); 2. Clock domain: Uart_CLKx (slow domain); 3. Actions: Receive: 15 channels of sensor data, for example, by feeding the data into a huge 4KB buffer; Assembly: The MoveState state machine checks the address and size (ExPackLen, ExPackTag) of each data packet, and then adds concatenation (frame header field, status word field, user data field and length field) to the original data according to the requirements of LVDS. Assembly: Once a complete frame of data is assembled in the buffer, it is left untouched and awaits the next instruction.

[0060] Function: It solves the problem of "multi-source concurrency" and transforms the scattered 15 data streams into neat "frame-by-frame" data packets.

[0061] Phase Two: Cross-Clock Domain Processing (Handshake Mechanism) 1. Trigger point: A frame of data in the first-level buffer is ready; 2. Actions: Full Frame Transfer (Slow → Relay): Before issuing the notification signal, the TifoState state machine, still in the Uart_CLKx clock domain, writes the entire assembled protocol frame data from the first-level buffer to the second-level buffer (BRAM1KB_S32R32) via the write port (CKA) of the second-level buffer. This transfer operation is completed entirely in the slow domain (Uart_CLKx). During the write process, the second clock domain does not access the second-level buffer, thus ensuring the integrity and consistency of the frame data.

[0062] Signaling (slow → fast): After the data in the first-level buffer in the low-speed domain is ready and the entire frame is written to the second-level buffer, the high-speed domain is notified. Synchronization processing: Because the clocks on both sides are not synchronized, this notification signal needs to go through two levels of registers (RdTbufSig[0], RdTbufSig[1]) to "deboil" (eliminate metastability) and ensure that the signal is accurately transmitted to the high-speed domain; Function: This is a "neural connection" between two modules, which then informs the downstream that the data is ready and the goods can be picked up.

[0063] Phase 3: High-speed transport and delivery (second-level buffer) 1. Location: Connects to downstream (LVDS sending engine); 2. Clock domain: Lvds_CLK1 (fast domain); 3. Actions: Read: After receiving the notification signal, the high-speed domain transporter (LvdsTxFsm state machine) immediately runs to the 1KB relay station (BRAM1KB_S32R32). Copying: The mover moves the assembled data frame from the first-level warehouse to the transfer station in its entirety; the phrase "the mover moves the data frame to the transfer station in its entirety" is a figurative description. In reality, the transfer of the entire frame of data from the first-level buffer to the second-level buffer has already been completed in the second stage by the TifoState state machine in the slow domain (Uart_CLKx); LvdsTxFsm operates in the fast domain (Lvds_CLK1), and only reads the ready complete frame data in the second-level buffer through the read port (CKB), without directly accessing the first-level buffer. The accesses to the second-level buffer by the two clock domains do not overlap in time. Sending: The porter stands next to the high-speed conveyor belt (LVDS differential line), reads the data from the transfer station, performs 4B / 5B encoding, and then throws it onto the conveyor belt at extremely high speed; Function: It can solve the "rate matching" problem, with the first stage loading slowly and the second stage emptying instantly.

[0064] Phase 4: Confirmation and Reset (Feedback Handshake) 1. Trigger point: The high-speed transmission engine finishes sending this frame of data; 2. Actions: Receipt (Fast → Slow): The high-speed domain sends back an ExTbufFin pulse to notify the slow domain: "The shipment has been completed and the old data can be updated." Cleanup: Upon receiving an acknowledgment, the first-level buffer releases the 4KB buffer space occupied by the previous data frame and begins receiving the next wave of sensor data. Here, "4KB" refers to the total capacity of the first-level buffer. The actual storage space released each time is the storage space occupied by that frame of data. The maximum length of a single frame is MAX_T_LEN = 1024 bytes (i.e., 1KB, 256×32bit), and the specific amount released depends on the actual length of the frame. The release operation is implemented by updating the read pointer RdTifoPtr.

[0065] In summary, the cross-clock domain data transmission method and system based on two-level buffering proposed in this invention has the following advantages: By introducing a first-level buffer within the first clock domain to complete the word-by-word assembly of the protocol frame, and then moving the entire frame to the second-level buffer before issuing the frame ready signal, a two-level buffering mechanism is used to completely separate the protocol assembly process from the cross-clock domain transmission process. This fundamentally avoids the second clock domain from initiating a read before the frame data is complete, effectively improving the integrity of the protocol frame transmission. At the same time, the cross-clock domain handshake mechanism formed by the frame ready signal and the transmission completion signal, combined with the constraint that the second-level buffer stores only one frame at any given time, can enhance the timing controllability of cross-clock domain data transmission and improve the overall transmission reliability of the system.

[0066] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for cross-clock domain data transmission based on a two-level buffer, characterized in that, Including the following: Within the first clock domain, the data source data is assembled word by word with the corresponding protocol fields and written sequentially into the first-level buffer to form a complete protocol frame; The complete protocol frame is moved to the second-level buffer. The second-level buffer stores only one complete protocol frame at any given time. After the entire frame is moved, a frame ready signal is sent to the second clock domain to trigger the second clock domain to send the complete protocol frame. Based on the completion signal of the second clock domain, release the storage space occupied by the moved frames in the first-level buffer.

2. The cross-clock domain data transmission method based on two-level buffering as described in claim 1, characterized in that, Within the first clock domain, the data source data is assembled word by word with the corresponding protocol fields and sequentially written into the first-level buffer. Specifically, the data source includes multiple data sources. Within the first clock domain, each data source is polled sequentially according to a preset polling scheduling strategy, and the data from each data source is assembled word by word with the corresponding protocol fields and sequentially written into the first-level buffer.

3. The cross-clock domain data transmission method based on two-level buffering as described in claim 2, characterized in that, Before assembling the data source data and corresponding protocol fields word by word and writing them sequentially into the first-level buffer, the process includes: detecting whether the remaining storage space in the first-level buffer is not less than the maximum length of a single frame; if the space is insufficient, pausing polling and writing until the space condition is met.

4. The cross-clock domain data transmission method based on two-level buffering as described in claim 1, characterized in that, The step of sending a frame ready signal to the second clock domain includes: transmitting the frame ready signal to the second clock domain after synchronization through at least two levels of serial registers, so as to eliminate cross-clock domain metastability.

5. The cross-clock domain data transmission method based on two-level buffering as described in claim 1, characterized in that, The step of releasing the storage space occupied by the moved frame in the first-level buffer according to the transmission completion signal of the second clock domain specifically includes: synchronizing the transmission completion signal to the first clock domain through at least two levels of serial registers, and performing rising edge detection on the synchronized signal, and triggering the release operation based on the rising edge detection result.

6. The cross-clock domain data transmission method based on two-level buffering as described in claim 1, characterized in that, The second-level buffer includes a dual-port memory with a write port and a read port; the write port operates in the first clock domain, and the read port operates in the second clock domain; the whole frame shift is completed through the write port, and the transmission of the complete protocol frame is completed through the read port.

7. The cross-clock domain data transmission method based on two-level buffering as described in claim 1, characterized in that, The complete protocol frame includes a frame header field, a status word field, a user data field, and a length field; the word-by-word assembly step writes the frame header field, status word field, user data field, and length field sequentially into the first-level buffer.

8. A cross-clock domain data transmission system based on two-level buffering, used to implement the cross-clock domain data transmission method based on two-level buffering as described in any one of claims 1-7, characterized in that, It includes a first-level buffer, an assembly and write module, a second-level buffer, a transfer control module, a send module, and a space release module; The first-level buffer is located in the first clock domain and is used to cache protocol frame data during assembly and to be moved. The assembly and writing module is used to assemble the data source data with the corresponding protocol fields word by word and write them sequentially into the first-level buffer to form a complete protocol frame. The second-level buffer is used to store only one complete protocol frame at any given time; The transfer control module is used to transfer the complete protocol frame to the second-level buffer in its entirety, and send a frame ready signal to the second clock domain after the transfer is completed; The sending module is used to respond to the frame ready signal, send the complete protocol frame in the second-level buffer, and send a sending completion signal to the first clock domain after the sending is completed; The space release module is used to release the storage space occupied by the moved frames in the first-level buffer according to the transmission completion signal.

9. The cross-clock domain data transmission system based on a two-level buffer as described in claim 8, characterized in that, It also includes a signal synchronization module, which includes at least two levels of serial registers; the frame ready signal is transmitted to the second clock domain after being synchronized by the signal synchronization module; the transmission completion signal is synchronized to the first clock domain by the signal synchronization module, and after rising edge detection, it triggers the space release module to perform a release operation.

10. The cross-clock domain data transmission system based on a two-level buffer as described in claim 8, characterized in that, The second-level buffer includes a dual-port memory with a write port and a read port; the write port operates in the first clock domain, and the shift control module completes the shifting of the entire frame through the write port; the read port operates in the second clock domain, and the sending module completes the transmission of the complete protocol frame through the read port.

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