Equalization control method and apparatus for PCIe communication, electronic device, and medium

Abstract

The present disclosure provides a method and device for equalization control of PCIe communication, an electronic device and a medium, which obtains a mode state value from a link training state machine, and realizes dynamic selection of equalization control mode. The equalization configuration parameters are obtained respectively through signal transmission between communication ends, solving the problem that the hardware equalization cannot be optimized respectively due to channel asymmetry (such as the difference in the lengths of downlink and uplink port wiring and driving capability). Meanwhile, the result control state machine jumps to the matching target state based on the result of bidirectional equalization processing, ensuring that the result after software intervention can be accurately recognized by hardware and corresponding state migration is performed, and the complete compatibility with the PCIe protocol hardware automatic equalization process is also retained.

Description

Technical Field

[0001] This disclosure relates to chip design technology, and in particular to a method and apparatus for equalization control of PCIe communication, electronic devices and media. Background Technology

[0002] In high-speed serial communication, such as high-speed serial communication based on the PCIe protocol, the signal is affected by factors such as channel loss, inter-symbol interference (ISI), and reflections during transmission. These factors lead to eye diagram closure at the receiver and an increased bit error rate (BER), thus reducing communication quality. To compensate for channel loss, PCIe protocol version 3.0 and above introduced equalization technology. Equalization technology is a means of conditioning the signal to reduce the impact of distortion. It includes a feed-forward equalizer (FFE) at the transmitter, a continuous time linear equalizer (CTLE) at the receiver, and a decision feedback equalizer (DFE). This minimizes jitter caused by ISI and some reflections caused by impedance mismatch, ensuring that the eye diagram at the decision input at the receiver can be opened, thus guaranteeing the stability and accuracy of data transmission.

[0003] Before establishing normal communication between PCIe devices, link training must be performed. Link training is an automated handshake process controlled by the Link Training and Status State Machine (LTSSM), which sequentially completes steps such as baud rate detection, channel alignment, speed negotiation, and equalization, ultimately bringing the link into a normal transmission state. Equalization is a crucial sub-stage of link training, used to adjust the signal compensation parameters at the transmitting and receiving ends to optimize signal quality. Equalization technology is typically implemented in high-speed serial communication interface controller chips, and its link training and equalization processes have a significant impact on the chip's transmission performance, power consumption, and stability.

[0004] The PCIe protocol stipulates that the equalization phase during link training can be automatically completed by hardware, i.e., hardware automatic equalization. This method is controlled by a hardware state machine, which completes coefficient adjustment and signal quality evaluation according to the protocol's preset process, and has the advantages of high speed and good protocol compatibility. However, hardware automatic equalization also has obvious shortcomings: its process is fixed and cannot flexibly adapt to complex link environments; debugging is difficult and intervention is difficult in abnormal situations; and it cannot use software to finely control the equalization process or troubleshoot faults.

[0005] Therefore, how to provide a specific and feasible software balancing solution while being compatible with hardware automatic balancing, so as to enhance the flexibility and robustness of the PCIe balancing process, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] In view of the above-mentioned problems in related technologies, this disclosure provides a method and apparatus for equalization control of PCIe communication, an electronic device and a medium.

[0007] In a first aspect, this disclosure provides a load balancing control method for PCIe communication, applied to a first communication terminal, the first communication terminal being a device supporting the PCIe protocol, the first communication terminal including a link training state machine, the method comprising: The mode state value is obtained from the link training state machine to determine the equalization control mode; In response to the mode state value indicating that the equalization control mode is the first equalization mode, a communication signal is transmitted to the second communication terminal to perform bidirectional equalization processing. The bidirectional equalization processing is used to establish bidirectional link parameter negotiation and equalization configuration between the first communication terminal and the second communication terminal to obtain suitable equalization configuration parameters in the signal transmission direction and the signal reception direction, respectively. The result of the bidirectional equalization process is fed back to the link training state machine so that the link training state machine jumps to the target state that matches the result of the bidirectional equalization process.

[0008] As an optional embodiment, obtaining mode state values ​​from the link training state machine to determine the equalization control mode includes: Read the value of the first configuration register in the link training state machine as the mode state value; In response to the mode state value being a first preset value, the equalization control mode is determined to be a first equalization mode; In response to the mode state value being a second preset value, the equalization control mode is determined to be a second equalization mode, which is an equalization mode in which equalization parameters are automatically adjusted and signal quality is evaluated by hardware.

[0009] As an optional embodiment, the step of transmitting a communication signal to the second communication terminal in response to the mode state value indicating that the equalization control mode is a first equalization mode, to perform bidirectional equalization processing, includes: Determine at least one candidate load balancer configuration, each of the candidate load balancer configurations including at least one load balancer configuration parameter; Based on the at least one candidate equalization configuration, a first communication signal is sent to the second communication terminal respectively, so as to determine a first target equalization configuration adapted to the signal transmission direction based on the evaluation result of the first communication signal by the second communication terminal; The second communication terminal receives a second communication signal sent by the second communication terminal based on the at least one candidate equalization configuration, and returns the evaluation result of the second communication signal to the second communication terminal so that the second communication terminal can determine a second target equalization configuration that is suitable for the signal receiving direction. The result of the bidirectional equalization process is determined based on the first target equalization configuration and the second target equalization configuration.

[0010] As an optional embodiment, determining at least one candidate load balancing configuration includes: Read at least one candidate load balancer configuration from the list of preset configurations; The preset configuration list includes at least one of the preset values ​​in the PCIe protocol specification, a hardware preset table, and a software configuration table. The preset values ​​in the PCIe protocol specification are combinations of load balancing parameters defined in the PCIe protocol specification. The hardware preset table is a fixed list of combinations of load balancing parameters stored in the hardware read-only memory area of ​​any communication end. The software configuration table is a list of combinations of load balancing parameters stored in a read-write memory and dynamically configured and updated by preset software or drivers.

[0011] As an optional embodiment, the step of sending a first communication signal to the second communication terminal based on the at least one candidate equalization configuration, and determining a first target equalization configuration adapted to the signal transmission direction based on the evaluation result of the first communication signal by the second communication terminal, includes: Iterate through at least one candidate load balancer configuration; For any of the candidate equalization configurations, the candidate equalization configuration is sent to the local physical layer so that the local physical layer sends a first communication signal according to the candidate equalization configuration. The evaluation score returned by the second communication terminal is received through inter-chip communication. The evaluation score is used to characterize the signal quality of the first communication signal received by the second communication terminal. In response to the completion of traversing all the candidate equalization configurations, the evaluation scores of the first communication signal of each candidate equalization configuration are compared to determine the candidate equalization configuration with the highest evaluation score as the first target equalization configuration.

[0012] As an optional embodiment, receiving the second communication signal sent by the second communication end based on the at least one candidate equalization configuration, and returning the evaluation result of the second communication signal to the second communication end so that the second communication end can determine a second target equalization configuration adapted to the signal reception direction, includes: Receive the second communication signal sent sequentially by the second communication terminal based on the at least one candidate equalization configuration; For each candidate equalization configuration corresponding to the second communication signal, the local physical layer is triggered to perform signal quality evaluation and obtain the corresponding evaluation score. The evaluation score is returned to the second communication terminal via inter-chip communication, so that the second communication terminal determines the candidate equilibrium configuration with the highest evaluation score as the second target equilibrium configuration based on the evaluation score.

[0013] As an optional embodiment, sending the candidate balancer configuration to the local physical layer for any one of the candidate balancer configurations includes: The candidate equalization configuration is written into the second configuration register corresponding to the PCIe physical layer interface via the advanced peripheral bus, so as to instruct the local physical layer to send a first communication signal according to the candidate equalization configuration, wherein the second configuration register is the control and status register of the PCIe physical layer interface; The second communication signal corresponding to each of the candidate equalization configurations triggers the local physical layer to perform signal quality evaluation and obtain the corresponding evaluation score, including: The evaluation trigger signal corresponding to the PCIe physical layer interface is set through the advanced peripheral bus to start the local physical layer to evaluate the received second communication signal and read the evaluation score returned by the PCIe physical layer interface.

[0014] As an optional embodiment, the inter-chip communication adopts any one of the following protocols: serial peripheral interface, universal asynchronous transceiver, and integrated circuit bus.

[0015] As an optional embodiment, determining the result of the bidirectional equalization process based on the first target equalization configuration and the second target equalization configuration includes: In response to the successful configuration of both the first target equalization configuration and the second target equalization configuration, the third configuration register and the fourth configuration register are set to the first state value to indicate that the result of the bidirectional equalization process is the first result state. In response to the failure of either the first target equalization configuration or the second target equalization configuration, the third configuration register is set to a first state value, and the fourth configuration register is set to a second state value to indicate that the result of the bidirectional equalization process is a second result state. The third configuration register is used to indicate whether the bidirectional equalization process has ended, and the fourth configuration register is used to indicate whether the bidirectional equalization process has been successful.

[0016] As an optional embodiment, feeding back the result of the bidirectional equalization processing to the link training state machine, so that the link training state machine jumps to a target state matching the result of the bidirectional equalization processing, includes: In response to the result of the bidirectional equalization processing being a first result state, the link training state machine is controlled to jump to the receive lock state. The receive lock state is the lock state entered after the link training in the PCIe protocol is completed and equalization is completed, and it is used to execute the link training to enter the normal transmission state. In response to the result of the bidirectional equalization processing being a second result state, the link training state machine is controlled to jump to a deceleration state. The deceleration state is a state in the PCIe protocol where the transmission rate is reduced and retried after the link training fails, and is used to reduce the transmission rate and restart the link training.

[0017] A second aspect of this disclosure provides a load balancing control device for PCIe communication, applied to a first communication terminal, the first communication terminal being a device supporting the PCIe protocol, the first communication terminal including a link training state machine, the device comprising: The mode state value acquisition module is used to acquire mode state values ​​from the link training state machine to determine the equalization control mode. A bidirectional equalization module is used to transmit communication signals to a second communication terminal in response to the mode state value indicating that the equalization control mode is the first equalization mode, so as to perform bidirectional equalization processing. The bidirectional equalization processing is used to establish bidirectional link parameter negotiation and equalization configuration between the first communication terminal and the second communication terminal, so as to obtain suitable equalization configuration parameters in the signal transmission direction and the signal reception direction respectively. The equalization result transmission module is used to feed back the result of the bidirectional equalization process to the link training state machine, so that the link training state machine jumps to the target state that matches the result of the bidirectional equalization process.

[0018] As an optional embodiment, the mode state value acquisition module includes: The mode state value determination unit is used to read the value of the first configuration register in the link training state machine as the mode state value. The first equalization mode unit is used to determine the equalization control mode as the first equalization mode in response to the mode state value being a first preset value. The second equalization mode unit is used to determine the equalization control mode as the second equalization mode in response to the mode state value being the second preset value. The second equalization mode is an equalization mode in which equalization parameters are automatically adjusted and signal quality is evaluated by hardware.

[0019] As an optional embodiment, the bidirectional equalization module includes: A candidate configuration determination unit is used to determine at least one candidate equilibrium configuration, each of the candidate equilibrium configurations including at least one equilibrium configuration parameter. A signal transmitting unit is configured to transmit a first communication signal to the second communication terminal based on the at least one candidate equalization configuration, so as to determine a first target equalization configuration adapted to the signal transmitting direction based on the evaluation result of the first communication signal by the second communication terminal. A signal receiving unit is configured to receive a second communication signal sent by the second communication terminal based on the at least one candidate equalization configuration, and return the evaluation result of the second communication signal to the second communication terminal so that the second communication terminal can determine a second target equalization configuration adapted to the signal receiving direction. The equilibrium result determination unit is used to determine the result of the bidirectional equilibrium processing based on the first target equilibrium configuration and the second target equilibrium configuration.

[0020] As an optional embodiment, the candidate configuration determination unit includes: The configuration read subunit is used to read at least one candidate load balancing configuration from a preset configuration list; The preset configuration list includes at least one of the preset values ​​in the PCIe protocol specification, a hardware preset table, and a software configuration table. The preset values ​​in the PCIe protocol specification are combinations of load balancing parameters defined in the PCIe protocol specification. The hardware preset table is a fixed list of combinations of load balancing parameters stored in the hardware read-only memory area of ​​any communication end. The software configuration table is a list of combinations of load balancing parameters stored in a read-write memory and dynamically configured and updated by preset software or drivers.

[0021] As an optional embodiment, the signal transmitting unit includes: Configure a traversal subunit for traversing the at least one candidate equilibrium configuration; A signal transmission subunit is configured to transmit a candidate equalization configuration to the local physical layer for any one of the candidate equalization configurations, so that the local physical layer transmits a first communication signal according to the candidate equalization configuration. The first signal evaluation subunit is used to receive an evaluation score returned by the second communication terminal via inter-chip communication. The evaluation score is used to characterize the signal quality of the first communication signal received by the second communication terminal. A first configuration determination subunit is configured to, in response to the completion of traversing all the candidate equalization configurations, compare the evaluation scores of the first communication signal of each of the candidate equalization configurations, so as to determine the candidate equalization configuration with the highest evaluation score as the first target equalization configuration.

[0022] As an optional embodiment, the signal receiving unit includes: A signal receiving subunit is used to receive a second communication signal sequentially sent by the second communication end based on the at least one candidate equalization configuration; The second signal evaluation subunit is used to trigger the local physical layer to perform signal quality evaluation for each of the candidate equalization configurations corresponding to the second communication signal, and obtain the corresponding evaluation score. The second configuration determination subunit is used to return the evaluation score to the second communication terminal through inter-chip communication, so that the second communication terminal determines the candidate equilibrium configuration with the highest evaluation score as the second target equilibrium configuration based on the evaluation score.

[0023] As an optional embodiment, the signal transmitting subunit is specifically used for: The candidate equalization configuration is written into the second configuration register corresponding to the PCIe physical layer interface via the advanced peripheral bus, so as to instruct the local physical layer to send a first communication signal according to the candidate equalization configuration, wherein the second configuration register is the control and status register of the PCIe physical layer interface; The second signal evaluation subunit is specifically used for: The evaluation trigger signal corresponding to the PCIe physical layer interface is set through the advanced peripheral bus to start the local physical layer to evaluate the received second communication signal and read the evaluation score returned by the PCIe physical layer interface.

[0024] As an optional embodiment, the inter-chip communication adopts any one of the following protocols: serial peripheral interface, universal asynchronous transceiver, and integrated circuit bus.

[0025] As an optional embodiment, the equalization result determination unit includes: The first register configuration subunit is configured to, in response to the successful configuration of both the first target equalization configuration and the second target equalization configuration, set the third configuration register and the fourth configuration register to the first state value respectively, so as to indicate that the result of the bidirectional equalization process is the first result state. The second register configuration subunit is configured to, in response to the failure of either the first target equalization configuration or the second target equalization configuration, set the third configuration register to a first state value and the fourth configuration register to a second state value, so as to indicate that the result of the bidirectional equalization process is a second result state. The third configuration register is used to indicate whether the bidirectional equalization process has ended, and the fourth configuration register is used to indicate whether the bidirectional equalization process has been successful.

[0026] As an optional embodiment, the equalization result transmission module includes: The first control unit is configured to control the link training state machine to jump to the receive lock state in response to the result of the bidirectional equalization processing being a first result state. The receive lock state is the lock state entered after the link training is completed and equalization is completed in the PCIe protocol, and is used to execute the link training to enter the normal transmission state. The second control unit is used to control the link training state machine to jump to the deceleration state in response to the result of the bidirectional equalization processing being a second result state. The deceleration state is the state in the PCIe protocol where the transmission rate is reduced and retried after the link training fails, and is used to reduce the transmission rate and restart the link training.

[0027] A third aspect of this disclosure provides an electronic device, including: Memory, used to store computer program products; A processor for executing a computer program product stored in memory, wherein when the computer program product is executed, it implements the method of any of the first aspects described above.

[0028] A fourth aspect of this disclosure provides a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the method of any one of the first aspects described above.

[0029] The fifth aspect of this disclosure provides a computer program product including computer program instructions that, when executed by a processor, implement any of the methods described in the first aspect above.

[0030] This disclosure overcomes the shortcomings of existing hardware automatic equalization schemes, such as fixed processes, inflexibility in adapting to complex link environments, and difficulty in debugging, by introducing a first equalization mode (i.e., software equalization mode). Specifically, it first obtains the mode state value from the link training state machine, realizing the dynamic selection of the equalization control mode. Communication signals are transmitted to the second communication terminal via software, and bidirectional link parameter negotiation and equalization configuration are performed, enabling the transmitting and receiving directions to obtain suitable equalization configuration parameters respectively. This solves the problem in hardware equalization where channel asymmetry (e.g., differences in downlink and uplink port trace lengths and drive capabilities) prevents separate optimization. Simultaneously, the method feeds back the bidirectional equalization processing results to the link training state machine and controls the state machine to jump to the matching target state. This ensures that the results after software intervention are accurately recognized by the hardware and the corresponding state transitions are executed (successfully jumping to the receive lock state for normal transmission, and failing to jump to the deceleration state for retry), while maintaining full compatibility with the PCIe protocol hardware automatic equalization process. Therefore, this solution improves the flexibility, debuggability, and robustness of link training while maintaining compatibility with existing hardware automatic equalization, making signal quality optimization and fault diagnosis possible in complex link environments.

[0031] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0033] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 This disclosure provides a schematic diagram of the framework structure of a link training state machine according to an exemplary embodiment.

[0034] Figure 2 This is a flowchart illustrating a balancing control method for PCIe communication, which is an exemplary embodiment of this disclosure.

[0035] Figure 3 This is a flowchart illustrating a balancing control method for PCIe communication, which is another exemplary embodiment of this disclosure.

[0036] Figure 4 This is a flowchart illustrating a balancing control method for PCIe communication, which is another exemplary embodiment of this disclosure.

[0037] Figure 5 This is a flowchart illustrating a balancing control method for PCIe communication, which is another exemplary embodiment of this disclosure.

[0038] Figure 6 This is a flowchart illustrating a balancing control method for PCIe communication, which is another exemplary embodiment of this disclosure.

[0039] Figure 7 This is a structural block diagram of a leveling control device for PCIe communication, which is an exemplary embodiment of the present disclosure.

[0040] Figure 8 This is a structural block diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0041] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0042] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the scope of this disclosure or its application or use.

[0043] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0044] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0045] This disclosure can be applied to electronic devices such as computer systems / servers, which can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with electronic devices such as computer systems / servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0046] Computer systems / servers and other electronic devices can be described in the general context of computer-executable instructions (such as program modules) executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are performed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0047] In order to accurately describe the technical content in this disclosure, and to accurately understand the embodiments of this disclosure, the terms used in the embodiments of this disclosure are explained or defined as follows: (1) Link training The automated handshake process performed before PCIe devices establish normal communication is controlled by the link training state machine. It includes steps such as baud rate detection, channel alignment, speed negotiation, and equalization, ultimately enabling the link to enter a normal transmission state.

[0048] (2) Link Training State Machine (LTSSM) The PCIe protocol defines a state machine for controlling the link training process, which sequentially goes through multiple states such as Detect, Polling, Configuration, and Recovery. The Recovery state includes a balancer sub-state.

[0049] (3) Equilibrium A key sub-state in link training is used to adjust the signal compensation parameters at the transmitting and receiving ends to optimize signal quality and reduce the effects of inter-symbol interference and reflection.

[0050] (4) Balanced control mode Used to indicate whether the equalization process is executed automatically by hardware or taken over by software, including a first equalization mode (e.g., software equalization) and a second equalization mode (e.g., automatic hardware equalization).

[0051] (5) Automatic hardware balancing The equalization mode in which equalization parameters are adjusted and signal quality is evaluated automatically by hardware, which is the hardware automatic equalization recommended by the PCIe protocol.

[0052] (6) First Configuration Register The register located in the link training state machine is used to store the mode state value. The software determines the equalization control mode by reading the register value. For example, the first preset value corresponds to the first equalization mode, and the second preset value corresponds to the second equalization mode.

[0053] (7) Candidate Equalization Configuration A set of parameters, including at least one load balancing configuration parameter, is used for trial and evaluation during the load balancing process. Its sources include, but are not limited to, preset values ​​in the PCIe protocol specification, hardware preset tables, and software configuration tables.

[0054] (8) Balanced configuration parameters Specific parameters in the equalization configuration, such as the equalization coefficient at the sending end, include but are not limited to Preshoot and De-emphasis.

[0055] (9) Preset values ​​in the PCIe protocol specification The combination of equalization configuration parameters defined by the PCIe protocol specification, namely the Preset specified by the PCIe protocol, is a set of equalization coefficients for the sending end.

[0056] (10) Hardware preset table A fixed list of equalization configuration parameters is stored in the hardware read-only memory area of ​​any communication terminal. After the chip is powered on and reset, the stored equalization parameter combination is automatically latched into the physical layer (PHY) control register by the hardware logic and takes effect immediately without the need for software loading or configuration.

[0057] (11) Software Configuration Table A list of combinations of load balancing parameters stored in read-write memory and dynamically configured and updated by preset software or drivers.

[0058] (12) Local Physical Layer (PHY) The physical layer circuit, located inside the communication terminal, is responsible for actually sending and receiving high-speed serial signals and interacts with the MAC layer through the PIPE interface.

[0059] (13) Inter-chip communication Communication between communication terminals is conducted through protocols such as Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), and Integrated Circuit Bus (I2C) to transmit evaluation results, status notifications, etc.

[0060] (14) Advanced Peripheral Bus (APB) The full name is Advanced Peripheral Bus, an on-chip bus used to connect low-bandwidth peripherals. In this embodiment of the disclosure, the software configures the registers related to the PIPE interface through the APB.

[0061] (15) PCIe Physical Layer Interface (PIPE) The full name is Physical Interface for PCI Express, which defines the interface standard between the MAC layer (Media Access Control Layer) and the PHY layer, including control signals and data paths. Specifically, the MAC layer is the logic module responsible for implementing the link training state machine and controlling the local physical layer through the PIPE interface. The second configuration register and evaluation trigger signals involved in this scheme all belong to the PIPE interface.

[0062] (16) Second Configuration Register The Control and Status Register (CSR) of the PCIe physical layer interface is used to write candidate equalizer configurations to instruct the local physical layer to send signals according to those configurations.

[0063] (17) Evaluate the trigger signal This control signal is used to initiate the local physical layer's quality assessment of received signals. The software sets this signal to an active state (e.g., high level) via the high-level peripheral bus. Upon detecting this signal, the local physical layer begins quality assessment of the currently received communication signal and returns an assessment score upon completion. This signal is a standard control signal in the PCIe Physical Layer Interface (PIPE).

[0064] (18) Two-way equalization processing This includes first-direction equalization (first communication end sends, second communication end evaluates) and second-direction equalization (second communication end sends, first communication end evaluates), ultimately enabling both parties to obtain suitable equalization configuration parameters in the sending and receiving directions respectively.

[0065] (19) Third Configuration Register A register used to indicate whether the bidirectional equalization process has ended. When the bidirectional equalization process is finished, the software sets it to the first state value.

[0066] (20) Fourth Configuration Register This register indicates whether the bidirectional equalization process was successful. It is set to the first status value upon success and the second status value upon failure.

[0067] (21) Receive lock status (RcvrLock) In the PCIe protocol, after the link training is completed and equalization is achieved, it enters a locked state, which is used to continue to execute subsequent training steps to enter the normal transmission state.

[0068] (22) Speeding state In the PCIe protocol, after a link training failure, the transmission rate is reduced and retried. This is used to reduce the transmission rate and restart the link training.

[0069] The technical solutions involved in the embodiments of this disclosure will be described in detail below.

[0070] As mentioned earlier, during PCIe link training, the Link Training State Machine (LTSSM) contains multiple states, among which the Recovery state is a phase used to handle link anomalies, perform rate changes, or perform equalization adjustments. Equalization is a key sub-state within the Recovery state, its function being to adjust signal compensation parameters (i.e., equalization configuration parameters) between the transmitter and receiver to reduce the effects of inter-symbol interference and reflections, thereby optimizing communication quality. The equalization control method of this disclosure embodiment is applied to the equalization sub-state within the Recovery state.

[0071] To enable those skilled in the art to more clearly understand the technical solutions of this disclosure, the link training state machine of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0072] Figure 1 This disclosure provides a schematic diagram of the framework structure of a link training state machine according to an exemplary embodiment. For example... Figure 1 As shown, in the Link Training State Machine (LTSSM), the system enters the recovery state via the Recovery entry point, first entering the receive lock state (RcvrLock) within the recovery state (represented as "Recovery-Receive Lock State" in the diagram). In this state, the Link Training State Machine (hereinafter referred to as the state machine) selects the subsequent equalization path based on the current value of the first configuration register (represented as the "configuration register" in the diagram). Specifically: If the value of the first configuration register is the second preset value (e.g., 0, corresponding to the second equalization mode), then the hardware automatic equalization branch in the recovery state (represented as "Recovery-Equalization (Hardware Automatic Equalization)" in the figure) is entered. The hardware automatically completes the equalization parameter adjustment and signal quality evaluation according to the PCIe protocol. If the execution of this branch is successful, it jumps to the receive configuration state in the recovery state (Recovery.RcvrCfg) (represented as "Recovery-Receive Configuration State" in the figure). If the execution fails, it jumps to the speed reduction state in the recovery state (Speed) (represented as "Recovery-Speed ​​Reduction State" in the figure).

[0073] If the value of the first configuration register is the first preset value (e.g., 1, corresponding to the first equalization mode), then the software equalization branch in the recovery state (represented as "recovery-equalization (software equalization)" in the figure) is entered, and the software takes over the entire equalization process; when the software equalization is successful, it also jumps to the receiving configuration state in the recovery state, and when it fails, it also jumps to the deceleration state in the recovery state.

[0074] From the receive configuration state (Recovery.RcvrCfg) in the recovery state, one can further exit to various target states, including: Loopback, Idle state in the recovery state (Recovery.Idle) (represented as "Recovery-Idle" in the diagram), Detect, L0 state (normal transmission state), Hot Reset, or Disabled. The triggering conditions for exiting to each target state follow the PCIe protocol standard, such as training completion, test mode, reset command, link disabling, re-detection, and idle waiting. Those skilled in the art can understand the specific implementation of these triggering conditions based on the PCIe protocol specification, and therefore will not be elaborated further.

[0075] In the above framework, the hardware automatic balancing branch is fully compatible with the PCIe standard protocol, while the software balancing branch completes bidirectional balancing through software control and feeds back the processing result (success or failure) to the link training state machine, which then jumps to the corresponding target state based on the result. Subsequent detailed implementation methods will be described in detail around the steps of the software balancing branch.

[0076] Figure 2 This is a flowchart illustrating a balanced control method for PCIe communication, as an exemplary embodiment of this disclosure. The balanced control method for PCIe communication, according to an embodiment of this disclosure, can be applied to a first communication end, which is a device supporting the PCIe protocol and includes a link training state machine.

[0077] In this embodiment, both the first and second communication terminals are devices supporting the PCIe protocol, each including a Link Training State Machine (LTSSM) and hardware logic for load balancing control (such as a PIPE interface, local physical layer PHY) and a software-accessible register interface (such as an APB bus). They are connected via a PCIe link and may also have inter-chip communication channels (such as SPI, UART, I2C).

[0078] The first communication end can be any of the following devices: a PCIe root complex, such as a PCIe controller or a standalone host bridge chip in a central processing unit (CPU), a downstream port (DSP) or an upstream port (USP) of a PCIe switch, a PCIe endpoint device, such as a graphics processing unit (GPU), a solid-state drive (SSD), a network interface card (NIC), etc.; or other integrated circuits with integrated PCIe interfaces, such as a PCIe hard core or soft core in an FPGA.

[0079] Correspondingly, the second communication end can be a peer device that establishes a PCIe link with the first communication end. Its device type is similar to that of the first communication end, but its role is reversed. For example, when the first communication end is a root complex, the second communication end is usually an endpoint device; when the first communication end is a downlink port of a switch, the second communication end can be an endpoint device or an uplink port of another switch.

[0080] To ensure the proper functioning of the equalization control method disclosed herein, the first and second communication terminals must have at least the following configurations: Hardware level: Support for PCIe 3.0 and above; implementation of a PIPE interface (or equivalent MAC-PHY interface); inclusion of configurable transmitter equalization coefficient registers (e.g., deepmph control) and receiver evaluation functions (e.g., fig_merit register); provision of APB or other on-chip buses to allow software access to these registers; additional inter-chip communication interfaces (e.g., GPIO-simulated SPI / UART) or utilization of existing sideband signals. Software level: The device driver or firmware includes an equalization control module capable of performing candidate configuration traversal, evaluation score comparison, optimal configuration selection, and register read / write operations; it can also exchange information with the peer via inter-chip communication; and it can configure the first configuration register (mode selection) and the third and fourth configuration registers (result feedback).

[0081] In actual chip products, the first communication terminal and the second communication terminal can be integrated into two different chips on the same circuit board, or they can belong to different boards and be interconnected through connectors. Regardless of the specific physical form, as long as the above-mentioned hardware and software configuration basics are met, the equalization control method disclosed herein can be applied.

[0082] like Figure 2 As shown, a leveling control method for PCIe communication according to an embodiment of this disclosure may include the following steps: Step 110: Obtain the mode state value from the link training state machine to determine the equalization control mode.

[0083] After the link training state machine enters the receive-locked state (RcvrLock) in the recovery state, the current configured mode state value can be obtained to determine the equalization control mode to be used in the subsequent equalization process. In this embodiment, the equalization control mode may include, for example, a first equalization mode and a second equalization mode, corresponding to hardware automatic equalization and software equalization, respectively. The mode state value allows system designers or users to flexibly and automatically implement equalization control and selection.

[0084] In one implementation of this disclosure, the mode state value can be stored in the link training state machine configuration register. The corresponding equalization control mode is determined by reading the value of this register. Specifically, a readable and writable register can be set internally or externally within the link training state machine. Its default value can be written by the hardware firmware, BIOS (Basic Input / Output System), or operating system driver during system startup. When the link training enters the receive-locked state in the recovery state, the software (e.g., the driver) can read the value of this register to determine the equalization control mode. For example, a register value of 1 indicates software equalization, while a register value of 0 indicates hardware automatic equalization.

[0085] As another implementation of this disclosure, the mode state value can be implemented in an embedded system based on a device tree. Specifically, a custom attribute, such as `pcie-equalization-mode`, can be added to the device tree node. Its value can be set to `software` (software equalization) or `hardware` (hardware automatic equalization) to correspond to software equalization and hardware automatic equalization, respectively. When the system starts, the bootloader or kernel parses the device tree, writes the attribute value to the mode register corresponding to the link training state machine, and then reads the value of the mode register to determine the equalization control mode. Without modifying the hardware, the equalization mode can be flexibly switched by modifying the device tree, which is particularly suitable for FPGA (Field-Programmable Gate Array) prototyping or scenarios where the equalization strategy needs to be adjusted according to different board configurations.

[0086] As another implementation of this disclosure, the mode state value can be dynamically written by an external controller via a bus interface (I²C / SMBus / APB). Specifically, the external controller within the system (such as a baseboard management controller (BMC) or an embedded microcontroller (MCU)) dynamically writes configuration values ​​to the mode register of the link training state machine during system operation via buses such as I²C, SMBus, or APB. For example, when a link quality degradation is detected, the BMC can proactively switch the mode to software equalization for fine-tuning. This method supports out-of-band management and can dynamically change the equalization strategy without restarting the system, improving system maintainability and troubleshooting capabilities.

[0087] As another implementation of this disclosure, the mode state value can be configured via pin strapping. Specifically, during chip power-on reset, the hardware logic samples the level state of a specific configuration pin (e.g., fixing a high or low level via pull-up / pull-down resistors) and latches this level into an internal register as the mode state value. The software can determine the equalization control mode by reading this latched value. In this way, the mode state value can be completely determined by the hardware without any software intervention, making it suitable for applications with extremely high deterministic requirements and where software intervention is not permitted, such as certain real-time systems or safety-critical systems.

[0088] As another implementation of this disclosure, the mode state value can be configured through negotiation flags (Ordered Sets) in the link training sequence. For example, during link training, the two communicating ends (e.g., the sender and receiver) can negotiate specific fields (e.g., the EC field or a vendor-defined field) in the training sequence (TS1 / TS2 Ordered Sets) to determine the balance control mode to be used. For instance, both parties agree that if a certain reserved bit is set, subsequent balance will use software balance; otherwise, hardware balance will be used, and the negotiation result will be stored as a register value. The balance control mode can be determined by reading the value of this negotiation result register. This method requires no local pre-configuration and is entirely determined by link adaptive negotiation, making it particularly suitable for unified balance strategies in multi-device interconnection scenarios, reducing the burden of manual configuration.

[0089] The embodiments disclosed herein can select any combination of one or more of the above methods according to actual product requirements, thereby achieving the best balance between flexibility, reliability, and ease of use, and ensuring that the link training state machine can accurately and efficiently enter the preset balanced control mode.

[0090] Step 120: In response to the mode state value indicating that the equalization control mode is the first equalization mode, a communication signal is transmitted to the second communication terminal to perform bidirectional equalization processing.

[0091] Bidirectional equalization processing is used to establish bidirectional link parameter negotiation and equalization configuration between the first communication end and the second communication end, so as to obtain suitable equalization configuration parameters in the signal transmission direction and the signal reception direction respectively.

[0092] In this embodiment, the first equalization mode is a preset operating mode in which software participates in controlling the adjustment of equalization coefficients and signal quality evaluation during PCIe link training. During the equalization process, software can configure registers, intervene in coefficient negotiation, or adjust parameters in real time, thereby achieving flexible control of the equalization process. Unlike the hardware equalization mode, which is entirely automated by the hardware state machine, the first equalization mode allows upper-layer software or drivers to dynamically adjust the equalization strategy according to the link environment. For example, it can increase the feedforward equalizer (FFE) coefficient for high-loss channels, adjust the decision feedback equalizer (DFE) taps for specific interference, or perform fault diagnosis and manual optimization in abnormal situations. For instance, when the PCIe device is powered on, the system software first reads the link status. If it determines that the current link environment is complex (such as the presence of a long-distance backplane or high insertion loss), it selects the first equalization mode. The software sets the initial values ​​of the equalization coefficients for the transmitting and receiving ends by configuring relevant registers, and then triggers link training. The hardware completes subsequent bidirectional equalization interactions based on the parameters set by the software. This mode has advantages such as high flexibility, strong debuggability, and adaptability to complex link scenarios, making up for the shortcomings of the fixed and difficult-to-intervene hardware automatic equalization process.

[0093] In this embodiment, the equalization process is taken over by software. Through cooperation between the first and second communication terminals, equalization configurations in both directions can be completed sequentially. Specifically, the first communication terminal first acts as a sender, traversing multiple candidate equalization configurations, such as multiple presets predefined in the PCIe protocol, and sequentially sending test signals to the second communication terminal. The second communication terminal evaluates the quality of each test signal and returns the evaluation result. The first communication terminal selects the optimal equalization configuration as the target equalization configuration for the transmission direction based on the evaluation result. Subsequently, the first communication terminal switches to the receiver role, receiving the test signals sent by the second communication terminal based on its candidate configurations, evaluating the signal quality, and returning the evaluation result to the second communication terminal, which then selects the target equalization configuration for its transmission direction. The above processes together constitute a complete bidirectional equalization process.

[0094] The embodiments disclosed herein include, but are not limited to, the following implementation methods for bidirectional equalization processing: As one implementation of this disclosure, the evaluation can be based on a traversal of the protocol's preset load balancer configurations. For example, the first communication terminal can select from a predefined preset list in the PCIe protocol specification, such as candidate load balancer configurations like P4, P6, P7, and P8, and apply them sequentially to the local physical layer in ascending order, then notify the second communication terminal to initiate the evaluation. Load balancing processing in this direction is completed based on the evaluation results from the second communication terminal. The reverse direction is similar and will not be elaborated further. This method fully complies with PCIe protocol requirements, is simple to implement, and offers optimal compatibility.

[0095] As another implementation of this disclosure, a coefficient vector can be formed by independently adjusting the specific values ​​of each equalization coefficient (e.g., Preshoot, De-emphasis) at the transmitting end, and then finding the optimal coefficient combination through evaluation feedback at the receiving end. This method provides a finer tuning granularity and is suitable for scenarios with extremely high requirements for signal quality.

[0096] As another implementation of this disclosure, adaptive equalization can be employed. Specifically, the receiver dynamically calculates and directly feeds back suggested coefficient adjustments to the transmitter based on real-time signal quality (such as eye diagram opening and bit error rate). The transmitter then gradually updates the coefficients accordingly, forming a closed-loop adaptive adjustment. This method does not require explicit traversal of preset configurations, has a fast convergence speed, and typically requires hardware support for the LMS (Least Mean Square) algorithm. It is suitable for situations where channel characteristics change in real time.

[0097] As another implementation of this disclosure, coefficient matching based on a lookup table (LUT) can be used. Specifically, a lookup table for channel characteristics to optimal coefficients can be pre-established through simulation or actual measurement. During equalization processing, the first communication end first measures channel characteristics, such as insertion loss and reflection, and then directly looks up the optimal coefficients in the table, without needing to send multiple sets of test signals. This method is the most efficient, but it relies on the accuracy of pre-calibrated data and is suitable for fixed link scenarios, such as backplanes and short-distance chip interconnects.

[0098] It should be noted that, in the signal transmission direction, the transmitting end is, for example, the first communication end, and the receiving end is, for example, the second communication end; conversely, in the signal reception direction, the transmitting end is, for example, the second communication end, and the receiving end is, for example, the first communication end. Accordingly, the second communication end can be a peer device that establishes a PCIe link with the first communication end, and its device type is similar to that of the first communication end, but its role is reversed (for example, when the first communication end is a root complex, the second communication end is usually an endpoint device; when the first communication end is a downlink port of a switch, the second communication end can be an endpoint device or an uplink port of another switch). The roles of the two can be interchanged during bidirectional balancing, and this disclosure does not limit this.

[0099] Step 130: Feedback the result of the bidirectional equalization process to the link training state machine so that the link training state machine jumps to the target state that matches the result of the bidirectional equalization process.

[0100] In this embodiment, the target state is the next working state in the link training state machine that is consistent with the result of the current equalization process. In the PCIe protocol, the Link Training State Machine (LTSSM) defines multiple states (such as detection state, polling state, configuration state, recovery state, L0 state, L1 state, etc.), each corresponding to a different stage of link training or the power management level of the link. The equalization stage is typically located in the equalization sub-stage of the recovery state. After bidirectional equalization is completed, depending on whether the equalization was successful and the degree of agreement between the two parties in the link, the LTSSM needs to jump to the corresponding subsequent state: if the equalization is successful and the link has established stable communication, the target state is L0 (normal operation state), at which point the link can begin transmitting data; if the equalization is partially successful but requires reconfiguration or fine-tuning of parameters, the target state may fall back to the configuration sub-state in the recovery state or re-enter the equalization sub-state; if the equalization fails, the target state is either the detection state or the polling state to restart link training. In short, the target state is the predetermined protocol state that LTSSM should enter based on the bidirectional equalization process results (including successful coefficient negotiation, signal quality meeting standards, and link width and rate determination). It determines the subsequent behavior of the link, such as data transmission or retraining. This definition clarifies that the target state is a defined node in the protocol's finite state machine, and its state transition is triggered by the current equalization result.

[0101] In this step, the result of the bidirectional equalization process is fed back to the link training state machine, causing it to transition to a target state matching the result. Specifically, when the bidirectional equalization process is successful (i.e., both the first and second target equalization configurations are successfully configured), the link training state machine should transition to the receive-locked state (RcvrLock) to continue subsequent training steps and enter the normal transmission state (L0). When the bidirectional equalization process fails, such as due to configuration failure in either direction or inter-chip communication timeout, the link training state machine can transition to the speed-down state (Speed) to reduce the transmission rate and restart link training. In other words, this step achieves the transmission of the final decision (success / failure) of the software equalization to the link training state machine in a hardware-recognizable manner, thereby triggering the corresponding state transition.

[0102] One implementation approach is to adjust the values ​​of corresponding registers based on the results of bidirectional equalization. For example, a register value of 1 indicates successful bidirectional equalization, while a register value of 0 indicates failure. The link training state machine can then read the values ​​of these two registers using combinational logic or sequential circuitry and execute transitions accordingly. This method is simple to implement, has low latency, and is fully compatible with existing register access mechanisms.

[0103] As another implementation method, after completing the bidirectional equalization process, an interrupt request can be sent to the link training state machine or interrupt controller to trigger the interrupt service routine of the link training state machine. The hardware will then automatically handle the state transition within the interrupt service routine. This method avoids continuous hardware polling of registers, reduces power consumption, and is suitable for power-sensitive systems.

[0104] As another implementation method, message bus transmission In Low Pin Count interfaces using PIPE 5.0 and above, custom messages, such as "Balanced Operation Complete" messages and their result parameters, can be sent via the message bus. Upon receiving this message, the Media Access Control (MAC) layer parses the success / failure information and triggers a state machine transition. This method reduces the number of dedicated pins, making it suitable for pin-constrained chip designs.

[0105] As another implementation, a dedicated hardware signal line, such as a GPIO or dedicated pin directly connected to the state machine control logic, can output a high / low level. The link training state machine detects the level change and immediately reads the result. This method offers the fastest response speed.

[0106] Figure 3 This is a flowchart illustrating a leveling control method for PCIe communication, as shown in another exemplary embodiment of this disclosure. Figure 3 As shown in the figure, a leveling control method for PCIe communication according to an embodiment of this disclosure may further include: Step 111: Read the value of the first configuration register in the link training state machine as the mode state value.

[0107] After the link training state machine enters the receive-locked state (RcvrLock) in the recovery state, the software reads the current value of the first configuration register located in the link training state machine through the Advanced Peripheral Bus (APB). This value is the mode state value. The first configuration register is a register defined internally by the link training state machine, for example, it can be named cfg_eq_software, and it is used to store the selection information of the equalization control mode.

[0108] The first configuration register is typically located in the Control and Status Register (CSR) space of the MAC layer, and its bit width can be 1 bit or more (e.g., using only the least significant bit). During system initialization, such as BIOS / UEFI boot or driver loading, a first preset value (e.g., 1) or a second preset value (e.g., 0) can be written to this register according to user configuration or firmware default settings. When the link training reaches the receive lock state in the recovery state, the driver performs a read transaction through the APB bus to obtain the value of this register as the mode status value.

[0109] By reading the first configuration register, the software can obtain the equalization control mode with extremely low latency, and this operation is fully compatible with the existing PCIe register access mechanism without any additional hardware overhead.

[0110] Step 112: In response to the mode state value being the first preset value, the equalization control mode is determined to be the first equalization mode.

[0111] If the mode state value read in step 111 is equal to the first preset value, such as 1, then it is determined that the first equalization mode, i.e., the software equalization mode, should be adopted. The characteristic of the first equalization mode is that the software takes over the entire equalization process, including determining candidate equalization configurations, controlling transmission, receiving evaluation results, selecting the optimal configuration, and feeding back the results to the state machine.

[0112] In this embodiment, a conditional statement can be used to compare the mode state value with a first preset value. If they are equal, an internal state variable can be set, for example, eq_mode = FIRST_EQUALIZATION_MODE. All subsequent control flows related to equalization will be implemented through the first equalization mode branch, i.e., the software equalization branch. At this time, the hardware automatic equalization logic is masked, and the link training state machine will not perform equalization on its own, but will wait for software instructions.

[0113] The judgment logic is simple and reliable, can accurately distinguish between the two equilibrium modes, and is easy to expand. For example, different preset values ​​can be added to add more modes.

[0114] Step 113: In response to the mode state value being the second preset value, the equalization control mode is determined to be the second equalization mode, which is an equalization mode in which the equalization parameters are automatically adjusted and the signal quality is evaluated by the hardware.

[0115] If the mode status value read in step 111 is equal to the second preset value, which is, for example, 0, then it is determined that the second equalization mode, i.e., the hardware automatic equalization mode, should be used. The second equalization mode is an equalization mode in which the equalization parameters are automatically adjusted and the signal quality is evaluated by hardware, and it fully follows the default hardware equalization process of the PCIe protocol.

[0116] The second equalization mode is a preset operating mode during PCIe link training, where the Link Training State Machine (LTSSM) automatically adjusts the equalization coefficients and evaluates the signal quality according to the protocol's defined procedures. In this mode, the equalization process is entirely driven by the hardware state machine, requiring no software intervention. For example, when the PCIe device powers on or the link resets, the LTSSM enters the equalization phase. The hardware automatically controls the feedforward equalizer (FFE) coefficients at the transmitting end and the continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE) parameters at the receiving end, sequentially completing coefficient negotiation, phase adjustment, and signal optimization, ultimately bringing the link into a normal transmission state. This mode offers advantages such as fast execution speed, good protocol compatibility, and controllable power consumption, making it suitable for most conventional link environments.

[0117] In this embodiment, a conditional statement can be used to compare the mode state value with a second preset value. If they are equal, the internal state variable is set to SECOND_EQUALIZATION_MODE, and the link training state machine is notified to skip the software takeover branch and continue executing hardware automatic balancing. At this time, the software no longer interferes with the balancing process, and the hardware state machine automatically completes coefficient traversal, evaluation, and configuration according to the PCIe protocol specification.

[0118] This branch ensures full backward compatibility with existing PCIe protocols. When the first configuration register is set to the second preset value, the entire balancing behavior is exactly the same as conventional hardware automatic balancing that does not employ this disclosure, without introducing any additional risks or compatibility issues.

[0119] Furthermore, it should be noted that the first preset value and the second preset value are two pre-set values ​​or conditional thresholds used to identify different equalization modes during the link training or equalization control process. The first preset value is compared with the mode state value to determine whether the current equalization control mode is the first equalization mode (e.g., software equalization mode); the second preset value is used to determine whether it is the second equalization mode (e.g., hardware automatic equalization mode). These two preset values ​​can be mutually exclusive; for example, the first preset value can be set to logic "1" or a specific register bit value, and the second preset value can be set to logic "0" or another specific value. In actual control, the system reads the value of the current equalization mode state register and compares it with the first preset value: if they are equal, the processing flow corresponding to the first equalization mode is triggered (e.g., software participation coefficient adjustment, sending training sequences, etc.); if they are equal to the second preset value, the processing flow corresponding to the second equalization mode is triggered (e.g., hardware automatic equalization). If neither is equal, it can be considered invalid or the default processing is executed. The specific values ​​of the first and second preset values ​​can be pre-configured according to the chip design or protocol agreement; they are key benchmarks for pattern recognition, ensuring that the link's equalization strategy can be accurately distinguished and executed.

[0120] This embodiment enables the software to acquire the equalization control mode with minimal overhead and dynamically select whether equalization is performed by software or hardware based on the mode state value. This preserves the protocol compatibility of automatic hardware equalization while providing a complete software equalization solution for scenarios requiring flexible debugging or complex link environments, achieving the design goal of a single chip serving two purposes.

[0121] Figure 4 This is a flowchart illustrating a leveling control method for PCIe communication, as shown in another exemplary embodiment of this disclosure. Figure 4 As shown in the figure, a leveling control method for PCIe communication according to an embodiment of this disclosure may further include the following steps: Step 121: Determine at least one candidate load balancer configuration, each candidate load balancer configuration including at least one load balancer configuration parameter.

[0122] In software load balancing mode, the first communication end needs to determine a set of load balancing configuration parameters to be tried. Each candidate load balancing configuration contains at least one load balancing configuration parameter, such as the combination of coefficients like Preshoot and De-emphasis at the sending end. These candidate load balancing configurations can come from predefined preset values ​​(Preset, such as P4, P6, P7, P8) in the PCIe protocol specification, or from parameter combinations stored in hardware preset tables or software configuration tables.

[0123] In this embodiment, the first communication terminal can read at least one candidate load balancer configuration from a preset configuration list. The preset configuration list can be implemented in the following ways: ① Protocol preset values: directly using the presets defined in the PCIe protocol specification. These preset values ​​have a fixed mapping table within the hardware PHY; only the preset number needs to be known. ② Hardware preset table: a list of fixed parameter combinations embedded in the chip's read-only memory area. It is directly latched and used after power-on reset, without the need for software loading. ③ Software configuration table: a list of parameter combinations stored in a read-write memory, dynamically configured and updated by the driver or firmware, allowing for on-site adjustment.

[0124] The software iterates through the list to obtain each candidate balance configuration sequentially. In the embodiments of this disclosure, the traversal order of the candidate balance configurations can be in ascending order of the Preset number, such as P4, P6, P7, and P8. For example, assuming the first communication end supports four Presets: P4, P6, P7, and P8, the software-defined array is, for example, uint8_t candidate_presets[] = {4, 6, 7, 8}, and int num_candidates = 4.

[0125] The preset configuration list allows for flexible selection of the load balancer configuration to be evaluated, supporting both standard protocol-defined presets and vendor-defined combinations of hardware or software parameters, thus improving the adaptability and scalability of the solution.

[0126] Step 122: Send a first communication signal to the second communication terminal based on at least one candidate equalization configuration, so as to determine the first target equalization configuration that adapts the signal transmission direction based on the evaluation result of the first communication signal by the second communication terminal.

[0127] In this embodiment, the first communication terminal can iterate through each candidate equalization configuration, apply them sequentially to the local physical layer (PHY), and send a first communication signal, such as the training sequence TS2, to the second communication terminal via a PCIe link. Upon receiving each signal, the second communication terminal performs a quality assessment and returns an assessment result, such as an evaluation score. The evaluation score can range from 0 to 255, with a higher value indicating better signal quality. After collecting the evaluation scores of the first communication signals corresponding to all candidate equalization configurations, the first communication terminal selects the candidate equalization configuration with the highest score as the first target equalization configuration for the signal transmission direction.

[0128] The evaluation score can be a comprehensive indicator or a single value used during PCIe link training or equalization to quantify the signal quality at the receiver (such as eye diagram opening, bit error rate, signal-to-noise ratio, etc.). It can be calculated by the signal monitoring circuitry at the receiver (e.g., eye diagram monitor, bit error rate counter) or the evaluation logic in the link training state machine, reflecting the link transmission performance under the current equalization parameter configuration. A higher evaluation score generally indicates better signal quality; for example, a fully open eye diagram, low bit error rate, and low jitter indicate a relatively ideal equalization coefficient configuration and stable link communication. Conversely, a lower evaluation score indicates poorer signal quality; for example, a closed eye diagram, high bit error rate, and severe crosstalk indicate that the current equalization parameters are insufficient to compensate for channel loss or that other interference exists, requiring further adjustment of the equalization coefficients at the transmitter and receiver (such as the parameters of a feedforward equalizer, continuous-time linear equalizer, or decision feedback equalizer). During the equalization process, the evaluation score can be compared with a preset pass threshold. If the score reaches or exceeds the threshold, the equalization is considered successful, and the link training state machine jumps to a normal working state (such as L0). If the score is below the threshold, the equalization is considered to have failed or needs to be retried, and the link training state machine may fall back to a state of retraining or parameter adjustment. The evaluation score provides a quantifiable decision basis for equalization processing.

[0129] Specifically, for each candidate load balancing configuration, the following operations can be performed: First, the candidate equalizer configuration can be written into the second configuration register corresponding to the PIPE interface, such as the Control and Status Register (CSR), via the APB bus, instructing the local PHY to send subsequent signals, i.e., the first communication signal, according to the candidate equalizer configuration. Then, the second communication end can be notified to start evaluating the quality of the currently transmitted signal through inter-chip communication; wherein, inter-chip communication can adopt any of the following protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), and Integrated Circuit Bus (I2C).

[0130] Secondly, the second communication terminal triggers its local PHY to perform an evaluation, and after obtaining the evaluation score, it returns it to the first communication terminal through inter-chip communication; Finally, the first communication terminal saves the score corresponding to the candidate configuration.

[0131] After traversing all candidate configurations, compare all scores and determine the candidate configuration corresponding to the highest score as the first target balanced configuration.

[0132] Continuing with the candidate list from step 121, the first communication terminal is configured with P4, P6, P7, and P8 in sequence. Assuming that the evaluation scores returned by the second communication terminal are 210, 235, 228, and 190 respectively, P6 with the highest score is determined as the first target equilibrium configuration.

[0133] By iterating through and comparing evaluation scores, the first communication end can select the optimal transmission configuration based on objective signal quality indicators rather than subjective guesswork, thereby maximizing the signal quality in the transmission direction.

[0134] Step 123: Receive the second communication signal sent by the second communication terminal based on at least one candidate equalization configuration, and return the evaluation result of the second communication signal to the second communication terminal so that the second communication terminal can determine the second target equalization configuration that adapts to the signal reception direction.

[0135] In this step, the first communication terminal switches to the receiving role, receiving the second communication signals sequentially transmitted by the second communication terminal based on its candidate equalization configuration. For each communication signal, the first communication terminal triggers its local physical layer to perform a signal quality assessment, obtains an assessment score, and then returns the score to the second communication terminal via inter-chip communication. Based on this, the second communication terminal selects the candidate equalization configuration with the highest score as its transmission direction, i.e., the second target equalization configuration in the signal reception direction.

[0136] In this embodiment of the disclosure, after the roles are reversed, the software of the first communication terminal performs the following operations: First, wait for the second communication terminal to notify the first communication terminal via inter-chip communication that signal evaluation can begin. For example, the second communication terminal sets its own equalization configuration according to its own candidate equalization configuration list, and after each setting, it will notify the first communication terminal via inter-chip communication that signal evaluation can begin. Secondly, for each incoming signal, the evaluation trigger signal in the PIPE interface is set via the APB bus, such as pipe_rxX_eq_eval, to start the local physical layer PHY to evaluate the quality of the currently received signal. Then, after the physical layer evaluation is completed, the evaluation score (which can be a value from 0 to 255) is output to the evaluation result signal of the PIPE interface (e.g., pipe_rxX_eq_fig_merit), and a valid indication signal (e.g., pipe_laneX_phystatus) is determined at the same time. After detecting the valid indication, the control and status register (CSR) corresponding to the pipe_rxX_eq_fig_merit signal is read through the APB bus to obtain the evaluation score.

[0137] Subsequently, the evaluation score is returned to the second communication terminal via inter-chip communication, so that the second communication terminal can collect all evaluation scores and select the candidate equalization configuration corresponding to the highest score as its second target equalization configuration. The inter-chip communication can use any of the following protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver / Transmitter (UART), and Integrated Circuit Bus (I2C).

[0138] In this step, the second communication end is able to obtain the optimal balanced configuration of its transmission direction in a completely symmetrical manner, thereby achieving bidirectional balance and ensuring that both ends of the link can obtain the best signal quality when transmitting data.

[0139] Step 124: Determine the result of the bidirectional equilibrium processing based on the first objective equilibrium configuration and the second objective equilibrium configuration.

[0140] After completing the equalization in both directions, the first communication terminal determines its first target equalization configuration for its signal transmission direction, and the second communication terminal also determines its second target equalization configuration for its signal transmission direction (corresponding to the signal reception direction of the first communication terminal). The first communication terminal needs to determine whether the final result of the entire bidirectional equalization process is successful or unsuccessful based on whether these two configurations are successfully configured and whether they meet the legal conditions. This result will be used for subsequent link training state machine transitions.

[0141] In this embodiment of the disclosure, the second communication terminal can also perform the same judgment as the first communication terminal. Specifically, the first communication terminal will notify the second communication terminal of its successful configuration result through inter-chip communication. The second communication terminal can combine the result of the first communication terminal and the result of successful configuration to determine the final result of its bidirectional equalization processing.

[0142] Furthermore, after completing the equalization configuration in the first direction (sent from the first communication terminal) and the second direction (sent from the second communication terminal), the first communication terminal can synthesize the configuration results of the two directions to determine the final state (success or failure) of the entire bidirectional equalization process, and can feed the result back to the link training state machine by setting two dedicated registers (the third configuration register and the fourth configuration register). The third configuration register indicates whether the bidirectional equalization process has ended, and the fourth configuration register indicates whether the bidirectional equalization process has succeeded. Specifically: if both the first and second target equalization configurations are successfully configured, the third and fourth configuration registers are set to the first state value, for example, both are 1, indicating that the result of the bidirectional equalization process is the first result state (e.g., success); if the configuration in either direction fails, the third configuration register is set to the first state value (indicating end), and the fourth configuration register is set to the second state value (e.g., 0), indicating that the result of the bidirectional equalization process is the second result state (failure).

[0143] In this embodiment, the first and second state values ​​are preset values ​​stored in the third and fourth configuration registers, used to indicate the result type of the bidirectional equalization processing in a hardware-readable manner. The first and second state values ​​can be mutually exclusive; for example, the first state value can be set to logic "1" (or high level), and the second state value can be set to logic "0" (or low level). The first result state is a successful bidirectional equalization processing state, meaning that the target equalization configurations of both the first and second communication ends have been successfully applied, and the link has stable communication conditions. The second result state is a failed bidirectional equalization processing state, meaning that the equalization configuration of at least one of the first and second communication ends has failed to be successfully applied, and the link cannot enter the normal transmission state. Specifically: when both the first and second target equalization configurations are successfully configured, the third and fourth configuration registers are set to the first state value, thereby jointly indicating that the current bidirectional equalization processing result is the first result state (success); when either one fails to configure, the third configuration register is set to the first state value, and the fourth configuration register is set to the second state value, thereby combining to indicate that the current bidirectional equalization processing result is the second result state (failure). Through this combined encoding method, the link training state machine can accurately determine the equalization result based on the state values ​​of these two registers and jump to the corresponding target state (for example, if successful, it enters the L0 state; if it fails, it falls back to the detection state or retrains).

[0144] At the first communication terminal, the value of the fourth configuration register can be determined by the following conditions: ① Whether the first target load balancing configuration has been successfully written to the local physical layer, i.e., the configuration operation has not been erroneous and the coefficients are within the legal range; ② Whether the second communication terminal has successfully completed its load balancing configuration can be determined through the inter-chip communication status or by the second communication terminal itself. ③ No inter-chip communication timeouts or other anomalies occurred during the entire process.

[0145] If all conditions are met, the bidirectional balancing process is considered successful; otherwise, if any condition is not met, it is considered a failure. The result is then temporarily stored, for example, through an internal variable `bidirectional_result`.

[0146] Subsequently, the following register write operations can be performed via the APB bus: Write the third configuration register to the first state value, for example, 1, indicating that the bidirectional equalization process has ended. If successful, also write the fourth configuration register to the first state value, for example, 1. If it fails, write the fourth configuration register to the second state value, for example, 0. The hardware (link training state machine) continuously monitors the third configuration register. When its value is the first state value, it reads the value of the fourth configuration register: if it is the first state value, the state machine jumps to the receive lock state (RcvrLock); if it is the second state value, it jumps to the speed reduction state (Speed).

[0147] For example, assume that the first target load balancer configuration (P6) has been successfully written to the local PHY, and a load balancer success confirmation message has been received from the second communication terminal via inter-chip communication, with no timeout exception.

[0148] The first communication signal refers to a specific signal sequence sent by the local communication device (first communication end) to the second communication end during link training or equalization, used for establishing a link, negotiating parameters, or evaluating signal quality, such as the high-speed training sequence defined in the PCIe protocol. The second communication signal is a specific signal sequence sent by the second communication end to the local communication device during link training or equalization, used for responding, negotiating parameters, or evaluating signal quality. Both are necessary signals in the bidirectional equalization process. By exchanging these signals, both parties in the link can complete coefficient exchange, phase calibration, signal optimization, and link state confirmation, thereby ensuring the link is established normally and enters a stable data transmission state. The distinction between the first and second communication signals clarifies the directionality and interaction logic of the signals, providing a basis for subsequent state machine transitions and equalization result determination.

[0149] In this step, the two separate unidirectional equilibrium results are integrated into a global decision, ensuring that equilibrium is considered successful only after both sides of the link have reached their optimal configuration, thus avoiding a half-tuned state where one side succeeds while the other fails. This comprehensive judgment mechanism improves the robustness and reliability of link training.

[0150] Through steps 121 to 124, the first communication end completes the core processing of bidirectional equalization in software: determining candidate configurations, sending test signals and evaluating them, receiving test signals from the other end and returning the evaluation results, and finally determining the global result. The entire process fully utilizes the collaboration between the PCIe link and inter-chip communication, enabling the software to flexibly and precisely control the equalization process while ensuring compatibility with hardware automatic equalization.

[0151] Figure 5 This is a flowchart illustrating a leveling control method for PCIe communication, as shown in another exemplary embodiment of this disclosure. Figure 5 As shown in the figure, a leveling control method for PCIe communication according to an embodiment of this disclosure may include the following steps: Step 131: In response to the result of the bidirectional equalization processing being the first result state, the control link training state machine jumps to the receive lock state. The receive lock state is the lock state entered after the link training in the PCIe protocol is completed and equalization is completed. It is used to execute the link training to enter the normal transmission state.

[0152] In this embodiment, when the result of the bidirectional equalization processing is a first result state, such as indicating successful bidirectional equalization, the link training state machine can automatically jump to the receive lock state (RcvrLock) via the pre-set third (e.g., its first state value indicates the end of bidirectional equalization) and fourth configuration registers (e.g., its first state value indicates successful bidirectional equalization). The receive lock state is a lock state entered after the link training in the PCIe protocol is completed and equalization is achieved, used to continue executing subsequent training steps to enter the normal transmission state (e.g., L0 state). Thus, the link training state machine is controlled and jumps are implemented, rather than the link training state machine deciding autonomously.

[0153] As one embodiment of this disclosure, the third configuration register is set to a first state value, for example, 1, and the fourth configuration register is also set to a first state value, for example, 1. The link training state machine can continuously monitor the third configuration register. When the third configuration register is detected to be at the first state value, the link training state machine continues to read the value of the fourth configuration register; since the fourth configuration register is also at the first state value, the link training state machine determines the result to be the first result state (success). At this time, the link training state machine control circuit actively jumps the current state from the equalization sub-state in the recovery state (or the receive configuration state in the recovery state) to the receive lock state (RcvrLock). This jump is automatically completed by the hardware without further software intervention. After entering the receive lock state, the link training state machine continues to execute subsequent steps (such as channel configuration, offset removal, etc.) according to the PCIe protocol, and finally enters the L0 normal transmission state.

[0154] For example, assume the third configuration register address is 0x1000_0008 and the fourth configuration register address is 0x1000_000C.

[0155] By combining the states of registers, the software controls the state machine to successfully transition with extremely low latency and simple hardware logic. This method ensures that the link training can quickly enter the normal transmission state after successful equalization, and fully complies with the state machine definition of the PCIe protocol, offering optimal compatibility.

[0156] Step 132: In response to the result of the bidirectional equalization processing being the second result state, the control link training state machine jumps to the deceleration state. The deceleration state is the state in the PCIe protocol where the transmission rate is reduced and retried after the link training fails. It is used to reduce the transmission rate and restart the link training.

[0157] When the result of bidirectional equalization is the second result state, i.e., the result of bidirectional equalization is failure, the link training state machine can automatically jump to the speed-down state through the pre-set third configuration register (e.g., the first state value, indicating completion) and the fourth configuration register (e.g., the second state value, indicating failure). The speed-down state is the state in the PCIe protocol where the transmission rate is reduced and retried after link training fails, used to reduce the transmission rate and restart link training.

[0158] In this step, if bidirectional equalization fails, such as failure of the first or second target equalization configuration, or inter-chip communication timeout, the third configuration register can be set to the first state value (e.g., 1), and the fourth configuration register can be set to the second state value (e.g., 0). The link training state machine can continuously monitor the third configuration register. When the third configuration register is detected to be in the first state value, the link training state machine reads the value of the fourth configuration register; since the fourth configuration register is in the second state value, the link training state machine determines the result to be the second result state (i.e., failure). At this time, the link training state machine control circuit actively jumps the current state from the equalization sub-state in the recovery state (or the receive configuration state in the recovery state) to the speed-down state. After entering the speed-down state, the link training state machine will reduce the transmission rate (e.g., from Gen4 to Gen3 or Gen2) and restart link training from the detection state or recovery state to try to establish a stable link again.

[0159] This mechanism enables the hardware to automatically slow down and retrain when software equalization fails, preventing system crashes or prolonged waiting times. The retry mechanism during slowdown is an inherent reliability feature of the PCIe protocol; this step seamlessly integrates it with the failure result of software equalization, ensuring the ultimate robustness of the link training.

[0160] Through steps 131 and 132, the software accurately transmits the final result of bidirectional equalization to the hardware link training state machine using the status values ​​of the two configuration registers. The hardware then automatically switches to either a receive-locked state (success) or a deceleration state (failure). This hardware-software handshake design ensures both rapid entry into normal transmission upon success and deceleration for retrying upon failure, thereby improving the reliability and protocol compatibility of link training.

[0161] To enable those skilled in the art to clearly and accurately understand the implementation methods of the embodiments of this disclosure, the following is combined with... Figure 6 The technical solutions of the embodiments of this disclosure will be described in full and in detail.

[0162] Figure 6This is a flowchart illustrating a leveling control method for PCIe communication, as shown in another exemplary embodiment of this disclosure. Figure 6 As shown in this embodiment, two PCIe communication ports may be included: a downlink port (DSP) and an uplink port (USP), which can correspond to the first communication port and the second communication port, respectively. Each communication port may include a central processing unit (CPU), a media access control layer (MAC), a physical layer (PHY), and an inter-chip communication interface. The MAC layer integrates a Link Training State Machine (LTSSM), a multiplexer (mux), an Advanced Peripheral Bus (APB) controller, and multiple configuration registers for equalization control, such as the first configuration register, second configuration register, third configuration register, and fourth configuration register described in the previous embodiment. The PHY layer includes a signal transmitter (TX) and a signal receiver (RX), and is connected to the MAC layer through the PCIe physical layer interface (PIPE).

[0163] After the link training state machine enters the receive-locked state (RcvrLock) in the Recovery state, the multiplexer selects the equalization path based on the current value of the first configuration register (e.g., which may be named cfg_eq_software): If the value of the first configuration register is the second preset value (e.g., 0), then hardware automatic equalization (second equalization mode) is selected, and the hardware state machine inside the MAC automatically completes the equalization parameter adjustment and signal quality assessment according to the PCIe protocol.

[0164] If the value of the first configuration register is the first preset value (e.g., 1), then software equalization (first equalization mode) is selected, and the CPU directly controls and responds to the relevant PIPE signals through the APB bus, and exchanges information with the peer through inter-chip communication.

[0165] The following example uses software load balancing mode, combined with... Figure 6 The interaction between the various modules is explained in detail, along with the specific steps of the bidirectional equalization process (using the DSP as the first communication terminal and the USP as the second communication terminal). (1) Sending end coefficient settings The DSP's CPU controls the PIPE interface signals via the APB bus to set the DSP's TX coefficients (i.e., candidate equalization configuration). Specifically, the CPU writes the candidate configuration (e.g., the PCIe protocol's predefined Preset P4) into the second configuration register (Control and Status Register CSR) corresponding to the PIPE interface, and the DSP's PHY then sends the first communication signal via TX according to this configuration.

[0166] (2) Notify the other end to prepare for assessment The DSP informs the USP via inter-chip communication (using SPI, UART, or I2C protocols): "Please prepare to evaluate the signal quality received by your RX."

[0167] (3) Evaluation of the signal performed at the other end After receiving the notification, the USP's CPU controls the PIPE interface signal via the APB bus to complete the signal quality assessment at its RX end. Specifically, this includes: setting the assessment trigger signal (pipe_rxX_eq_eval) in the PIPE interface to start the USP's PHY to assess the received signal; after the assessment is completed, the USP's PHY outputs the assessment score (0~255, the higher the value, the better) to the assessment score signal (pipe_rxX_eq_fig_merit), and the USP's CPU reads this score via the APB.

[0168] (4) Return the evaluation results The USP communicates the evaluation score to the DSP via inter-chip communication.

[0169] (5) Traverse other candidate configurations The DSP continues to try other TX coefficients (e.g., P6, P7, P8, etc.), repeating steps (1) to (4) above until all candidate configurations have been evaluated.

[0170] (6) Determine and apply the optimal configuration The DSP finds the candidate configuration with the highest evaluation score (i.e. the first target equalization configuration) among all the coefficients traversed, and then repeats steps (1) to (4) to finally set the optimal configuration to the DSP's TX end, and informs the USP through inter-chip communication whether the software equalization of the DSP on the link (lane) is successful.

[0171] (7) Role swapping completes reverse equilibrium Similarly, the roles of DSP and USP are reversed: USP acts as the transmitter and DSP acts as the receiver. Repeat steps (1) to (6) above to complete the TX coefficient setting of USP, and USP informs DSP through inter-chip communication whether the software equalization of USP on this lane (the basic physical channel in the PCIe bus) is successful.

[0172] (8) Final state jump When bidirectional software equalization of the lane (the basic physical channel in the PCIe bus) between the DSP and USP is successful, both CPUs notify their respective MAC link training state machines via the APB bus that software equalization is successful. Subsequently, both link training state machines transition to the receive-locked state (RcvrLock) and continue executing subsequent link training steps to enter the normal transmission state (L0). If equalization fails in either direction (e.g., inter-chip communication timeout, all candidate configurations are invalid), both link training state machines transition to the speed-down state, reducing the transmission rate and restarting link training.

[0173] In the description of the above embodiments, it should be noted that the operation flow, coefficient adjustment logic, and state transition rules followed by the first communication end and the second communication end during the execution of the equalization configuration are completely identical. In the embodiments of this disclosure, the use of "first" and "second" is only used to distinguish two different communication devices or communication directions (e.g., local end and peer end), and does not indicate any substantial difference in the execution steps between the two. In other words, both the first communication end and the second communication end follow the same equalization configuration method for setting equalization configuration parameters, sending signals, and providing result feedback. This symmetry design in this disclosure ensures bidirectional consistency of link training and avoids negotiation failures or state asynchrony problems caused by different configuration logic. Therefore, the descriptions of "first target equalization configuration" and "second target equalization configuration" in the embodiments are based on the same set of operation rules; they differ only in role names, and their implementation methods are completely corresponding.

[0174] This disclosure provides flexible control over the equalization process during PCIe link training. Users or the system can freely choose between a first equalization mode (software equalization) and a second equalization mode (hardware automatic equalization) by setting a first configuration register. In software equalization mode, the CPU finely controls each stage of bidirectional equalization through the APB bus and inter-chip communication, adapting to complex link environments and facilitating debugging. Simultaneously, the hardware automatic equalization branch ensures full compatibility with existing PCIe protocols. This improves the robustness, debuggability, and protocol compatibility of link training.

[0175] The equalization control method for PCIe communication disclosed herein relies on an actual PCIe hardware architecture. In physical implementation, this method runs on a PCIe device containing real hardware such as a link training state machine, a media access control layer, a physical layer, and an advanced peripheral bus. During execution, the software directly reads and writes physical storage units such as the first to fourth configuration registers via the APB bus, sends control signals through the PIPE interface to adjust the equalization coefficients (such as Preshoot and De-emphasis) at the physical layer transmitter, and triggers the physical layer to perform quality assessment on the received analog electrical signals. All operation steps correspond one-to-one with hardware modules, ultimately changing the transmission rate and operating mode of the physical link by controlling the state transitions of the link training state machine (e.g., transitioning to a receive-locked state or a deceleration state), thereby directly affecting the transmission quality of the high-speed serial signal.

[0176] This disclosure allows for wide deployment in various hardware products supporting the PCIe protocol, including PCIe root complexes in central processing units, independent host bridge chips, downlink or uplink ports of PCIe switches, endpoint devices (such as graphics processors, solid-state drives, and network interface cards), and field-programmable gate arrays or application-specific integrated circuits (ASICs) with integrated PCIe interfaces. These devices are commonly found in high-speed data transmission fields such as servers, personal computers, communication base stations, industrial control, and automotive electronics. In these real-world environments, the quality of link equalization directly affects the system's stable throughput and bit error rate. By flexibly selecting hardware automatic equalization or software equalization, and utilizing the hardware-software collaborative mechanism provided in this disclosure, optimal signal quality can be obtained under complex link conditions, thereby improving the transmission performance and reliability of the device.

[0177] In summary, this disclosure overcomes the shortcomings of existing hardware automatic equalization schemes, such as fixed processes, inflexibility in adapting to complex link environments, and difficulty in debugging, by introducing a first equalization mode (i.e., software equalization mode). Specifically, it first obtains the mode state value from the link training state machine, realizing the dynamic selection of the equalization control mode. Communication signals are transmitted to the second communication end via software, and bidirectional link parameter negotiation and equalization configuration are performed, enabling the transmitting and receiving directions to obtain suitable equalization configuration parameters respectively. This solves the problem in hardware equalization where channel asymmetry (e.g., differences in downlink and uplink port trace lengths and drive capabilities) prevents separate optimization. Simultaneously, this method feeds back the bidirectional equalization processing results to the link training state machine and controls the state machine to jump to the matching target state. This ensures that the results after software intervention can be accurately identified by the hardware and the corresponding state transitions are executed (successfully jumping to the receive lock state for normal transmission, and failing to jump to the deceleration state for retry), while maintaining full compatibility with the PCIe protocol's hardware automatic equalization process. Therefore, this solution improves the flexibility, debuggability and robustness of link training while being compatible with existing hardware automatic equalization, making signal quality optimization and fault diagnosis possible in complex link environments.

[0178] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0179] Correspondingly, this disclosure also provides apparatus embodiments corresponding to the foregoing method embodiments. Figure 7 This is a structural block diagram of a PCIe communication equalization control device according to an exemplary embodiment of the present disclosure. The equalization control device for PCIe communication according to this embodiment can be applied to a first communication end, which is a device supporting the PCIe protocol and includes a link training state machine.

[0180] like Figure 7 As shown, an equalization control device for PCIe communication according to an embodiment of this disclosure may include: The mode state value acquisition module 710 is used to acquire mode state values ​​from the link training state machine to determine the equalization control mode. The bidirectional equalization module 720 is used to transmit communication signals to the second communication terminal in response to the mode state value indicating that the equalization control mode is the first equalization mode, so as to perform bidirectional equalization processing. The bidirectional equalization processing is used to establish bidirectional link parameter negotiation and equalization configuration between the first communication terminal and the second communication terminal, so as to obtain suitable equalization configuration parameters in the signal transmission direction and the signal reception direction respectively. The equalization result transmission module 730 is used to feed back the result of the bidirectional equalization process to the link training state machine, so that the link training state machine jumps to the target state that matches the result of the bidirectional equalization process.

[0181] As an optional embodiment, the mode state value acquisition module includes: The mode state value determination unit is used to read the value of the first configuration register in the link training state machine as the mode state value. The first equalization mode unit is used to determine the equalization control mode as the first equalization mode in response to the mode state value being a first preset value. The second equalization mode unit is used to determine the equalization control mode as the second equalization mode in response to the mode state value being the second preset value. The second equalization mode is an equalization mode in which equalization parameters are automatically adjusted and signal quality is evaluated by hardware.

[0182] As an optional embodiment, the bidirectional equalization module includes: A candidate configuration determination unit is used to determine at least one candidate equilibrium configuration, each of the candidate equilibrium configurations including at least one equilibrium configuration parameter. A signal transmitting unit is configured to transmit a first communication signal to the second communication terminal based on the at least one candidate equalization configuration, so as to determine a first target equalization configuration adapted to the signal transmitting direction based on the evaluation result of the first communication signal by the second communication terminal. A signal receiving unit is configured to receive a second communication signal sent by the second communication terminal based on the at least one candidate equalization configuration, and return the evaluation result of the second communication signal to the second communication terminal so that the second communication terminal can determine a second target equalization configuration adapted to the signal receiving direction. The balance result determination unit is used to determine the result of the bidirectional balance processing based on the first target balance configuration and the second target balance configuration.

[0183] As an optional embodiment, the candidate configuration determination unit includes: The configuration read subunit is used to read at least one candidate load balancing configuration from a preset configuration list; The preset configuration list includes at least one of the preset values ​​in the PCIe protocol specification, a hardware preset table, and a software configuration table. The preset values ​​in the PCIe protocol specification are combinations of load balancing parameters defined in the PCIe protocol specification. The hardware preset table is a fixed list of combinations of load balancing parameters stored in the hardware read-only memory area of ​​any communication end. The software configuration table is a list of combinations of load balancing parameters stored in a read-write memory and dynamically configured and updated by preset software or drivers.

[0184] As an optional embodiment, the signal transmitting unit includes: Configure a traversal subunit for traversing the at least one candidate equilibrium configuration; A signal transmission subunit is configured to transmit a candidate equalization configuration to the local physical layer for any one of the candidate equalization configurations, so that the local physical layer transmits a first communication signal according to the candidate equalization configuration. The first signal evaluation subunit is used to receive an evaluation score returned by the second communication terminal via inter-chip communication. The evaluation score is used to characterize the signal quality of the first communication signal received by the second communication terminal. A first configuration determination subunit is configured to, in response to the completion of traversing all the candidate equalization configurations, compare the evaluation scores of the first communication signal of each of the candidate equalization configurations, so as to determine the candidate equalization configuration with the highest evaluation score as the first target equalization configuration.

[0185] As an optional embodiment, the signal receiving unit includes: A signal receiving subunit is used to receive a second communication signal sequentially sent by the second communication end based on the at least one candidate equalization configuration; The second signal evaluation subunit is used to trigger the local physical layer to perform signal quality evaluation for each of the candidate equalization configurations corresponding to the second communication signal, and obtain the corresponding evaluation score. The second configuration determination subunit is used to return the evaluation score to the second communication terminal through inter-chip communication, so that the second communication terminal determines the candidate equilibrium configuration with the highest evaluation score as the second target equilibrium configuration based on the evaluation score.

[0186] As an optional embodiment, the signal transmitting subunit is specifically used for: The candidate equalization configuration is written into the second configuration register corresponding to the PCIe physical layer interface via the advanced peripheral bus, so as to instruct the local physical layer to send a first communication signal according to the candidate equalization configuration, wherein the second configuration register is the control and status register of the PCIe physical layer interface; The second signal evaluation subunit is specifically used for: The evaluation trigger signal corresponding to the PCIe physical layer interface is set through the advanced peripheral bus to start the local physical layer to evaluate the received second communication signal and read the evaluation score returned by the PCIe physical layer interface.

[0187] As an optional embodiment, the inter-chip communication adopts any one of the following protocols: serial peripheral interface, universal asynchronous transceiver, and integrated circuit bus.

[0188] As an optional embodiment, the equalization result determination unit includes: The first register configuration subunit is configured to, in response to the successful configuration of both the first target equalization configuration and the second target equalization configuration, set the third configuration register and the fourth configuration register to the first state value respectively, so as to indicate that the result of the bidirectional equalization process is the first result state. The second register configuration subunit is configured to, in response to the failure of either the first target equalization configuration or the second target equalization configuration, set the third configuration register to a first state value and the fourth configuration register to a second state value, so as to indicate that the result of the bidirectional equalization process is a second result state. The third configuration register is used to indicate whether the bidirectional equalization process has ended, and the fourth configuration register is used to indicate whether the bidirectional equalization process has been successful.

[0189] As an optional embodiment, the equalization result transmission module includes: The first control unit is configured to control the link training state machine to jump to the receive lock state in response to the result of the bidirectional equalization processing being a first result state. The receive lock state is the lock state entered after the link training in the PCIe protocol is completed and equalization is completed, and is used to execute the link training to enter the normal transmission state. The second control unit is used to control the link training state machine to jump to the deceleration state in response to the result of the bidirectional equalization processing being a second result state. The deceleration state is the state in the PCIe protocol where the transmission rate is reduced and retried after the link training fails, and is used to reduce the transmission rate and restart the link training.

[0190] The equalization control device for PCIe communication in this disclosure corresponds to the equalization control method embodiments for PCIe communication described above in terms of specific implementation and beneficial technical effects. Related contents can be referenced, cited, and combined with each other, and will not be repeated here.

[0191] Below, for reference Figure 8This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0192] Figure 8 A block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0193] like Figure 8 As shown, the electronic device includes one or more processors and memory.

[0194] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0195] The memory can store one or more computer program products, and the memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage medium, and the processor can run the computer program products to implement the equalization control methods for PCIe communication and / or other desired functions described in the various embodiments of this disclosure above.

[0196] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0197] In addition, the input device may also include, for example, a keyboard, a mouse, etc.

[0198] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0199] Of course, for the sake of simplicity, Figure 8 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0200] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the equalization control methods for PCIe communication according to various embodiments of this disclosure as described in the foregoing portions of this specification.

[0201] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0202] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform steps in the equalization control method for PCIe communication according to various embodiments of this disclosure as described in the foregoing portion of this specification.

[0203] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0204] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0205] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0206] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0207] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0208] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0209] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0210] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for equalization control in PCIe communication, characterized in that, Applied to a first communication terminal, which is a device supporting the PCIe protocol, the first communication terminal includes a link training state machine, and the method includes: The mode state value is obtained from the link training state machine to determine the equalization control mode; In response to the mode state value indicating that the equalization control mode is the first equalization mode, a communication signal is transmitted to the second communication terminal to perform bidirectional equalization processing. The bidirectional equalization processing is used to establish bidirectional link parameter negotiation and equalization configuration between the first communication terminal and the second communication terminal to obtain suitable equalization configuration parameters in the signal transmission direction and the signal reception direction, respectively. The result of the bidirectional equalization process is fed back to the link training state machine so that the link training state machine jumps to the target state that matches the result of the bidirectional equalization process.

2. The method according to claim 1, characterized in that, The step of obtaining mode state values ​​from the link training state machine to determine the equalization control mode includes: Read the value of the first configuration register in the link training state machine as the mode state value; In response to the mode state value being a first preset value, the equalization control mode is determined to be a first equalization mode; In response to the mode state value being a second preset value, the equalization control mode is determined to be a second equalization mode, which is an equalization mode in which equalization parameters are automatically adjusted and signal quality is evaluated by hardware.

3. The method according to claim 1 or 2, characterized in that, In response to the mode state value indicating that the equalization control mode is the first equalization mode, a communication signal is transmitted to the second communication terminal to perform bidirectional equalization processing, including: Determine at least one candidate load balancer configuration, each of the candidate load balancer configurations including at least one load balancer configuration parameter; Based on the at least one candidate equalization configuration, a first communication signal is sent to the second communication terminal respectively, so as to determine a first target equalization configuration adapted to the signal transmission direction based on the evaluation result of the first communication signal by the second communication terminal; The system receives a second communication signal sent by the second communication terminal based on the at least one candidate equalization configuration, and returns the evaluation result of the second communication signal to the second communication terminal so that the second communication terminal can determine a second target equalization configuration that is suitable for the signal receiving direction. The result of the bidirectional equalization process is determined based on the first target equalization configuration and the second target equalization configuration.

4. The method according to claim 3, characterized in that, Determining at least one candidate equilibrium configuration includes: Read at least one candidate load balancer configuration from the list of preset configurations; The preset configuration list includes at least one of the preset values ​​in the PCIe protocol specification, a hardware preset table, and a software configuration table. The preset values ​​in the PCIe protocol specification are combinations of load balancing parameters defined in the PCIe protocol specification. The hardware preset table is a fixed list of combinations of load balancing parameters stored in the hardware read-only memory area of ​​any communication end. The software configuration table is a list of combinations of load balancing parameters stored in a read-write memory and dynamically configured and updated by preset software or drivers.

5. The method according to claim 3, characterized in that, The step of sending a first communication signal to the second communication terminal based on the at least one candidate equalization configuration, and determining a first target equalization configuration adapted to the signal transmission direction based on the evaluation result of the first communication signal by the second communication terminal, includes: Iterate through at least one candidate load balancer configuration; For any of the candidate equalization configurations, the candidate equalization configuration is sent to the local physical layer so that the local physical layer sends a first communication signal according to the candidate equalization configuration. The evaluation score returned by the second communication terminal is received through inter-chip communication. The evaluation score is used to characterize the signal quality of the first communication signal received by the second communication terminal. In response to the completion of traversing all the candidate equalization configurations, the evaluation scores of the first communication signal of each candidate equalization configuration are compared to determine the candidate equalization configuration with the highest evaluation score as the first target equalization configuration.

6. The method according to claim 3, characterized in that, The step of receiving the second communication signal sent by the second communication terminal based on the at least one candidate equalization configuration, and returning the evaluation result of the second communication signal to the second communication terminal so that the second communication terminal can determine the second target equalization configuration adapted to the signal reception direction, includes: Receive the second communication signal sent sequentially by the second communication terminal based on the at least one candidate equalization configuration; For each candidate equalization configuration corresponding to the second communication signal, the local physical layer is triggered to perform signal quality evaluation and obtain the corresponding evaluation score. The evaluation score is returned to the second communication terminal via inter-chip communication, so that the second communication terminal determines the candidate equilibrium configuration with the highest evaluation score as the second target equilibrium configuration based on the evaluation score.

7. The method according to claim 5 or 6, characterized in that, For any of the candidate balancer configurations, sending the candidate balancer configuration to the local physical layer includes: The candidate equalization configuration is written into the second configuration register corresponding to the PCIe physical layer interface via the advanced peripheral bus, so as to instruct the local physical layer to send a first communication signal according to the candidate equalization configuration, wherein the second configuration register is the control and status register of the PCIe physical layer interface; The second communication signal corresponding to each of the candidate equalization configurations triggers the local physical layer to perform signal quality evaluation and obtain the corresponding evaluation score, including: The evaluation trigger signal corresponding to the PCIe physical layer interface is set through the advanced peripheral bus to start the local physical layer to evaluate the received second communication signal and read the evaluation score returned by the PCIe physical layer interface.

8. The method according to claim 5 or 6, characterized in that, The inter-chip communication adopts any one of the following protocols: serial peripheral interface, universal asynchronous transceiver, and integrated circuit bus.

9. The method according to claim 3, characterized in that, Determining the result of the bidirectional equalization process based on the first target equalization configuration and the second target equalization configuration includes: In response to the successful configuration of both the first target equalization configuration and the second target equalization configuration, the third configuration register and the fourth configuration register are set to the first state value to indicate that the result of the bidirectional equalization process is the first result state. In response to the failure of either the first target equalization configuration or the second target equalization configuration, the third configuration register is set to a first state value, and the fourth configuration register is set to a second state value to indicate that the result of the bidirectional equalization process is a second result state. The third configuration register is used to indicate whether the bidirectional equalization process has ended, and the fourth configuration register is used to indicate whether the bidirectional equalization process has been successful.

10. The method according to claim 1 or 9, characterized in that, The step of feeding back the result of the bidirectional equalization process to the link training state machine, so that the link training state machine jumps to a target state that matches the result of the bidirectional equalization process, includes: In response to the result of the bidirectional equalization processing being a first result state, the link training state machine is controlled to jump to the receive lock state. The receive lock state is the lock state entered after the link training in the PCIe protocol is completed and equalization is completed, and it is used to execute the link training to enter the normal transmission state. In response to the result of the bidirectional equalization processing being a second result state, the link training state machine is controlled to jump to a deceleration state. The deceleration state is a state in the PCIe protocol where the transmission rate is reduced and retried after the link training fails, and is used to reduce the transmission rate and restart the link training.

11. A leveling control device for PCIe communication, characterized in that, Applied to a first communication terminal, the first communication terminal is a device supporting the PCIe protocol, the first communication terminal includes a link training state machine, and the device includes: The mode state value acquisition module is used to acquire mode state values ​​from the link training state machine to determine the equalization control mode. A bidirectional equalization module is used to transmit communication signals to a second communication terminal in response to the mode state value indicating that the equalization control mode is the first equalization mode, so as to perform bidirectional equalization processing. The bidirectional equalization processing is used to establish bidirectional link parameter negotiation and equalization configuration between the first communication terminal and the second communication terminal, so as to obtain suitable equalization configuration parameters in the signal transmission direction and the signal reception direction respectively. The equalization result transmission module is used to feed back the result of the bidirectional equalization process to the link training state machine, so that the link training state machine jumps to the target state that matches the result of the bidirectional equalization process.

12. An electronic device, characterized in that, include: Memory, used to store computer program products; A processor for executing a computer program product stored in the memory, wherein when the computer program product is executed, it implements the method described in any one of claims 1-10.

13. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1-10.

14. A computer program product comprising computer program instructions, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1-10.

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