Serial transceiver multi-lane transmit phase alignment method and apparatus

Abstract

The embodiment of the specification provides a serial transceiver multi-channel sending phase alignment method and device, comprising: performing first synchronous reset on reference sending channels and adjustment sending channels in the same four-channel group based on the same clock source; after completing the first synchronous reset, performing coarse adjustment on the adjustment sending channels, performing first phase adjustment through a phase interpolator, so that the read-write pointers of the sending buffers of the adjustment sending channels cross the half-full boundary and trigger overflow or underflow events; in response to the events, performing second synchronous reset on the two sending channels, clearing the overflow flags and rebuilding the initial phase window of the two sending buffers; after completing the second synchronous reset, performing fine adjustment on the adjustment sending channels, performing second phase adjustment through the phase interpolator until the sending output phase difference of the two channels is less than a predetermined threshold. The random difference of the output phase after the reset of the multi-channel sending channels is effectively eliminated, and the phase consistency and power-on repeatability of the multi-channel high-speed serial output are improved.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of communication technology, and in particular to a method and apparatus for phase alignment of multi-channel transmission of a serial transceiver. Background Technology

[0002] High-speed serial transceivers such as GT, GTH, and GTY in high-speed FPGAs or SoCs are typically used in scenarios involving multi-lane data output, optical module interfaces, high-speed acquisition and backhaul, JESD, Aurora, PCIe custom links, and multi-channel synchronous transmission. In these scenarios, although multiple transmit channels may share the same reference clock or the same QPLL / CPLL, each channel still contains circuits such as PCS, PMA, parallel-to-serial conversion, clock division, reset release, TX buffer, phase alignment, and programmable phase interpolators. Discrepancies exist between different channels in the FIFO read / write pointer position after power-on reset, local clock tree propagation delay, PMA output clock phase, and board-level routing errors, causing the serial data edges of each channel to not arrive at the receiver at the same time. For systems requiring deterministic delay and lane-to-lane deskew, this skew reduces sampling margin and, in severe cases, can cause training sequence misalignment, parallel data reassembly failure, or inconsistent cross-channel data frame boundaries.

[0003] There are three common approaches to handling phase differences in existing projects. The first approach relies entirely on the GT IP's built-in reset timing and the default operating state of the TX Buffer, allowing the TX Buffer to absorb the phase difference between the TXUSRCLK field and the PMA parallel clock XCLK field. This method is simple to implement, but after reset, the TX Buffer can only reach an approximately half-full or half-empty state, and the relative positions of the read and write pointers of different channels are not completely consistent, making it difficult to guarantee a deterministic phase relationship across multiple channels. The second approach uses the TX Buffer Bypass mode and executes the officially recommended TX phase alignment procedure. This method helps reduce latency but requires additional phase alignment logic, clock constraints, and a more stringent clock topology. In some devices or existing projects, the Bypass mode also occupies phase alignment circuitry, making it difficult for users to simultaneously use TXPI for manual phase control. The third approach compensates through external delay lines, board-level equalization, receiver-side elastic buffering, or protocol layer training codes. These methods typically rely on external devices or protocol support and cannot directly resolve the output phase difference caused by the randomness of the transmitter GT's internal reset.

[0004] Preliminary searches revealed one of the closest disclosed solutions to be Xilinx, Inc.'s US Patent 9331724B2, entitled "Lane-to-lane de-skew for transmitters," corresponding to US Publication US20160080008A1 and Chinese Publication CN107077445A. This patent discloses a method of using the transmitter FIFO's flag signal feedback to adjust the phase interpolator, thereby achieving similar delays for the data buffers of multiple transmitters and reducing inter-channel skew. The core idea of ​​this solution is to locate state changes based on read / write address differences or FIFO flag signals and perform delay equalization on multiple transmitters separately. This disclosure demonstrates that FIFO status flags and PI adjustment can be used for lane-to-lane de-skew, but it does not provide a specific engineering process for 7-series GT channels in the same quad, shared QPLL, and TX buffer enabled mode, including "maximum step inducing TX buffer overflow / underflow, synchronous reset to establish a common initial boundary, and then fine-tuning a single channel through DRP minimum step."

[0005] The AMD / Xilinx GT transceiver user manuals disclose the basic interface meanings of TX Buffer, TXBUFSTATUS, and TXPhase Interpolator PPM Controller. These manuals state that TXBUFSTATUS[1] indicates that the TX FIFO has overflowed or underflowed and remains so until the TX Buffer is reset, while TXBUFSTATUS[0] indicates that the TX FIFO is at least half full. They also state that the TX Buffer needs to be reset when it overflows or underflows, and that TXPIPPMSTEPSIZE controls the direction and step size of the PI Code increment / decrement. The above information pertains to device interface and operational constraints and does not disclose how to combine these signals to construct a reproducible dual-channel transmit phase alignment method.

[0006] Therefore, the existing technology still has the following problems: under the condition of keeping the TX Buffer enabled to obtain a stable working margin, the read / write phase and output edge phase of the TX Buffer after the reset of multiple 7-series GT channels may still be inconsistent; if the minimum step fine-tuning is directly entered, the initial deviation range is large, the search time is long and the direction judgment is unstable; if Buffer Bypass is used instead, it will introduce higher design complexity and may not be suitable for systems that have adopted TX Buffer Enable mode.

[0007] Therefore, a better solution is urgently needed. Summary of the Invention

[0008] In view of this, embodiments of this specification provide a method for phase alignment of multi-channel transmissions in a serial transceiver. One or more embodiments of this specification also relate to a phase alignment apparatus for multi-channel transmissions in a serial transceiver, a computing device, a computer-readable storage medium, and a computer program, to address technical deficiencies in the prior art.

[0009] According to a first aspect of the embodiments of this specification, a multi-channel transmission phase alignment method for a serial transceiver is provided, comprising: The reference transmission channel and the adjustment transmission channel located in the same four-channel group are first synchronously reset based on the same clock source; After the first synchronous reset is completed, coarse adjustment is performed on the transmission channel. The coarse adjustment is to perform the first phase adjustment so that the read / write pointer of the transmission buffer of the transmission channel crosses the half-full boundary and triggers an overflow or underflow event. In response to an overflow or underflow event, a second synchronous reset is performed on the reference transmit channel and the adjustment transmit channel to clear the overflow or underflow flags of the transmit buffer of the adjustment transmit channel and rebuild the initial phase windows of the transmit buffers of both transmit channels. After the second synchronous reset is completed, fine-tuning is performed on the adjusted transmission channel. Fine-tuning involves performing a second phase adjustment until the phase difference between the transmission outputs of the reference transmission channel and the adjusted transmission channel is less than a predetermined threshold.

[0010] In one possible implementation, the first phase adjustment includes: first performing a predetermined number of maximum step phase adjustments along a first direction, and then performing another number of maximum step phase adjustments along a second direction opposite to the first direction, wherein the number of steps in the second direction is greater than the number of steps in the first direction; after each step, waiting for a predetermined number of user clock cycles, and then sampling and adjusting the buffer overflow status signal of the transmit channel; if the signal is not set, continuing to perform subsequent steps; if the signal is set, confirming that an overflow or underflow event has occurred.

[0011] In one possible implementation, the predetermined number of times is 150, and the other number is 300; the predetermined number of user clock cycles is 1,000 transmit user clock cycles; the reset hold time of the second synchronous reset is 200 transmit user clock cycles, and after the reset is released, it waits for the reset completion signals of both transmit channels to be high.

[0012] In one possible implementation, both the first and second synchronous resets are achieved by simultaneously asserting the transmit reset signals of the two transmit channels; the second phase adjustment is achieved by setting the phase interpolator manual overwrite enable signal to an active state and writing the phase interpolator code value through the configuration register read / write port, with each fine adjustment changing only one minimum step unit; the phase difference between the transmit outputs of the reference transmit channel and the adjustment transmit channel is determined by an external oscilloscope, on-chip logic analyzer, training sequence boundary detection module, or receiver data word arrival time comparison module.

[0013] In one possible implementation, the method is implemented by an internal state machine of a programmable logic device. The states of the state machine include an idle state, a waiting-for-reset-complete state, a forward coarse-tuning state, a reverse coarse-tuning state, a detection buffer state, a synchronous reset state, a waiting-for-reset-again-complete state, a manual fine-tuning state, and an alignment-complete state. The transition conditions between each state are triggered by a synchronous sampling signal.

[0014] In one possible implementation, for more than two transmission channels, one channel is selected as the reference transmission channel, and the first phase adjustment, second synchronization reset, and second phase adjustment process are executed on the remaining channels respectively; or multiple adjustment transmission channels are controlled in parallel during the first phase adjustment stage, and the final phase interpolator code value is locked channel by channel during the second phase adjustment stage.

[0015] In one possible implementation, the reference transmission channel and the adjustment transmission channel are high-speed serial transceiver channels in a programmable logic device. The two channels share the same phase-locked loop as a clock source and are both configured with a transmit buffer in enabled mode. The method is applied to a quadrature phase shift keying modulation and demodulation system. The two high-speed serial transceiver channels are used to output in-phase branch data and quadrature branch data, respectively. After the second phase adjustment, the phase difference between the two outputs is less than 30 picoseconds.

[0016] According to a second aspect of the embodiments of this specification, a serial transceiver multi-channel transmission phase alignment device is provided, comprising: The first reset module is configured to perform a first synchronous reset on the reference transmission channel and the adjustment transmission channel located in the same four-channel group based on the same clock source. The channel coarse adjustment module is configured to perform coarse adjustment on the transmission channel after the first synchronous reset is completed. The coarse adjustment is to perform the first phase adjustment so that the read / write pointer of the transmission buffer of the transmission channel crosses the half-full boundary and triggers an overflow or underflow event. The second reset module is configured to perform a second synchronous reset on the reference transmission channel and the adjustment transmission channel in response to an overflow or underflow event, so as to clear the overflow or underflow flag of the transmission buffer of the adjustment transmission channel and rebuild the initial phase window of the transmission buffer of the two transmission channels. The channel fine-tuning module is configured to perform fine-tuning on the adjusted transmission channel after completing the second synchronous reset. Fine-tuning involves performing a second phase adjustment until the phase difference between the transmission outputs of the reference transmission channel and the adjusted transmission channel is less than a predetermined threshold.

[0017] According to a third aspect of the embodiments of this specification, a computing device is provided, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the steps of the above-described serial transceiver multi-channel transmission phase alignment method.

[0018] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided that stores computer-executable instructions, which, when executed by a processor, implement the steps of the above-described serial transceiver multi-channel transmission phase alignment method.

[0019] According to a fifth aspect of the embodiments of this specification, a computer program is provided, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the above-described serial transceiver multi-channel transmission phase alignment method.

[0020] This specification provides a method and apparatus for multi-channel transmit phase alignment of a serial transceiver, comprising: performing a first synchronous reset on a reference transmit channel and an adjustment transmit channel within the same four-channel group based on the same clock source; after completing the first synchronous reset, performing coarse adjustment on the adjustment transmit channel by using a phase interpolator to perform a first phase adjustment, causing the read / write pointer of the transmit buffer of the adjustment transmit channel to cross the half-full boundary and trigger an overflow or underflow event; in response to the event, performing a second synchronous reset on the two transmit channels, clearing the overflow flag and reconstructing the initial phase window of the two transmit buffers; after completing the second synchronous reset, performing fine adjustment on the adjustment transmit channel by using a phase interpolator to perform a second phase adjustment until the phase difference of the transmit output of the two channels is less than a predetermined threshold. By combining coarse and fine-stage adjustment, both convergence speed and alignment accuracy are considered, effectively eliminating random differences in the output phase after the multi-channel transmit channels are reset, and improving the phase consistency and power-on repeatability of the multi-channel high-speed serial output. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating a multi-channel transmission phase alignment method for a serial transceiver provided in one embodiment of this specification; Figure 2 This is a schematic diagram illustrating the principle of a multi-channel transmission phase alignment method for a serial transceiver provided in one embodiment of this specification; Figure 3This is a timing diagram illustrating a multi-channel transmission phase alignment method for a serial transceiver provided in one embodiment of this specification; Figure 4 This is an oscilloscope schematic diagram of a multi-channel transmission phase alignment method for a serial transceiver provided in one embodiment of this specification; Figure 5 This is a schematic diagram of the structure of a serial transceiver multi-channel transmission phase alignment device according to one embodiment of this specification; Figure 6 This is a structural block diagram of a computing device provided in one embodiment of this specification. Detailed Implementation

[0022] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0023] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0024] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0025] This specification provides a method for phase alignment of multiple channels of a serial transceiver, and also relates to a device for phase alignment of multiple channels of a serial transceiver, a computing device, and a computer-readable storage medium, which are described in detail in the following embodiments.

[0026] See Figure 1 , Figure 1 A flowchart is shown of a serial transceiver multi-channel transmission phase alignment method according to an embodiment of this specification, which specifically includes the following steps.

[0027] Step 101: Perform a first synchronization reset on the reference transmission channel and the adjustment transmission channel located in the same four-channel group based on the same clock source; Step 102: After completing the first synchronous reset, perform coarse adjustment on the transmission channel. The coarse adjustment is to perform the first phase adjustment so that the read / write pointer of the transmission buffer of the transmission channel crosses the half-full boundary and triggers an overflow or underflow event. Step 103: In response to an overflow or underflow event, perform a second synchronous reset on the reference transmit channel and the adjustment transmit channel to clear the overflow or underflow flag of the transmit buffer of the adjustment transmit channel and rebuild the initial phase window of the transmit buffer of the two transmit channels. Step 104: After completing the second synchronization reset, fine-tuning is performed on the adjusted transmission channel. Fine-tuning involves performing a second phase adjustment until the phase difference between the transmission outputs of the reference transmission channel and the adjusted transmission channel is less than a predetermined threshold.

[0028] In this context, a serial transceiver refers to the high-speed serial transceiver core resource within a programmable logic device (PLD) used for high-speed serial data transmission and reception. It includes sub-circuit modules such as a physical coding sublayer, a physical media access layer, a parallel-to-serial conversion circuit, a transmit buffer, a clock divider circuit, and a phase interpolator. Multi-channel refers to the existence of at least two independently operating transmit channels within the same four-channel group. These channels share some clock resources and a reference clock input within the same four-channel group, but each has its own independent transmit data path, transmit buffer, and phase adjustment circuit. A four-channel group refers to the basic unit of a high-speed serial transceiver within a PLD, defined by physical location. A four-channel group typically contains four transceiver channels and shares a phase-locked loop (PLL) resource. Channels within the same four-channel group have similar layouts, traces, and clock distribution delays. A reference transmit channel is the channel selected as the phase reference during multi-channel phase alignment. This channel maintains its transmit output phase unchanged throughout the alignment process, and its phase state serves as a reference for adjusting other channels. Adjusting the transmit channel refers to the channel whose transmit output phase is actively adjusted during multi-channel phase alignment. This channel gradually changes the output edge timing of the serial data through a phase interpolator to align it with the output edge of the reference transmit channel. First synchronous reset refers to a reset operation performed simultaneously on both transmit channels at the beginning of the alignment process. This reset operation acts on the transmit buffers and associated state machines in the transmit channels, causing both channels to start operating from a defined initial state. Coarse adjustment refers to the process of rapidly changing the output phase of the transmit channel with a large adjustment step size. The purpose of this process is to significantly change the read / write pointer relationship of the transmit buffer and cross the buffer's operating boundary. First phase adjustment refers to applying directional step drive through the phase interpolator control port, causing the phase interpolator code value to change significantly in a predetermined direction, thereby causing a corresponding shift in the transmit buffer's read-side clock phase. The transmit buffer refers to the first-in-first-out (FIFO) memory buffer inside the high-speed serial transceiver used to isolate the user clock domain from the physical media access layer clock domain. This buffer has a detectable half-full status flag and overflow or underflow latch flags. The read and write pointers refer to the counters in the transmit buffer that indicate the write and read addresses, respectively. The relative distance between the read and write pointers determines the fill level of the buffer. When the relative distance crosses the buffer capacity boundary, an overflow or underflow event is triggered. The half-full boundary refers to the state point where the transmit buffer is filled to or exceeds half its capacity. At this boundary, the half-full status flag of the buffer changes. An overflow or underflow event refers to a state anomaly triggered when the relative position of the write and read pointers of the transmit buffer exceeds the normal range. Specifically, it is an overflow event where the write pointer catches up with the read pointer, causing data to be overwritten, or an underflow event where the read pointer catches up with the write pointer, causing data to be read repeatedly. After this event occurs, the buffer's error status flag is latched and maintained.The second synchronous reset refers to the simultaneous reset operation performed on both transmit channels again after an overflow or underflow event is detected. The purpose of this operation is to clear the latched error status flags and allow the transmit buffers of both transmit channels to restart from the same initial state. The initial phase window refers to the state range in which the read and write pointers of the transmit buffers are located relative to each other after the reset is released. This range is determined by the reset operation resetting the read and write pointers to a predetermined starting position. Fine-tuning refers to the process of precisely adjusting the output phase of the transmit channels in small adjustment steps. This process is performed after the coarse adjustment and the second synchronous reset have brought the two channels into similar phase windows, to achieve final fine alignment. The second phase adjustment refers to the gradual application of phase adjustment in minimum step units by directly configuring the phase interpolator code value, changing the phase by one unit step each time. The transmit output phase difference refers to the time interval between the data edges generated at the serial data output interface of the reference transmit channel and the adjusted transmit channel. This interval is determined by the difference in clock propagation delay between the two channels and the difference in phase interpolator configuration. The predetermined threshold refers to a pre-set phase difference tolerance value. When the phase difference between the transmission outputs of the two channels is less than this value, the alignment accuracy requirement is considered to be met. This value is determined based on the system's tolerance for channel skew.

[0029] The present invention will be further described below through a detailed embodiment: In this embodiment, a serial transceiver multi-channel transmit phase alignment method is applied to two adjacent high-speed serial transceiver transmit channels within a programmable logic device. These two channels are located in the same four-channel group and share the same high-speed transmit clock output by the phase-locked loop.

[0030] First, a synchronous reset is performed. After confirming that the reference clock has been stably locked, the system's control state machine simultaneously asserts the transmit reset signals for both transmit channels, which lasts for a predetermined number of user clock cycles. During the reset assertion, the transmit buffers of each of the two transmit channels are reset, the read / write pointers within the buffers are reset to their predetermined initial positions, and all status flags are cleared. After the reset is released, the state machine waits for the reset completion signals of both transmit channels to go high, indicating that the initialization sequence of the physical coding sublayer and physical media access layer within each channel has been completed. Through the first synchronous reset, the two transmit channels are placed at a starting point that is as consistent as possible, providing a comparable benchmark for subsequent adjustments.

[0031] Coarse adjustment is then performed. The state machine enters the coarse adjustment phase, applying only the first phase adjustment to the adjusted transmission channel, while the reference transmission channel maintains its current phase configuration. During coarse adjustment, the state machine issues step commands to the phase interpolator of the adjusted transmission channel via the phase interpolator control port. Each step command changes the phase interpolator code value by a maximum step in a predetermined direction, which is the maximum single adjustment allowed by the phase interpolator control port. Coarse adjustment is performed by executing several maximum steps in one direction, followed by more maximum steps in the opposite direction. As the phase interpolator code value changes significantly, the read-side clock phase of the transmission buffer inside the adjusted transmission channel is continuously shifted, causing the relative distance between the buffer's read and write pointers to change continuously. When the read-side clock phase shifts to a certain extent, the read-write pointer relationship crosses the half-full boundary and continues to move towards the buffer's capacity limit. Eventually, the relative position of the write and read pointers exceeds the normal range, triggering a buffer overflow or underflow event. After each step, the state machine waits for a predetermined number of user clock cycles to ensure that the buffer status bits have propagated stably. It then samples and adjusts the buffer overflow status signal of the transmit channel. When this signal is set, the state machine confirms that an overflow or underflow event has occurred, and the coarse adjustment phase is complete.

[0032] In response to an overflow or underflow event, a second synchronous reset is executed. Upon detecting that the buffer overflow status signal is set, the state machine immediately asserts the transmit reset signals of both transmit channels simultaneously. This assertion lasts for a predetermined number of user clock cycles, ensuring that the overflow or underflow flags of the transmit buffers of both channels are completely cleared, and that the internal state machines of both channels are reinitialized. After the reset is released, the state machine waits again for the reset completion signals of both transmit channels to go high. Through the second synchronous reset, the transmit buffers of the two transmit channels are rebuilt to a common initial phase window, eliminating the abnormal states caused by intentionally induced overflows or underflows during the coarse-tuning phase, and significantly reducing the phase difference between the two channels caused by the randomness of their respective power-on resets.

[0033] Finally, fine-tuning is performed. The state machine enters the fine-tuning phase, continuing to adjust only the transmission channel, while the phase configuration of the reference transmission channel remains locked. During fine-tuning, the state machine directly writes the target code value to the phase interpolator of the transmission channel through the configuration register read / write port, changing only the code value of a minimum step unit each time. The direction of fine-tuning is determined based on the detection result of the phase difference between the outputs of the two channels: if the output phase of the transmission channel lags behind the reference channel, it steps in the direction that advances the output phase; if the output phase of the transmission channel leads the reference channel, it steps in the direction that lags the output phase. Phase difference detection is performed by the data word arrival time comparison module at the receiver. This module determines the direction and magnitude of the phase difference by comparing the difference in the time when the same training sequence transmitted by the two channels is captured at the receiver. After each step, the state machine waits for a predetermined number of user clock cycles to allow the phase change to stabilize, and then detects the phase difference again. This process is repeated iteratively, with each step causing the phase difference between the transmission outputs of the two channels to decrease monotonically until the difference is less than a predetermined threshold. At this point, the state machine locks the phase interpolator code value of the current transmission channel and reports to the system that the alignment is complete.

[0034] The beneficial effects of this embodiment include at least the following: by establishing initial consistency between the two channels starting with a first synchronous reset, and then actively inducing detectable buffer boundary events through the maximum step phase adjustment in coarse tuning, the originally unobservable random phase difference is transformed into a clear overflow state flag, providing a clear termination criterion for phase tuning; the second synchronous reset executed in response to this boundary event not only meets the requirement that the device must reset after an abnormal buffer state, but also pulls the two channels into a common initial phase reconstruction window, effectively eliminating the abnormal state introduced during coarse tuning; finally, fine convergence is achieved through the minimum step phase adjustment in fine tuning, so that the final alignment accuracy is limited only to the minimum resolution of the phase interpolator. This method, without changing the transmit buffer enable configuration, balances convergence speed and alignment accuracy through two-stage coarse and fine tuning, improving the determinism and reproducibility of multi-channel transmit phase alignment.

[0035] In one possible implementation, the first phase adjustment includes: first performing a predetermined number of maximum step phase adjustments along a first direction, and then performing another number of maximum step phase adjustments along a second direction opposite to the first direction, wherein the number of steps in the second direction is greater than the number of steps in the first direction; after each step, waiting for a predetermined number of user clock cycles, and then sampling and adjusting the buffer overflow status signal of the transmit channel; if the signal is not set, continuing to perform subsequent steps; if the signal is set, confirming that an overflow or underflow event has occurred.

[0036] The first direction refers to an initial direction of change in the phase interpolator code value. This direction corresponds to moving the output phase of the adjusted transmission channel along a specific direction, specifically the direction in which the phase interpolator code value increases or decreases. The predetermined number of steps refers to the preset number of steps for performing the maximum step phase adjustment along the first direction. This number is determined based on the maximum single-step adjustment amplitude of the phase interpolator and the depth of the transmission buffer to ensure that the steps along this direction generate sufficient displacement in the read / write pointer relationship. The maximum step phase adjustment refers to the maximum step size allowed by the phase interpolator control port for each step instruction. This maximum step size is the maximum valid value that the step size field in the control port can take, and each step changes the phase interpolator code value by this maximum amount. The second direction refers to the direction of change in the phase interpolator code value opposite to the first direction. When the first direction is increasing, the second direction is decreasing, and vice versa. The other number refers to the preset number of steps for performing the maximum step phase adjustment along the second direction. This number is greater than the predetermined number of steps along the first direction, so that the read / write pointer relationship can move backward from its position after stepping in the first direction, crossing the half-full boundary and eventually reaching the buffer capacity limit. The buffer overflow status signal refers to a status bit provided by the transmit buffer to indicate whether an overflow or underflow event has occurred. This signal is set and latched after an overflow or underflow event occurs, and is not cleared until the transmit buffer is reset.

[0037] The aforementioned method will be further illustrated by a detailed embodiment below: This embodiment follows the state after the completion of the first synchronous reset, and further describes the specific implementation of the first phase adjustment in the coarse adjustment stage.

[0038] After completing the first synchronous reset and confirming that the reset completion signals of both transmission channels are high in the foregoing embodiment, the state machine enters the coarse adjustment stage and begins to perform the first phase adjustment on the transmission channels. In this embodiment, the first phase adjustment adopts a sequence of first performing a predetermined number of maximum step phase adjustments along the first direction, and then performing another number of maximum step phase adjustments along the second direction opposite to the first direction.

[0039] Specifically, the state machine first sets the direction control bit of the phase interpolator control port to the value corresponding to the first direction, and simultaneously sets the step size field to the maximum valid value. The state machine then generates a predetermined number of step pulses, each pulse causing the phase interpolator code value of the adjusted transmission channel to change by a maximum step amount along the first direction. After each step pulse is issued, the state machine waits for a predetermined number of user clock cycles. This waiting time is used to compensate for all propagation delays required from the issuance of the step command to the actual phase switching of the phase interpolator, to the corresponding changes in the transmit buffer read / write pointer relationship, and finally to the completion of the buffer status signal flip. After the wait period, the state machine samples the buffer overflow status signal of the adjusted transmission channel. If this signal is not set, it indicates that the current step in the first direction has not yet reached the buffer's capacity limit, and the state machine continues to execute the next step. If the buffer overflow status signal is set during the step in the first direction, the state machine directly confirms that an overflow or underflow event has occurred, the coarse adjustment is completed, and the subsequent step in the second direction is not executed.

[0040] If the buffer overflow status signal is not set after a predetermined number of steps in the first direction, the state machine switches the direction control bit of the phase interpolator control port to the second direction, opposite to the first direction, while keeping the step size field at its maximum effective value. The state machine then performs another number of maximum step phase adjustments in the second direction. Since the number of steps in the second direction is greater than the number in the first direction, and the predetermined number of steps in the first direction has already moved the read / write pointer relationship a certain distance from its initial position along the first direction, performing more steps in the reverse direction is sufficient to make the read / write pointer relationship cross the initial position and continue moving towards the buffer capacity limit in the second direction. The waiting and sampling process after each step is the same as in the first direction: after each step, wait for a predetermined number of user clock cycles, then sample the buffer overflow status signal; if it is not set, continue stepping; if it is set, confirm that an overflow or underflow event has occurred.

[0041] By executing a sequence of first performing a small number of maximum steps in one direction and then performing a larger number of maximum steps in the opposite direction, regardless of the initial relative position of the read and write pointers of the transmit buffer after the first synchronization reset, this sequence ensures that the read and write pointer relationship will inevitably cross the half-full boundary and reach the buffer's capacity limit in a single coarse adjustment process, thereby reliably triggering an overflow or underflow event.

[0042] The beneficial effects of this embodiment include at least the following: by using two maximum step sequences in opposite directions, the coarse adjustment process does not depend on the random direction of the initial half-full state of the transmit buffer after the first synchronous reset, thus avoiding overflow or underflow trigger failures caused by uncertain initial phase positions; the setting that the number of times in the second direction is greater than the number of times in the first direction ensures that the read / write pointer relationship will inevitably cross the buffer capacity limit during the reverse movement, improving the determinism and repeatability of triggering overflow or underflow events after each power-on or reset; waiting for a predetermined number of clock cycles after each step to resample the status signal ensures the reliability of status sampling and avoids misjudgments caused by signal propagation delays.

[0043] In one possible implementation, the predetermined number of times is 150, and the other number is 300; the predetermined number of user clock cycles is 1,000 transmit user clock cycles; the reset hold time of the second synchronous reset is 200 transmit user clock cycles, and after the reset is released, it waits for the reset completion signals of both transmit channels to be high.

[0044] The predetermined number of times (150 times) refers to the specific number of steps for performing the maximum step phase adjustment along the first direction, which is 150 steps. The other number (300 times) refers to the specific number of steps for performing the maximum step phase adjustment along the second direction, which is 300 steps. The transmit user clock cycle refers to the clock cycle used by the user-side data interface of the transmit channel. This clock is provided by the user logic to the high-speed serial transceiver to drive the parallel transmission of transmit data and the read / write operations of the transmit buffer. The reset hold time refers to the duration of the second synchronous reset interrupt transmission reset signal. This duration must be sufficient for the overflow flag of the transmit buffer to be cleared, the buffer read / write pointer to be reset to its initial position, and the internal state machine to complete reinitialization. The reset completion signal refers to the indication signal provided by the high-speed serial transceiver to indicate that the internal reset sequence of the channel has been completed. This signal goes high after all channel initialization is completed. Both channels having high reset completion signals is a necessary condition for entering the subsequent fine-tuning stage.

[0045] The aforementioned method will be further illustrated by a detailed embodiment below: Based on the aforementioned coarse adjustment stage, this embodiment further provides the specific values ​​of the parameters for each stage and their functions.

[0046] In the coarse adjustment phase of the aforementioned embodiment, the state machine first performs 150 maximum step phase adjustments along the first direction, waiting for 1,000 transmit user clock cycles and sampling the buffer overflow status signal after each step. If the overflow status signal is detected within 150 steps, the coarse adjustment is complete. If the overflow status signal is not detected after 150 steps, the state machine switches directions and performs 300 maximum step phase adjustments along the second direction, again waiting for 1,000 transmit user clock cycles and sampling the buffer overflow status signal after each step. The selection of this combination of step numbers is based on the following: 150 forward maximum steps are sufficient to cause a large phase shift in the phase interpolator, covering most of the possible distribution range of the relative positions of the read and write pointers after the first synchronous reset; if the forward direction fails to reach the boundary, the 300 reverse maximum steps not only compensate for the 150 forward displacements but also provide an additional 150 net reverse displacements, sufficient to make the read and write pointer relationship reach the buffer capacity limit from the other side of the initial position.

[0047] The waiting time after each step is one thousand transmit user clock cycles. This duration takes into account the code value switching response time of the phase interpolator, the setup time of the read-side clock phase change, and the propagation delay of the transmit buffer state bit update. At the operating frequency of the high-speed serial transceiver, one thousand transmit user clock cycles are sufficient to ensure that all the above transient processes complete and stabilize, so that the buffer overflow state signal sampled by the state machine is a reliable and valid final state, rather than a glitch or metastable value during the transition process.

[0048] When the state machine detects that the buffer overflow status signal is set, it immediately executes the second synchronous reset. The reset hold time for the second synchronous reset is two hundred transmit user clock cycles. During this duration, the state machine simultaneously asserts the transmit reset signals of both transmit channels. The two hundred transmit user clock cycles hold time is sufficient for the overflow or underflow flags of the transmit buffers of both transmit channels to be physically cleared, the buffer read / write pointers to be reset from the abnormal position to the preset initial position, and for other related state machines within the channel to complete the complete transition process from the abnormal state to the normal initial state. After the reset is released, the state machine enters a waiting phase, continuously monitoring the reset completion signals of both transmit channels. Only when both reset completion signals are high does the state machine confirm that the second synchronous reset has been fully effective and that both channels are ready to enter the subsequent fine-tuning phase.

[0049] The beneficial effects of this embodiment include at least the following: the specific combination of 150 forward maximum steps and 300 reverse maximum steps has been verified under a large number of actual working conditions to reliably cover various possible initial buffer filling states, thereby increasing the probability of coarse adjustment triggering overflow or underflow events; the waiting time of 1,000 transmitting user clock cycles ensures the reliability of state sampling and avoids false triggering or missed triggering due to insufficient timing margin; the reset hold time of 200 transmitting user clock cycles not only fully guarantees the clearing of abnormal states and the re-initialization of channels, but also avoids the impact of excessively long reset time on system startup efficiency; and the joint confirmation mechanism of the reset completion signals of the two channels ensures that both channels are in a ready state before the fine adjustment stage begins.

[0050] In one possible implementation, both the first and second synchronous resets are achieved by simultaneously asserting the transmit reset signals of the two transmit channels; the second phase adjustment is achieved by setting the phase interpolator manual overwrite enable signal to an active state and writing the phase interpolator code value through the configuration register read / write port, with each fine adjustment changing only one minimum step unit; the phase difference between the transmit outputs of the reference transmit channel and the adjustment transmit channel is determined by an external oscilloscope, on-chip logic analyzer, training sequence boundary detection module, or receiver data word arrival time comparison module.

[0051] The transmit reset signal is a control signal used to reset the transmit channel of the high-speed serial transceiver. When asserted, this signal triggers the reinitialization of the transmit buffer, physical coding sublayer state machine, and physical media access layer state machine within the transmit channel. Simultaneous assertion means that the transmit reset signals of both transmit channels are set to active on the same clock edge, remain active for the same duration, and then release simultaneously, ensuring a definite time synchronization between the reset start point and reset process of the two channels. The phase interpolator manual override enable signal is an enable bit used to switch the phase interpolator control mode. When this signal is active, it allows user logic to directly write the phase interpolator code value through the configuration register read / write port, instead of relying on the internal automatic phase tracking loop for adjustment. The configuration register read / write port refers to the serial or parallel interface in the programmable logic device used to access the internal configuration registers of the high-speed serial transceiver. Through this port, user logic can read and write various configurable parameters of the transceiver during normal operation. The minimum step unit refers to the phase adjustment amount corresponding to a change of one least significant bit in the phase interpolator code value. This adjustment amount is the minimum resolution achievable by the phase interpolator and determines the final alignment accuracy achievable during the fine-tuning stage. An external oscilloscope is an external measuring instrument connected to the transmit output pin of a high-speed serial transceiver. It measures the edge time difference by simultaneously observing the output waveforms of two channels. An on-chip logic analyzer is a debugging tool embedded within a programmable logic device, used to capture the timing relationships of internal digital signals. A training sequence boundary detection module is a circuit unit used to identify the start position of a specific training sequence at the receiver. It infers the phase difference at the transmitter by comparing the times when the boundaries of the training sequences of two channels are detected. A receiver data word arrival time comparison module is a circuit unit used at the receiver to determine the phase difference at the transmitter by comparing the times when parallel data words from two channels are correctly received and latched.

[0052] The aforementioned method will be further illustrated by a detailed embodiment below: Based on the foregoing embodiments, this embodiment further describes the specific implementation methods of the first synchronous reset and the second synchronous reset, as well as the specific implementation methods of the second phase adjustment and phase difference determination.

[0053] In terms of reset implementation, both the first and second synchronous resets employ the method of simultaneously asserting the reset signals of the two transmission channels. The system control state machine maintains a synchronous reset control logic unit, which is connected to the reset input of the reference transmission channel and the reset input of the adjustment transmission channel, respectively. When the state machine enters a state requiring a reset, the reset control logic unit simultaneously sets both reset signals to high level on the rising edge of the same transmission user clock cycle. After holding this high level for a predetermined number of clock cycles, the reset control logic unit simultaneously releases both reset signals to low level on the rising edge of the same transmission user clock cycle. This simultaneous assertion and release method ensures that the reset operations of the two channels are strictly aligned in timing, avoiding asynchronous initialization between channels due to differences in the arrival time of the reset signals.

[0054] In the implementation of the second phase adjustment, the fine-tuning stage employs a direct code value writing method for phase control. The state machine first enables the manual override signal of the phase interpolator in the transmission channel, allowing the interpolator to be decoupled from internal automatic control and accept external code value writing. Subsequently, the state machine performs a write operation on the phase interpolator's code value register via the configuration register read / write port. During each write operation, the state machine adds or subtracts a minimum step unit from the target code value, then sends the new code value along with the write enable pulse to the phase interpolator configuration register of the transmission channel via the configuration register read / write port. After the write pulse takes effect, the phase interpolator switches its output phase to the phase point corresponding to the new code value. Changing only a minimum step unit at a time ensures that the phase change is gradual and precise, preventing the phase adjustment process from skipping the target alignment point due to excessively large single changes.

[0055] Regarding phase difference determination, the phase difference between the transmitted outputs of the two channels is determined by the data word arrival time comparison module at the receiving end. This module is located in the receiving device corresponding to the transmitting end and is used to receive two serial data streams from the reference transmission channel and the adjustment transmission channel. In specific implementation, the two transmission channels start transmitting the same training sequence at the same time, which includes predetermined frame header flags. At the receiving end, the data word arrival time comparison module performs serial-to-parallel conversion and word boundary locking on the two data streams respectively, and detects the arrival time of the frame header flags in their respective training sequences. The module internally maintains two independent capture registers, which record the user clock cycle count values ​​of the successful detection of the frame header flags in the two data streams. Subtracting the two count values ​​yields the quantized value of the phase difference between the transmitted outputs of the reference transmission channel and the adjustment transmission channel, which is expressed as a fraction or integer multiple of the user clock cycle. When the difference is greater than a predetermined threshold, the comparison module feeds back a direction indication signal to the state machine, informing which direction the fine-tuning stage should continue in; when the difference is less than the predetermined threshold, the comparison module feeds back an alignment completion signal to the state machine, triggering the termination of the fine-tuning stage.

[0056] The beneficial effects of this embodiment include at least the following: by simultaneously asserting the transmission reset signals of two channels, the synchronization of the reset operation is ensured, eliminating the additional phase difference introduced by the inconsistent arrival times of the reset signals; by using the phase interpolator manual overlay enable signal and the configuration register read / write port in combination, direct and fine control of the phase interpolator code value is achieved, avoiding interference from the automatic tracking loop during the fine-tuning stage; by adjusting the smallest step unit successively, the fine-tuning process has a definite convergence direction and endpoint, avoiding the problem of excessive step size exceeding the optimal alignment point; by using the data word arrival time comparison module at the receiving end to determine the phase difference, and using the arrival time difference of the training sequence frame header flag bit as the feedback basis, the organic integration of phase detection and data reception is achieved, without the need to introduce additional external measurement equipment.

[0057] In one possible implementation, the method is implemented by an internal state machine of a programmable logic device. The states of the state machine include an idle state, a waiting-for-reset-complete state, a forward coarse-tuning state, a reverse coarse-tuning state, a detection buffer state, a synchronous reset state, a waiting-for-reset-again-complete state, a manual fine-tuning state, and an alignment-complete state. The transition conditions between each state are triggered by a synchronous sampling signal.

[0058] The internal state machine of a programmable logic device (PLD) refers to a finite state machine circuit implemented within the PLD using a hardware description language or schematic diagram. This state machine consists of a register set and combinational logic, and can switch between different states according to a predetermined state transition diagram under clock drive. The idle state is the initial state the state machine is in after power-on or system reset. In this state, the state machine waits for a start command and does not send control signals to any transmit channels. The waiting-for-reset-complete state is the waiting state the state machine is in after the reset signal of the first or second synchronous reset is released. In this state, the state machine continuously monitors the reset completion signals of the two transmit channels until both are high before transitioning to the next state. The forward coarse adjustment state is the state where the state machine performs maximum step phase adjustment along a first direction. In this state, the state machine controls the direction and step size fields of the phase interpolator control port and sends step pulses at a predetermined rhythm. The reverse coarse adjustment state is the state where the state machine performs maximum step phase adjustment along a second direction. This state is entered after the forward coarse adjustment state has been executed a predetermined number of times without triggering an overflow event. The "Detect Buffer State" state refers to the state where the state machine waits and samples the overflow status signal of the transmit channel buffer after each step. This state alternates with the forward coarse adjustment state and the reverse coarse adjustment state, forming a step-sampling cycle. The "Synchronous Reset State" state refers to the state where the state machine performs a second synchronous reset after detecting the buffer overflow status signal. In this state, the state machine simultaneously asserts the transmit reset signals of both transmit channels and holds them for a predetermined time. The "Waiting for Reset to Complete Again" state refers to the waiting state the state machine is in after the reset signal of the second synchronous reset is released. This state has the same function as the "Waiting for Reset to Complete" state but is located at a different stage in the process, used to ensure that the second synchronous reset is fully effective before entering the fine-tuning stage. The "Manual Fine-Tuning State" state refers to the state machine performing the second phase adjustment. In this state, the state machine sequentially writes the phase interpolator code value through the configuration register read / write port, changing it by a minimum step unit each time, and determines the direction of the next step based on the phase difference feedback. The "Alignment Complete" state refers to the terminal state the state machine is in after detecting that the phase difference between the transmit outputs of the two channels is less than a predetermined threshold. In this state, the state machine locks the current configuration and reports alignment complete to the system, no longer actively changing the phase configuration of any channel. Synchronous sampling signals refer to control signals that are synchronously captured by the rising edge of the state machine's drive clock. These include reset completion signals, buffer overflow status signals, and phase difference judgment feedback signals. All state transition conditions are sampled and evaluated on the same edge of the drive clock to avoid metastability and state transition uncertainties caused by asynchronous signals.

[0059] The aforementioned method will be further illustrated by a detailed embodiment below: Based on the foregoing embodiments, this embodiment further describes the specific way in which the method is implemented by the internal state machine of the programmable logic device, including the state definition of the state machine and the transition relationship between each state.

[0060] This state machine is instantiated in the user logic area of ​​the programmable logic device. The driving clock uses the same user clock as the transmitting channel to ensure that all operations of the state machine have a definite timing relationship with the data transmission of the transmitting channel. The state machine contains a current state register and a counter register group for temporarily storing count values. The transitions between states are all controlled by a synchronous sampling signal triggered by the rising edge of the driving clock.

[0061] Once the system powers on and the state machine receives the start-align command, it starts from the idle state. In the idle state, the state machine sets all control outputs to safe levels and does not operate any transmit channels. Upon receiving the start command, the state machine transitions to the synchronous reset state, executes the first synchronous reset operation, and simultaneously asserts the transmit reset signals of both transmit channels and holds them for a predetermined time before releasing them. The state machine then enters the waiting-for-reset-complete state, continuously sampling the reset completion signals of both transmit channels. Only when both reset completion signals are high does the state machine confirm that the first synchronous reset has fully taken effect and transition to the positive coarse-tuning state.

[0062] In the forward coarse adjustment state, the state machine configures the phase interpolator control port to apply the maximum step along the first direction, and immediately transitions to the detection buffer state after issuing a step pulse. In the detection buffer state, the state machine starts a counter to wait for a predetermined number of user clock cycles. After the wait is completed, it samples and adjusts the buffer overflow status signal of the transmit channel. If this signal is set, the state machine directly transitions to the synchronous reset state to perform a second synchronous reset. If this signal is not set and the cumulative number of forward coarse adjustments has not yet reached the predetermined number, the state machine returns to the forward coarse adjustment state to continue the next step. If this signal is not set and the cumulative number of forward coarse adjustments has reached the predetermined number, the state machine transitions to the reverse coarse adjustment state.

[0063] In the reverse coarse adjustment state, the state machine switches the phase interpolator control port to a second direction opposite to the first direction, maintains the maximum step size, and transitions to the detection buffer state after issuing one step pulse, executing the same waiting and sampling process as the forward coarse adjustment. If the buffer overflow status signal is detected and set, the state machine transitions to the synchronous reset state. If the signal is not set and the cumulative number of steps for reverse coarse adjustment has not yet reached another number, the state machine returns to the reverse coarse adjustment state to continue stepping. If no overflow event is detected after all predetermined number of reverse coarse adjustments, the state machine returns to the idle state and reports an exception; however, this situation rarely occurs in actual implementation due to the coverage of the 150 plus 300 step sequence.

[0064] When the state machine enters the synchronous reset state due to the detection of a buffer overflow status signal, it simultaneously asserts the transmit reset signals of both transmit channels and maintains them for two hundred transmit user clock cycles. It then releases the reset signal and transitions to the waiting-for-reset-complete state. In this state, the state machine continuously samples the reset completion signals of both transmit channels, only transitioning to the manual fine-tuning state when both are high.

[0065] In manual fine-tuning mode, the state machine enables the manual overwrite signal of the phase interpolator for the transmission channel and writes the phase interpolator code value sequentially through the configuration register read / write port, changing it by a minimum step unit each time. After each write, the state machine waits for a predetermined number of user clock cycles to allow the phase change to stabilize, and then determines the direction of the next step based on the phase difference direction fed back by the data word arrival time comparison module at the receiving end. If the feedback indicates that the adjustment channel phase is leading, the step is taken in the direction that lags the phase; if the feedback indicates that the adjustment channel phase is lagging, the step is taken in the direction that leads the phase. After each step, the state machine re-evaluates whether the phase difference is less than a predetermined threshold. When the phase difference is less than the predetermined threshold, the state machine transitions to the alignment complete state.

[0066] In the alignment complete state, the state machine latches the current phase interpolator code value, stops all step operations, sends an alignment complete interrupt signal to the system main control logic, and remains in this state until the system issues a new alignment start command or the system is reset.

[0067] The beneficial effects of this embodiment include at least the following: The complete alignment process control is achieved through a finite state machine, giving the method a deterministic execution timing and predictable behavior, facilitating its synthesis and verification in programmable logic devices; the division of each state corresponds one-to-one with the process steps, making the design and debugging of the state machine clear and straightforward; all state transition conditions are triggered by synchronous sampling signals, avoiding the metastability risks that asynchronous signals may introduce, and improving the reliability of the state machine under different process corners and operating conditions; the hardware-based control implemented by the state machine makes it possible to automatically execute the complete alignment process after power-on or reset, without the need for external processor intervention.

[0068] In one possible implementation, for more than two transmission channels, one channel is selected as the reference transmission channel, and the first phase adjustment, second synchronization reset, and second phase adjustment process are executed on the remaining channels respectively; or multiple adjustment transmission channels are controlled in parallel during the first phase adjustment stage, and the final phase interpolator code value is locked channel by channel during the second phase adjustment stage.

[0069] More than two transmit channels refer to three or more transmit channels that need to be aligned with each other within the same four-channel group or across multiple four-channel groups. Selecting a channel as the reference transmit channel means specifying one channel from all channels to be aligned, keeping its phase configuration unchanged, and adjusting the phase of all other channels with reference to this channel. Performing separate adjustments for the remaining channels means sequentially and independently performing a complete coarse and fine adjustment process for each adjusted channel. Once a channel is aligned, its phase configuration is not changed before processing the next channel. Parallel control of multiple adjusted transmit channels in the first phase adjustment stage means simultaneously applying the first phase adjustment to multiple adjusted channels during the coarse adjustment process, causing the transmit buffers of each adjusted channel to move simultaneously towards the boundary. Each channel independently detects whether it has triggered an overflow or underflow event. Channel-by-channel locking in the second phase adjustment stage means that in the fine adjustment stage, instead of parallel operation, fine adjustment is performed channel by channel until the channel meets the alignment conditions, then its phase code value is locked before processing the next channel, to avoid cross-interference between adjusted channels during the fine adjustment process.

[0070] The aforementioned method will be further illustrated by a detailed embodiment below: Based on the foregoing embodiments, this embodiment further describes two extended implementation methods for scenarios with more than two transmission channels.

[0071] When three or more transmission channels in the system require phase alignment, one channel is first selected as the reference transmission channel. The principle for selecting the reference is that the phase state of the channel is considered stable and does not need to be changed in subsequent processes. Typically, the channel with the central physical location or the channel with the most stable phase performance after the initial power-on can be selected. Once the reference is selected, this channel does not participate in any phase adjustment operations throughout the alignment process, and its phase interpolator code value remains unchanged.

[0072] In the first extended implementation, the system employs a serial processing strategy for each adjustment channel. The state machine first executes the aforementioned first phase adjustment, overflow or underflow event detection, second synchronization reset, and second phase adjustment procedures for the first adjustment channel until the transmit output phase difference between this channel and the reference channel is less than a predetermined threshold. Then, the phase interpolator code value of this channel is locked. After locking, the state machine maintains the reference channel as the selected original reference channel and uses the second adjustment channel as the new adjustment target, executing all the aforementioned procedures. This process continues until all adjustment channels have completed their respective alignment procedures. This serial approach has a clear structure, with each channel's procedure being independent and without cross-influence, making it suitable for scenarios with a small number of channels and where the overall alignment time is not critical.

[0073] In the second extended implementation, the system employs a parallel control strategy in the first phase adjustment stage and a channel-by-channel locking strategy in the second phase adjustment stage. Specifically, the state machine applies the first phase adjustment to multiple adjustment transmission channels simultaneously during the coarse adjustment stage. Internally, the state machine maintains an independent step counter for each adjustment channel. In each parallel step operation, all adjustment channels simultaneously receive step commands with the same direction and synchronous advance amount. Each adjustment channel independently monitors its own buffer overflow status signal. When an adjustment channel triggers an overflow or underflow event first, the system records the event and immediately performs a second synchronous reset on all adjustment channels, reconstructing the transmission buffers of all channels to a common initial phase window. In the subsequent fine adjustment stage, the state machine no longer operates in parallel but performs the second phase adjustment channel-by-channel, starting from the first adjustment channel. After each channel completes fine adjustment, its phase interpolator code value is locked, and then the next channel is processed, until all adjustment channels have completed fine adjustment. This parallel coarse adjustment plus serial fine adjustment approach can shorten the overall process time during the coarse adjustment stage by utilizing parallelism, while avoiding potential mutual interference when multiple adjustment channels are adjusted simultaneously during the fine adjustment stage through serial locking.

[0074] The beneficial effects of this embodiment include at least the following: the two extended implementation methods enable the method to be flexibly applied to systems with more than two transmission channels, covering a wider range of practical application scenarios; the serial processing method has a simple structure and clear process, and is suitable for designs with a small number of channels; the parallel coarse adjustment plus serial fine adjustment method takes into account both the parallel efficiency of the coarse adjustment stage and the stability requirements of the fine adjustment stage, and can effectively shorten the overall alignment time of the multi-channel system; both methods maintain the mechanism of independent fine adjustment of each channel, ensuring that each channel can eventually achieve the predetermined alignment accuracy with the reference channel.

[0075] In one possible implementation, the reference transmission channel and the adjustment transmission channel are high-speed serial transceiver channels in a programmable logic device. The two channels share the same phase-locked loop as a clock source and are both configured with a transmit buffer in enabled mode. The method is applied to a quadrature phase shift keying modulation and demodulation system. The two high-speed serial transceiver channels are used to output in-phase branch data and quadrature branch data, respectively. After the second phase adjustment, the phase difference between the two outputs is less than 30 picoseconds.

[0076] Programmable logic devices (PLDs) are programmable integrated circuits that include configurable logic resources, memory resources, and a high-speed serial transceiver hard core. Users can define their internal logic functions through configuration files. A high-speed serial transceiver channel refers to a dedicated hard core circuit integrated within the PLD, supporting serial data transmission and reception rates from gigabits per second to tens of gigabits per second. Sharing the same phase-locked loop (PLL) as a clock source means that the serial output clocks of both transmit channels originate from the output frequency division link of the same PLL. This PLL is locked to an externally input reference clock, providing both channels with transmit clocks of the same frequency and a deterministic phase relationship. Transmit buffer enabled mode means that the transmit buffer is set to an active state in the configuration parameters of the high-speed serial transceiver. Data from the user clock domain is first written to the transmit buffer, and then read from the buffer by the physical medium access layer (PML) clock domain and converted from parallel to serial. This mode provides phase difference absorption capability between the two clock domains. A quadrature phase-shift keying (QPSK) modulation and demodulation system refers to a system that uses QPSK modulation to modulate and demodulate data. Its transmitter needs to map the serial bitstream into two parallel data paths: an in-phase branch and a quadrature branch, which are then converted from digital to analog and up-converted. The in-phase and quadrature branch data refer to two mutually orthogonal baseband signal components in QPSK modulation. During modulation, these components are multiplied by the in-phase carrier and the quadrature carrier, respectively, and then superimposed to form the modulated signal. Thirty picoseconds refers to a time accuracy where the phase difference between the outputs of two aligned high-speed serial transceiver channels is less than thirty picoseconds.

[0077] The aforementioned method will be further illustrated by a detailed embodiment below: This embodiment, based on the foregoing embodiments, further describes the specific application of the method in a quadrature phase shift keying modulation and demodulation system.

[0078] In the transmitter implementation of a quadrature phase-shift keying (QPSK) modulation and demodulation system, a programmable logic device (PLD) is used as the core of the baseband signal processing. This PLD internally instantiates two high-speed serial transceiver channels. These two channels are located within the same four-channel group and share the same phase-locked loop (PLL) as the high-speed transmit clock source. An external voltage-controlled crystal oscillator (VCO) provides a reference clock input to the PLL. After the PLL is locked, it generates a high-speed clock signal for serial output. This clock signal is simultaneously distributed to the physical medium access layer (PML) clock domain of both high-speed serial transceiver channels. Both channels are configured with transmit buffers in enabled mode to reliably traverse high-speed parallel data from the baseband processing clock domain to the PML clock domain.

[0079] In the system's workflow, the baseband signal modulated by quadrature phase-shift keying (QPSK) is decomposed into in-phase and quadrature branch data. The in-phase branch data is sent to the user data interface of the reference transmission channel, while the quadrature branch data is sent to the user data interface of the adjustment transmission channel. Both data streams have the same parallel data bit width and data rate, and originate from the same baseband processing clock domain; therefore, they have a definite timing relationship when entering the user clock domain of their respective transmission channels. However, due to the phase discrepancies of the independent transmit buffers, clock divider links, and parallel-to-serial conversion circuits within the two high-speed serial transceiver channels after power-on or reset, the edge times of the two serial outputs at the transmit pins may be inconsistent. This inconsistency degrades the synchronous sampling performance of the in-phase and quadrature branches at the receiver.

[0080] To address the aforementioned issues, the system implements the aforementioned state machine within the programmable logic device and automatically executes the aforementioned alignment process each time the system powers on or a channel is reset. The state machine first performs a first synchronous reset on both channels. After the reset is complete, it enters a coarse adjustment phase, applying a first phase adjustment of 150 maximum steps forward and then 300 maximum steps backward to the adjustment transmission channel carrying orthogonal branch data, until an overflow or underflow event is triggered in the transmission buffer of that channel. In response to this event, the state machine performs a second synchronous reset on both channels, reconstructing the initial phase windows of the two transmission buffers. Subsequently, the state machine enters a fine adjustment phase, sequentially writing phase interpolator code values ​​through the configuration register read / write port, using the phase difference direction fed back by the data word arrival time comparison module at the receiving end as a reference, and stepping by a minimum step unit each time, until the phase difference between the two channel transmission outputs is less than a predetermined threshold.

[0081] In a laboratory testing environment, a high-speed oscilloscope was used to simultaneously probe the transmit output pins of two high-speed serial transceiver channels. Test results showed that, after employing the aforementioned alignment procedure, the serial data edge phase difference between the reference transmit channel carrying in-phase branch data and the adjusted transmit channel carrying quadrature branch data was stably controlled within thirty picoseconds. This accuracy is sufficient to ensure that when synchronously sampling the in-phase and quadrature branch data at the receiver, the edge offset of the two data streams does not introduce significant sampling errors.

[0082] The beneficial effects of this embodiment include at least the following: by applying the aforementioned method to the quadrature phase shift keying modulation and demodulation system, the phase inconsistency problem caused by the internal reset randomness of the two transmission links of the in-phase branch and the quadrature branch in the system is solved, thereby improving the output quality of the modulated signal; the two channels share the same phase-locked loop and are both configured with the transmission buffer in enabled mode, achieving precise phase synchronization between channels through the phase alignment process while maintaining system stability; the alignment accuracy of 30 picoseconds is much smaller than the unit symbol width of quadrature phase shift keying modulation at a typical code rate, providing sufficient sampling margin for the receiver and reducing the demodulation bit error rate caused by channel skew.

[0083] The following is in conjunction with the appendix Figure 2 The multi-channel transmission phase alignment method of the serial transceiver is further explained below. Figure 2 A system architecture diagram of a serial transceiver multichannel transmission phase alignment method provided in one embodiment of this specification is shown.

[0084] This method is applicable to at least two GT channels within the same quad, particularly suitable for GT transceivers such as GTX / GTH in Xilinx 7 series Kintex-7 (K7) and Virtex-7 (V7) devices; it is preferably suitable for scenarios where two channels share the same QPLL, both channel TX buffers are enabled, and the reset control of both channels is synchronized. The system defines one channel as the reference channel and the other as the adjustment channel; the phase state of the reference channel remains unchanged after power-on, while the adjustment channel controls TXPI through TXPIPPM and DRP to change its transmit output phase. The method generally includes steps such as power-on waiting, reset completion confirmation, coarse adjustment overflow induction, stabilization waiting, overflow detection, synchronous reset, re-reset completion confirmation, and minimum step fine-tuning.

[0085] The hardware structure of this scheme includes: a shared QPLL module, dual GT TX channels, a training sequence generation module, a synchronous reset control module, a TXBUFSTATUS sampling module, a TXPIPPM coarse adjustment control module, a DRP fine adjustment control module, and a phase comparison or alignment determination module. The two GT TX channels are located in the same quad, both using the same QPLL as the clock source, and configured with TXBUF_EN=TRUE or TX_BUFFER_USE=TRUE. The GTTXRESET or TXPCSRESET of the two channels are generated by the same state machine to ensure that the reset assertion and release have a definite synchronous relationship. TXBUFSTATUS[1:0] is sampled by the TXUSRCLK clock domain, where TXBUFSTATUS[1] serves as an overflow / underflow latch flag, and TXBUFSTATUS[0] serves as a reference for the half-full state of the TX Buffer.

[0086] In the first phase, after the system powers on, a predetermined delay is executed, preferably 1 second, to ensure the stability of the reference clock, QPLL lockout, power supply, and GT internal reset link. After the delay, the control state machine monitors the TXRESETDONE or GTRESETDONE signals of two channels. The state machine only enters the coarse-tuning phase when both channels indicate that the reset is complete; if either channel fails to complete the reset, the state machine remains in a waiting state to avoid writing PI configuration during the uncertain GT initialization process.

[0087] In the second stage, the state machine performs coarse adjustment of the adjustment channel using TXPIPPM. The coarse adjustment uses the maximum step size F, i.e., TXPIPPMSTEPSIZE[3:0] takes the maximum effective step value, and the direction is determined by the direction control bit of TXPIPPMSTEPSIZE. In a preferred embodiment, the state machine first performs 150 maximum steps in the first direction, and then performs 300 maximum steps in the opposite direction. This combination causes TXPI to produce a sufficiently large relative movement to the read-side phase of the adjustment channel, thereby pushing the read-write pointer relationship of TXBuffer across the half-full boundary and eventually triggering overflow or underflow. After each step, the state machine waits for 1000 TXUSRCLK cycles to allow the FIFO read-write pointer and status bit to complete stable propagation, and then samples TXBUFSTATUS[1]. If TXBUFSTATUS[1] is not set, the coarse adjustment cycle continues; if TXBUFSTATUS[1] is set, it is considered that the adjustment channel has reached a verifiable buffer boundary event.

[0088] This scheme does not regard TX Buffer overflow as a fault termination condition, but rather as a controllable trigger event for establishing a common phase reference. Since TXBUFSTATUS[1] remains high after overflow or underflow until TX Buffer is reset, the state machine can reliably capture the event. By first forcing the FIFO boundary to be touched with a larger step and then resetting the two channels uniformly, the output phase difference caused by each channel being randomly in different half-full intervals after power-on can be reduced. The maximum number of steps in the coarse adjustment stage can be set according to the device PI step size, line rate, THUSRCLK frequency and FIFO depth; 150 times and 300 times are preferred empirical values, and this scheme does not restrict the use of different count values ​​under other channel numbers, other devices or other line rates.

[0089] In the third stage, when TXBUFSTATUS[1] is set, the state machine immediately enters the synchronous reset process. The preferred method is to simultaneously assert GTTXRESET for both channels; alternatively, depending on the system design, TXPCSRESET can be asserted simultaneously, or an equivalent reset signal capable of resetting the TX buffer can be used. See [link to relevant documentation]. Figure 3 TXSTATUS[1] is TXBUFSTATUS[1]. The reset hold time is preferably 200 TXUSRCLK cycles to ensure that the TX Buffer overflow flag is cleared and the PCS / PMA related state machine is reinitialized. After the reset is released, the state machine waits again for both channels TXRESETDONE to be high. Through the combination of "coarse adjustment boundary event + dual-channel synchronous reset", the two channels are pulled back to a more consistent initial phase window, which narrows the search range for subsequent fine adjustment.

[0090] In the fourth stage, the system performs TXPI fine-tuning. Fine-tuning uses DRP to directly configure the PI code, making TXPIPPMOVRDEN active, and gradually writing the target PI code through TXPI_PPM_CFG or the device's corresponding TXPH_CFG / TXPI configuration register. Each fine-tuning step changes only the minimum step size, preferably incrementing or decrementing the PI code by one, and the new code value is activated by a write pulse. During fine-tuning, the reference channel does not change its phase, and the adjustment channel selects the increment or decrement direction based on the phase comparison result of the dual-channel outputs. Phase comparison can be performed by an external oscilloscope, on-chip logic analyzer, training sequence boundary detection module, receiver data word arrival time comparison module, or other equivalent phase determination modules. When the arrival time difference between the two output edges or training data words is detected to be less than a predetermined threshold, the state machine latches the current PI code, ending the alignment process.

[0091] In an implementable register configuration, the TXPI control ports include TXPIPPMEN, TXPIPPMSEL, TXPIPPMOVRDEN, and TXPIPPMSTEPSIZE. During coarse adjustment, TXPIPPMEN and TXPIPPMSEL are active, TXPIPPMOVRDEN is in normal step mode, and TXPIPPMSTEPSIZE is set to maximum step size and switched by direction. During fine adjustment, TXPIPPMOVRDEN switches to direct control mode, TXPIPPMSTEPSIZE can be set to zero, and the control logic is written to the PI Code via DRP. For devices that require phase alignment related attributes, ports or attributes such as PCS_RSVD_ATTR[1], TXDLY_LCFG[2], TXPHALIGN, TXPHALIGNEN, TXPHOVRDEN, TXPHDLYPD, and TXPH_CFG can be further configured. Their specific names vary depending on the user manual of different series of devices.

[0092] The core inventive points of this application include at least the following aspects. First, TXPI is used as a controllable phase actuator in TX Buffer enabled mode instead of switching to Buffer Bypass mode; second, the overflow / underflow latching characteristics of TXBUFSTATUS[1] are used as the coarse adjustment completion criterion to actively induce detectable boundary events; third, after the boundary event occurs, synchronous TX reset is performed on the two channels to eliminate the abnormal state generated during the coarse adjustment process and rebuild a more consistent FIFO initial phase; fourth, after synchronous reset, only one channel is subjected to DRP minimum step fine adjustment, so that the system can quickly enter the alignment window and obtain fine-grained output phase control; fifth, the maximum step sequence of "several times in one direction + more times in the opposite direction" is adopted so that the coarse adjustment does not depend on the accidental direction of the initial half-full state, thereby improving the determinism of triggering overflow / underflow after each power-on.

[0093] It should be noted that this method can be implemented using an internal state machine within the FPGA. The states of the state machine include S_IDLE, S_ASSERT_RST, S_WAIT_DLY, S_WAIT_RST_DONE, S_FORWARD_ADJ, S_BACKWARD_ADJ, S_LOCKED, S_CHECK_ST, S_RST_AGAIN, S_MANU_ADJ, S_MANU_WAIT, S_MANU_CHECK, and S_ALIGN_DONE. State transition conditions can all be triggered by the synchronous sampling signal, facilitating synthesis implementation. For more than two channels, a common reference channel can be selected, and the coarse adjustment, synchronous reset, and fine adjustment processes described above can be performed on the remaining channels separately; alternatively, multiple adjustment channels can be controlled in parallel during the coarse adjustment stage, and the final PI Code can be locked channel by channel during the fine adjustment stage.

[0094] See Figure 4 In one implemented embodiment, this solution is applied to a QPSK modulation and demodulation system. This system is implemented on a Xilinx Virtex-7 (V7) FPGA development board, with a GT serial output code rate of 5Gbps. The QPSK transmitter maps the I and Q channels to two GT outputs respectively. After employing the TX Buffer enable mode, TXPIPPM coarse-tuning overflow induction, dual-channel synchronous reset, and DRP minimum step fine-tuning process described in this application, the phase difference between the two GT outputs is compressed to less than 30ps. This result demonstrates that this solution is not only suitable for theoretical multi-channel GT phase alignment but also supports synchronous I / Q outputs in practical high-speed modulation and demodulation links.

[0095] This application has the following beneficial effects: Compared with the existing scheme that only relies on the default reset state of TX Buffer, this application actively drives TXPI to trigger the TX Buffer boundary event and then synchronously resets the two channels, so that the two channels no longer remain in an uncontrollable random half-full state. This process transforms the originally difficult-to-observe read-write phase difference into a detectable TXBUFSTATUS[1] latch event, reducing the impact of the initial phase randomness on the final alignment result.

[0096] Compared to the Buffer Bypass approach, this application retains the TX Buffer enabled mode, preserving the TX Buffer's ability to absorb the phase difference between the TXUSRCLK and PMA XCLK domains, thus avoiding the introduction of complex Bypass phase alignment timing, additional clock constraints, and stricter low-latency design limitations. For projects already using TX Buffer Enable mode, this method requires no significant modifications to the GT Wizard configuration, facilitating implementation on existing hardware platforms via state machines and DRP control logic.

[0097] Compared to a simple minimum step search scheme, this application first uses a maximum step to complete coarse adjustment and establish a reset baseline, and then proceeds to minimum step fine adjustment. The coarse adjustment stage narrows the fine adjustment search range, while the fine adjustment stage ensures the final phase resolution, thus balancing convergence speed and alignment accuracy. The preferred sequence of 150 unidirectional steps and 300 reverse steps can cover different initial phase positions, increasing the probability and determinism of triggering overflow / underflow events after each startup.

[0098] The reset strategy in this application is consistent with the requirement in the device datasheet that the TX Buffer should be reset after overflow or underflow. The system immediately and synchronously resets after using overflow / underflow as the criterion, preventing abnormal FIFO states from entering the normal data transmission phase, thus avoiding sacrifice of final link stability. The reset is held for 200 clock cycles and then fine-tuned after `reset_done`, preventing transient states during the reset release process from affecting phase determination.

[0099] The controlled objects in this application are mainly the existing GT port and DRP registers, including TXPIPPM, TXBUFSTATUS, GTTXRESET / TXPCSRESET, and PI Code configuration registers, without requiring external delay chips or additional analog phase detection circuits. This method consumes few logic resources, is easy to embed into reusable IP or power-on calibration state machines, and is also convenient to configure the number of steps, waiting periods, and phase thresholds at different line rates through software registers.

[0100] This application can improve the deterministic delay consistency of multi-channel transmission, enhance the edge alignment of two or more high-speed serial outputs, and reduce the complexity of data reassembly, cross-channel sampling, and training sequence acquisition at the receiver. For instruments, communication systems, radar systems, acquisition and playback systems, high-speed inter-board interconnects, and other systems requiring synchronization of multiple GT outputs, this solution can improve inter-channel phase consistency and power-on repeatability without changing the main hardware architecture.

[0101] In the aforementioned QPSK modulation and demodulation implementation verification, this solution has been tested at a 5Gbps code rate on a Xilinx V7 FPGA development board. After the I and Q channels are output through two GT channels respectively, the phase difference is less than 30ps. This verification result directly corresponds to the multi-channel transmission phase inconsistency problem that this application aims to solve, indicating that this method can achieve measurable and reproducible phase alignment in actual high-speed serial output links.

[0102] Corresponding to the above method embodiments, this specification also provides embodiments of a serial transceiver multi-channel transmission phase alignment device. Figure 5 A schematic diagram of a multi-channel transmission phase alignment device for a serial transceiver provided in one embodiment of this specification is shown. Figure 5 As shown, the device includes: The first reset module 501 is configured to perform a first synchronous reset on the reference transmission channel and the adjustment transmission channel located in the same four-channel group based on the same clock source. The channel coarse adjustment module 502 is configured to perform coarse adjustment on the transmission channel after the first synchronous reset is completed. The coarse adjustment is to perform the first phase adjustment so that the read / write pointer of the transmission buffer of the transmission channel crosses the half-full boundary and triggers an overflow or underflow event. The second reset module 503 is configured to perform a second synchronous reset on the reference transmission channel and the adjustment transmission channel in response to an overflow or underflow event, so as to clear the overflow or underflow flag of the transmission buffer of the adjustment transmission channel and rebuild the initial phase window of the transmission buffer of the two transmission channels. The channel fine-tuning module 504 is configured to perform fine-tuning on the adjusted transmission channel after completing the second synchronous reset. The fine-tuning is to perform a second phase adjustment until the phase difference between the transmission outputs of the reference transmission channel and the adjusted transmission channel is less than a predetermined threshold.

[0103] In one possible implementation, the first phase adjustment includes: first performing a predetermined number of maximum step phase adjustments along a first direction, and then performing another number of maximum step phase adjustments along a second direction opposite to the first direction, wherein the number of steps in the second direction is greater than the number of steps in the first direction; after each step, waiting for a predetermined number of user clock cycles, and then sampling and adjusting the buffer overflow status signal of the transmit channel; if the signal is not set, continuing to perform subsequent steps; if the signal is set, confirming that an overflow or underflow event has occurred.

[0104] In one possible implementation, the predetermined number of times is 150, and the other number is 300; the predetermined number of user clock cycles is 1,000 transmit user clock cycles; the reset hold time of the second synchronous reset is 200 transmit user clock cycles, and after the reset is released, it waits for the reset completion signals of both transmit channels to be high.

[0105] In one possible implementation, both the first and second synchronous resets are achieved by simultaneously asserting the transmit reset signals of the two transmit channels; the second phase adjustment is achieved by setting the phase interpolator manual overwrite enable signal to an active state and writing the phase interpolator code value through the configuration register read / write port, with each fine adjustment changing only one minimum step unit; the phase difference between the transmit outputs of the reference transmit channel and the adjustment transmit channel is determined by an external oscilloscope, on-chip logic analyzer, training sequence boundary detection module, or receiver data word arrival time comparison module.

[0106] In one possible implementation, the method is implemented by an internal state machine of a programmable logic device. The states of the state machine include an idle state, a waiting-for-reset-complete state, a forward coarse-tuning state, a reverse coarse-tuning state, a detection buffer state, a synchronous reset state, a waiting-for-reset-again-complete state, a manual fine-tuning state, and an alignment-complete state. The transition conditions between each state are triggered by a synchronous sampling signal.

[0107] In one possible implementation, for more than two transmission channels, one channel is selected as the reference transmission channel, and the first phase adjustment, second synchronization reset, and second phase adjustment process are executed on the remaining channels respectively; or multiple adjustment transmission channels are controlled in parallel during the first phase adjustment stage, and the final phase interpolator code value is locked channel by channel during the second phase adjustment stage.

[0108] In one possible implementation, the reference transmission channel and the adjustment transmission channel are high-speed serial transceiver channels in a programmable logic device. The two channels share the same phase-locked loop as a clock source and are both configured with a transmit buffer in enabled mode. The method is applied to a quadrature phase shift keying modulation and demodulation system. The two high-speed serial transceiver channels are used to output in-phase branch data and quadrature branch data, respectively. After the second phase adjustment, the phase difference between the two outputs is less than 30 picoseconds.

[0109] The above is a schematic scheme of a serial transceiver multi-channel transmission phase alignment device according to this embodiment. It should be noted that the technical solution of this serial transceiver multi-channel transmission phase alignment device belongs to the same concept as the technical solution of the serial transceiver multi-channel transmission phase alignment method described above. For details not described in detail in the technical solution of the serial transceiver multi-channel transmission phase alignment device, please refer to the description of the technical solution of the serial transceiver multi-channel transmission phase alignment method described above.

[0110] Figure 6 A structural block diagram of a computing device 600 according to one embodiment of this specification is shown. The components of the computing device 600 include, but are not limited to, a memory 610 and a processor 620. The processor 620 is connected to the memory 610 via a bus 630, and a database 650 is used to store data.

[0111] The computing device 600 also includes an access device 640, which enables the computing device 600 to communicate via one or more networks 660. Examples of these networks include Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or combinations of communication networks such as the Internet. The access device 640 may include one or more of any type of wired or wireless network interface (e.g., a network interface card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, a Wi-MAX (Worldwide Interoperability for Microwave Access) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, or a Near Field Communication (NFC) interface.

[0112] In one embodiment of this specification, the above-described components of the computing device 600 and Figure 6 Other components, not shown, can also be connected to each other, for example, via a bus. It should be understood that... Figure 6 The block diagram of the computing device shown is for illustrative purposes only and is not intended to limit the scope of this specification. Those skilled in the art can add or replace other components as needed.

[0113] The computing device 600 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 600 can also be a mobile or stationary server.

[0114] The processor 620 executes computer-executable instructions that, when executed by the processor, implement the steps of the aforementioned serial transceiver multi-channel transmission phase alignment method. The above is an illustrative scheme of a computing device according to this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the aforementioned serial transceiver multi-channel transmission phase alignment method belong to the same concept. Details not described in detail in the technical solution of the computing device can be found in the description of the technical solution of the aforementioned serial transceiver multi-channel transmission phase alignment method.

[0115] An embodiment of this specification also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the above-described serial transceiver multi-channel transmission phase alignment method.

[0116] The above is an illustrative scheme of a computer-readable storage medium according to this embodiment. It should be noted that the technical solution of this storage medium belongs to the same concept as the technical solution of the above-described serial transceiver multi-channel transmission phase alignment method. For details not described in detail in the technical solution of the storage medium, please refer to the description of the technical solution of the above-described serial transceiver multi-channel transmission phase alignment method.

[0117] An embodiment of this specification also provides a computer program, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the above-described serial transceiver multi-channel transmission phase alignment method.

[0118] The above is an illustrative scheme of a computer program according to this embodiment. It should be noted that the technical solution of this computer program belongs to the same concept as the technical solution of the above-described serial transceiver multi-channel transmission phase alignment method. For details not described in detail in the technical solution of the computer program, please refer to the description of the technical solution of the above-described serial transceiver multi-channel transmission phase alignment method.

[0119] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0120] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0121] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0122] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0123] The preferred embodiments disclosed above are merely illustrative of this specification. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. A method for phase alignment of multi-channel transmission in a serial transceiver, characterized in that, include: The reference transmission channel and the adjustment transmission channel located in the same four-channel group are first synchronously reset based on the same clock source; After the first synchronous reset is completed, a coarse adjustment is performed on the adjusted transmission channel. The coarse adjustment is to perform a first phase adjustment so that the read / write pointer of the transmission buffer of the adjusted transmission channel crosses the half-full boundary and triggers an overflow or underflow event. In response to the overflow or underflow event, a second synchronous reset is performed on the reference transmission channel and the adjusted transmission channel to clear the overflow or underflow flag of the transmission buffer of the adjusted transmission channel and rebuild the initial phase window of the transmission buffer of the two transmission channels. After the second synchronization reset is completed, fine-tuning is performed on the adjusted transmission channel. The fine-tuning is to perform a second phase adjustment until the phase difference between the transmission outputs of the reference transmission channel and the adjusted transmission channel is less than a predetermined threshold.

2. The method according to claim 1, characterized in that, The first phase adjustment includes: first performing a predetermined number of maximum step phase adjustments along a first direction, and then performing another number of maximum step phase adjustments along a second direction opposite to the first direction, wherein the number of adjustments in the second direction is greater than the number of adjustments in the first direction; after each step, waiting for a predetermined number of user clock cycles, and then sampling the buffer overflow status signal of the adjusted transmission channel; if the signal is not set, continuing to perform subsequent steps; if the signal is set, confirming that the overflow or underflow event has occurred.

3. The method according to claim 2, characterized in that, The predetermined number of times is 150 times, and the other number of times is 300 times; the predetermined number of user clock cycles is 1,000 transmitting user clock cycles; the reset hold time of the second synchronous reset is 200 transmitting user clock cycles, and after the reset is released, it waits for the reset completion signals of both transmitting channels to be high level.

4. The method according to claim 1, characterized in that, Both the first synchronous reset and the second synchronous reset are achieved by simultaneously asserting the transmit reset signals of the two transmit channels; the second phase adjustment is achieved by setting the phase interpolator manual overwrite enable signal to an effective state and writing the phase interpolator code value through the configuration register read / write port, with each fine adjustment changing only one minimum step unit; the transmit output phase difference between the reference transmit channel and the adjustment transmit channel is determined by an external oscilloscope, on-chip logic analyzer, training sequence boundary detection module, or receiver data word arrival time comparison module.

5. The method according to claim 1, characterized in that, The method is implemented by an internal state machine of a programmable logic device. The states of the state machine include an idle state, a waiting-for-reset-complete state, a forward coarse adjustment state, a reverse coarse adjustment state, a detection buffer state, a synchronous reset state, a waiting-for-reset-again-complete state, a manual fine adjustment state, and an alignment-complete state. The transition conditions between each state are triggered by a synchronous sampling signal.

6. The method according to any one of claims 1 to 5, characterized in that, For more than two transmission channels, one channel is selected as the reference transmission channel, and the first phase adjustment, the second synchronization reset, and the second phase adjustment process are executed on the remaining channels respectively. Alternatively, multiple adjustment transmission channels can be controlled in parallel during the first phase adjustment stage, and the final phase interpolator code value can be locked channel by channel during the second phase adjustment stage.

7. The method according to claim 1, characterized in that, The reference transmission channel and the adjustment transmission channel are high-speed serial transceiver channels in a programmable logic device. The two channels share the same phase-locked loop as a clock source and are both configured with a transmit buffer in enabled mode. The method is applied to a quadrature phase-shift keying modulation and demodulation system. The two high-speed serial transceiver channels are used to output in-phase branch data and quadrature branch data, respectively. After the second phase adjustment, the phase difference between the two outputs is less than 30 picoseconds.

8. A serial transceiver multi-channel transmission phase alignment device, characterized in that, include: The first reset module is configured to perform a first synchronous reset on the reference transmission channel and the adjustment transmission channel located in the same four-channel group based on the same clock source. The channel coarse adjustment module is configured to perform coarse adjustment on the adjusted transmission channel after the first synchronous reset is completed. The coarse adjustment is to perform a first phase adjustment so that the read / write pointer of the transmission buffer of the adjusted transmission channel crosses the half-full boundary and triggers an overflow or underflow event. The second reset module is configured to perform a second synchronous reset on the reference transmission channel and the adjustment transmission channel in response to the overflow or underflow event, so as to clear the overflow or underflow flag of the transmission buffer of the adjustment transmission channel and rebuild the initial phase window of the transmission buffer of the two transmission channels. The channel fine-tuning module is configured to perform fine-tuning on the adjusted transmission channel after completing the second synchronous reset. The fine-tuning involves performing a second phase adjustment until the phase difference between the transmission outputs of the reference transmission channel and the adjusted transmission channel is less than a predetermined threshold.

9. A computing device, characterized in that, include: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the serial transceiver multi-channel transmission phase alignment method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the serial transceiver multichannel transmission phase alignment method according to any one of claims 1 to 7.

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