A ternary computer architecture based on dual rail encoding and a method for implementing the same

Abstract

The application discloses a system architecture and a method for realizing ternary calculation on the basis of binary hardware. The system organizes the calculation resources in a 1+N recursive tree structure (N=3^K, K>=1), and the core innovation is that, on the basis of standard CMOS binary transistors, an independent ternary logic layer is constructed through double-line coding, ternary values (-1, 0, +1) are mapped to a binary signal pair, the standard binary transistor can execute ternary operation without modification, and the dependence on tri-state transistors is broken. A total main control unit supports double-mode switching of a throughput mode and a reliable mode: in the throughput mode, different trit bits are calculated in parallel by each execution unit, and in the reliable mode, all execution units calculate the same trit bit and then vote by majority. The system comprises 31 instruction sets of A-J ten series, a four-level security defense system, majority voting linkage, and a true priority interrupt nesting. 405+ tests are completed on a 4-board ESP32-S3 (standard binary chip), and the system can be directly used in standard CMOS process.

Description

Technical Field

[0002] This invention relates to the field of computer architecture, specifically to a novel computer architecture and its implementation method that utilizes binary physical devices (standard CMOS transistors) to perform ternary logic calculations. Background Technology

[0003] The concept of ternary computers can be traced back to the Setun computer developed by the Soviet Union in 1958. Setun used a ferrite core to implement balanced ternary (-1, 0, +1) operations. Theoretically, the information density of ternary is log23≈1.585 times that of binary, and it is naturally symmetrical in expressing positive and negative values.

[0004] However, there has been no further substantial progress in ternary computers. The fundamental reason lies in a technological bottleneck: the physical implementation of a three-state transistor is extremely difficult. Traditional ternary systems require a single signal line to stably distinguish and transmit three voltage levels (negative, zero, and positive), which is far more complex in semiconductor physics and manufacturing processes than binary systems (which only require distinguishing between high and low voltage levels). For over half a century, academia and industry have waited, and the three-state transistor has still not reached commercial maturity.

[0005] This predicament led to a near-complete standstill in research in the field, forming what this invention calls the "extreme logic trap"—that is, researchers generally believe that a true ternary computer cannot be built until the advent of the tri-state transistor.

[0006] All currently known ternary arithmetic schemes face at least one of the following problems: (a) It relies on three-state transistor technology, which is not yet commercially available, and cannot be manufactured on existing semiconductor process lines; (b) It remains only at the theoretical or simulation stage, lacking physical hardware verification; (c) It only implements limited ternary arithmetic functions and lacks a complete instruction set, operating system support and security mechanisms; (d) The architecture lacks scalability and cannot adapt to computing needs of different scales. Summary of the Invention

[0007] The technical problem to be solved by this invention is: how to build a complete, scalable and practically operable ternary computer system under the existing standard CMOS binary transistor technology, and break through the technical prejudice that "three-state transistors must be available first".

[0008] This invention proposes a novel technical approach—implementing a ternary logic layer through double-wire encoding based on the physical foundation of binary transistors. Its core idea is: The binary hardware can fully express and perform ternary operations by using three of the four combinations (00, 01, 10, 11) of two binary signal lines (line A and line B).

[0009] Based on this, a 1+3 recursive tree multi-board distributed architecture was designed (supporting dynamic switching between throughput and reliability modes), a triple-redundant majority voting mechanism, a complete AJ series ternary instruction set, a K series system-level security mechanism, and a D series four-level security defense system. The architecture overview is as follows: Figure 1 As shown.

[0010] Encoding table (e.g.) Figure 2 As shown, the correspondence between the line A / line B voltage levels and their ternary values ​​is as follows: | Ternary Values ​​| Line A | Line B | Physical Meaning | |:---:|:---:|:---:|------| | -1 | LOW | HIGH | Negative value | | 0 | LOW | LOW | Zero | | +1 | HIGH | LOW | Positive Value | | (N / A) | HIGH | HIGH | Not used | Key features: Each trit occupies 2 bits of physical resources, but gains the full computing power of ternary logic. Lines A and B are both standard binary digital signals, which can be generated and processed by any CMOS digital circuit. The encoding scheme is independent of the transistor type of the hardware platform (it can run on any binary digital logic such as TTL, CMOS, and NMOS). Implementation of ternary arithmetic in binary hardware (full adder decision logic as follows) Figure 5 (as shown) The core algorithm of a balanced ternary full adder (pseudocode): function t_full_add(a, b, carry_in): / / a, b, carry_in ∈ {-1, 0, +1} sum = a + b + carry_in / / sum ∈ [-3, +3], binary signed integer arithmetic if sum >= +2: carry_out = +1 result = sum - 3 else if sum>= -1: carry_out = 0 result = sum else if sum == -2: carry_out = -1 result = +1 else: / / sum == -3 carry_out = -1 result = 0 return (result, carry_out) / / result ∈ {-1, 0, +1}, carry_out ∈ {-1, 0, +1} Similarly, ternary subtraction, multiplication, and division can all be converted into binary signed integer operations and then normalized to the range {-1, 0, +1}.

[0011] 3.3.1 The essential difference from existing dual-track coding technology It should be clearly pointed out that the dual-rail encoding scheme described in this invention differs fundamentally from known dual-rail encoding (such as Null Convention Logic, NCL, etc.) in asynchronous circuit design in terms of technical purpose, encoding semantics, and engineering effects. | Comparison Dimensions | Existing dual-track encoding (such as NCL) | This invention's dual-line encoding | |:---|:---|:---| | Technical Purpose | Asynchronous Handshake Protocol (request / acknowledge) | Balanced Ternary Arithmetic Operations | | Encoding Semantics | Data Valid / Invalid (DATA / NULL) Binary State | Ternary Value (-1 / 0 / +1) Triple State | | Fourth State | NULL (indicates no valid data) | Not used (HIGH / HIGH is a reserved state) | | Arithmetic Operations | Does not support ternary arithmetic mapping | Deep integration of encoding and ternary full adder decision logic | | Application Areas | Asynchronous Circuit Timing Closure | Ternary Instruction Set Execution on Binary Hardware | Key differences explained in detail: (a) Different Objectives: The core objective of existing dual-track encoding is to solve the timing problem of asynchronous circuits—achieving clockless data handshakes through the NULL state in the two lines. Each data line requires a complete request-acknowledge cycle. The purpose of the dual-track encoding in this invention is completely different: to achieve complete balanced ternary computation capability on standard CMOS binary hardware.

[0012] (b) Different Coupling Depths of Encoding and Operation: Existing dual-track encoding only focuses on "whether the data is ready" and does not participate in the definition of arithmetic logic. This invention deeply integrates dual-track encoding with balanced ternary arithmetic—the encoding mapping (-1↔LH, 0↔LL, +1↔HL) is specifically designed for the full adder decision logic in Section 3.3. When the full adder performs sum = a + b + carry_in (binary signed integer operation), this mapping makes the normalization from binary integer to ternary value only require a simple threshold comparison (≥+2→carry+1; ≤-2→borrow-1), without the need for table lookups or complex state transitions.

[0013] (c) Different engineering constraints: Existing dual-track coding requires special asynchronous circuit design processes and specialized logic synthesis tools. The dual-track coding of this invention runs on standard synchronous digital logic and does not require any asynchronous design tools or special processes.

[0014] (d) Verifiability: The above differences can be verified in the actual machine test of this invention—the same set of dual-line encoding logic correctly executed all arithmetic operations of ternary addition / subtraction / multiplication / division on a standard ESP32-S3 microcontroller and passed 405+ tests. This proves that the dual-line encoding of this invention is not a simple transplant or superficial modification of known dual-track encoding, but a completely new encoding-operation coupling scheme specifically designed for balanced ternary calculations.

[0015] In summary, the novelty of this invention's two-line encoding lies not in the "use of two lines" format, but in: (i) the specific mapping relationship between the encoding and balanced ternary arithmetic, (ii) the deep coupling design of this mapping with the full adder decision logic, and (iii) the systems engineering approach to implementing the entire scheme as a complete instruction set on standard synchronous binary hardware. None of these three points appear in known two-line encoding literature.

[0016] Basic structure (first layer): Main control unit (Board #1) / | \ Execution Unit #1 Execution Unit #2 Execution Unit #3 (Board #2) (Board #3) (Board #4) ALU+x ALU+y ALU+z (trit 2) (trit 1) (trit 0) Division of responsibilities: Main control unit: fetches instructions, decodes opcodes, dispatches arithmetic instructions to corresponding execution units, processes control flow instructions, collects and summarizes calculation results, and manages OS scheduling. Execution Unit (ALU Board): Receives a single trit operand, performs arithmetic / logical operations, and returns the result trit and carry information to the main unit. Recursive expansion (taking the second level as an example): Main control unit / | \ Secondary Primary #1 Secondary Primary #2 Secondary Primary #3 / | \ / | \ / | \ E1 E2 E3 E4 E5 E6 E7 E8 E9 When more computing power is needed, the execution units in their original positions are upgraded to "secondary master control units," each managing three new execution units. The main master control unit communicates only with the three secondary master control units, which are responsible for task distribution and result collection from their subordinate units.

[0017] Extended formula: Total number of computational units in layer K (K≥0, K=0 is only the main layer): $$N_K = \frac{3^{K+1} - 1}{2}$$ K=0: 1 unit (main unit) K=1: 4 units (current implementation) K=2: 13 units K=3: 40 units 3.4.1 Dual-mode operation mechanism The core design philosophy of the 1+3 architecture is that the three execution units can dynamically switch between two operating modes to flexibly balance computational throughput and result reliability. Mode 1 – Throughput Mode (i.e., bit-slice mode): Each of the three execution units is responsible for a different trit bit, enabling fully parallel processing of ternary data. Take 3-trit addition as an example: Execution unit #1 (board 2) → Process trit[2] (most significant bit) Execution unit #2 (board 3) → Process trit[1] Execution unit #3 (board 4) → Process trit[0] (least significant bit) The three boards perform calculations simultaneously, completing a 3-trit operation in one go, with a delay of approximately one calculation cycle. Mode 2 – Reliability Mode (TMR mode): Each of the three execution units independently calculates the exact same operand for the same trit bit, and the final result is determined by majority vote. In this mode: All three boards received identical copies of the operands. Each operation is performed independently and the result trit is returned. The main control unit performs a two-out-of-three majority vote. Each calculation produces only one trit; 3-trit data requires three sequential executions, with a delay of approximately three calculation cycles. However, any single-board calculation error is automatically corrected, improving reliability by approximately three orders of magnitude. Dual-mode switching mechanism: The system operates in throughput mode by default. When the sentinel layer of the security defense system detects any of the following trigger conditions, the system will automatically switch to reliable mode: The number of suspicious events in any execution unit exceeds the threshold (default 3 times). Communication error rate exceeds preset threshold External manual command trigger Switching to system-wide redundancy—once in reliable mode, all arithmetic instructions enable triple redundancy until a system health check passes, at which point throughput mode is restored. This dual-mode switching is transparent to upper-layer software; the instruction set and programming model remain unaffected.

[0018] Dual-mode extension of the hierarchy: In the second-level expansion (13 boards, K=2), each of the three secondary master control units has three subordinate execution units, and the computing architecture is as follows: Main control unit ├── Secondary Master #1 ─── [E1, E2, E3] ← A 3-element TMR group ├── Secondary Master #2 ─── [E4, E5, E6] ← A 3-element TMR group └── Secondary Main #3 ─── [E7, E8, E9] ← A 3-element TMR group At this point, the nine execution units are divided into three TMR groups, each group simultaneously calculating a different trit bit. This means that at K=2 level, the system can simultaneously achieve both throughput mode (three trits in parallel) and reliability mode (each trit has three redundancies) – the contradiction between the two is naturally resolved at higher expansion levels.

[0019] This dual-mode design is one of the core innovations of this invention—it provides the flexibility of choosing between throughput and reliability in the minimum implementation (4 boards), while gaining the advantages of both in the extended implementation (13 boards). This design philosophy of "trading space for choice and hierarchy for balance" reflects the profound advantages of the 1+3 recursive architecture.

[0020] This invention implements 31 complete ternary instructions across ten series of AJ: Instruction format (10-trit fixed length, such as...) Figure 3 (as shown) Bit 0 1 2 3 4 5 6 7 8 9 ┌───────────┬──────────┬──────────┐ │ Opcode │ Target / Result │ Operands │ │ 4 trit │ 3 trit │ 3 trit │ └───────────┴──────────┴──────────┘ Complete instruction set: | Series | Instructions | Opcodes | Function Description | |:---:|------|:---:|------| | A | NOP ​​| 0 | No operation | | A | LDA | 1 | Load from memory to accumulator | | A | STA | 2 | Store accumulator to memory | | A | LDI | 3 | Load immediate value | | A | ADD | 4 | Ternary addition (ACC←ACC+MEM) | | A | ADI | 5 | Immediate Ternary Addition | | B | SUB | 6 | Ternary Subtraction | | B | SUI | 7 | Immediate Ternary Subtraction | | B | MUL | 8 | Ternary Multiplication | | B | MUI | 9 | Immediate Ternary Multiplication | | C | DIV | 10 | Ternary division | | C | DVI | 11 | Immediate Ternary Division | | — | NEG | 12 | Ternary Invert (ACC←-ACC) | | — | CMP | 13 | Ternary Comparison (with Flag) | | — | CPI | 14 | Immediate number ternary comparison | | — | JMP | 15 | Unconditional jump | | — | JZ | 16 | Zero Redirect | | — | JP | 17 | Redirecting | | — | JN | 18 | Negative jump | | — | JNZ | 19 | Non-zero jump | | — | CALL | 20 | Subroutine call | | — | RET | 21 | Subroutine return | | — | HLT | 22 | Downtime | | F | PUSH | 23 | Push onto stack | | F | POP | 24 | Pop | | F | IN | 25 | Three-state switch input | | F | OUT | 26 | LED Tri-state Output | | — | JO | 27 | Overflow Jump | | — | JNO | 28 | No overflow redirection | | E | SWI | 29 | Software interrupt (system call) | | E | RTI | 30 | Interrupt Return |

[0021] Distributed execution process such as Figure 4 As shown, the execution process comprises seven stages: instruction fetch, decoding, dispatch, computation, majority voting, result collection, and aggregation. The execution process for each instruction type is detailed below: (a) Execution of arithmetic instructions Taking the ternary addition TADD as an example, assuming the data width is 3 trit (value range [-13, +13]): 1. Total master-slave memory read operations A (3 trits) and B (3 trits) 2. The master sends A's trit[0] and B's trit[0] to execution unit #1 (board 2). 3. The master sends A's trit[1] and B's trit[1] to execution unit #2 (board 3). 4. The master sends A's trit[2] and B's trit[2] to execution unit #3 (board 4). 5. Each execution unit computes the full sum (a + b + carry_in) of a single trit in parallel, producing (result_trit, carry_out). 6. Carry / borrow propagates between adjacent execution units via a carry chain. 7. The main unit collects the result_trit values ​​from the three execution units and concatenates them into the final result. (b) Execution of control commands Control instructions (JMP / JZ / CALL / RET, etc.) only involve modifications to the program counter and stack, and are handled independently by the master unit without needing to be dispatched to the execution unit.

[0022] (c) Dual-board parallel operation mode With BOARD_ID=1 (master) and BOARD_ID=2 (secondary master) working together, the master motherboard runs the OS kernel and scheduler (os_board0_h.cpp), while the secondary motherboard runs the ALU and file system (sub_master1_h.cpp). The two boards communicate asynchronously via the ESP-NOW wireless protocol to achieve streaming processing of computing tasks.

[0023] 3.6.1 Triple Redundancy Majority Voting Mechanism The Triple Modular Redundancy (TMR) mechanism of this invention is a specific implementation of the reliable mode described in Section 3.4.1. This mechanism utilizes the inherent structure of "3 execution units" in the 1+3 architecture to achieve triple modular redundancy fault tolerance without increasing hardware.

[0024] Working principle (in) Figure 4 In a distributed execution process, the voting step occurs after result collection and before result aggregation. 1. Redundant Distribution: In reliable mode, the main control unit sends identical operand copies to all three execution units for each trit bit to be computed. Each of the three execution units independently performs the arithmetic and logical operations on that trit bit. Each unit receives identical operands but performs independent operations without communicating with each other.

[0025] 2. Majority Voting: After receiving three independent calculation results, the main control unit performs a two-out-of-three majority vote: If at least two of the three results match, the majority consensus value is taken as the final correct result for that trit bit. If the three results are all different (i.e., three different values: -1, 0, and +1 each), the exception handling process is triggered.

[0026] 3. Exception handling (three-level progression): Level 1 – Retry: The main control unit resends the same operands to the corresponding execution units, and each unit re-executes the calculation and returns the result. If the majority of retry results are consistent, the result is adopted and the exception record is cleared.

[0027] Level 2 – Degradation: If the three results are still different after retrying, the main control unit marks the execution unit as "suspicious" and degrades the calculation of the trit bit to local calculation by the main control unit (bypassing the execution unit and completing it directly at the main control unit, at which point the main control unit acts as the fourth independent calculation source).

[0028] Level 3 – Linked Reporting: Suspicious execution unit information is reported to the sentinel layer (second layer) of the security defense system. If the cumulative number of suspicious events of a single execution unit exceeds the preset threshold (3 times by default), the sentinel layer automatically upgrades the security threat level and notifies the remote termination layer (third layer) to prepare to isolate or restart the execution unit.

[0029] 4. Throughput - Reliability Trade-offs and Cost Transparency: This invention truthfully discloses the computational cost of the reliable model, without exaggeration or evasion: | Comparison Dimensions | Throughput Mode (Bit Fragment) | Reliability Mode (TMR) | |:---|:---|:---| | 3-trit data parallelism | 3 trits computed simultaneously | 1 trit at a time, 3 times sequentially | Theoretical delay (3-trit operation) | 1 × computation cycle | 3 × computation cycle | | Fault Tolerance | None (Single Board Error = Result Error) | Any single board error is corrected | | Applicable Scenarios | Routine Computing | High Reliability / Security Sensitive Scenarios | 5. Efficiency improvements through layer expansion: In the K=2 layer (13 boards) architecture, the conflict between throughput mode and reliability mode is naturally resolved—the 9 execution units are divided into 3 TMR groups, and each group of 3 boards simultaneously calculates different trit bits, achieving both throughput and reliability: Parallelism = 3 trit / cycle (same as K=1 layer throughput mode) Fault tolerance = Each trit has 3 layers of redundancy (same as the K=1 layer reliability mode). Hardware efficiency = Throughput mode fault tolerance can be achieved by adding only one layer of expansion (9 boards → 3 TMRs). Design advantages: The minimum 4-board system can support two modes simultaneously, and the switching is completed automatically by triggering conditions, which is transparent to the upper-layer software. The 13-board expansion system achieves both high throughput and high reliability without sacrificing the advantages of either. Linked with the four-level security defense system: majority voting anomalies directly trigger security alerts, forming a computation-security closed loop; No single point of failure is introduced: a momentary error in any execution unit does not affect the correctness of the final calculation result.

[0030] This mechanism is one of the core innovations of this invention. It achieves triple redundancy in the minimum system through the natural three-unit structure of the 1+3 architecture with an honest cost model (throughput for reliability), and simultaneously obtains the advantages of both at a higher level through recursive expansion.

[0031] 3.6.1.1 Carry chain processing in reliable mode In reliable mode (TMR), the handling of carry chains differs from that in throughput mode and requires separate explanation: Problem: In reliable mode, three redundant copies of the same trit bit each generate carry output independently (carry_out_0, carry_out_1, carry_out_2). When propagating the carry to the higher-order trit bits, it is necessary to determine which copy's carry should be used.

[0032] Solution – Three-level carry processing: 1. Carry-majority voting: The main control unit performs the same majority voting logic as the result trit on the carry outputs of the three replicas—if at least two of the three carry values ​​are consistent, then the carry output of that bit is the majority consistent value, and it is passed to the calculation of the next bit.

[0033] 2. Handling Inconsistent Carry Values: If the three carry values ​​are all different (one each of -1, 0, and +1), it indicates a serious calculation anomaly in that bit. In this case: Set the carry value to 0 (a conservative strategy to prevent errors from propagating to higher bits). Trigger the exception handling process (Section 3.6.1, Step 3) Retry on this bit 3. 3-trit sequential carry procedure in reliable mode: Taking 3-trit addition as an example: trit[0]: Three copies are computed independently → majority vote (result_0, carry_0) trit[1]: Each of the three copies receives carry_0 → independent calculation → majority vote (result_1, carry_1) trit[2]: Each of the three copies receives carry_1 → independent calculation → majority vote (result_2, carry_2) Final result: (result_2, result_1, result_0) The entire process involves three majority votes, with each vote executing both the result and carry for that bit simultaneously. In case of a carry error, the result is conservatively cleared to zero and a retry is triggered to ensure that the calculation of higher bits is not corrupted by erroneous carry.

[0034] This design ensures that carry propagation in reliable mode also benefits from the fault tolerance of triple redundancy, and the carry chain does not become a weak link.

[0035] The security system adopts a defense-in-depth design, consisting of four layers from the outside in (e.g., Figure 6 (as shown) First Tier – Board Guardian: Maintain the registration status of all online execution units. Periodically send heartbeats and wait for a response (5-second interval; 3 consecutive lost heartbeats = offline). Offline units are automatically removed and attempts are made to restore them. Statistical analysis of the operating status and error count of each unit. The second layer – Sentinel: Global behavior monitoring Abnormal instruction sequence detection (such as consecutive illegal opcodes) State machine abnormal transition detection Linked with majority voting mechanism: Upon receiving an "Execution unit marked as suspicious" event from the main control unit, when the number of suspicious events accumulates to exceed a preset threshold (3 times by default), the security threat level is automatically upgraded and the third-level remote termination layer is notified. Trigger a tiered alarm and report to the central administrator. The third layer – Remote Terminator: The master retains the right to remotely terminate. Activation can be achieved via serial port commands, sentinel triggering, or manual methods. Send a restart command after forcibly terminating the target unit. The fourth layer – the Root Vault: Root credentials are stored independently in the on-chip eFuse secure area or a dedicated encrypted flash memory partition. Access requires hardware security boot chain verification and multi-factor authentication. Unauthorized access attempts trigger hardware-level automatic erasure (utilizing eFuse's one-time programmability or flash encryption key revocation). Logically isolated from normal computing tasks via a memory protection unit (MPU / PMP), root credentials are read only during the secure boot phase and are not exposed to the general address space during runtime.

[0036] Interrupt nesting timing as follows Figure 7 As shown in the screenshot, the actual test output log is as follows: Figure 8 As shown. On the ESP32-S3 platform, true priority interrupt nesting was verified using the ESP-IDF timer driver and two levels of hardware interrupt priorities: Test configuration: Timer TG1_T0: Low priority (Level 1), 20ms timing period, ISR execution time is approximately 12ms. Timer TG1_T1: High priority (Level 2), 1ms timing period, extremely short ISR execution. Total test duration: 2000ms CPU Bonding: Two ISRs are assigned to the same CPU core (Core 1). Actual results: Low ISR trigger count: 100 times (theoretical value: 2000ms / 20ms = 100) High ISR trigger count: 2017 times (theoretical value: ≈2000ms / 1ms = 2000) Maximum nesting depth: 2 (≥2: confirm that higher priority preempts lower priority) Number of preemption attempts: 1200 (when a high-priority ISR enters while a low-priority ISR is in progress) Low priority PS.INTLEVEL: 1 High priority PS.INTLEVEL: 2 Test result: PASS Technical Breakthrough: During testing, it was discovered that the ESP32-S3's timer alarm enable register (tn_alarm_en) is a self-clearing type—the hardware automatically clears this bit after an alarm is triggered, causing subsequent interrupts to stop triggering. The solution is to directly write to the hardware register at the end of the ISR to re-enable it, bypassing the automatic reload bug in the ESP-IDF driver layer. Detailed Implementation

[0037] | Components | Specifications | |------|------| | Main Controller Chip | ESP32-S3 (Xtensa LX7 Dual-Core, 240MHz) | | Number of onboard units | 4 | | Communication Method | ESP-NOW (2.4GHz Wi-Fi MAC Layer) | | Input Device | Dual-button switch (GPIO10: Left, GPIO11: Right, INPUT_PULLUP) | | Output Device | LED (GPIO48) | | Development Environment | PlatformIO (Arduino framework + ESP-IDF component) | Physical connection: | Physical Board | BOARD_ID | COM Port | Function | |:---:|:---:|:---:|------| Board 1 | 1 | COM3 | Main Control Unit | | Board 2 | 2 | COM4 | ALU Execution Unit (trit bit 2) | | Board 3 | 3 | COM5 | ALU Execution Unit (trit bit 1) | | Board 4 | 4 | COM9 | ALU Execution Unit (trit bit 0) |

[0038] A combined state-coded ternary input is obtained through two physical switches (left switch GPIO10 and right switch GPIO11, both configured as INPUT_PULLUP): | Left switch | Right switch | Ternary value | Encoding meaning | |:---:|:---:|:---:|------| | Press | Release | -1 | Press left, don't press right | | Release | Press | +1 | Press right, don't press left | Press | Press | 0 | Press both to reset | | Release | Release | 0 | Even without pressing, it resets to zero | This encoding method is highly robust: any switch with poor contact or in a floating state is encoded as a valid state, and no uncertain output will be generated.

[0039] The result of a ternary operation is expressed by controlling three states of the LED: LED constantly on → Positive value (+1) LED off → Zero value (0) LED blinking → Negative value (-1)

[0040] Memory layout: PROG_SIZE = 128 instructions (10 trits per instruction) DATA_SIZE = 729 data words (6 trits each) OS_MAX_PROGRAMS = 4 (1 supervisor + 3 users, corresponding to a 1+3 architecture) TIME_SLICE_MS = 200ms Process management: Each program is allocated 32 instruction spaces and 182 data words. Cooperative round-robin scheduling (currently) will be upgraded to preemptive scheduling in the future (utilizing K② interrupt nesting). The system call SWI serves as the entry point from user mode to kernel mode.

[0041] This project has established a complete testing system from unit testing to system-level verification: Test level: 1. Single instruction testing: Each instruction is verified independently (Python simulation + real machine comparison) 2. Instruction sequence testing: program fragments (such as prime number detection, sorting algorithms) 3. System-level testing: multi-board collaboration, interrupt nesting, spinlocks 4. Stress testing: Long-term operation, boundary conditions Test statistics: 26 Python test scripts (6,069 lines of test code) 95+ main assertions / validation points 405+ Real-world test items Pass rate: 100% in 405+ completed real-world functional tests (this data is based on the completed test set and does not include long-term stability tests that have not yet been performed and all theoretical combinations of boundary conditions). Representative test cases: (a) G1 Basic ALU Test: Verify the correctness of single trit operations in ternary addition / subtraction / multiplication. (b) J1 Prime Number Detection: Implementing a prime number determination algorithm using ternary instructions (c) I3 Fast Fourier Transform: Ternary Complex Number Operations (d) K2 interrupt nesting: verifying true priority preemption (see section 3.8 for actual machine data)

[0042] This invention quantifies the performance advantage of ternary over binary by conducting rigorous comparative experiments on the same hardware platform using both ternary instruction sets and equivalent binary algorithms. All data below are based on real-world testing and Python equivalent simulation comparisons.

[0043] 4.6.1 Sorting – The Natural Advantage of Three-Way Partitioning The ternary comparison instruction (TCMP) returns a tri-state flag {-1, 0, +1}, natively supporting three-way partitioning (less than / equal to / greater than), eliminating the need for additional comparisons to determine equality. | Array size | Number of comparisons in three-way quicksort | Number of comparisons in two-way quicksort | Savings | |:---:|:---:|:---:|:---:| | n=500 | 4,771 | 4,812 | 1% | | n=1000 | 10,174 | 11,126 | 9% | | n=2000 | 21,806 | 25,262 | 16% | The advantage is even more significant in scenarios with duplicate values ​​(saving 49% when the duplication rate is 90%), because equal partitions directly skip equal elements and do not need to participate in subsequent recursive comparisons.

[0044] 4.6.2 Prime number detection – zero values ​​are automatically skipped In ternary modular exponentiation, after the exponent is decomposed into trit, approximately 33% of the trit values ​​are 0, and the multiplication operations corresponding to these trit values ​​are automatically skipped. Simultaneously, ternary naturally skips multiples of 3 (end trit = 0), reducing the number of candidate exponents by 33%. | Indicator | Ternary | Binary | Savings | |:---|:---:|:---:|:---:| | Miller-Rabin modular exponentiation iterations | 3,118 | 4,631 | 33% | | 0-trit auto-skip rate | 31% | Not applicable | — | | Number of candidates (skipping multiples of 3) | 1,334 | 2,000 | 33% | 4.6.3 Encryption – Exponential Growth of Key Space The ternary key space is 3^n, and the binary key space is 2^n, with the difference increasing exponentially as the key length grows: | Key length (trit) | Ternary space | Binary equal-length space | Ternary multiples | |:---:|:---:|:---:|:---:| | 4 | 81 | 16 | 5.1× | | 6 | 729 | 64 | 11.4× | | 8 | 6,561 | 256 | 25.6× | | 10 | 59,049 | 1,024 | 57.7× | | 12 | 531,441 | 4,096 | 129.7× | A 12-trit key space (531,441 combinations) is sufficient to resist brute-force attacks. The ternary one-time pad (OTP) avalanche effect reaches 100%—any change in any trit in the key results in a change in all trits of the ciphertext.

[0045] 4.6.4 Fast Fourier Transform – Radix-3 Zero-Padding-Free When the signal length is exactly 3^p, the radix-3 FFT does not require zero padding, thus avoiding spectral distortion caused by zero padding. | Metrics | Radix-3 FFT (n=27) | Radix-2 FFT (n=32) | |:---|:---:|:---:| | Zero fill waste | 0% | 15.6% | | Butterfly Operands | 378 | 320 | The radix-3 FFT operates on the same order of magnitude as the radix-2 FFT on signals of the same length (3^p), and does not introduce spectral distortion due to zero padding.

[0046] 4.6.5 Physical Simulation – Positive and Negative Symmetry Zero Drift The balanced ternary numerical range [-N, N] is naturally perfectly symmetrical with positive and negative values, while the two's complement [-N-1, N] has an extra negative value, breaking the symmetry. | Indicators | Ternary (6-trit, 729 levels) | Binary (8-bit, 256 levels) | |:---|:---:|:---:| | Numerical range symmetry | [-364, 364] Perfectly symmetric | [-128, 127] with an additional 0.8% negative values ​​| | Integer accumulation drift | Zero drift (±1 exact cancellation) | Slightly negative bias | | Sinusoidal function quantization average error| 0.000687 | 0.001959 | Fair Comparison Note: Based on a fair comparison of information capacity, 6-trit (information capacity log2(3)×6≈9.51 bits) corresponds to approximately 10-bit binary (2^10=1024 levels). The comparison of 6-trit vs 8-bit in the table above shows an inequality in information capacity (729 levels vs 256 levels). The above data also shows that ternary achieves better quantization accuracy with less information capacity (729<1024). If we compare the information capacity fairly (6-trit vs 10-bit), the advantage of ternary in information density still holds, and it adds the structural advantage of positive and negative symmetry, which binary does not possess at all.

[0047] 4.6.6 Search – Shallower Iteration Depth Ternary search can reduce the search space to 1 / 3 in each round, with a theoretical iteration depth of log3(n), which is about 37% shallower than the log2(n) of binary search. In actual tests on a scale of 100K, ternary search requires 27.7 comparisons, while binary search requires 29.5, saving about 6%.

[0048] 4.6.7 Comprehensive Advantage Root Cause Analysis All the advantages of the above algorithms can be attributed to the advantages of balanced ternary triple roots: 1. Naturally compatible with three-state comparison: TCMP returns three branches in a single return, eliminating the need for additional equality checks when sorting / searching; 2. Information density 1.585 times: Fewer bits are needed for the same numerical range, reducing the number of iterations and storage space; 3. Zero value ratio is about 33%: about 1 / 3 of the randomly uniformly distributed trit values ​​are zero, and the calculation of these zero trit values ​​can be automatically skipped in arithmetic operations.

[0049] | Category | Number of Files | Number of Lines | |------|:---:|------| | Embedded C++ Core Source Code | 14 | 6,756 | | Python debugging tools / testing | 40 | 12,905 | | Test output file | 7 | 482 | | Historical Backups | 3 | 4,704 | | Total active code | — | 19,661 |

[0050] In addition to the aforementioned ESP32-S3 microcontroller embodiment, this invention can also be implemented based on a Field Programmable Gate Array (FPGA) as a second embodiment. The FPGA implementation path is naturally compatible with the two-line encoding scheme of this invention—all logic is implemented on standard binary digital circuits.

[0051] FPGA Implementation Plan Overview: 1. Two-line encoding logic synthesis: The two-line encoding rule described in claim 4 is directly synthesized into FPGA lookup table (LUT) logic - each trit occupies 2 LUT input bits, and the decision logic of the ternary full adder (see pseudocode in section 3.3) can be synthesized into combinational logic circuits, with a critical path delay of no more than 5ns (on typical domestic FPGA devices).

[0052] 2. 1+3 architecture on-chip implementation: One main control unit IP core and three ALU execution unit IP cores are instantiated on a single FPGA. The IP cores are interconnected through the FPGA’s internal AXI-Stream or a custom parallel bus, replacing the ESP-NOW wireless communication implemented in ESP32-S3.

[0053] 3. Interface compatibility: The FPGA can still be connected to the tri-state switch array (GPIO input) and LED tri-state output interface (GPIO output) as described in claim 16, keeping the human-machine interaction method unchanged.

[0054] 4. Feasibility of Domestic Production: This embodiment can be implemented using domestically produced FPGA devices (such as Gowin Semiconductor GW2A series and Anlogic Technology EG4 series), combined with domestically produced EDA tools (such as Huada Jiutian), to achieve a completely independent and controllable supply chain. The process node uses mature 110nm or 55nm processes.

[0055] 5. Verification method: The FPGA implementation can be carried out through the standard process of simulation-synthesis-placement and routing-on-board verification. The test vectors of the 31 instruction sets described in claim 5 are replayed on the FPGA and the consistency is verified by comparing the test results of the ESP32-S3 implementation version item by item.

[0056] This FPGA embodiment demonstrates that the hardware implementation of the present invention is independent of a specific microcontroller or processor core—as long as the platform has standard binary digital logic capabilities, it can support a two-line encoded ternary logic layer. This further strengthens the process compatibility claim of claim 18. Beneficial effects

[0057] Compared with the prior art, the present invention has the following beneficial effects: 1. Not reliant on tri-state transistors: Complete ternary logic is implemented on standard CMOS binary transistors using two-wire encoding, and can be manufactured using any existing semiconductor process line. This fundamentally solves the core engineering obstacle of ternary computers for more than half a century—the technological prejudice that "we must wait for the advent of tri-state transistors"; 2. Information Density and Asymmetric Advantages: Each balanced ternary trit carries approximately log23 ≈ 1.585 bits of information. In sorting algorithms, this saves up to 49% of comparisons in scenarios involving duplicate values; in encryption applications, the 12-trit key space (531,441) is 129.7 times larger than the equal-length binary key space (4,096); and in prime number detection, zero trits are automatically skipped, saving 33% of modular exponentiation iterations. 3. Triple redundancy majority voting ensures reliability: It naturally utilizes the redundancy structure of the three execution units in the 1+3 architecture to achieve distributed triple redundancy fault tolerance—the momentary failure of any single execution unit does not affect the correctness of the final calculation result, and it forms a computation-security closed loop in conjunction with the four-level security defense system. 4. Infinitely Scalable Architecture: The 1+3 recursive tree architecture supports fractal expansion, with a theoretically unbounded upper limit for expansion. Actual expansion is limited only by communication bandwidth and physical space. The expansion formula for the Kth layer is N_K = (3^(K+1)-1) / 2, with each layer adding 3^K computational units. 5. Complete instruction set closed loop: The AJ series of 31 instructions covers all scenarios of operation, control, system, security and application, and has completed 405+ real machine function tests on 4 boards of hardware; 6. Built-in security capabilities: A four-level defense system provides layer-by-layer protection from the board level to the root credentials, and is linked with majority voting anomaly detection, making it suitable for security-sensitive scenarios such as military applications; 7. Distributed collaboration and fault tolerance: Multi-board ESP-NOW wireless communication enables distributed computing. Single-board failures can be automatically compensated by majority voting mechanism without affecting the correctness of global calculations. 8. True interrupt nesting: Verified the preemption capability between interrupts of different priorities (measured nesting depth ≥ 2, preemption count 1200 times / 2 seconds), laying the foundation for real-time systems; 9. Low process threshold: The architecture has no special requirements for semiconductor processes; it can be fabricated using mature processes (180nm and above) and is not affected by export controls on advanced processes. There are already FPGA implementation paths available. Industrial applicability

[0058] This invention is based on the commercially available ESP32-S3 chip and requires no custom hardware. It can be used directly in production. Chip manufacturing: Any standard CMOS foundry (TSMC, SMIC, Hua Hong, etc.) Process nodes: Mature processes such as 180nm / 130nm / 65nm are sufficient. EDA tools: Standard digital IC design flow, can use open source or domestic EDA tools. FPGA verification: Domestic FPGAs (Gowin, Anlu) can be used for pre-tape-out verification. This invention has been verified through 4-board actual testing and can be directly applied in engineering. Attached Figure Description

[0059] Appendix Figure 1 Overview of the 1+3 recursive tree architecture. The fractal structure is shown in the first layer (4 panels), the second layer (13 panels), and the third layer (40 panels). Mark the hierarchical relationship between the main master, secondary masters, and execution units. Appendix Figure 2 : Schematic diagram of the dual-line encoding scheme. Three signal waveform diagrams: the correspondence between ternary values ​​-1 / 0 / +1 and the level of line A / line B. Appendix Figure 3 Command format diagram. 10-trit instruction word structure: opcode (4trit) + target (3trit) + operand (3trit). Appendix Figure 4 Distributed execution flowchart. A complete flowchart of the process: board 0 fetches instructions → decodes → distributes instructions → calculates on each board → collects results → summarizes results. Appendix Figure 5 : Logic diagram of a full adder. Balanced ternary full adder: Logic for determining the input (a, b, carry_in) → output (sum, carry_out). Appendix Figure 6 Security defense system hierarchy diagram. Four-layer concentric circle structure: Guardian→Sentinel→Terminator→Vault. Appendix Figure 7 : Interrupt nesting waveform diagram. K② shows the timing of preemption by a high-priority ISR during the execution of a low-priority ISR in the test. Appendix Figure 8 Screenshot of actual test results. K② The actual machine output log shows nest_depth=2 and preempt_count=1200.

Claims

1. A system architecture for implementing ternary calculations based on binary hardware, characterized in that, include: The system comprises a main control unit and N execution units, where N = 3^K and K is a positive integer. The main control unit and the N execution units are connected via a communication protocol, forming a 1+N distributed computing architecture. All hardware in the system is implemented based on standard binary digital circuits, without relying on tri-state transistors or any non-standard semiconductor devices. Ternary logic states {-1, 0, +1} are mapped to binary signal pairs using a double-line encoding method, allowing standard binary transistors to perform ternary operations without modification—that is, building an independent ternary logic layer on top of the binary physical layer, achieving separation between the carrier (binary hardware) and the logic (ternary calculation). The main control unit has dual-mode operation capability—in throughput mode, it distributes operands with different ternary bits (trit) in arithmetic logic operation instructions to different execution units for parallel computation; in reliable mode, it distributes copies of the same operand with the same trit bit to all execution units for redundant computation and majority voting, as well as processing control flow instructions. Each execution unit is responsible for arithmetic and logical operations on at least one ternary bit (trit). Each trit is represented as a ternary value (-1, 0, +1) on binary hardware using the double-line encoding method. After performing a single trit operation on the received operand, the execution unit returns the trit result and carry / borrow information to the main control unit. The 1+N architecture achieves elastic scaling of computing power through recursive expansion—that is, any execution unit can be further upgraded to a secondary main control unit with three subordinate execution units. The three execution units under each secondary main control unit naturally form a triple redundancy group, forming a multi-layer distributed computing structure of 1+3+9+…+3^K.

2. A method for implementing ternary calculation based on binary hardware, applied to the system as described in claim 1, characterized in that, Includes the following steps: (a) Encoding step: Each ternary value (-1, 0, +1) is mapped to a level combination of two binary signal lines (line A, line B), so that ternary logic operations are converted into binary signed integer operations, thereby implementing ternary arithmetic logic on standard binary digital circuits without the need for tri-state transistors; (b) Instruction fetch and decoding step: The main control unit fetches the instruction from memory and parses the opcode to determine the instruction type; (c) Distribution step: If the instruction is an arithmetic logic operation, the main control unit decomposes the operand into trit bits, encapsulates the operand of each trit bit into a message frame, and sends it to the corresponding execution unit through the communication protocol; (d) Parallel computing step: Each execution unit independently executes the ternary arithmetic logic operation of a single trit, producing the result trit and carry / borrow information; (e) Majority voting step: The main control unit sends the same operand to at least three execution units with the same trit bit, receives three independent operation results, and determines the final correct value of the trit bit through a majority voting mechanism; (f) Summarization step: The main control unit concatenates the trit results of each trit bit after majority voting into a complete operation result, and handles cross-bit carry / borrow propagation; (g) Write-back step: Write the summarized operation result back to memory or output it to a peripheral device.

3. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the following functional modules in the system as described in claim 1: instruction decoding module, operand trit decomposition and distribution module, single trit ternary arithmetic logic operation module, multi-board majority voting module, carry chain propagation module, and multi-level process scheduling module.

4. The system as claimed in claim 1 or the method as claimed in claim 2, characterized in that, The dual-line encoding method is as follows: Two binary signal lines (line A and line B) are used to encode ternary values. The encoding rule is as follows: Through the above encoding rule, complete ternary logic operations can be implemented on a standard CMOS binary transistor without relying on a tri-state transistor.

5. The system as claimed in claim 1 or the method as claimed in claim 2, characterized in that, It includes a complete set of balanced ternary instructions, which includes: (a) Arithmetic operation instructions: ternary addition (TADD), ternary subtraction (TSUB), ternary multiplication (TMUL), and ternary division (TDIV), wherein the arithmetic operations are implemented based on a balanced ternary full adder, which processes inputs a, b, and carry_in ∈ {-1, 0, +1}, and outputs sum ∈ {-1, 0, +1} and carry_out ∈ {-1, 0, +1}; (b) Comparison instructions (TCMP): outputting tri-state flags—negative value (-1) indicates less than, zero (0) indicates equal to, and positive value (+1) indicates greater than; (c) Control flow instructions: unconditional jump (JMP), conditional jump based on tri-state flags (JZ zero jump, JP positive jump, JN negative jump, JNZ non-zero jump), subroutine call and return (CALL / RET); (d) System call instructions (SWI): These are used by software interrupts to enter the operating system kernel from a user program. Service numbers include process yield (YIELD), print output (PRINT), sleep (SLEEP), program exit (EXIT), spinlock acquisition (LOCK), and spinlock release (UNLOCK).

6. The system as claimed in claim 1 or the method as claimed in claim 2, characterized in that, The collaborative execution method of the main control unit in reliable mode specifically includes: (a) After fetching the instruction, the main control unit identifies the instruction opcode type; (b) If it is an arithmetic logic operation instruction and in reliable mode, the main control unit sends copies of the same operands to all three execution units for each trit bit to be calculated. Each execution unit independently calculates the operation result and carry / borrow information for that trit bit and returns the result to the main control unit. The calculation order in reliable mode is to execute each trit bit sequentially from the least significant trit bit to the most significant trit bit, with the calculation of the next bit depending on the carry output after the majority vote of the previous bit; (c) The main control unit performs a majority vote on the three operation results received for the same trit bit: if at least two of the three results are consistent, the majority consistent value is the final result of that trit bit; if the three results are different (-1, 0, +1 respectively), exception handling is triggered—including redistributing the calculation or marking the trit bit as untrustworthy; (d) For carry / borrow information, a majority vote is performed simultaneously: if at least two of the three carry values ​​are the same, the majority value is used as the carry to be passed to the next bit; if the three carry values ​​are different, the carry is conservatively set to zero and exception handling is triggered; (e) If it is in throughput mode or a control instruction (jump, call, return), the main control unit handles it itself or distributes it by bit slice, without triggering the majority vote process.

7. The system or method as described in claim 6, characterized in that, The specific process for handling anomalies is as follows: (a) When the three calculation results of the same trit bit are different, the main control unit records the anomaly event and the corresponding trit bit position and execution unit identifier; (b) The main control unit resends the operands to each execution unit corresponding to the trit bit, and each execution unit re-executes the calculation and returns the result; (c) If the result is consistent after retry, the result is adopted and the anomaly record is cleared; if the three results are still different after retry, the execution unit is marked as "suspicious", the calculation of the trit bit is downgraded to local calculation by the main control unit, and the information of the suspicious execution unit is reported to the security defense system.

8. The system as claimed in claim 1, characterized in that, It includes a multi-layered security defense system: Layer 1 (board-level protection layer): monitors the online status of each execution unit, detects offline / abnormal units through a heartbeat mechanism, automatically attempts to restore or marks them as offline, and counts the anomaly count and error rate of each unit; Layer 2 (sentinel layer): continuously monitors the system behavior pattern, detects abnormal patterns including continuous illegal opcodes, abnormal state machine transitions, and persistent inconsistencies in majority voting of execution units, and triggers tiered alarms; The third layer (remote termination layer): The main control unit retains the authority to remotely force termination and restart any execution unit. Upon detecting the alarm or receiving a manual termination command, it can remotely terminate the target execution unit and send a restart command. The fourth layer (root vault layer): The system root credentials are stored in the on-chip eFuse secure area or a dedicated flash encrypted partition. Access requires verification through the hardware secure boot chain and multi-factor authentication. Unauthorized access triggers hardware-level automatic erasure. The root credentials and normal computing tasks are logically isolated through a memory protection unit (MPU / PMP). The second layer, the sentinel layer, is linked to the majority voting mechanism described in claim 6. When an execution unit is marked as "suspicious" and the accumulated suspicious events exceed a preset threshold, the sentinel layer automatically upgrades the security threat level and notifies the third layer, the remote termination layer.

9. The system as described in claim 1, wherein the recursive expansion method is as follows: When the system needs to expand its computing power, the original execution unit is upgraded to a secondary master control unit. The secondary master control unit manages three subordinate execution units, forming a 1+3+9 expansion architecture. The three execution units under each secondary master control unit naturally constitute a triple redundancy group, which can simultaneously achieve bit slice throughput and triple redundancy. After expansion, the original main master control unit only communicates with the secondary master control unit. The secondary master control unit is responsible for coordinating the distribution of computing tasks, majority voting, and result collection of its subordinate execution units. The main master control unit does not increase its communication burden or voting computation due to the expansion. This expansion method can be recursively applied at any level. The total number of computing units after the Kth level expansion is (3^(K+1)-1) / 2.

10. The system as claimed in claim 1, characterized in that, The communication protocol uses direct frame transmission at the MAC layer. The message frame includes: message type field, board identifier field, opcode field, operand trit value field, sequence number field, result trit value field, flag trit value field, and reserved field.

11. The dual-line encoding as described in claim 4, characterized in that, The implementation of balanced ternary arithmetic on binary hardware is as follows: ternary addition / subtraction / multiplication is converted into binary signed integer operations. The results of the operations are then normalized to map back to the range {-1, 0, +1}: When the sum ∈ [-3, +3], if sum ≥ +2, the carry-out is +1 and the result is sum-3; if sum ∈ [-1, +1], the carry-out is 0 and the result is sum; if sum ≤ -2, the carry-out is -1 and the result is sum+3.

12. The instruction set as described in claim 5, characterized in that, Each instruction consists of 10 balanced ternary bits (trit), of which the opcode occupies 4 trits, the target / result address occupies 3 trits, and the operand / immediate value occupies 3 trits; the encoding space of the instruction set can accommodate 3^4=81 opcodes, 3^3=27 address units, and 3^3=27 immediate value values.

13. The security defense system as described in claim 8, characterized in that, The parameters of the heartbeat mechanism are set as follows: the heartbeat sending interval is 5 seconds, the response timeout time does not exceed 60% of the heartbeat interval, and the corresponding execution unit is determined to be offline after 3 consecutive lost heartbeat responses. After being determined to be offline, the corresponding execution unit is automatically removed from the online registry and an attempt is made to re-establish the communication connection.

14. The system as claimed in claim 1, characterized in that, The system further includes an interrupt nesting mechanism: it supports true priority preemption between interrupts of different priorities, and higher priority interrupts can occur and preempt CPU execution during the execution of lower priority interrupt service routines. The preemption count and nesting depth can be recorded by the system in real time and reported through the debugging interface. The interrupt nesting mechanism supports at least 2 levels of nesting depth and at least 1 preemption frequency per millisecond.

15. The interrupt nesting mechanism as described in claim 14, characterized in that, Continuous interrupt triggering is achieved by directly manipulating the hardware timer register: at the end of the interrupt service routine, the alarm enable bit (alarm_en) and autoreload bit (autoreload) are directly written to the timer hardware register to bypass the problem that the driver layer's autoreload may fail due to the hardware self-clearing after the alarm is triggered, thus ensuring that the interrupt is continuously and periodically triggered.

16. The system as claimed in claim 1, characterized in that: The input interface is a tri-state switch array—each pair of switches consists of a left switch and a right switch, and the ternary value is encoded by pressing the combination: This encoding method ensures that any switch with poor contact or floating state is encoded as a valid value, and no uncertain output is generated; The output interface expresses the ternary operation result through three states of LED beads: LED on indicates a positive value (+1), LED off indicates a zero value (0), and LED flashing indicates a negative value (-1).

17. The system as claimed in claim 1, characterized in that, The process control block (PCB) data structure is used to manage the concurrent execution of multiple programs. The PCB includes: program counter value, stack pointer value, accumulator value, flag register value, stack storage area, memory protection boundary - including program segment base address and limit, data segment base address and limit, program status fields - including four states: ready / running / blocked / terminated, remaining time slice for sleep, and statistics.

18. The system as claimed in claim 1, characterized in that, The entire implementation of the system is based on commercially available standard CMOS binary chips—including but not limited to ESP32 series microcontrollers, RISC-V series microcontrollers, or application-specific integrated circuits manufactured based on standard CMOS processes. The dual-line encoded logic layer is built entirely on binary digital logic circuits and does not rely on tri-state transistor processes, ferrite cores, or any special semiconductor physical devices.

19. The computer-readable storage medium as claimed in claim 3, characterized in that, The computer program contains a complete set of balanced ternary instructions, including: ternary arithmetic operation instructions (addition, subtraction, multiplication, division), tri-state comparison instructions, tri-state conditional jump instructions (zero jump, positive jump, negative jump, non-zero jump), subroutine call and return instructions, system call instructions, stack operation instructions, and tri-state input / output instructions; the instruction set contains 31 instructions, each instruction is a 10-trit fixed-length code, and the opcode occupies 4 trits.

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