Radar moving target indication and detection cascade processing method and system based on URAM

Abstract

The application discloses a radar moving target display and detection cascade processing method and system based on URAM, and the method comprises the following steps: constructing a URAM cascade storage matrix; receiving radar pulse compression data and performing inter-pulse difference processing to obtain MTI result data; when the URAM storage area is in a writing state, writing each MTI result data in the current CPI into the current URAM storage area; after the distance-Doppler data matrix formed by each MTI result data in the current CPI is written into the current URAM storage area, switching the current URAM storage area to a reading state, and switching another URAM storage area to a writing state; when any URAM storage area is in the reading state, reading the corresponding distance-Doppler data matrix, and obtaining the corresponding processing result through moving target detection processing. The application can meet the large-capacity and high real-time data processing requirements in the moving target display and detection cascade processing.

Description

Technical Field

[0001] This invention relates to the field of radar signal processing technology, specifically to a URAM-based cascaded processing method and system for radar moving target display and detection. Background Technology

[0002] The on-chip memory resources of an FPGA mainly include flip-flop register files, distributed RAM, and block RAM. Among them, flip-flop register files are typically used for sequential logic such as pipelined registers, status registers, and small-width shift registers; distributed RAM is implemented based on lookup tables and is suitable for small-capacity data storage; block RAM, as a commonly used large-capacity on-chip cache resource in FPGAs, has advantages such as stable operating timing, high bandwidth, easy expansion, and no logic resource consumption, but its total capacity is usually only tens of Mb to tens of Mb, which is difficult to meet the storage requirements of large-scale radar signal processing scenarios.

[0003] In radar moving target detection (MTD) processing, range-Doppler data needs to be completely stored and matrix transposed within a single coherent processing time. Taking a real-world application system as an example, each sub-beam includes at most 2048 sampling points in the range dimension and at most 128 accumulations in the Doppler dimension. Furthermore, each sub-beam needs to be further subdivided into sum beam, elevation difference beam, and azimuth difference beam. With 16 bits each for the I and Q channels of single-point complex data, the storage capacity for MTD data corresponding to the three sub-beam sets can reach 72 Mb. Due to the real-time nature of radar signal processing, when data from the previous coherent processing time is written, MTD data still needs to be processed. Therefore, at least twice the storage capacity is required for ping-pong caching, resulting in an on-chip storage capacity requirement of 144 Mb. The block RAM resources of common FPGA chips are insufficient to meet this capacity requirement.

[0004] To address the issue of insufficient storage capacity, existing solutions typically employ external DDR memory. While DDR offers gigabyte-level storage capacity, it requires access through an FPGA hard-core controller, resulting in unpredictable access latency. For high-speed, real-time, and time-sensitive applications such as radar signal processing, external DDR, although providing substantial storage capacity, struggles to meet the deterministic low-latency requirements of real-time storage, transposition, and retrieval of range-Doppler data matrices. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a radar moving target display and detection cascade processing method and system based on URAM, so as to reduce the dependence on external memory, avoid the impact of uncertain external memory access delay on radar real-time signal processing, and meet the requirements of large-capacity and high real-time data processing in the moving target display and moving target detection cascade processing.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A URAM-based cascaded processing method for radar moving target display and detection, applied to FPGA, includes the following steps: S1, Construct a URAM cascaded storage matrix on the FPGA chip, which consists of multiple URAMs cascaded together, and the URAM cascaded storage matrix includes two URAM storage areas that are read and written alternately; S2, receive radar pulse compression data after pulse compression of radar signal, and perform inter-pulse differential processing on the radar pulse compression data to obtain moving target display processing result data output in range dimension order; S3, when one of the URAM storage areas is in the write state, write the moving target display processing result data of each moving target within the current coherent processing time into the current URAM storage area according to the distance unit position, speed unit position and URAM cascade position corresponding to the moving target display processing result data; S4. After the current URAM storage area is filled with the distance-Doppler data matrix formed by the display processing results data of each moving target within the current coherent processing time, the current URAM storage area is switched to the read state, and another URAM storage area is switched to the write state, so as to alternately execute the writing of the display processing results data of the moving target within the current coherent processing time and the reading of the display processing results data of the moving target within the previous coherent processing time between the two URAM storage areas. S5: When any URAM storage area is in read state, read the corresponding range-Doppler data matrix and obtain the corresponding processing result through moving target detection processing.

[0007] Further, in step S1, a URAM cascaded storage matrix consisting of multiple cascaded URAMs is constructed on the FPGA chip, including: The address bus, data bus, and status bus of adjacent URAMs are connected to form a URAM cascade structure; cascade order parameters, cascade mask parameters, and cascade address parameters are configured for each URAM in the URAM cascade structure. The concatenation sequence parameter is used to indicate the first, middle, or last bit of the corresponding URAM in the concatenation structure. The concatenation mask parameter is used to indicate the number of concatenated URAMs and the valid bits of the URAM index bits in the address bus. The concatenation address parameter is used to indicate the address index value of the corresponding URAM in the URAM concatenation structure and is used to match with the externally input address control signal to determine the data to be written to the corresponding URAM.

[0008] Further, in step S2, the inter-pulse differential processing includes: The radar pulse compression data is received in a time-division multiplexing manner within a coherent processing time. The radar pulse compression data output first is cached in the FPGA on-chip BRAM. When subsequent radar pulse compression data is input, the cached radar pulse compression data is read from the FPGA on-chip BRAM. The data of the same range cell in the subsequent radar pulse compression data and the cached radar pulse compression data are differentially processed to obtain the moving target display processing result data.

[0009] Furthermore, the inter-pulse differential processing is either dual-pulse cancellation processing or triple-pulse cancellation processing; when the inter-pulse differential processing is dual-pulse cancellation processing, N-1 sets of range dimension data are output within one coherent processing time; when the inter-pulse differential processing is triple-pulse cancellation processing, N-2 sets of range dimension data are output within one coherent processing time, where N is the number of radar pulse compression data sets output in a time-division manner within one coherent processing time; Specifically, when the inter-pulse differential processing employs double-pulse cancellation processing or triple-pulse cancellation processing, resulting in the number of speed units actually input to the URAM cascaded storage matrix being less than the number of speed units required for moving target detection processing, zero values ​​are further written to the URAM addresses corresponding to the unwritten speed units to complete the zero-padding operation for subsequent moving target detection processing.

[0010] Further, step S3 includes: Set a distance unit counter, a speed unit counter, and a URAM counter; wherein, the distance unit counter is used to indicate the number of distance units that have been written to the URAM, the speed unit counter is used to indicate the number of speed units that have been written to the URAM, and the URAM counter is used to indicate the specific URAM label in the URAM cascaded storage matrix where the current data is written; When the current URAM storage area is in the write state, the received moving target display processing result data corresponding to the adjacent distance unit is written to the high and low bits of the URAM respectively, and the distance unit counter is incremented. When the distance unit counter reaches the number of distance units that can be written to the current URAM, it is determined that the data writing of the current URAM is complete, the URAM counter is automatically switched to the next cascaded URAM, and the internal address of the URAM is reassigned to zero; When the distance unit counter reaches the total number of distance units corresponding to the moving target display processing result data of the current speed unit, it is determined that the distance unit data under the current speed unit has been written, the speed unit counter is incremented, and the distance unit counter and URAM counter are cleared to receive the moving target display processing result data corresponding to the next speed unit.

[0011] Furthermore, step S3 also includes repeatedly writing distance unit data under each velocity unit; In step S4, the condition for determining that the current URAM storage area is full is: when the speed unit counter reaches the total number of speed units within a coherent processing time, it is determined that the multiple sets of moving target display processing result data within the current coherent processing time have been written. The range-Doppler data matrix is ​​a matrix formed within the current URAM storage area, which is obtained by arranging the range dimension data and the velocity dimension data.

[0012] Further, step S5 includes: When any URAM storage area is in read state, a URAM read address is generated. The URAM read address includes a URAM index address segment for determining the accessed URAM in multiple cascaded URAMs and a URAM internal address segment for determining the internal storage cell of the accessed URAM. According to a preset read address order, the range-Doppler data matrix in the URAM storage area is accessed sequentially according to the URAM index address segment and the URAM internal address segment. Multiple velocity cell data under the same range cell are read one after another, and a velocity-dimensional fast Fourier transform operation is performed on the read multiple velocity cell data under the same range cell to obtain the moving target detection processing result of the corresponding range cell.

[0013] Furthermore, in step S5, data from the same range unit but different velocity units in the range-Doppler data matrix are combined into a moving target detection operation group. The number of moving target detection operation groups that a single URAM can store is calculated based on the quotient of the total number of sampling points that a single URAM can store and the number of accumulated points within a coherent processing time. The number of URAMs cascaded for range-Doppler data storage within a coherent processing time is calculated based on the quotient of the number of range dimension points corresponding to the working waveform and the number of moving target detection operation groups that a single URAM can store.

[0014] A URAM-based radar moving target display and detection cascade processing system includes an interconnected microprocessor and a memory, wherein the microprocessor is programmed or configured to execute the steps of the URAM-based radar moving target display and detection cascade processing method.

[0015] A computer-readable storage medium storing a computer program / instructions programmed or configured to execute, via a processor, the steps of a URAM-based radar moving target display and detection cascade processing method.

[0016] Compared with the prior art, the advantages of the present invention are as follows: This invention constructs a cascaded URAM storage matrix on an FPGA chip to cache range-Doppler data within the coherent processing time. This fully utilizes the large storage capacity of URAM, avoiding the impact of insufficient BRAM capacity and external DDR access latency on real-time radar processing. By setting up two URAM storage areas for alternating read and write operations, ping-pong processing of data at different coherent processing times can be achieved, avoiding data overwriting and improving the real-time performance of continuous processing. By performing inter-pulse differential processing on radar pulse compression data and writing it into the URAM storage area according to the range and velocity dimensions, a range-Doppler data matrix can be formed, providing a data foundation for subsequent moving target detection. By performing moving target detection after reading the range-Doppler data matrix from the URAM storage area, the cascaded URAM storage matrix can simultaneously possess data caching and matrix transpose reading functions, improving data access efficiency. This invention can realize large-capacity on-chip caching, real-time ping-pong processing, and efficient matrix transpose reading in the radar moving target display and detection process, and is suitable for high-speed, time-sensitive radar signal processing scenarios. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the implementation of a URAM-based cascaded processing method for radar moving target display and detection in a specific application embodiment.

[0018] Figure 2 This is a schematic diagram illustrating an example of a non-cascaded URAM interface (left half) and a cascaded URAM interface (right half) in a specific application embodiment.

[0019] Figure 3 This is a schematic diagram of a 3×3 cascaded matrix array composed of multiple URAMs in a specific application embodiment.

[0020] Figure 4 This is a schematic diagram of the range-Doppler data matrix structure used in moving target detection processing in a specific application embodiment.

[0021] Figure 5 This is a schematic diagram of the ping-pong storage process for moving target detection in a specific application embodiment.

[0022] Figure 6 This is a flowchart of the dynamic target display processing in a specific application embodiment.

[0023] Figure 7 This is a schematic diagram illustrating the storage and writing logic of the distance-Doppler data matrix in URAM in a specific application embodiment.

[0024] Figure 8 This is a schematic diagram of the state transitions for FPGA-controlled URAM write operations in a specific application embodiment.

[0025] Figure 9This is a data flow diagram for implementing moving target detection operations based on URAM in a specific application embodiment. Detailed Implementation

[0026] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0027] Generally, the on-chip memory resources of an FPGA include flip-flop register files, distributed random access memory (DRAM), and block random access memory (BRAM). Flip-flop register files are implemented based on flip-flops, with each flip-flop natively supporting 1 bit of data storage. Within an FPGA, they are typically used for pipeline registers, status registers, and small-width shift registers, forming the basis for sequential logic implementation. DRAM is implemented using lookup table multiplexing and can be natively configured as a 64×1-bit single-port random access memory. Multiple lookup tables can be cascaded to expand bit width and depth, but the data capacity of DRAM is relatively small, typically in the kilobyte (KB) range. BRAM is an independent, dedicated static random access memory (SRAM) hard core, serving as the core carrier for large-capacity data caching within the FPGA. It features stable timing, easy convergence, high bandwidth, strong scalability, and does not consume logic resources. The total on-chip data capacity can typically reach tens of megabytes (MB), meeting the storage requirements of most scenarios.

[0028] With the increase in FPGA operating clock frequency and the number of high-speed interfaces, radar signal processing systems place higher demands on on-chip storage capacity and real-time read / write capabilities. Even if the block random access memory (BRAM) can achieve a total data storage capacity of tens of megabytes (MB), it may still not meet the system requirements in specific radar moving target detection processing scenarios. Taking the radar system corresponding to this embodiment as an example, the signal processing of three sub-beams needs to be completed within one radar coherent processing time. Each sub-beam has a maximum of 2048 sampling points in the range dimension and a maximum of 128 accumulations in the Doppler dimension. In addition, each sub-beam uses sum-difference amplitude angle measurement in both the elevation and azimuth dimensions, so each sub-beam needs to be further subdivided into a sum beam, an elevation difference beam, and an azimuth difference beam.

[0029] Since the radar system needs to fully store 2048×128 points of data and transpose the range-Doppler data matrix to complete moving target detection processing, and uses 16 bits each of the I-channel and Q-channel data of the single-point complex data for calculation, the moving target detection data storage capacity of a single sub-beam set is: .

[0030] The data storage required for the three sub-beamsets is: .

[0031] Furthermore, due to the real-time requirements of radar signal processing, after storing the range-Doppler data from the previous coherent processing time, the data for the next coherent processing time begins to be updated and output, while the moving target detection module is still processing the data from the previous coherent processing time. Therefore, the FPGA needs to allocate at least twice the amount of data for ping-pong processing, meaning that at least 144Mb of on-chip storage capacity is required. Common Xilinx Virtex7 series chips, such as the XC7VX690T, have 52.92Mb of block random access memory (BRAM) resources; for the XCVU13P chip using the Ultra Scale+ architecture, its BRAM resources are expanded to 94.5Mb. Based on the above data volume analysis, storing data solely through BRAM is insufficient to meet the storage requirements of the radar system corresponding to this embodiment.

[0032] In some implementations, to address the issue of insufficient storage capacity, external Double Data Rate (DDR) synchronous dynamic random access memory is typically used. DDR's advantage over BRAM lies in its storage capacity reaching the gigabyte level; however, it requires access through the FPGA's hard-core controller (MIG IP core), resulting in non-deterministic access latency. Therefore, for high-speed, time-sensitive systems like radar signal processing, while DDR offers higher data capacity, it struggles to meet stringent real-time requirements.

[0033] This embodiment provides a URAM-based cascaded processing method for radar moving target display and detection, applied to an FPGA. This method utilizes the large capacity, cascaded capability, and low-latency read / write characteristics of on-chip URAM in the FPGA, combined with BRAM to complete the moving target display processing of radar pulse compression data, and uses a cascaded URAM storage matrix to complete the storage, transpose reading, and moving target detection processing of the range-Doppler data matrix.

[0034] like Figure 1 As shown, the URAM-based radar moving target display and detection cascade processing method of this embodiment includes the following steps: S1, Construct a URAM cascaded storage matrix on the FPGA chip, which consists of multiple URAMs cascaded together, and the URAM cascaded storage matrix includes two URAM storage areas that are read and written alternately; S2, receive radar pulse compression data after pulse compression of radar signal, and perform inter-pulse differential processing on the radar pulse compression data to obtain moving target display processing result data output in range dimension order; S3, when one of the URAM storage areas is in the write state, write the moving target display processing result data of each moving target within the current coherent processing time into the current URAM storage area according to the distance unit position, speed unit position and URAM cascade position corresponding to the moving target display processing result data; S4. After the current URAM storage area is filled with the distance-Doppler data matrix formed by the display processing results data of each moving target within the current coherent processing time, the current URAM storage area is switched to the read state, and another URAM storage area is switched to the write state, so as to alternately execute the writing of the display processing results data of the moving target within the current coherent processing time and the reading of the display processing results data of the moving target within the previous coherent processing time between the two URAM storage areas. S5: When any URAM storage area is in read state, read the corresponding range-Doppler data matrix and obtain the corresponding processing result through moving target detection processing.

[0035] In specific application examples, URAM is a new type of high-capacity, dedicated, high-density on-chip memory hard core (hereinafter referred to as URAM) introduced by Xilinx in its Ultra Scale+ series FPGAs / SoCs. It provides the hardware foundation for implementing a memory solution between BRAM and DDR. With its large data storage capacity, built-in cascaded wiring resources, and low-latency read / write mode, URAM can build larger-dimensional memory arrays, making it very suitable for on-chip storage and pipelined processing of two-dimensional data in radar signal processing.

[0036] As a novel on-chip memory resource within an FPGA, URAM's main characteristics include: a single URAM has a data storage capacity of 288Kb; URAM is a dual-port, single-clock synchronous memory with a fixed storage width of 72 bits and a storage depth of 4096; both ports can address the entire storage space, but each port can only complete one read or write operation per clock cycle; multiple URAMs can be cascaded to form a larger storage area (up to 360Mb on the VU13P chip), and have dedicated wiring resources; with proper processing, cascading of URAMs will not cause timing loss. Therefore, this implementation uses a combination of URAM and BRAM to achieve radar moving target detection processing, where URAM is responsible for storing, transposing, and retrieving radar range-Doppler data, and BRAM is responsible for performing velocity-dimensional fast Fourier transform operations.

[0037] URAM input / output interface implementations, such as Figure 2As shown, the interfaces include the operating clock CLK, sleep mode control SLEEP, address bus ADDR, read / write enable EN, read / write control RDB_WR, byte enable BWE, input data bus DIN, reset terminal RST, output data bus DOUT, and read access status RDACCESS. The specific meanings of the corresponding interfaces are shown in Table 1 below (Table 1 only lists the interfaces used in this system): Table 1 URAM Input / Output Interface Description

[0038] In this embodiment, step S1 involves constructing a URAM cascaded storage matrix on the FPGA chip, consisting of multiple cascaded URAMs. This includes connecting the address bus, data bus, and status bus of adjacent URAMs to form a URAM cascaded structure; configuring cascaded order parameters, cascaded mask parameters, and cascaded address parameters for each URAM in the cascaded structure. The cascaded order parameters indicate the first, middle, or last bit of the corresponding URAM in the cascaded structure; the cascaded mask parameters indicate the number of cascaded URAMs and the valid bits of the URAM index bits in the address bus; and the cascaded address parameters indicate the address index value of the corresponding URAM in the cascaded structure and are used to match with externally input address control signals to determine which URAM is written to the corresponding URAM.

[0039] In specific application embodiments, when multiple URAMs are cascaded, adjacent URAMs simply connect their address buses, data buses, and status buses together (corresponding to...). Figure 2 The CAS_IN and CAS_OUT interfaces). The interface configuration details in URAM cascading mode are shown in Table 2 below: Table 2 Interface Configuration Description in URAM Cascading Mode Interface Name illustrate CASCADE_ORDER Used to indicate the URAM cascading order: NONE: Indicates that the URAM is not in cascading mode. FIRST: Indicates that the URAM is at the beginning of the cascade. MIDDLE: Indicates that the URAM is in the middle of the cascade. LAST: Indicates that the URAM is at the end of the cascade. SELF_MASK Used to indicate the number of URAMs cascaded and the valid bits of ADDR[22:12]. 11'h7ff: Non-cascaded mode, ADDR[22:12] invalid. 11'h7fe: Up to 2 URAMs cascaded, ADDR[22:13] invalid. 11'h7fc: Up to 4 URAMs cascaded, ADDR[22:14] invalid. 11'h7f8: Up to 8 URAMs cascaded, ADDR[22:15] invalid. And so on. SELF_ADDR Used to indicate the address index value of a specific URAM in a URAM cascade.

[0040] In one specific example, multiple URAMs can be cascaded to form a memory array. For example... Figure 3As shown, in the 3×3 cascaded matrix, each column consists of three URAMs vertically cascaded. The cascade order parameter CASCADE_ORDER is set to FIRST, MIDDLE, and LAST modes according to the cascade order. The entire matrix uses a total of nine URAMs. The cascade mask parameter SELF_MASK is set to 7F0 to make the corresponding address bits ADDR[15:12] in the address bus valid. The row and column positions of the URAMs in the matrix are indicated by the pre-set cascade address parameter SELF_ADDR. The high 2 bits of the address bits can be used to represent the column position, and the low 2 bits can be used to represent the row position. The externally input address control signal ADDR is matched with the cascade mask parameter SELF_MASK to determine the data to be written into the corresponding URAM.

[0041] MTD (Moving Target Detection) essentially uses a high-performance FIR filter bank to bandpass filter the slow-time dimension data of radar echoes, thereby distinguishing echoes of different frequency components. Although MTD itself does not have clutter suppression capabilities, by distinguishing echo signals of different spectra, it can indirectly suppress clutter by not outputting data from the zero-Doppler channel. FFT is the simplest method to implement MTD. It forms a Doppler filter bank by performing FFT operations on the slow-time dimension data, and estimates the target velocity by determining the Doppler gate the target falls into. The advantage of this method is its simplicity and ease of implementation. When the pulse repetition frequency remains constant, the more times the pulses are accumulated, the higher the velocity measurement accuracy, but at the same time, it consumes a lot of time and BRAM resources. The MTD input data format is defined as follows:

[0042] Where N represents the number of coherent accumulation pulses within one coherent processing time (CPI), and M represents the number of range cells within each pulse repetition period (PRT). After pulse compression, the radar signal outputs M data points in the fast time dimension, and is continuously output N times in the slow time dimension within one coherent processing time. The fast time dimension data is arranged in rows, while the slow time dimension data is arranged in columns, ultimately forming a sequence such as... Figure 4 The diagram shows an N×M distance-Doppler data matrix. Moving target detection processing involves reading the data within the matrix along the slow time dimension, and then sequentially reading out N data points from each fast time dimension for processing (e.g., performing FFT operations).

[0043] Because moving target detection can only be performed after the range-Doppler matrix is ​​full, but the fast time dimension data for the next coherent processing time enters the module before all the data in the matrix has been processed, without ping-pong processing, the fast time dimension data will overwrite the data from the previous coherent processing time when stored row by row. Therefore, ping-pong processing is required for storing the range-Doppler data matrix. A diagram illustrating ping-pong processing is shown below. Figure 5 As shown. Specifically, the data from the first coherent processing time is stored in the first URAM storage area. Once it is full, the data in the first URAM (RAM A) storage area can be read out for moving target detection calculations. At this time, the data from the second coherent processing time is stored in the second URAM (RAM B) storage area. Before the data in the second URAM storage area is full, the data read out of the first URAM storage area must complete the FFT operation. When the data from the third coherent processing time arrives, it is stored back in the first URAM storage area, and the data in the second URAM storage area is used for FFT operations, and so on. Taking the processing requirements of this system as an example, the total required data capacity is:

[0044] The FPGA chip used in this system is Xilinx-XCVU13P. Since the on-chip BRAM alone cannot store these data, a combination of BRAM and URAM is required to complete the MTD operation.

[0045] It should be noted that a URAM storage area is only allowed to switch to write mode after the data reading in the previous coherent processing time is completed, in order to prevent another URAM storage area from being overwritten before it has been read.

[0046] In this embodiment, step S2 involves receiving radar pulse compression data after pulse compression of the radar signal, and performing inter-pulse differential processing on the radar pulse compression data to obtain moving target indication processing result data output in range dimension order. Generally, moving target detection (MTD) is used to process pulse-compressed data. However, in the signal processing of pulse Doppler radar, moving target indication processing (MTI) is usually added before moving target detection to suppress static clutter or low-speed moving targets. The moving target indication filter can be implemented using a delay line canceller: by performing inter-pulse subtraction processing on the echo, the fixed clutter components in the echo signal are canceled, while the target signal, due to its movement, usually does not have its phase change canceled. This cancels out components such as static clutter while retaining the signal of the moving target.

[0047] In this embodiment, in step S2, as follows: Figure 6As shown, the inter-pulse differential processing includes: receiving time-division multiplexing radar pulse compression data within a coherent processing time, buffering the first-output radar pulse compression data in the FPGA on-chip BRAM; when subsequent radar pulse compression data is input, reading the buffered radar pulse compression data from the FPGA on-chip BRAM, and performing differential processing on the data of the same range unit in the subsequent radar pulse compression data and the buffered radar pulse compression data to obtain the moving target display processing result data.

[0048] In step S2, the inter-pulse differential processing is either double-pulse cancellation processing or triple-pulse cancellation processing. When the inter-pulse differential processing is double-pulse cancellation processing, N-1 sets of range dimension data are output within one coherent processing time. When the inter-pulse differential processing is triple-pulse cancellation processing, N-2 sets of range dimension data are output within one coherent processing time, where N is the number of radar pulse compression data sets output in a time-division manner within one coherent processing time. Specifically, when the inter-pulse differential processing uses double-pulse cancellation processing or triple-pulse cancellation processing such that the number of velocity units actually input to the URAM cascaded storage matrix is ​​less than the number of velocity units required for moving target detection processing, zero values ​​are further written to the URAM addresses corresponding to the unwritten velocity units to complete the zero-padding operation for subsequent moving target detection processing.

[0049] Specifically, moving target display (MTI) processing essentially involves performing inter-pulse differential operations on the pulse compression signal's range cell data. Since the pulse compression results within a coherent processing time are output in a time-division multiplexing manner, the pulse compression results of the previous frame need to be buffered in a BRAM. Then, when the pulse compression results of the next frame are input, the buffered pulse compression results are read out and differentially processed to obtain the final MTI processing result data. Therefore, if there are N sets of pulse compression data within the coherent processing time, MTI will output N-1 sets of range dimension data under double-pulse cancellation and N-2 sets of range dimension data under triple-pulse cancellation. MTI processing can be implemented using BRAM.

[0050] In this embodiment, in step S3, when one of the URAM storage areas is in a write state, the moving target display processing result data within the current coherent processing time is written into the current URAM storage area according to the distance unit position, velocity unit position, and URAM cascade position corresponding to the moving target display processing result data.

[0051] Specifically, the URAM cascade position determines the value of the high 11 bits [22:12] of the URAM write address, meaning that with four URAMs cascaded, the URAM address can be from 0x0000 to 0x0004; the distance unit and the speed unit together determine the value of the low 12 bits [11:0] of the URAM write address: such as Figure 4As shown, N sets of slow time dimension data of the same fast time dimension are sequentially written to different addresses of the same URAM, and the address changes from 0 to N-1; the address of the next N sets of slow time dimension data of the fast time dimension is written to from N to 2N-1; when a URAM is full of data, it switches to the next URAM and continues to write according to the rules.

[0052] like Figure 7 As shown, the moving target display processing results are first arranged according to the fast time dimension (range dimension), and then according to the slow time dimension (velocity dimension), while the moving target detection processing reads and calculates according to the velocity dimension. By utilizing the cascading function of URAM, a range-Doppler storage matrix can be constructed, and the URAM cascading addresses can be planned, thus enabling the function of storing and then transposing the input data for retrieval.

[0053] Same distance unit Different speed units The data constitutes an MTD operation group. Therefore, the maximum number of MTD operation groups that a single URAM can store is calculated based on the quotient of the total number of sampling points that a single URAM can store and the number of accumulated points within a coherent processing time. The calculation expression is:

[0054] Where N is the number of accumulated points, which is also the number of PRTs within a CPI. Since MTI performs double-pulse or triple-pulse cancellation, the actual speed unit input to the URAM may be N-1 or N-2. In this case, the subsequent MTD-FFT zero-padding operation can be completed by writing zero values ​​to the corresponding URAM address.

[0055] The number of URAMs cascaded for a range-Doppler data storage within a CPI is calculated as the quotient of the number of range dimension points corresponding to the working waveform and the number of moving target detection operation groups that a single URAM can store. The calculation expression is:

[0056] in, This represents the number of distance points corresponding to the working waveform.

[0057] In this embodiment, step S3 includes: setting a distance unit counter, a speed unit counter, and a URAM counter; wherein, the distance unit counter is used to indicate the number of distance units written to the URAM, the speed unit counter is used to indicate the number of speed units written to the URAM, and the URAM counter is used to indicate the specific URAM label in the URAM cascaded storage matrix where the current data is written; when the current URAM storage area is in the writing state, the received moving target display processing result data corresponding to adjacent distance units are written to the high and low bits of the URAM respectively, and the distance unit counter is incremented; when the distance unit counter reaches the number of distance units that can be written to the current URAM, it is determined that the data writing of the current URAM is complete, the URAM counter is incremented to switch to the next cascaded URAM, and the internal address of the URAM is reassigned to zero; when the distance unit counter reaches the total number of distance units corresponding to the moving target display processing result data of the current speed unit, it is determined that the distance unit data writing of the current speed unit is complete, the speed unit counter is incremented, and the distance unit counter and the URAM counter are cleared to receive the moving target display processing result data corresponding to the next speed unit.

[0058] In specific application embodiments, URAM write operations can be implemented through a status register, including an idle state, the current URAM write state, the URAM address update state, and the speed unit update state. A schematic diagram of the write operation state transitions is shown below. Figure 8 As shown, the specific steps are as follows: In the IDLE state, the state machine is in an idle state. At this time, the URAM has not yet received the coherent processing time start flag, and all state counters are set to reset values. The FPGA uses three counters for state transitions: a distance cell counter (Range_Cnt), which indicates the number of distance cells written to the URAM; a speed cell counter (Speed_Cnt), which indicates the number of speed cells written to the URAM; and a URAM counter (URAM_Cnt), which indicates the specific URAM label in the cascaded storage matrix where the current data is written. In the idle state, all three counter values ​​are reset to 0.

[0059] In the current URAM write state CURRENT_URAM_WRITE, the state machine is in the current URAM data write state. In this state, every two processing clock cycles, the received moving target display processing result data from adjacent distance units is written to the high and low bits of the URAM. At this time, the distance unit counter increments by 2, indicating that two distance unit data have been written; the speed unit counter remains unchanged, and the URAM counter remains unchanged. When the distance unit counter reaches the number of moving target detection operation groups that a single URAM can write (e.g., 64), it indicates that the current URAM data has been written completely, and the state transitions to the URAM address update state URAM_ADDR_FRESH. When the distance unit counter reaches the total number of distance units corresponding to a set of moving target display processing result data for the current speed unit (e.g., 4000), it indicates that all distance dimension data under the current speed unit has been written completely, and the state transitions to the speed unit update state SPEED_FRESH. When the received moving target display processing result data from adjacent distance units is written to the high and low bits of the URAM, as follows... Figure 7 As shown, data from every two adjacent distance cells is written to the high and low bits of the same address in the URAM; the lower 36 bits are written with the smaller distance cell number (e.g., N), and the higher 36 bits are written with the larger distance cell number (e.g., N+1). Additionally, each 36-bit segment contains the complex data for a single sampling point, with the higher 18 bits containing the imaginary part of the data and the lower 18 bits containing the real part, facilitating direct input of subsequent URAM read data into the FFT operation.

[0060] In the URAM address update state URAM_ADDR_FRESH, the URAM counter is incremented by 1, indicating that a write operation is being performed on the next cascaded URAM. At this time, the internal address ADDR[11:0] of the URAM needs to be reassigned to zero, and the state machine jumps back to the current URAM write state CURRENT_URAM_WRITE.

[0061] In the SPEED_FRESH state (velocity unit update state), the velocity unit counter is incremented by 1, indicating that a set of range dimension data corresponding to one velocity unit has been written. At this point, preparation is made to receive the next set of moving target display processing result data corresponding to the next velocity unit, and the range unit counter and URAM counter are cleared. The state then transitions to the current URAM write state CURRENT_URAM_WRITE. Furthermore, when the velocity unit counter reaches the total number of velocity units within a coherent processing time (e.g., 128), it indicates that all range-Doppler data within a coherent processing time has been written, and the state transitions to the IDLE state.

[0062] In this embodiment, step S3 further includes repeatedly writing distance unit data under each velocity unit; in step S4, the condition for determining that the current URAM storage area is full is: when the velocity unit counter reaches the total number of velocity units within a coherent processing time, it is determined that the multiple sets of moving target display processing result data within the current coherent processing time have been written; the range-Doppler data matrix is ​​a matrix formed in the current URAM storage area by arranging the distance dimension data and the velocity dimension data.

[0063] In one specific embodiment, the storage capacity of a single URAM is 72 bits × 4K. The moving target display processing result data of this system is 16-bit complex data, so the bit width of each URAM can write up to two sampling points of moving target display processing result data. Therefore, a single URAM can store up to 8K sampling points of moving target display processing result data.

[0064] Taking the farthest working waveform of this system as an example, its range dimension has 2048 points and its accumulated points are 128. Moving target display processing uses three-pulse cancellation processing, therefore, a single URAM stores 64 moving target detection operation groups. Cascading 32 URAMs is sufficient to store range-Doppler data for one coherent processing time. The URAM-based range-Doppler matrix transposer can write data from different velocity units within the same range unit to a predefined write address, transpose it, and then sequentially read it out using another port. Its URAM storage and writing logic diagram is shown below. Figure 7 As shown.

[0065] In step S4, after the current URAM storage area is filled with the range-Doppler data matrix formed by the display processing results data of each moving target within the current coherent processing time, the current URAM storage area is switched to read mode, and another URAM storage area is switched to write mode, so as to alternately execute the writing of the display processing results data of the moving target within the current coherent processing time and the reading of the display processing results data of the moving target within the previous coherent processing time between the two URAM storage areas.

[0066] Specifically, two URAM storage areas are used for ping-pong read / write. The current URAM storage area is used to write the display processing results data of each moving target within the current coherent processing time, forming the corresponding range-Doppler data matrix therein; the other URAM storage area is used to read the range-Doppler data matrix that has been filled in the previous coherent processing time and perform moving target detection processing. When the current URAM storage area is full, it is switched to read mode, and when the other URAM storage area completes reading, it is switched to write mode. Thus, data writing within the current coherent processing time and data reading within the previous coherent processing time are alternately executed between the two URAM storage areas.

[0067] In step S5, when any URAM storage area is in read state, the corresponding range-Doppler data matrix is ​​read, and the corresponding processing result is obtained through moving target detection processing.

[0068] In this embodiment, step S5 includes: when any URAM storage area is in a read state, generating a URAM read address, wherein the URAM read address includes a URAM index address segment for determining the accessed URAM in multiple cascaded URAMs and a URAM internal address segment for determining the internal storage unit of the accessed URAM; accessing the range-Doppler data matrix in the URAM storage area in a preset read address order according to the URAM index address segment and the URAM internal address segment, reading multiple velocity unit data under the same range unit one by one, and performing a velocity-dimensional fast Fourier transform operation on the read multiple velocity unit data under the same range unit to obtain the moving target detection processing result of the corresponding range unit.

[0069] Furthermore, when any URAM storage area is in read mode, the read addresses of each level of the URAM in the URAM storage area are accessed sequentially according to a preset read order; for each distance cell in the range-Doppler data matrix, multiple velocity cell values ​​corresponding to that distance cell are read out continuously, and the continuously read velocity cell values ​​are input into the fast Fourier transform module for velocity dimension operation to obtain the moving target detection processing result corresponding to that distance cell; the reading of velocity cell values ​​and fast Fourier transform processing corresponding to each distance cell are repeated until the moving target detection processing of the range-Doppler data matrix in the URAM storage area in read mode is completed.

[0070] In a specific embodiment, the URAM read operation sequentially accesses the URAM address, outputs all 128 velocity unit values ​​of each range unit sequentially, and then performs a 128-point Fast Fourier Transform to transpose the range-Doppler data matrix. The data flow diagram for moving target detection based on URAM is shown below. Figure 9 As shown, the process is as follows: the moving target display processing result data is input into the URAM writing module; the first URAM storage area and the second URAM storage area are alternately written and read; the URAM storage area in the reading state sequentially outputs the 128-point velocity unit values ​​under the same distance unit; the output data enters the 128-point fast Fourier transform module for velocity dimension calculation; the fast Fourier transform module outputs the moving target detection processing result.

[0071] Specifically, the data flow for moving target detection based on URAM is as follows: Moving target display processing structure data is written into the pre-allocated URAM addresses according to the distance and velocity unit labels; for real-time processing, two URAMs are allocated to process adjacent CPI data in a ping-pong manner; the URAM storage area in read mode outputs 128 different velocity unit data points within the same distance unit in ascending order of distance unit size; since each URAM unit can cache up to 64 sets of range-Doppler data, after each URAM outputs 64 sets of 128-point data, it switches to the next URAM to continue outputting; the output data flows into the 128-point Fast Fourier Transform module for velocity-dimensional Fourier transform processing; the Fast Fourier Transform module outputs the moving target detection processing result, and its output order is the same as the input order, i.e., different 128-point velocity unit data points within the same distance unit are output first, and then the output switches to the next distance unit data point.

[0072] As described above, this invention utilizes on-chip URAM to construct a cascaded storage matrix and combines it with BRAM to complete moving target display processing. By alternately reading and writing the two URAM storage areas, it can simultaneously write moving target display processing result data within the current coherent processing time and read and process the range-Doppler data matrix that has already been filled in the previous coherent processing time. The writing process is controlled by the range unit counter, velocity unit counter, and URAM counter, so that multiple sets of moving target display processing result data within the current coherent processing time are arranged according to the range dimension and velocity dimension to form a range-Doppler data matrix. By sequentially reading multiple velocity unit data under the same range unit for moving target detection processing, on-chip storage, transpose reading, and computation processing of the range-Doppler matrix are realized.

[0073] Compared with the prior art, the present invention has the following beneficial effects: This invention constructs a URAM cascaded storage matrix on an FPGA chip, consisting of multiple cascaded URAMs, enabling range-Doppler data to be stored, transposed, and retrieved on the FPGA chip itself. Compared to using only BRAM for data caching, this method utilizes the larger on-chip storage capacity of URAM to hold range-Doppler data within a coherent processing time. Compared to external DDR, data access is located on the FPGA chip, reducing the impact of uncertain external storage access latency on the real-time radar signal processing.

[0074] The URAM cascaded storage matrix of this invention includes two URAM storage areas that are read and written alternately. When one URAM storage area is writing moving target display processing result data within the current coherent processing time, the other URAM storage area can read the range-Doppler data matrix that has already been filled in the previous coherent processing time. This achieves ping-pong processing of adjacent coherent processing time data and avoids the current input data from overwriting the previous coherent processing time data that has not yet completed the moving target detection processing.

[0075] In this invention, radar pulse compression data is first processed by inter-pulse differential processing to obtain moving target display processing result data output in range dimension order. Then, the data is written into the current URAM storage area according to the range unit position, velocity unit position, and URAM cascade position. This allows multiple sets of moving target display processing result data within the current coherent processing time to be arranged in the URAM storage area according to the range and velocity dimensions to form a range-Doppler data matrix. This enables the data arriving in range dimension order at input to be organized into a data format suitable for subsequent reading in the velocity dimension and moving target detection processing.

[0076] This invention controls the URAM writing process through a distance unit counter, a velocity unit counter, and a URAM counter. It can switch to the next cascaded URAM after the current URAM is full, and switch to the next velocity unit after the distance unit data under the current velocity unit is written. This allows the orderly writing of the display processing results data of each moving target within the current coherent processing time to be completed according to the URAM cascade structure and the arrangement relationship of the range-Doppler data matrix.

[0077] The URAM reading process of this invention sequentially accesses the URAM read address to read multiple velocity unit data under the same range unit from the range-Doppler data matrix, and then performs moving target detection processing on these multiple velocity unit data. The URAM cascaded storage matrix is ​​not only used for data caching, but also for realizing the transpose reading of the range-Doppler data matrix, enabling the cascaded processing of radar moving target display and moving target detection to be executed continuously on the chip.

[0078] The present invention further provides a URAM-based radar moving target display and detection cascade processing system, including a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the steps of the URAM-based radar moving target display and detection cascade processing method.

[0079] The present invention further provides a computer-readable storage medium storing a computer program / instructions, the computer program / instructions being programmed or configured to execute, via a processor, the steps of a URAM-based radar moving target display and detection cascade processing method.

[0080] The system and medium of the present invention, corresponding to the methods described above, also have the advantages described above.

[0081] The present invention can implement all or part of the processes in the methods of the above embodiments, or it can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of the above method embodiments. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. Computer-readable media include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing the computer programs and / or modules stored in the memory, and by calling data stored in the memory. The memory may include high-speed random access memory, as well as non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital (SD) cards, flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0082] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A cascaded processing method for radar moving target display and detection based on URAM, characterized in that, Applied to FPGAs, the method includes the following steps: S1, Construct a URAM cascaded storage matrix on the FPGA chip, which consists of multiple URAMs cascaded together, and the URAM cascaded storage matrix includes two URAM storage areas that are read and written alternately; S2, receive radar pulse compression data after pulse compression of radar signal, and perform inter-pulse differential processing on the radar pulse compression data to obtain moving target display processing result data output in range dimension order; S3, when one of the URAM storage areas is in the write state, write the moving target display processing result data of each moving target within the current coherent processing time into the current URAM storage area according to the distance unit position, speed unit position and URAM cascade position corresponding to the moving target display processing result data; S4. After the current URAM storage area is filled with the distance-Doppler data matrix formed by the display processing results data of each moving target within the current coherent processing time, the current URAM storage area is switched to the read state, and another URAM storage area is switched to the write state, so as to alternately execute the writing of the display processing results data of the moving target within the current coherent processing time and the reading of the display processing results data of the moving target within the previous coherent processing time between the two URAM storage areas. S5: When any URAM storage area is in read state, read the corresponding range-Doppler data matrix and obtain the corresponding processing result through moving target detection processing.

2. The URAM-based radar moving target display and detection cascade processing method according to claim 1, characterized in that, In step S1, a URAM cascaded storage matrix consisting of multiple cascaded URAMs is constructed on the FPGA chip, including: The address bus, data bus, and status bus of adjacent URAMs are connected to form a URAM cascade structure; cascade order parameters, cascade mask parameters, and cascade address parameters are configured for each URAM in the cascade structure. The concatenation sequence parameter is used to indicate the first, middle, or last bit of the corresponding URAM in the concatenation structure. The concatenation mask parameter is used to indicate the number of concatenated URAMs and the valid bits of the URAM index bits in the address bus. The concatenation address parameter is used to indicate the address index value of the corresponding URAM in the URAM concatenation structure and is used to match with the externally input address control signal to determine the data to be written to the corresponding URAM.

3. The URAM-based radar moving target display and detection cascade processing method according to claim 1, characterized in that, In step S2, the inter-pulse differential processing includes: The radar pulse compression data is received in a time-division multiplexing manner within a coherent processing time. The radar pulse compression data output first is cached in the FPGA on-chip BRAM. When subsequent radar pulse compression data is input, the cached radar pulse compression data is read from the FPGA on-chip BRAM. The data of the same range cell in the subsequent radar pulse compression data and the cached radar pulse compression data are differentially processed to obtain the moving target display processing result data.

4. The URAM-based radar moving target display and detection cascade processing method according to claim 3, characterized in that, The inter-pulse differential processing is either double-pulse cancellation processing or triple-pulse cancellation processing; when the inter-pulse differential processing is double-pulse cancellation processing, N-1 sets of range dimension data are output within one coherent processing time; when the inter-pulse differential processing is triple-pulse cancellation processing, N-2 sets of range dimension data are output within one coherent processing time, where N is the number of radar pulse compression data sets output in a time-division manner within one coherent processing time. Specifically, when the inter-pulse differential processing employs double-pulse cancellation processing or triple-pulse cancellation processing, resulting in the number of speed units actually input to the URAM cascaded storage matrix being less than the number of speed units required for moving target detection processing, zero values ​​are further written to the URAM addresses corresponding to the unwritten speed units to complete the zero-padding operation for subsequent moving target detection processing.

5. The URAM-based cascaded processing method for radar moving target display and detection according to claim 1, characterized in that, Step S3 includes: Set a distance unit counter, a speed unit counter, and a URAM counter; wherein, the distance unit counter is used to indicate the number of distance units that have been written to the URAM, the speed unit counter is used to indicate the number of speed units that have been written to the URAM, and the URAM counter is used to indicate the specific URAM label in the URAM cascaded storage matrix where the current data is written; When the current URAM storage area is in the write state, the received moving target display processing result data corresponding to the adjacent distance unit is written to the high and low bits of the URAM respectively, and the distance unit counter is incremented. When the distance unit counter reaches the number of distance units that can be written to the current URAM, it is determined that the data writing of the current URAM is complete, the URAM counter is automatically switched to the next cascaded URAM, and the internal address of the URAM is reassigned to zero; When the distance unit counter reaches the total number of distance units corresponding to the moving target display processing result data of the current speed unit, it is determined that the distance unit data under the current speed unit has been written, the speed unit counter is incremented, and the distance unit counter and URAM counter are cleared to receive the moving target display processing result data corresponding to the next speed unit.

6. The URAM-based cascaded processing method for radar moving target display and detection according to claim 5, characterized in that, Step S3 also includes repeatedly writing distance unit data for each velocity unit; In step S4, the condition for determining that the current URAM storage area is full is: when the speed unit counter reaches the total number of speed units within a coherent processing time, it is determined that the multiple sets of moving target display processing result data within the current coherent processing time have been written. The range-Doppler data matrix is ​​a matrix formed within the current URAM storage area, which is obtained by arranging the range dimension data and the velocity dimension data.

7. The cascaded processing method for radar moving target display and detection based on URAM according to claim 1, characterized in that, Step S5 includes: When any URAM storage area is in read state, a URAM read address is generated. The URAM read address includes a URAM index address segment for determining the accessed URAM in multiple cascaded URAMs and a URAM internal address segment for determining the internal storage cell of the accessed URAM. According to a preset read address order, the range-Doppler data matrix in the URAM storage area is accessed sequentially according to the URAM index address segment and the URAM internal address segment. Multiple velocity cell data under the same range cell are read one after another, and a velocity-dimensional fast Fourier transform operation is performed on the read multiple velocity cell data under the same range cell to obtain the moving target detection processing result of the corresponding range cell.

8. The cascaded processing method for radar moving target display and detection based on URAM according to claim 1, characterized in that, In step S5, data from the same range unit and different velocity units in the range-Doppler data matrix are combined into a moving target detection operation group. The number of moving target detection operation groups that a single URAM can store is calculated based on the quotient of the total number of sampling points that a single URAM can store and the number of accumulated points within a coherent processing time. The number of URAMs cascaded for range-Doppler data storage within a coherent processing time is calculated based on the quotient of the number of range dimension points corresponding to the working waveform and the number of moving target detection operation groups that a single URAM can store.

9. A URAM-based radar moving target display and detection cascaded processing system, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to perform the steps of the URAM-based radar moving target display and detection cascade processing method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program / instructions, characterized in that, The computer program / instructions are programmed or configured to execute the steps of the URAM-based radar moving target display and detection cascade processing method according to any one of claims 1 to 8 via a processor.

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