In-memory processing system including an extended architecture

Abstract

The present disclosure relates to in-memory processing systems including an extended architecture. An in-memory processing (PIM) system includes a plurality of PIM devices, and a PIM hub system configured to control the plurality of PIM devices. The PIM hub system includes an instruction decoder and sequencer configured to receive macro instructions and generate and output a plurality of micro instructions based on the macro instructions, a multicast interconnect configured to output one or more sets of sub-micro instructions based on the plurality of micro instructions, and a plurality of PIM controllers each coupled to the plurality of PIM devices via a plurality of channels, the plurality of PIM controllers configured to generate and output one or more sets of PIM commands based on the one or more sets of sub-micro instructions.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2025-0045743, filed with the Korean Intellectual Property Office on April 8, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various implementations of this teaching generally relate to in-memory processing systems, and more specifically, to in-memory processing systems including extended architectures. Background Technology

[0004] Large Language Model (LLM) systems are sophisticated artificial intelligence (AI) models designed to understand and generate human-like text based on massive amounts of training data. These models utilize deep learning techniques, particularly neural networks, to analyze language patterns and generate coherent, context-aware text. A key characteristic of LLMs is their scale, which allows models to capture complex language structures and nuances by training on datasets containing billions of words. Therefore, there is a need to scale the in-memory processing (PIM) system responsible for performing operations applied to LLMs. Furthermore, in PIM systems with scalable architectures, multiple methods are required to efficiently control a large number of PIM devices. Summary of the Invention

[0005] A PIM system according to an embodiment of the present disclosure may include a plurality of PIM devices and a PIM central system configured to control the plurality of PIM devices. The PIM central system may include: an instruction decoder and sequencer configured to receive macro instructions and generate and output a plurality of micro instructions based on the macro instructions; a multicast interconnect configured to output one or more sub-micro instruction sets based on the plurality of micro instructions; and a plurality of PIM controllers, each PIM controller coupled to the plurality of PIM devices via a plurality of channels, the plurality of PIM controllers configured to generate and output one or more PIM command sets based on one or more sub-micro instruction sets.

[0006] A PIM system according to an embodiment of the present disclosure may include a PIM system comprising a plurality of in-memory processing (PIM) devices and a PIM central system configured to control the plurality of PIM devices. The PIM central system may include: a multicast interconnect configured to receive macro instructions and generate and output one or more sub-macro instructions based on the macro instructions; a plurality of instruction decoders and sequencers configured to generate and output one or more microinstruction sets based on one or more sub-macro instructions; and a plurality of PIM controllers, each PIM controller coupled to one of the plurality of PIM devices via a corresponding channel of a plurality of channels, configured to generate and output one or more PIM command sets based on one or more microinstruction sets.

[0007] A PIM system according to an embodiment of the present disclosure may include a plurality of in-memory processing (PIM) devices and a PIM central system configured to control the plurality of PIM devices. The PIM central system may include: a first-level instruction decoder and sequencer configured to receive macro instructions and generate and output first-level micro instructions based on the macro instructions; a second-level instruction decoder and sequencer configured to generate and output a second-level microinstruction set based on the first-level microinstructions; a multicast interconnect configured to generate and output one or more sub-microinstruction sets based on the second-level microinstruction set; and a plurality of PIM controllers configured to generate one or more PIM command sets based on one or more sub-microinstruction sets and output one or more PIM command sets to the plurality of PIM devices.

[0008] A PIM system according to an embodiment of the present disclosure may include a plurality of in-memory processing (PIM) devices and a PIM central system coupled to the plurality of PIM devices via a plurality of channels to control the plurality of PIM devices. The PIM central system may include: a multicast interconnect configured to receive macro instructions and generate and output one or more sub-macro instructions based on the macro instructions; a plurality of first-level instruction decoders and sequencers configured to generate and output one or more first-level micro instructions based on one or more sub-macro instructions; a plurality of second-level instruction decoders and sequencers configured to generate and output one or more sets of second-level micro instructions based on one or more first-level micro instructions; and a plurality of PIM controllers configured to generate and output one or more sets of PIM commands based on one or more sets of second-level micro instructions. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an implementation of the in-memory processing (PIM) system according to the present disclosure.

[0010] Figure 2 It is shown Figure 1 A block diagram illustrating an example of a PIM device included in a PIM system.

[0011] Figure 3 It is shown Figure 2 A diagram showing an example of a processing unit included in a PIM device.

[0012] Figures 4 to 6 This is a diagram illustrating various examples of channel masks included in macro instructions and channel masks included in micro instructions generated by the instruction decoder and sequencer.

[0013] Figure 7 This is a diagram illustrating an example of a first macro instruction used in a PIM system according to this disclosure.

[0014] Figures 8 to 10 It is shown in Figure 1 Execution in the PIM system Figure 7 A diagram showing the process of the first macro instruction.

[0015] Figure 11 This is a diagram illustrating the second macro instruction used in the PIM system according to this disclosure.

[0016] Figures 12 to 14 It is shown in Figure 1 Execution in the PIM system Figure 11 A diagram illustrating an example process for the second macro instruction.

[0017] Figures 15 to 18 It is shown in Figure 1 Execution in the PIM system Figure 11 A diagram of another example process for the second macro instruction.

[0018] Figure 19 This is a diagram illustrating the third macro instruction used in the PIM system according to this disclosure.

[0019] Figures 20 to 23 It is shown in Figure 1 Execution in the PIM system Figure 19 A diagram illustrating an example process for the third macro instruction.

[0020] Figures 24 to 27 It is shown in Figure 1 Execution in the PIM system Figure 19 A diagram of another example process of the third macro instruction.

[0021] Figure 28 This is a diagram illustrating the fourth macro instruction used in the PIM system according to this disclosure.

[0022] Figures 29 to 31 It is shown in Figure 1 Execution in the PIM system Figure 28 A diagram showing the process of the fourth macro instruction.

[0023] Figure 32 This is a block diagram illustrating another embodiment of the PIM system according to the present disclosure.

[0024] Figures 33 to 35 It is shown in Figure 32 Execution in the PIM system Figure 7 A diagram showing the process of the first macro instruction.

[0025] Figures 36 to 39 It is shown in Figure 32 Execution in the PIM system Figure 11 A diagram illustrating an example process for the second macro instruction.

[0026] Figures 40 to 42 It is shown in Figure 32 Execution in the PIM system Figure 11 A diagram of another example process for the second macro instruction.

[0027] Figures 43 to 46 It is shown in Figure 32 Execution in the PIM system Figure 19 A diagram illustrating an example process for the third macro instruction.

[0028] Figures 47 to 49 It is shown in Figure 32 Execution in the PIM system Figure 19 A diagram of another example process of the third macro instruction.

[0029] Figures 50 to 52 It is shown in Figure 32 Execution in the PIM system Figure 28 A diagram showing the process of the fourth macro instruction.

[0030] Figure 53 This is a block diagram illustrating yet another embodiment of the PIM system according to the present disclosure.

[0031] Figure 54 It is shown Figure 53 A diagram illustrating the example operation of the first-level instruction decoder and sequencer included in the PIM system.

[0032] Figure 55 This is a block diagram illustrating another embodiment of the PIM system according to the present disclosure.

[0033] Figure 56 It is shown Figure 55 A diagram illustrating example operations of multicast interconnection included in a PIM system.

[0034] Figure 57 This is a block diagram illustrating yet another embodiment of the PIM system according to the present disclosure. Detailed Implementation

[0035] Terms such as “first” and “second” are used to distinguish multiple elements and do not imply the size, order, priority, number, or importance of these elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0036] When one element is referred to as "connected" or "coupled" to another element, the two elements can be directly connected or connected through one or more intermediate elements between them. When two elements are referred to as "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there are no intermediate elements between the two elements.

[0037] Terms such as “above,” “up,” “inside,” “higher,” “high,” “low,” “left,” “right,” “column,” “row,” “horizontal,” and other terms that suggest relative spatial relationships or orientations are used for the purpose of facilitating description or reference to the accompanying drawings and have no other limiting effect.

[0038] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided only as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0039] Figure 1 This is a block diagram illustrating an implementation of the in-memory processing (PIM) system according to the present disclosure. Figure 2 It is shown Figure 1 A block diagram illustrating an example of a PIM device included in a PIM system. Figure 3 It is shown Figure 2 A diagram showing an example of a processing unit included in a PIM device.

[0040] Reference Figure 1 The PIM system 10 includes multiple PIM devices (such as first to j-th PIM devices 110(0) to 110(j-1)) and a PIM central system 200. Here, "j" represents a natural number greater than or equal to 2. The first to j-th PIM devices 110(0) to 110(j-1) are coupled to the PIM central system 200 via first to j-th channels CH0 to CH"j-1, respectively. The first to j-th channels CH0 to CH"j-1 represent the physical connection between the first to j-th PIM devices (PIM0 to PIM"j-1") 110(0) to 110(j-1) and the PIM central system 200. Each of the first to j-th channels CH0 to CH"j-1 is configured to have an independent data bus. Therefore, signal transmission between the first to j-th PIM devices 110(0) to 110(j-1) and the PIM central system 200 can be performed in parallel through the corresponding first to j-th channels CH0 to CH"j-1. Figure 1As shown, the first PIM device 110 (0) is coupled to the PIM central system 200 via the first channel CH0. The second PIM device 110 (1) is coupled to the PIM central system 200 via the second channel CH1. The third PIM device 110 (2) is coupled to the PIM central system 200 via the third channel CH2. The "j-1" PIM device 110 (j-2) is coupled to the PIM central system 200 via the "j-1" channel CH "j-2". The j-th PIM device 110 (j-1) is coupled to the PIM central system 200 via the j-th channel CH "j-1". Although not shown in the figure, in another embodiment, two or more PIM devices may share a single channel to be coupled to the PIM central system 200. In this case, the PIM system 10 may include a number of PIM devices corresponding to multiples of "j".

[0041] In one embodiment, each of the first to j-th PIM devices 110(0) to 110(j-1) can be configured as a bare die. Although not shown in the figures, in one embodiment, two of the first to j-th PIM devices 110(0) to 110(j-1) can be packaged together into a single package. For example, the first PIM device 110(0) and the second PIM device 110(1) can constitute a first PIM package. The third PIM device 110(2) and the fourth PIM device (not shown) can constitute a second PIM package. In the same manner, the "j-1" PIM device 110("j-2") and the j-th PIM device 110(j-1) can constitute the "j / 2" PIM package. In one embodiment, the PIM system 10 can be configured as a card, wherein the first to j-th PIM devices 110(0) to 110(j-1) and the PIM central system 200 are mounted on the same board.

[0042] Reference Figure 2 The PIM device 300 may include multiple storage units, such as first to sixteenth storage units BK0 to BK15, a global buffer GB, and multiple processing elements, such as first to sixteenth processing elements PE0 to PE15. The following description of the PIM device 300 is equally applicable. Figure 1The PIM system 10 includes first to j-th PIM devices 110(0) to 110(j-1). In one example, the first to sixteenth memory banks BK0 to BK15 may be a memory array or group of memory arrays constituting dynamic random access memory (DRAM). Therefore, the first to sixteenth memory banks BK0 to BK15 can operate independently of each other. Each of the first to sixteenth memory banks BK0 to BK15 may include multiple rows and multiple columns. Each of the multiple rows may be specified by a row address, and each of the multiple columns may be specified by a column address. In one embodiment, the first to sixteenth memory banks BK0 to BK15 may store weight data used as operands for matrix-vector multiplication operations.

[0043] A global buffer GB may include multiple storage areas, such as multiple registers. Each storage area of ​​the global buffer GB may be specified by a column address. That is, a specific column of the first through sixteenth memory banks BK0 through BK15 and a specific storage area of ​​the global buffer GB may be specified by a column address. In one embodiment, the global buffer GB may store vector data used as operands for matrix-vector multiplication operations. In one embodiment, the storage capacity of the global buffer GB may be equal to the page size of each of the first through sixteenth memory banks BK0 through BK15. In another embodiment, the storage capacity of the global buffer GB may be less than or greater than the page size of each of the first through sixteenth memory banks BK0 through BK15.

[0044] The first to sixteenth processing elements PE0 to PE15 are coupled to the first to sixteenth memory banks BK0 to BK15, respectively. For example, the first processing element PE0 is coupled to the first memory bank BK0. The second processing element PE1 is coupled to the second memory bank BK1. Similarly, the sixteenth processing element PE15 is coupled to the sixteenth memory bank BK15. On the other hand, the first to sixteenth processing elements PE0 to PE15 are also coupled to the global buffer GB.

[0045] Processing units PE0 to PE15, from the first to the sixteenth memory banks BK0 to BK15 respectively, can receive first operational data, such as a weight dataset. For example, processing unit PE0 can receive the first weight dataset from the first memory bank BK0. Processing unit PE1 can receive the second weight dataset from the second memory bank BK1. Similarly, processing unit PE15 can receive the sixteenth weight dataset from the sixteenth memory bank BK15. Processing units PE0 to PE15 can collectively receive second operational data, such as vector data, from the global buffer GB. Using the weight dataset received from the first to the sixteenth memory banks BK0 to BK15 and the vector data received from the global buffer GB respectively, processing units PE0 to PE15 can perform operations such as multiplication-accumulation (MAC).

[0046] In this example, the PIM device 300 is described as comprising the same number of storage units BK0 to BK15 and processing elements PE0 to PE15, but this is merely an example. In other embodiments, the PIM device 300 may include different numbers of storage units and processing elements. For example, the PIM device 300 may have a structure where two storage units share one processing element. In this case, the number of processing elements may be half the number of storage units. Alternatively, the PIM device 300 may have a structure where four storage units share one processing element. In this case, the number of processing elements may be one-quarter the number of storage units.

[0047] Reference Figure 3 Processing element 400 may include a multiplication circuit, an addition circuit, an accumulator (ACC) 430, and an activation function circuit (AF) 440. The multiplication circuit may include first to "k" multipliers (MUL(0) to MUL(k-1)) 410(0) to 410(k-1), where "k" represents a natural number greater than or equal to 2. The addition circuit may be configured as an adder tree 420 comprising multiple adders. The following description of processing element 400 is equally applicable. Figure 2 The PIM device 300 includes the first to sixteenth processing elements PE0 to PE15.

[0048] The first to the "k"th multipliers 410(0) to 410(k-1) receive the first to the "k"th weight data W(0) to W(k-1) from the storage. The first to the "k"th multipliers 410(0) to 410(k-1) receive the first to the "k"th vector data V(0) to V(k-1) from the global buffer. The first to the "k"th multipliers 410(0) to 410(k-1) perform multiplication operations on the corresponding weight data W(0) to W(k-1) and the corresponding vector data V(0) to V(k-1) to output the first to the "k"th multiplication data M(0) to M(k-1). Specifically, the first multiplier 410(0) performs multiplication operations on the first weight data W(0) and the first vector data V(0) to output the first multiplication data M(0). The second multiplier 410(1) performs a multiplication operation on the second weight data W(1) and the second vector data V(1) to output the second multiplication data M(1). Similarly, the "k"th multiplier 410(k-1) performs a multiplication operation on the "k"th weight data W(k-1) and the "k"th vector data V(k-1) to output the "k"th multiplication data M(k-1).

[0049] Adder tree 420 receives the first to the "k"th multiplication data M(0) to M(k-1) from the outputs of the first to the "k"th multipliers 410(0) to 410(k-1). Adder tree 420 performs addition operations on the first to the "k"th multiplication data M(0) to M(k-1). Adder tree 420 outputs the result data generated by the addition operation as multiplication-accumulation data MA. Although in Figure 3 The exact wording is omitted, but the adder tree 420 may include multiple adders arranged in a tree structure. The adder tree 420 transmits the multiplication-accumulation data MA to the accumulator 430.

[0050] Accumulator 430 may include an accumulator adder and a latch circuit. The accumulator adder performs an accumulation operation by adding the multiplication-accumulation data MA transmitted from adder tree 420 to latched data fed back from the latch circuit, thereby generating accumulated addition data. The latch circuit latches the accumulated addition data generated by the accumulator adder. The accumulated addition data latched in the latch circuit is fed back to the accumulator adder as latched data in the next MAC operation. When all MAC operations are completed, the latch circuit outputs the latched accumulated addition data as the MAC result data MAC_RST.

[0051] The activation function circuit 440 can receive MAC result data (MAC_RST) from the accumulator 430. The activation function circuit 440 can perform activation function processing on the MAC result data (MAC_RST) to output the processed result data (AF_RST). Through activation function processing, the processed result data (AF_RST) can acquire nonlinearity. In one embodiment, the activation function processing can be performed using a sigmoid function, a hyperbolic tangent function, a rectified linear unit (ReLU) function, a Leaky ReLU function, or a Swish function.

[0052] Refer again Figure 1 The PIM central system 200 controls the operation of the first to j-th PIM devices 110(0) to 110(j-1). The PIM central system 200 can be coupled to a host computer. The PIM central system 200 can also be coupled to another PIM central system included in a different PIM system. The PIM central system 200 can receive macro instructions from the host computer. Based on the macro instructions transmitted from the host computer, the PIM central system 200 can generate one or more PIM command sets. The PIM central system 200 can transmit one or more PIM command sets to one or more of the first to j-th PIM devices 110(0) to 110(j-1).

[0053] In one embodiment, the macro instruction transmitted to the PIM central system 200 may have a payload format that does not include a header or metadata. In other embodiments, the macro instruction may have a format that is differentiated based on the destination address. In one embodiment, the macro instruction may be one of a first macro instruction, a second macro instruction, a third macro instruction, and a fourth macro instruction. The first to fourth macro instructions may all include an operation type. The operation type included in the first macro instruction may be specified as a first operation type, such as "MAC", which requests to perform a MAC operation in the first to j PIM devices 110(0) to 110(j-1). The operation types included in the second and third macro instructions may be specified as second operation types, such as "WRGB", which requests a global buffer write operation to store vector data in the global buffers included in the first to j PIM devices 110(0) to 110(j-1). In one embodiment, the vector data may be used as an operand in a matrix-vector multiplication (GEMV) operation. The operation type included in the fourth macro instruction can be specified as a third operation type, such as "WRBIAS," which requests a bias data write operation to store bias data into latching circuits included in the first to j-th PIM devices 110(0) to 110(j-1). In one embodiment, the bias data can be defined as data added to the result of a matrix-vector multiplication in a multilayer perceptron (MLP) operation. In one embodiment, the macro instruction may also include a request for a load operation or a store operation to local memory.

[0054] In one implementation, in addition to the operation type designated as the first operation type "MAC", the first macro instruction may also include an iteration count, a channel mask, a row address, and a column address. The iteration count included in the first macro instruction may specify a number "m" (where "m" is a natural number greater than or equal to 2), indicating how many times the MAC operation is performed. The channel mask included in the first macro instruction may include the first to j bits corresponding to the first to j channels, respectively. The row address included in the first macro instruction may specify the row of the storage bank containing weight data used as operands in the MAC operation. The column address included in the first macro instruction may specify the starting column position of the storage bank containing the weight data used in the MAC operation.

[0055] In one implementation, in addition to the operation type specified as the second operation type "WRGB", the second macro instruction may also include an iteration count, a channel mask, a local memory address, a column address, and a broadcast bit. The iteration count included in the second macro instruction may be a number "m", indicating how many times the global buffer write operation is performed. The channel mask included in the second macro instruction may include the first to the j-th bits corresponding to the first to the j-th channels, respectively. The local memory address included in the second macro instruction may specify the starting storage location of the data to be accessed in local memory. The column address included in the second macro instruction may specify the starting storage location of the vector data stored in the global buffer. The broadcast bit included in the second macro instruction may be set to a first binary value indicating a broadcast operation or a second binary value indicating a non-broadcast operation. In one implementation, the first binary value may be binary "1", and the second binary value may be binary "0".

[0056] In one implementation, in addition to the operation type specified as the second operation type "WRGB", the third macro instruction may also include an iteration count, a channel mask, a local memory address, a column address, a broadcast bit, and a local memory increment size. The iteration count included in the third macro instruction may be specified as a number "m", indicating how many times the global buffer write operation is performed. The channel mask included in the third macro instruction may include the first to the j-th bits corresponding to the first to the j-th channels, respectively. The local memory address included in the third macro instruction may specify the starting storage location of the data to be accessed in local memory. The column address included in the third macro instruction may specify the starting storage location of the vector data stored in the global buffer. The broadcast bit included in the third macro instruction may be set to a first binary value indicating a broadcast operation or a second binary value indicating a non-broadcast operation. The local memory increment size included in the third macro instruction may specify the unit size by which the local memory address is incremented.

[0057] In one implementation, in addition to the operation type designated as the third operation type "WRBIAS", the fourth macro instruction may also include a channel mask, a local memory address, and a MAC latch ID. The fourth macro instruction may also include broadcast bits. The channel mask included in the fourth macro instruction may include the first to the j-th bits corresponding to the first to the j-th channels, respectively. The local memory address included in the fourth macro instruction may specify the starting storage location of the bias data stored in local memory. The MAC latch ID included in the fourth macro instruction may specify the latch circuit that latches the bias data among the plurality of latch circuits included in each of the first to the j-th PIM devices 110(0) to 110(j-1). When the fourth macro instruction includes broadcast bits, since the bias data provided to each channel of the PIM system 10 is different, the broadcast bits may have a binary value indicating a non-broadcast transmission method.

[0058] In one implementation, the PIM central system 200 may include a host interface (HOST I / F) 211, a network router (NET RTR) 212, an instruction decoder and sequencer 220, a local memory 230, an arithmetic logic unit (ALU) 240, a multicast interconnect 250, and first to j-th PIM controllers 260(0) to 260(j-1).

[0059] Host interface 211 performs the connection with the host. In one embodiment, host interface 211 may be a PCIe (PCI Express) endpoint (PCIe EP). Although Figure 1 Not shown, but PCIe endpoint 211 can receive data packets transmitted from the host's root complex. In one embodiment, PCIe endpoint 211 can perform serial-to-parallel conversion, decoding, frame symbol removal, and error detection on the data packets. PCIe endpoint 211 can transmit data packets to instruction decoder and sequencer 220 and / or multicast interconnect 250. In one embodiment, data packets transmitted from the host to host interface 211 may include macro instructions. When macro instructions are transmitted from the host, host interface 211 can transmit macro instructions to instruction decoder and sequencer 220.

[0060] Network router 212 can be coupled to a network router (hereinafter referred to as "another network router") included in another PIM central system located adjacent to PIM central system 200 to establish a network connection. In one embodiment, network router 212 can be an inter-chip router that performs inter-chip network communication. Network router 212 can forward data packets received from multicast interconnect 250 to the other network router. Network router 212 can receive data packets from the other network router and forward them to multicast interconnect 250. When the destination of data packets received from the other network router is a PIM central system other than PIM central system 200, network router 212 can also forward the received data packets to the other network router.

[0061] The instruction decoder and sequencer 220 can receive macro instructions transmitted from the host to the PIM central system 200 via the host interface 211. The instruction decoder and sequencer 220 may include an instruction decoder and an instruction sequencer. In one embodiment, the instruction decoder can decode the macro instructions received from the host to generate multiple micro instructions. The instruction sequencer can transmit the multiple micro instructions generated by the instruction decoder to the multicast interconnect 250. In another embodiment, the instruction decoder can decode the macro instructions received from the host to generate multiple local memory instructions and multiple micro instructions. The instruction sequencer can transmit the local memory instructions generated by the instruction decoder to local memory 230 and transmit the multiple micro instructions generated by the instruction decoder to the multicast interconnect 250.

[0062] More specifically, the operation of the instruction decoder and sequencer 220 will be described with reference to the first, second, third, and fourth examples. In the first example, a first macro instruction, including an operation type designated as "MAC", iteration count, channel mask, row address, and column address, is input to the instruction decoder and sequencer 220. In the second example, a second macro instruction, including an operation type designated as "WRGB", iteration count, channel mask, local memory address, column address, and broadcast bit, is input to the instruction decoder and sequencer 220. In the third example, a third macro instruction, including an operation type designated as "WRGB", iteration count, channel mask, local memory address, column address, broadcast bit, and local memory increment size, is input to the instruction decoder and sequencer 220. In the fourth example, a fourth macro instruction, including an operation type designated as "WRBIAS", channel mask, local memory address, MAC latch ID, and broadcast bit, is input to the instruction decoder and sequencer 220.

[0063] In the first example, the instruction decoder and sequencer 220 generate microinstructions based on a first macroinstruction, the number of which equals the number of iterations included in the first macroinstruction. The microinstructions generated in the first example may include an operation type designated as a first operation type "MAC", a channel mask, a row address, and a column address. The channel mask included in the microinstruction may be configured identically to the channel mask included in the first macroinstruction. The row addresses included in the microinstruction may have the same values ​​as the row addresses included in the first macroinstruction. The column addresses included in the microinstruction may sequentially increment from the column addresses included in the first macroinstruction.

[0064] In the second example, the instruction decoder and sequencer 220 generate at least one local memory instruction and at least one micro instruction based on a second macro instruction. When the broadcast bit included in the second macro instruction has a first binary value (e.g., a binary value "1"), the instruction decoder and sequencer 220 generate a number of local memory instructions and micro instructions equal to the number of iterations included in the second macro instruction. When the broadcast bit included in the second macro instruction has a second binary value (e.g., a binary value "0"), the instruction decoder and sequencer 220 generate a number of local memory instructions and micro instructions obtained by multiplying the number of iterations included in the second macro instruction by the number of bits with a value of "1" in the channel mask included in the second macro instruction.

[0065] In the second example, the local memory instruction generated by the instruction decoder and sequencer 220 may include a local memory command and a local memory address. The local memory command included in the local memory instruction may be a command specifying a read operation on local memory, for example, specified as "RD_LM". The local memory address included in the local memory instruction may sequentially increment from the local memory address included in the second macro instruction. In the second example, the microinstruction generated by the instruction decoder and sequencer 220 may include an operation type specified as the second operation type "WRGB", a channel mask, a column address, and a broadcast bit. The column address included in the microinstruction may sequentially increment from the column address included in the second macro instruction. The broadcast bit included in the microinstruction may have the same value as the broadcast bit included in the second macro instruction.

[0066] Depending on the bit value of the broadcast bit, the channel mask included in the microinstruction can be configured the same as or different from the channel mask included in the second macroinstruction. In one embodiment, when the broadcast bit included in the second macroinstruction has a first binary value (e.g., binary value "1"), the instruction and data transmission scheme can be specified as a broadcast transmission scheme, wherein the same instruction and data are transmitted to all channels. In one embodiment, a broadcast transmission scheme can be defined as a scheme in which the same data is transmitted to all channels. In this case, the channel mask included in the microinstruction generated by the instruction decoder and sequencer 220 can be configured the same as the channel mask included in the second macroinstruction. On the other hand, when the broadcast bit has a second binary value (e.g., binary value "0"), the instruction and data transmission scheme can be specified as a non-broadcast transmission scheme, such as a unicast or multicast transmission scheme, wherein different instructions or data are transmitted to different channels. In one embodiment, a non-broadcast transmission scheme can be defined as a scheme in which different data is transmitted to each channel. In this case, the channel mask included in the microinstruction generated by the instruction decoder and sequencer 220 can be configured differently from the channel mask included in the second macroinstruction.

[0067] Specifically, when the broadcast bit included in the second macro instruction has a binary value of "0", for each channel mask included in the microinstruction generated by the instruction decoder and sequencer 220, one bit in the channel mask (hereinafter referred to as the "channel bit") can have the same bit value as the corresponding bit in the channel mask included in the second macro instruction. Therefore, for each channel mask included in the microinstruction, the channel bit can have a binary value of "0" or "1", depending on the corresponding bit in the second macro instruction. Furthermore, all other bits in the channel mask included in each microinstruction, except for the channel bit, can have a binary value of "0".

[0068] In the third example, the instruction decoder and sequencer 220 generate at least one local memory instruction and at least one micro instruction based on a third macro instruction. When the broadcast bit included in the third macro instruction has a first binary value (e.g., a binary value "1"), the instruction decoder and sequencer 220 generate a number of local memory instructions and micro instructions equal to the number of iterations included in the third macro instruction. When the broadcast bit included in the third macro instruction has a second binary value (e.g., a binary value "0"), the instruction decoder and sequencer 220 generate a number of local memory instructions and micro instructions obtained by multiplying the number of iterations included in the third macro instruction by the number of bits with a value of "1" in the channel mask included in the third macro instruction.

[0069] In the third example, the local memory instruction generated by the instruction decoder and sequencer 220 may include a local memory command and a local memory address. The local memory command included in the local memory instruction may be specified as "RD_LM", which indicates a read operation on local memory. The local memory address included in the local memory instruction may be sequentially incremented starting from the local memory address included in the third macro instruction, with the increment size specified by the local memory increment size included in the third macro instruction.

[0070] In the third example, the microinstructions generated by the instruction decoder and sequencer 220 may include an operation type designated as the second operation type "WRGB", a channel mask, a column address, and a broadcast bit. The column address included in the microinstruction may be sequentially incremented starting from the column address included in the third macro instruction. The broadcast bit included in the microinstruction may have the same value as the broadcast bit included in the third macro instruction.

[0071] The channel mask included in the microinstruction can be configured the same as or different from the channel mask included in the third macroinstruction, depending on the bit value of the broadcast bit. In one implementation, when the broadcast bit included in the third macroinstruction has a first binary value (e.g., binary value "1"), the instruction and data transmission scheme can be specified as a broadcast transmission scheme. In this case, the channel mask included in the microinstruction generated by the instruction decoder and sequencer 220 can be configured the same as the channel mask included in the third macroinstruction. On the other hand, when the broadcast bit has a second binary value (e.g., binary value "0"), the instruction and data transmission scheme can be specified as a non-broadcast transmission scheme. In this case, the channel mask included in the microinstruction generated by the instruction decoder and sequencer 220 can be configured differently from the channel mask included in the third macroinstruction.

[0072] Specifically, when the broadcast bit included in the third macro instruction has a binary value of "0", for each channel mask included in the microinstruction generated by the instruction decoder and sequencer 220, one bit in the channel mask (hereinafter referred to as the "channel bit") can have the same bit value as the corresponding bit in the channel mask included in the third macro instruction. Therefore, for each channel mask included in the microinstruction, the channel bit can have a binary value of "0" or "1", depending on the corresponding bit in the third macro instruction. Furthermore, all other bits in the channel mask included in each microinstruction, except for the channel bit, can have a binary value of "0".

[0073] In the fourth example, the instruction decoder and sequencer 220 generate local memory instructions and micro-instructions equal to the number of bits with binary values ​​of "1" in the channel mask bits included in the fourth macro instruction. In this fourth example, the local memory instructions generated by the instruction decoder and sequencer 220 may include a local memory command and a local memory address. The local memory command included in the local memory instructions may be specified as "RD_LM," indicating a read operation on local memory. The local memory address included in the local memory instructions can be sequentially incremented starting from the local memory address included in the fourth macro instruction.

[0074] In the fourth example, the microinstructions generated by the instruction decoder and sequencer 220 may include an operation type designated as the third operation type "WRBIAS", a channel mask, and a MAC latch ID. The channel mask included in the microinstructions generated by the instruction decoder and sequencer 220 is configured differently from the channel mask included in the fourth macro instruction. Specifically, among the bits of each channel mask included in the microinstruction, one bit (called the "channel bit") has a binary value of "1", while all other bits have a binary value of "0". The MAC latch ID included in the microinstruction may have the same value as the MAC latch ID included in the fourth macro instruction. When the fourth macro instruction includes a broadcast bit, each microinstruction generated in the fourth example may also include a broadcast bit. In this case, the broadcast bit included in each microinstruction may have the same value as the broadcast bit included in the fourth macro instruction.

[0075] Figures 4 to 6 This is a diagram illustrating various examples of channel masks included in macro instructions and channel masks included in micro instructions generated by the instruction decoder and sequencer. Figures 4 to 6 In the description, for example, assuming the number of channels is "j", the number of iterations included in the macro instruction is "m". Here, both "j" and "m" are natural numbers equal to or greater than 2.

[0076] like Figures 4 to 6As shown, in the following example, the channel mask included in the macro instruction is configured as a binary stream, comprising a number of bits equal to the channel number "j", i.e., from the first bit to the j-th bit. The first bit of the channel mask included in the macro instruction, i.e., the least significant bit (LSB), has a bit value "CM0". "CM0" can be a binary value "0" or "1". The second bit of the channel mask included in the macro instruction has a bit value "CM1", which can also be a binary value "0" or "1". Similarly, the ("j-1")-th bit of the channel mask included in the macro instruction has a bit value "CM"j-2, which can also be a binary value "0" or "1". The j-th bit of the channel mask, i.e., the most significant bit (MSB), has a bit value "CM"j-1, which can also be a binary value "0" or "1".

[0077] First refer to Figure 4 For example, suppose a first macro instruction is input to the instruction decoder and sequencer 220. Although not shown in the figure, the first macro instruction may include an operation type designated as a first operation type "MAC", an iteration number designated as "m", and a channel mask configured as a binary stream "CMj-1 CMj-2 ...CM1 CM0". The following description based on this example can also be applied to the case of inputting a second macro instruction, which includes an operation type designated as a second operation type "WRGB", an iteration number designated as "m", a broadcast bit designated as a binary value "1", and a channel mask configured as a binary stream "CMj-1 CMj-2 ...CM1 CM0". Furthermore, the following description can also be applied to the case of inputting a third macro instruction, which includes an operation type designated as a second operation type "WRGB", an iteration number designated as "m", a broadcast bit designated as a binary value "1", a channel mask configured as a binary stream "CMj-1 CMj-2 ...CM1 CM0", and a local memory increment size.

[0078] The instruction decoder and sequencer 220 generate and output multiple microinstructions, for example, first to "m"th microinstructions, the number of which equals the number of iterations "m". The first to "m"th microinstructions each include a first to "m"th channel mask. For example, the first microinstruction includes a first channel mask, the second microinstruction includes a second channel mask, and similarly, the "m"th microinstruction includes an "m"th channel mask. Each of the first to "m"th channel masks includes first to j-th bits, identical to those bits included in the channel mask of the first macroinstruction. The first to j-th bits of each of the first to "m"th channel masks have the same bit values ​​as the first to j-th bits of the channel mask included in the first macroinstruction. That is, each of the first to "m"th channel masks is configured as the same binary stream "CMj-1 CMj-2 ...CM1 CM0".

[0079] Next, refer to Figure 5 For example, suppose a second macro instruction with the broadcast bit specified as a binary value "0" is input to the instruction decoder and sequencer 220. Although not shown in the figure, the second macro instruction may include an operation type specified as the second operation type "WRGB", an iteration number specified as "m", a broadcast bit specified as a binary value "0", and a channel mask configured as a binary stream "CMj-1 CMj-2 ...CM1 CM0". The following description of this example can also be applied to the case where a third macro instruction with the broadcast bit specified as a binary value "0" is input to the instruction decoder and sequencer 220. The third macro instruction may include an operation type specified as the second operation type "WRGB", an iteration number specified as "m", a channel mask configured as a binary stream "CMj-1 CMj-2 ...CM1 CM0", a broadcast bit specified as a binary value "0", and a local memory increment size.

[0080] The instruction decoder and sequencer 220 generate and output multiple microinstructions, such as the first to the "m×t"th microinstructions, where "t" is the number of bits with a value of "1" in the first to j-th bits of the channel mask included in the second macro instruction, and "m" is the number of iterations. Here, "t" represents a natural number from 0 to j. In one example, when the i-th bit in the first to j-th bits of the channel mask included in the second macro instruction has a binary value of "1", the instruction decoder and sequencer 220 generate "m" i-th microinstructions. These "m" i-th microinstructions all include the i-th channel mask. In another example, when all bit values ​​(CM0 to CMj-1) of the channel mask included in the second macro instruction are "1", the instruction decoder and sequencer 220 generate and output "m×j" microinstructions. In other words, when the broadcast bit included in the second macro instruction has a binary value of "0", the instruction decoder and sequencer 220 can generate and output up to "m×j" microinstructions.

[0081] The following describes the case where all bits of the channel mask included in the second macro instruction are "1", i.e., all bits of CM0 to CMj-1 are binary values ​​of "1". In this case, the instruction decoder and sequencer 220 output the first to the "m×j"th microinstructions, each with a corresponding first to the "m×j"th channel mask. The first microinstruction output from the instruction decoder and sequencer 220 includes the first channel mask. The second microinstruction output from the instruction decoder and sequencer 220 includes the second channel mask. Similarly, the "m×j"th microinstruction output from the instruction decoder and sequencer 220 includes the "m×j"th channel mask.

[0082] When the instruction decoder and sequencer 220 generate "m×t" microinstructions, the "m×t" channel masks can be divided into first to "m" groups, each group including "t" channel masks. In this example, since "t" equals "j", each group in the first to "m" groups includes "j" channel masks. Hereinafter, the "j" channel masks included in each group in the first to "m" groups will be referred to as the first to "j" sub-channel masks. The first to "j" sub-channel masks included in the first group correspond to the first to "j" channel masks in the first to "m×t" channel masks. The first to "j" sub-channel masks included in the second group correspond to the (j+1) to "2×j" channel masks in the first to "m×t" channel masks. Similarly, the first to "j" sub-channel masks included in the m-th group correspond to the ("m×tt") to "m×t" channel masks in the first to "m×t" channel masks.

[0083] Each of the first to the m-th groups includes first to the j-th sub-channel masks, and the number of bits in each sub-channel mask is the same as the number of bits in the channel mask included in the second macro instruction. Since the channel mask included in the second macro instruction includes first to the j-th bits, each of the first to the j-th sub-channel masks included in each of the first to the m-th groups also includes first to the j-th bits. In each of the first to the m-th groups, the first bit of each of the first to the j-th sub-channel masks corresponds to the LSB, and the j-th bit corresponds to the MSB.

[0084] In each of the first to the "m"th groups, the first to the jth sub-channel masks are configured with the same binary stream for the i-th sub-channel mask (where i is a natural number from 1 to j). In other words, in the first to the "m×j"th channel masks, the "(n-1)×j+i"th channel mask (i.e., the i-th sub-channel mask of each of the first to the "m"th groups) is configured with the same binary stream. Here, "n" represents the first to the "m"th groups, and "n" is a natural number from 1 to "m". For example, when "i" = 1, the first sub-channel masks of the first to the "m"th groups (i.e., the "(n-1)×j+1"th channel mask) are all configured with the same binary stream. When "i" = 2, the second sub-channel masks of the first to the "m"th groups (i.e., the "(n-1)×j+2"th channel mask) are all configured with the same binary stream. Similarly, when "i" = "j", the j-th sub-channel mask of the first to the "m"th groups (i.e. the "(n-1)×j+j"th channel mask) are all configured to the same binary stream.

[0085] In each of the first to the "m"th groups, the i-th bit of the i-th sub-channel mask is designated as the channel bit. This channel bit, i.e., the i-th bit of each i-th sub-channel mask in each of the first to the "m"th groups, has the same bit value as the i-th bit of the first to the "j"th bits of the channel mask included in the second macro instruction, i.e., a bit value of "1". Furthermore, all bits other than the channel bit in the first to the "j"th bits of each i-th sub-channel mask in each of the first to the "m"th groups have a binary value of "0".

[0086] like Figure 5As shown, in the case of the first ("i"=1) sub-channel mask of the first group, the channel bit, i.e., the first ("i"=1) bit, has the same bit value CM0 as the first bit of the channel mask included in the second macro instruction, i.e., the binary value "1", while the second to j bits all have the binary value "0". In the case of the second ("i"=2) sub-channel mask of the first group, the channel bit, i.e., the second ("i"=2) bit, has the same bit value CM1 as the second bit of the channel mask included in the second macro instruction, i.e., the binary value "1", while the first bit and the third to j bits all have the binary value "0". Similarly, in the case of the ("j-1") ("i"="j-1") sub-channel mask of the first group, the channel bit, i.e., the ("j-1") ("i"="j-1") bit, has the same bit value CMj-2 as the ("j-1") bit of the channel mask included in the second macro instruction, which is the binary value "1", while the first to ("j-2") bits and the j-th bit all have the binary value "0". Likewise, in the case of the j("i"="j") sub-channel mask of the first group, the channel bit, i.e., the j("i"="j") bit, has the same bit value CMj-1 as the j-th bit of the channel mask included in the second macro instruction, which is the binary value "1", while the first to ("j-1") bits all have the binary value "0".

[0087] In the case of the first ("i"=1) sub-channel mask of the second group (i.e., the (j+1)th channel mask), the channel bit, i.e., the first ("i"=1) bit, has the same bit value CM0 as the first bit of the channel mask included in the second macro instruction, i.e., the binary value "1", while the second to jth bits all have the binary value "0". Similarly, in the case of the jth ("i"="j") sub-channel mask of the second group (i.e., the (j+j)th channel mask), the channel bit, i.e., the jth ("i"="j") bit, has the same bit value CMj-1 as the jth bit of the channel mask included in the second macro instruction, i.e., the binary value "1", while the first to ("j-1")th bits all have the binary value "0".

[0088] Similarly, in the case of the first ("i"=1) sub-channel mask of the "m"th group (i.e., the ((m-1)×j+1)th channel mask), the channel bit, i.e., the first ("i"=1)th bit, has the same bit value CM0 as the first bit of the channel mask included in the second macro instruction, i.e., the binary value "1", while the second to jth bits all have the binary value "0". Likewise, in the case of the j ("i"="j") sub-channel mask of the "m"th group (i.e., the ((m-1)×j+j)th channel mask), the channel bit, i.e., the j ("i"="j")th bit, has the same bit value CMj-1 as the jth bit of the channel mask included in the second macro instruction, i.e., the binary value "1", while the first to ("j-1")th bits all have the binary value "0".

[0089] Next, refer to Figure 6 For example, suppose a fourth macro instruction is input to the instruction decoder and sequencer 220. Although not shown in the figure, the fourth macro instruction may include an operation type specified as the third operation type "WRBIAS", an iteration number specified as "m", and a channel mask configured as a binary stream "CMj-1 CMj-2 ...CM1 CM0".

[0090] The instruction decoder and sequencer 220 generate a certain number of micro-instructions, for example, "t" micro-instructions, the number of which is equal to the number of bits with a binary value of "1" in the first to j-th bits of the channel mask included in the fourth macro instruction. For example, when the i-th bit in the first to j-th bits of the channel mask included in the fourth macro instruction has a binary value of "1", the instruction decoder and sequencer 220 generate the i-th micro-instruction, and the i-th micro-instruction includes the i-th channel mask. Figure 6 As shown, when all bits of the channel mask included in the fourth macro instruction are "1" (i.e., when CM0 to CMj-1 are all "1"), the instruction decoder and sequencer 220 generate the first to j micro-instructions, and each of the first to j micro-instructions includes the corresponding first to j channel mask. For example, the first micro-instruction includes the first channel mask, the second micro-instruction includes the second channel mask, the ("j-1")th micro-instruction includes the ("j-1")th channel mask, and similarly, the j-th micro-instruction includes the j-th channel mask.

[0091] Similar to the channel masks included in the fourth macro instruction, each of the first to j-th channel masks includes the first to j-th bits. In the first to j-th channel masks, the i-th channel mask (where "i" is a natural number from 1 to "j") has the i-th bit designated as the channel bit. This channel bit, i.e., the i-th bit of the i-th channel mask, has the same bit value as the i-th bit of the first to j-th bit masks included in the fourth macro instruction, i.e., the binary value "1". Furthermore, all bits of the i-th channel mask other than the channel bit, i.e., all bits of the first to j-th bit masks except the i-th bit, have the binary value "0". Figure 6 As shown, in the case of the first ("i"=1) channel mask, the channel bit, i.e., the first bit, has the same bit value as CM0 of the fourth macro instruction, i.e., the binary value "1", while the second to j bits all have the binary value "0". In the case of the second ("i"=2) channel mask, the channel bit, i.e., the second bit, has the same bit value as CM1 of the fourth macro instruction, i.e., the binary value "1", while the first bit and the third to j bits all have the binary value "0". Similarly, in the case of the ("j-1") ("i"="j-1") channel mask, the channel bit, i.e., the ("j-1") bit, has the same bit value as CMj-2 of the fourth macro instruction, i.e., the binary value "1", while the first to ("j-2") bits and the j bit all have the binary value "0". In the case of the j-th ("i"="j") channel mask, the channel bit, i.e. the j-th bit, has the same bit value as CMj-1 of the fourth macro instruction, i.e., the binary value "1", while the first to ("j-1") bits all have the binary value "0".

[0092] Refer again Figure 1Local memory 230 is coupled to instruction decoder and sequencer 220 and multicast interconnect 250. Local memory 230 can receive local memory instructions output from instruction decoder and sequencer 220. Local memory 230 performs local memory operations, such as local memory read operations and local memory write operations, based on local memory instructions. In one embodiment, in the case of a second or third example of an operation type designated as "WRGB", i.e., when the local memory instruction is generated by a second or third macro instruction, local memory 230 can output data stored at the storage location specified by the local memory address included in the local memory instruction, i.e., vector data, and transmit the vector data to multicast interconnect 250. In one embodiment, in the case of a fourth example of an operation type designated as "WRBIAS", i.e., when the local memory instruction is generated by a fourth macro instruction, local memory 230 can output data stored at the storage location specified by the local memory address included in the local memory instruction, i.e., bias data, and transmit the bias data to multicast interconnect 250. In one example, local memory 230 may include static random access memory (SRAM).

[0093] The Arithmetic Logic Unit (ALU) 240 can perform additional operations to assist the operations performed in the first to j-th PIM devices 110(0) to 110(j-1). ALU 240 can receive ALU instructions requesting additional operations from the instruction decoder and sequencer 220. In one example, ALU 240 can perform collective communication operations or collective communication computations, such as aggregation, full aggregation, reduction, reduction-dispersion, and full reduction operations. ALU 240 can receive data for collective communication operations or collective communication computations from network router 212 via multicast interconnect 250. ALU 240 can also transmit data generated as a result of collective communication computations to network router 212 via multicast interconnect 250.

[0094] Multicast interconnect 250 is coupled to instruction decoder and sequencer 220 and local memory 230. Multicast interconnect 250 can also be coupled to host interface 211, network router 212, and arithmetic logic unit (ALU) 240. Multicast interconnect 250 is coupled to first to j-th PIM controllers 260(0) to 260(j-1) via first to j-th channels CH0 to CH"j-1, respectively. Figure 1As shown, the multicast interconnect 250 is coupled to the first PIM controller 260 (0) via the first channel CH0. The multicast interconnect 250 is coupled to the second PIM controller 260 (1) via the second channel CH1. The multicast interconnect 250 is coupled to the "i"th PIM controller 260 (i-1) via the "i"th channel CH"i-1". Similarly, the multicast interconnect 250 is coupled to the ("j-1")th PIM controller 260 (j-2) via the ("j-1")th channel CH"j-2". The multicast interconnect 250 is coupled to the jth PIM controller 260 (j-1) via the jth channel CH"j-1".

[0095] Multicast interconnect 250 can receive microinstructions output from instruction decoder and sequencer 220. Multicast interconnect 250 can receive local memory data output from local memory 230, and can also transfer data to local memory 230. Multicast interconnect 250 can receive data from ALU 240, and can also transfer data to ALU 240. In one embodiment, when microinstructions are transferred from instruction decoder and sequencer 220 to multicast interconnect 250, multicast interconnect 250 can generate one or more sub-microinstruction sets based on the microinstructions. In another embodiment, when microinstructions and local memory data are transferred from instruction decoder and sequencer 220 and local memory 230 to multicast interconnect 250 respectively, multicast interconnect 250 can generate one or more sub-microinstruction sets based on the microinstructions and local memory data.

[0096] In one implementation, the multicast interconnect 250 can generate "t" sub-microinstruction sets, where "t" is the number of bits with binary values ​​of "1" in the first to j-th bits of the channel mask included in the first to "m" microinstructions. In this case, the multicast interconnect 250 can generate at most "j" sub-microinstruction sets. In another implementation, when "m×t" microinstructions are input to the multicast interconnect 250, the multicast interconnect 250 can generate "m×t" sub-microinstruction sets corresponding to the number of microinstructions. In this case, the multicast interconnect 250 can generate at most "m×j" sub-microinstruction sets. In yet another implementation, when "t" microinstructions are input to the multicast interconnect 250, the multicast interconnect 250 can generate "t" sub-microinstruction sets corresponding to the number of microinstructions. In this case, the multicast interconnect 250 can generate at most "j" sub-microinstruction sets.

[0097] More specifically, in a first example where the first macro instruction is input into the PIM central system 200, the multicast interconnect 250 receives the first through "m" micro instructions from the instruction decoder and sequencer 220. As previously stated, "m" represents the number of iterations included in the first macro instruction. When the i-th bit of the first through j-th bits of the channel mask included in each of the first through "m" micro instructions has a binary value of "1", the multicast interconnect 250 generates the i-th sub-micro instruction set. Conversely, when the i-th bit of the first through j-th bits of the channel mask included in each of the first through "m" micro instructions has a binary value of "0", the multicast interconnect 250 does not generate the i-th sub-micro instruction set.

[0098] For example, in the first example, when each channel mask included in the first through "m" microinstructions is "1111 11111111 1111", that is, when all of the first through sixteenth bits of each channel mask have a binary value of "1", the multicast interconnect 250 generates the first through sixteenth sub-microinstruction sets. In another example, when each channel mask included in the first through "m" microinstructions is "0000 1111 0000 1111", that is, when the first through fourth bits and the ninth through twelfth bits of each channel mask have a binary value of "1", the multicast interconnect 250 generates the first through fourth sub-microinstruction sets and the ninth through twelfth sub-microinstruction sets. Furthermore, the fifth through eighth sub-microinstruction sets and the thirteenth through sixteenth sub-microinstruction sets are not generated. Each sub-microinstruction set generated in the first example may include the first through "m" sub-microinstructions. Each of the first through "m" sub-microinstructions may include an operation type, row address, and column address designated as the first operation type "MAC".

[0099] In the second example where a second macro instruction is input into the PIM central system 200, and in the third example where a third macro instruction is input into the PIM central system 200, when both the second and third macro instructions include broadcast bits designated as binary values ​​"1", the multicast interconnect 250 receives first to "m"th local memory data from local memory 230 and first to "m"th micro instructions from the instruction decoder and sequencer 220. The multicast interconnect 250 generates "t" sub-micro instruction sets, where "t" is the number of bits with binary values ​​"1" in the first to j-th bits of the channel mask included in the first to "m"th micro instructions. For example, when the i-th bit of the first to j-th bits of the channel mask included in the first to "m"th micro instructions has a binary value "1", the multicast interconnect 250 generates the i-th sub-micro instruction set. Conversely, when the i-th bit has a binary value "0", the multicast interconnect 250 does not generate the i-th sub-micro instruction set. Each i-th submicro instruction set may include first to "m" submicro instructions. Each of the first to "m" submicro instructions may include an operation type designated as the second operation type "WRGB", local memory data, and a column address.

[0100] In the second and third examples, where both the second and third macro instructions include a broadcast bit designated as a binary value "0", the multicast interconnect 250 generates "m×t" sub-microinstruction sets corresponding to the number of "m×t" microinstructions. Specifically, when the i-th microinstruction among the "m×t" microinstructions is input to the multicast interconnect 250, the multicast interconnect 250 generates the "(n-1)×j+i" sub-microinstruction set for the i-th channel CH "i-1". Conversely, when the i-th microinstruction among the "m×t" microinstructions is not input, the multicast interconnect 250 does not generate the "(n-1)×j+i" sub-microinstruction set. In one embodiment, each "(n-1)×j+i" sub-microinstruction set may include an operation type designated as the second operation type "WRGB", local memory data, and a column address.

[0101] In the fourth example where the fourth macro instruction is input to the PIM central system 200, the multicast interconnect 250 receives first to j-th local memory data from local memory 230 and first to j-th microinstructions from the instruction decoder and sequencer 220. When the i-th microinstruction among the first to j-th microinstructions is input to the multicast interconnect 250, the multicast interconnect 250 generates the i-th sub-microinstruction set. Conversely, when the i-th microinstruction among the first to j-th microinstructions is not input to the multicast interconnect 250, the multicast interconnect 250 does not generate the i-th sub-microinstruction set. In one embodiment, the i-th sub-microinstruction set may include an operation type designated as the third operation type "WRBIAS", local memory data, and a MAC latch ID.

[0102] Multicast interconnect 250 transmits submicro instruction sets to one or more of the first to j-th PIM controllers 260(0) to 260(j-1). First, in a first example where the operation type included in the macro instruction is specified as the first operation type "MAC", for example, it is assumed that multicast interconnect 250 generates the i-th submicro instruction set. In this case, multicast interconnect 250 transmits the i-th submicro instruction set to the i-th PIM controller 260(i-1) via the i-th channel CH"i-1". Similarly, in the second and third examples where the broadcast bit has a binary value "1" and the operation type is specified as the second operation type "WRGB", multicast interconnect 250 transmits the i-th submicro instruction set to the i-th PIM controller 260(i-1) via the i-th channel CH"i-1. In these cases, multicast interconnect 250 sequentially transmits the first to "m" submicro instructions included in the i-th submicro instruction set to the i-th PIM controller 260(i-1).

[0103] Next, in the second and third examples where the macro instruction has a broadcast bit "0" and an operation type specified as "WRGB", for example, assume that the multicast interconnect 250 generates the "(n-1)×j+i"th submicro instruction set. In this case, the multicast interconnect 250 transmits the "(n-1)×j+i"th submicro instruction set to the i-th PIM controller 260 (i-1) via the i-th channel CH "i-1". For example, first, the multicast interconnect 250 transmits the first group ("n"=1) of the i-th submicro instruction set to the i-th PIM controller 260 (i-1) via the i-th channel CH "i-1". Next, the multicast interconnect 250 transmits the second group ("n"=2) of the (j+i)th submicro instruction set to the i-th PIM controller 260 (i-1) via the i-th channel CH "i-1". Next, the multicast interconnect 250 transmits the (2×j+i)th submicro instruction set of the third group ("n"=3) to the i-th PIM controller 260 (i-1) via the i-th channel CH"i-1. Similarly, the multicast interconnect 250 transmits the (3×j+i)th submicro instruction set of the fourth group ("n"=4) to the ((m-2)×j+i)th submicro instruction set of the ("m-1")th group sequentially to the i-th PIM controller 260 (i-1) via the i-th channel CH"i-1. Finally, the multicast interconnect 250 transmits the ((m-1)×j+i)th submicro instruction set to the i-th PIM controller 260 (i-1) via the i-th channel CH"i-1.

[0104] Next, in the fourth example where the operation type included in the macro instruction is specified as the third operation type "WRBIAS", for example, it is assumed that the multicast interconnect 250 generates the i-th submicro instruction set. In this case, the multicast interconnect 250 transmits the i-th submicro instruction set to the i-th PIM controller 260(i-1) via the i-th channel CH"i-1". For example, when generating the first to j-th submicro instruction sets in the fourth example, the multicast interconnect 250 transmits the first to j-th submicro instruction sets to the first to j-th PIM controllers 260(0) to 260(j-1) via the first to j-th channels CH0 to CH"j-1, respectively.

[0105] The first to j-th PIM controllers 260(0) to 260(j-1) are respectively coupled to the first to j-th PIM devices 110(0) to 110(j-1) through the first to j-th channels CH0 to CH"j-1". Figure 1 As shown, the first PIM controller 260(0) is coupled to the first PIM device 110(0) via the first channel CH0. The second PIM controller 260(1) is coupled to the second PIM device 110(1) via the second channel CH1. The i-th PIM controller 260(i-1) is coupled to the i-th PIM device 110(i-1) via the i-th channel CH"i-1". Similarly, the ("j-1")-th PIM controller 260(j-2) is coupled to the ("j-1")-th PIM device 110(j-2) via the ("j-1")-th channel CH"j-2". The j-th PIM controller 260(j-1) is coupled to the j-th PIM device 110(j-1) via the j-th channel CH"j-1".

[0106] In one embodiment, each of the first to j-th PIM controllers 260(0) to 260(j-1) may receive a submicro instruction set from the multicast interconnect 250. In this case, each of the first to j-th PIM controllers 260(0) to 260(j-1) may generate a PIM command set based on the received submicro instruction set. In another embodiment, each of the first to j-th PIM controllers 260(0) to 260(j-1) may receive one or more submicro instruction sets from the multicast interconnect 250. In this case, each of the first to j-th PIM controllers 260(0) to 260(j-1) may generate one or more PIM command sets based on the one or more submicro instruction sets.

[0107] More specifically, in the first example where the macro instruction has an operation type designated as the first operation type "MAC", when the i-th submicro instruction set is transmitted from the multicast interconnect 250, the i-th PIM controller 260 (i-1) generates the i-th PIM command set corresponding to the i-th submicro instruction set. In this case, the i-th PIM command set includes an activation PIM command and first to "m"th PIM commands. The activation PIM command may include a command (such as the "ACT" command) for activating a row of memory specified by a row address, and the row address itself. Each of the first to "m"th PIM commands may include an operation type designated as the first operation type "MAC" and a column address. The i-th PIM controller 260 (i-1) transmits the i-th PIM command set to the i-th PIM device 110 (i-1) via the i-th channel CH "i-1".

[0108] In the second and third examples where the macro instruction includes an operation type designated as the second operation type "WRGB" and a broadcast bit designated as the binary value "1", when the i-th submicro instruction set is transmitted from the multicast interconnect 250, the i-th PIM controller 260 (i-1) generates the i-th PIM command set corresponding to the i-th submicro instruction set. In this case, the i-th PIM command set includes first to "m" PIM commands. Each of the first to "m" PIM commands includes an operation type designated as "WRGB", local memory data, and a column address. The i-th PIM controller 260 (i-1) transmits the i-th PIM command set to the i-th PIM device 110 (i-1) via the i-th channel CH "i-1".

[0109] In the second and third examples where the macro instruction includes an operation type designated as the second operation type "WRGB" and a broadcast bit designated as the binary value "0", when the "(n-1)×j+i"th submicro instruction set is transmitted from the multicast interconnect 250 to the i-th PIM controller 260 (i-1), the i-th PIM controller 260 (i-1) generates the corresponding "(n-1)×j+i"th PIM command set. In this case, each "(n-1)×j+i"th PIM command set includes an operation type designated as "WRGB", local memory data, and a column address. The i-th PIM controller 260 (i-1) transmits each "(n-1)×j+i"th PIM command set to the i-th PIM device 110 (i-1) via the i-th channel CH "i-1".

[0110] In the fourth example where the macro instruction includes an operation type designated as the third operation type "WRBIAS", when the i-th submicro instruction set is transmitted from the multicast interconnect 250, the i-th PIM controller 260 (i-1) generates the i-th PIM command set corresponding to the i-th submicro instruction set. In this case, the i-th PIM command set includes the operation type designated as "WRBIAS", local memory data, and MAC latch ID. The i-th PIM controller 260 (i-1) transmits the i-th PIM command set to the i-th PIM device 110 (i-1) via the i-th channel CH"i-1".

[0111] Figure 7 This is a diagram illustrating an example of a first macro instruction used in a PIM system according to this disclosure.

[0112] Reference Figure 7 The first macro instruction 510 may include an operation type, a number of iterations, a channel mask, a row address, and a column address. In one embodiment, the column address, row address, channel mask, number of iterations, and operation type may be arranged in LSB to MSB order of the first macro instruction 510.

[0113] In one implementation, the operation type can be specified as a first operation type "MAC", which requests the execution of a MAC operation in the PIM device. The iteration number specifies the number of times the MAC operation will be executed in the PIM device. The channel mask includes bits corresponding to the channels included in the PIM system. For example, when the PIM system includes sixteen channels, the first bit of the channel mask, i.e., LSB, corresponds to the first channel CH0 among the first to sixteenth channels CH0 to CH15. The second bit of the channel mask corresponds to the second channel CH1 among the first to sixteenth channels. Similarly, the sixteenth bit of the channel mask, i.e., MSB, corresponds to the sixteenth channel CH15.

[0114] The channel for transmitting sub-micro instruction sets and PIM command sets can be determined based on the binary values ​​of the bits included in the channel mask. For example, among the first to j bits of the channel mask, when the i-th bit has a first binary value (such as "1"), the sub-micro instruction set and PIM command set can be transmitted through the i-th channel CH"i". Conversely, when the i-th bit has a second binary value (such as "0"), no sub-micro instruction set or PIM command set is transmitted through the i-th channel. The row address specifies the row of the memory bank storing the weight data used for MAC operations in the PIM device. The column address specifies the starting column address of the memory bank storing the weight data used for MAC operations and the starting storage location of the global buffer storing vector data.

[0115] Figures 8 to 10 It is shown in Figure 1Execution in the PIM system Figure 7 The diagram illustrates the process of the first macro instruction. In this example, it is assumed that the PIM system 10 includes channels CH0 through CH15, numbered from 1 to 16. Furthermore, it is assumed, for example, that the operation type, iteration count, channel mask, row address, and column address of the first macro instruction are set to operation type "MAC", iteration count "64", channel mask "1111 1111 1111 1111", row address "0", and column address "0", respectively.

[0116] Reference Figure 8 Upon receiving the first macro instruction, the instruction decoder and sequencer 220 decode the first macro instruction and generate a number of micro instructions equal to the iteration count "m" (i.e., 64). Since the iteration count in the first macro instruction is set to "64", the instruction decoder and sequencer 220 generate sixty-four micro instructions, namely the first to the sixty-fourth micro instructions. Each of the first to the sixty-fourth micro instructions includes an operation type, a channel mask, a row address, and a column address. The iteration count included in the first macro instruction is not included in the first to the sixty-fourth micro instructions. The operation type, channel mask, and row address included in each of the first to the sixty-fourth micro instructions are the same as those included in the first macro instruction. Specifically, the operation type of the first to the sixty-fourth micro instructions is specified as the first operation type "MAC", the channel mask is specified as "1111 1111 11111111", and the row address is specified as "0".

[0117] The column address values ​​included in the first through sixty-fourth microinstructions are different. That is, from the first microinstruction to the sixty-fourth microinstruction, the column address increments sequentially by one, starting from column address "0" included in the first macroinstruction. For example... Figure 8 As shown, the column address included in the first microinstruction is "0", which is the same as the starting column address of the first macroinstruction. The column address included in the second microinstruction is "1", which is the next value after the column address "0" of the first microinstruction. The column address included in the third microinstruction is "2", which is the next value after the column address "1" of the second microinstruction. Similarly, the column address included in the sixty-third microinstruction is "62", which immediately follows the column address "61" (not shown) of the sixty-second microinstruction. The column address included in the sixty-fourth microinstruction is "63", which immediately follows the column address "62" of the sixty-third microinstruction. The instruction decoder and sequencer 220 transmits the first to sixty-fourth microinstructions to the multicast interconnect 250.

[0118] Reference Figure 9The multicast interconnect 250 generates and outputs one or more sub-micro-instruction sets based on the first to sixty-fourth micro-instructions transmitted from the instruction decoder and sequencer 220. The number of sub-micro-instruction sets output by the multicast interconnect 250 can be determined by the channel mask included in each of the first to sixty-fourth micro-instructions. (See reference...) Figure 1 Each of the first to sixty-fourth microinstructions includes a corresponding channel mask. The first to sixty-fourth channel masks are identical to the channel masks included in the first macroinstruction and have the same binary stream. The number of sub-microinstruction sets output by the multicast interconnect 250 is equal to the number of bits with a binary value of "1" in any of the channel masks included in the first to sixty-fourth microinstructions. In this example, all of the first to sixty-fourth channel masks have the value "1111 1111 1111 1111", meaning that the first to sixteenth bits all have a binary value of "1". Therefore, the multicast interconnect 250 outputs the first to sixteenth sub-microinstruction sets.

[0119] Each sub-microinstruction set in the first through sixteenth sub-microinstruction sets includes sub-microinstructions one through sixty-four. Each sub-microinstruction in the first through sixty-fourth sub-microinstructions includes an operation type, a row address, and a column address. The operation type, row address, and column address included in each sub-microinstruction in the first through sixty-fourth sub-microinstructions are the same as those included in the corresponding first through sixty-fourth microinstructions. Therefore, each first sub-microinstruction included in the first through sixteenth sub-microinstruction sets has an operation type "MAC", a row address "0", and a column address "0". Each second sub-microinstruction included in the first through sixteenth sub-microinstruction sets has an operation type "MAC", a row address "0", and a column address "1". Similarly, each sixty-fourth sub-microinstruction included in the first through sixteenth sub-microinstruction sets has an operation type "MAC", a row address "0", and a column address "63".

[0120] Multicast interconnect 250 sequentially transmits the first to sixteenth submicro-instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15), respectively. Specifically, the first to sixty-fourth submicro-instructions included in the first submicro-instruction set are sequentially transmitted to the first PIM controller 260(0). The first to sixty-fourth submicro-instructions included in the second submicro-instruction set are sequentially transmitted to the second PIM controller 260(1). Similarly, the first to sixty-fourth submicro-instructions included in the sixteenth submicro-instruction set are sequentially transmitted to the sixteenth PIM controller 260(15). Thus, the first to sixteenth PIM controllers (PIMC0 to PIMC15) sequentially receive the first submicro-instructions from multicast interconnect 250. Subsequently, the first to sixteenth PIM controllers (PIMC0 to PIMC15) sequentially receive the second submicro-instructions from multicast interconnect 250. Although omitted in the figure, the first to sixteenth PIM controllers sequentially receive the third to sixty-fourth submicro-instructions from multicast interconnect 250 in the same manner. Finally, the first through sixteenth PIM controllers sequentially receive the sixty-fourth submicro instruction.

[0121] Reference Figure 10 The first to sixteenth PIM controllers 260(0) to 260(15) generate the first to sixteenth PIM command sets based on the first to sixteenth sub-micro instruction sets, respectively. The first to sixteenth PIM controllers 260(0) to 260(15) transmit the first to sixteenth PIM command sets to the first to sixteenth PIM devices 110(0) to 110(15), respectively. Figure 10 As shown, the first PIM controller 260 (0) transmits a first PIM command set generated based on a first sub-micro instruction set to the first PIM device 110 (0). The second PIM controller 260 (1) transmits a second PIM command set generated based on a second sub-micro instruction set to the second PIM device 110 (1). Similarly, the sixteenth PIM controller 260 (15) transmits a sixteenth PIM command set generated based on a sixteenth sub-micro instruction set to the sixteenth PIM device 110 (15). The transmission of the first to sixteenth PIM command sets from the first to sixteenth PIM controllers to the first to sixteenth PIM devices is performed in parallel.

[0122] In one implementation, each of the first to sixteenth PIM command sets includes an activation PIM command and first to sixty-fourth PIM commands. The activation PIM command includes an activation command (ACT) and a row address. Each of the first to sixty-fourth PIM commands includes an operation type and a column address. The row address included in the activation PIM command is the same as the row address included in the first to sixty-fourth sub-micro instructions. The operation type and column address included in the first to sixty-fourth PIM commands are respectively the same as the operation type and column address included in the corresponding first to sixty-fourth sub-micro instructions. Therefore, the activation PIM command includes the activation command "ACT" and row address "0". Each first PIM command included in the first to sixteenth PIM command sets includes an operation type "MAC" and column address "0". Each second PIM command included in the first to sixteenth PIM command sets includes an operation type "MAC" and column address "1". Similarly, each sixty-fourth PIM command included in the first to sixteenth PIM command sets includes an operation type "MAC" and column address "63".

[0123] Although not shown in the figure, upon receiving the first to sixteenth PIM command sets, the first to sixteenth PIM devices 110(0) to 110(15) activate the row in the memory specified by the row address "0" included in the activation PIM command. Subsequently, the processing elements included in the first to sixteenth PIM devices 110(0) to 110(15), in response to the first to sixty-fourth PIM commands, receive weight data stored in the column specified by the column address of the activated row in the memory, and vector data stored in the storage location specified by the column address of the global buffer. The processing elements included in the first to sixteenth PIM devices 110(0) to 110(15) perform a MAC (multiplication-accumulation) operation using the received weight data and vector data.

[0124] Figure 11 This is a diagram illustrating the second macro instruction used in the PIM system according to this disclosure.

[0125] Reference Figure 11 The second macro instruction 520 may include an operation type, iteration count, channel mask, local memory address, column address, and broadcast bits. In one embodiment, the broadcast bits, column address, local memory address, channel mask, iteration count, and operation type may be arranged in the second macro instruction 520 in order from LSB to MSB. The operation type may be specified as a second operation type "WRGB", which instructs to write data (e.g., vector data) to the global buffer GB of the PIM device (e.g., as shown in the image). Figure 2(As shown in the diagram). The iteration count specifies the number of write operations to be performed to write vector data to the global buffer of the PIM device. The channel mask can have multiple bits, each corresponding to one of the channels included in the PIM system. Based on the binary values ​​of the bits included in the channel mask, the channel to which the submicro instruction set and PIM command set are to be transmitted can be determined. The local memory address specifies the starting address in local memory where the vector data to be written to the global buffer of the PIM device is stored. The column address specifies the starting storage location in the storage area of ​​the global buffer where the vector data to be written is to be stored. The broadcast bit can be set to a first binary value, such as "1", or a second binary value, such as "0". When the broadcast bit has a first binary value, such as "1", the instruction and data transmission mode can be specified as a broadcast transmission mode. Conversely, when the broadcast bit has a second binary value, such as "0", the instruction and data transmission mode can be specified as a non-broadcast transmission mode, such as a unicast or multicast transmission mode.

[0126] Figures 12 to 14 It is shown in Figure 1 Execution in the PIM system Figure 11 A diagram illustrating an example process of the second macro instruction. In this example, it is assumed that the PIM system 10 includes channels CH0 to CH15, numbered from 1 to 16. Further, it is assumed that in the second macro instruction 520, the operation type is set to "WRGB", the iteration count is set to "64", the channel mask is set to "1111 11111111 1111", the local memory address is set to "0", the column address is set to "0", and the broadcast bit is set to "1".

[0127] Reference Figure 12 Upon receiving the second macro instruction, the instruction decoder and sequencer 220 decodes it and generates a number of local memory instructions and micro instructions equal to the number of iterations. Since the iteration number specified in the second macro instruction is "64", the instruction decoder and sequencer 220 generates sixty-four local memory instructions and sixty-four micro instructions. The instruction decoder and sequencer 220 transmits these sixty-four local memory instructions to local memory 230 and these sixty-four micro instructions to multicast interconnect 250.

[0128] Each of the sixty-four local memory instructions includes a local memory read command RD_LM and a local memory address. The local memory addresses included in these sixty-four instructions can have different values ​​from each other. Specifically, the local memory address included in the first local memory instruction is equal to the starting address of the local memory specified in the second macro instruction, i.e., "0". The local memory address included in the second local memory instruction is "1", i.e., the address following "0". Similarly, although not shown, the local memory address included in the third local memory instruction is "2", i.e., the address following "1", and so on. The local memory address included in the sixty-fourth local memory instruction is "63", which is the address following "62". In other words, the local memory addresses increment sequentially by "1" starting from "0".

[0129] Each of the sixty-four microinstructions includes an operation type, channel mask, column address, and broadcast bit. The number of iterations is not included in the microinstruction. Because the broadcast bit is set to "1", the channel masks included in the sixty-four microinstructions have the same binary stream. The operation type, channel mask, and broadcast bit included in each microinstruction are the same as those included in the second macroinstruction. Therefore, all sixty-four microinstructions have the same operation type ("WRGB"), the same channel mask ("1111 1111 1111 1111"), and the same broadcast bit ("1"). However, the column addresses included in the 64 microinstructions are different from each other.

[0130] Specifically, the column address included in the first microinstruction is "0", which is the same as the starting column address specified in the second macroinstruction. The column address included in the second microinstruction is "1", which is the next column address after "0", and so on. Although not shown, the column address of the sixty-third microinstruction is "62", and the column address of the sixty-fourth microinstruction is "63". Therefore, the column addresses increment sequentially by "1" starting from "0".

[0131] After receiving sixty-four local memory instructions from the instruction decoder and sequencer 220, the local memory 230 sequentially outputs sixty-four data values ​​DA0 to DA63 and transmits them to the multicast interconnect 250. Specifically, the first data DA0 output by the local memory 230 corresponds to the data stored in the first region of the local memory at address "0". The second data DA1 corresponds to the data stored in the second region at address "1". Similarly, although not shown, the sixty-fourth data DA63 corresponds to the data stored in the sixty-fourth region at address "63". The first to sixty-fourth regions of the local memory 230 can be arranged adjacently and consecutively.

[0132] Reference Figure 13The multicast interconnect 250 generates and outputs one or more sub-micro-instruction sets based on the first to sixty-fourth data DA0 to DA63 transmitted from local memory 230 and the first to sixty-fourth micro-instructions transmitted from the instruction decoder and sequencer 220. The number of sub-micro-instruction sets output from the multicast interconnect 250 can be determined based on the bit values ​​of the channel masks included in the first to sixty-fourth micro-instructions. Specifically, the number of sub-micro-instruction sets output by the multicast interconnect 250 is equal to the number of bits in the channel mask that have a binary value of "1". In this example, since the channel mask included in each of the first to sixty-fourth micro-instructions has the value "1111 1111 1111 1111" (which specifies all the first to sixteenth channels), the multicast interconnect 250 outputs the first to sixteenth sub-micro-instruction sets.

[0133] Each of the first to sixteenth submicro-instruction sets includes the first to sixty-fourth submicro-instructions. Each of the first to sixty-fourth submicro-instructions includes an operation type, data, and a column address. The operation type included in each of the first to sixty-fourth submicro-instructions is the same as the operation type included in the first to sixty-fourth micro-instructions. The data included in the first to sixty-fourth submicro-instructions respectively corresponds to the first to sixty-fourth data transferred from local memory 230 to multicast interconnect 250. The column addresses included in the first to sixty-fourth submicro-instructions are the same as the column addresses included in the first to sixty-fourth micro-instructions. Therefore, each first submicro-instruction included in each of the first to sixteenth submicro-instruction sets includes the operation type "WRGB", data DA0, and column address "0". Each second submicro-instruction includes the operation type "WRGB", data DA1, and column address "1". Similarly, each sixty-fourth submicro-instruction includes the operation type "WRGB", data DA63, and column address "63".

[0134] The multicast interconnect 250 sequentially transmits the first to sixteenth sub-micro instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15), respectively. Specifically, the multicast interconnect 250 sequentially transmits the first to sixty-fourth sub-micro instructions included in the first sub-micro instruction set to the first PIM controller 260(0). The multicast interconnect 250 sequentially transmits the first to sixty-fourth sub-micro instructions included in the second sub-micro instruction set to the second PIM controller 260(1). Similarly, the multicast interconnect 250 sequentially transmits the first to sixty-fourth sub-micro instructions included in the sixteenth sub-micro instruction set to the sixteenth PIM controller 260(15).

[0135] The transmission of the first to sixteenth submicro-instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15) can be performed in parallel. Specifically, the multicast interconnect 250 first transmits the first submicro-instruction included in the first to sixteenth submicro-instruction sets to the corresponding first to sixteenth PIM controllers 260(0) to 260(15). Then, the multicast interconnect 250 transmits the second submicro-instruction to the corresponding first to sixteenth PIM controller. This sequence also continues for the third to sixty-third submicro-instructions. Finally, the multicast interconnect 250 transmits the sixty-fourth submicro-instruction included in the first to sixteenth submicro-instruction sets to the corresponding first to sixteenth PIM controller.

[0136] Reference Figure 14 The first to sixteenth PIM controllers 260(0) to 260(15) generate the first to sixteenth PIM command sets based on the first to sixteenth sub-micro instruction sets, respectively. The first to sixteenth PIM controllers 260(0) to 260(15) transmit the corresponding PIM command sets to the first to sixteenth PIM devices 110(0) to 110(15) through the first to sixteenth channels CH0 to CH15, respectively. Specifically, the first PIM controller 260(0) generates the first PIM command set based on the first sub-micro instruction set and transmits the generated first PIM command set to the first PIM device 110(0). The second PIM controller 260(1) generates the second PIM command set based on the second sub-micro instruction set and transmits the generated second PIM command set to the second PIM device 110(1). Similarly, the sixteenth PIM controller 260 (15) generates the sixteenth PIM command set based on the sixteenth submicro instruction set and transmits the generated sixteenth PIM command set to the sixteenth PIM device 110 (15).

[0137] In one implementation, each of the first to sixteenth PIM command sets may include the first to sixty-fourth PIM commands. Each of the first to sixty-fourth PIM commands may include an operation type, local memory data, and a column address. The operation type, local memory data, and column address included in each of the first to sixty-fourth PIM commands are the same as those included in the first to sixty-fourth submicro-instructions. Therefore, each first PIM command included in the first to sixteenth PIM command sets includes the operation type "WRGB", local memory data DA0, and column address "0". Each second PIM command includes the operation type "WRGB", local memory data DA1, and column address "1". Similarly, each sixty-fourth PIM command includes the operation type "WRGB", local memory data DA63, and column address "63".

[0138] The transmission of the first to sixteenth PIM command sets from the first to sixteenth PIM controllers 260(0) to 260(15) to the first to sixteenth PIM devices 110(0) to 110(15) can be performed in parallel. Specifically, the first to sixteenth PIM controllers 260(0) to 260(15) respectively transmit the first PIM command included in the corresponding first to sixteenth PIM command sets to the corresponding first to sixteenth PIM devices 110(0) to 110(15). Then, the first to sixteenth PIM controllers transmit the second PIM command included in the corresponding command set. This process is also continued sequentially for the third to sixty-third PIM commands. Finally, the first to sixteenth PIM controllers transmit the sixty-fourth PIM command included in the corresponding command set.

[0139] Although not shown in the figures, each of the first to sixteenth PIM devices 110(0) to 110(15) stores the first to sixty-fourth data DA0 to DA63 included in the first to sixty-fourth PIM commands at sixty-four designated storage locations in a global buffer, specified by the corresponding column address. The first to sixty-fourth data stored in the global buffer of the first to sixteenth PIM devices 110(0) to 110(15) can be used as operand data, i.e., vector data, during the execution of operations by the processing elements included in the respective PIM devices.

[0140] Figures 15 to 18 It is shown in Figure 1 Execution in the PIM system Figure 11 A diagram illustrating another example of the second macro instruction's process. In this example, assume that PIM system 10 includes channels CH0 through CH15, numbered one through sixteen. Further assume that the operation type of the second macro instruction is set to "WRGB", the iteration count is set to "32", the channel mask is set to "1111 1111 11111111", the local memory address is set to "0", the column address is set to "0", and the broadcast bit is set to "0". (Refer to...) Figures 9 to 11 Compared to the example described above (where the number of iterations was set to "64" and the broadcast bit was set to a binary value of "1"), in this example, the number of iterations is set to "32" and the broadcast bit is set to a binary value of "0". Therefore, the differences between the two examples include the reduced number of iterations and the use of a non-broadcast transmission mode in this example.

[0141] Reference Figure 15When the second macro instruction, whose broadcast bit is set to a binary value of "0", is transmitted, the instruction decoder and sequencer 220 decode the second macro instruction to generate local memory instructions and micro instructions equal to the product of the iteration number and the number of bits with binary value "1" in the channel mask. Since the iteration number in the second macro instruction is set to "32" and the number of bits with binary value "1" in the channel mask is "16", the instruction decoder and sequencer 220 generate 32 × 16, i.e., 512 local memory instructions and 512 micro instructions, such as the first to the 512th local memory instructions and the first to the 512th micro instructions. The instruction decoder and sequencer 220 transmits the first to the 512th local memory instructions to the local memory 230 and the first to the 512th micro instructions to the multicast interconnect 250.

[0142] Each of the first through 512 local memory instructions includes a command specifying a local memory read operation, such as "RD_LM", and a local memory address. The local memory addresses included in the first through 512 local memory instructions have different values. In one embodiment, from the first through 512 local memory instructions, the local memory addresses are sequentially incremented by "1" starting from the initial address "0" specified by the second macro instruction. Specifically, the first local memory instruction includes the local memory address "0" corresponding to the initial address. The second local memory instruction includes the local memory address "1", which is the next address after "0". Similarly, although not shown in the figures, the 512 local memory instruction includes the local memory address "511", which immediately follows the 511 address "510".

[0143] Each of the first through 512 microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit. The operation type and broadcast bit included in the first through 512 microinstructions are the same as those included in the second macroinstruction. Therefore, each microinstruction is configured with an operation type set to the second operation type "WRGB" and a broadcast bit set to "0". The column addresses included in the first through 512 microinstructions have different values ​​from each other.

[0144] Specifically, the column addresses increment sequentially by "1" from the initial column address "0" specified in the second macro instruction. Therefore, the first microinstruction has a column address of "0". The second microinstruction has a column address of "1", immediately following the first. Although not explicitly stated, the third microinstruction has a column address of "2", immediately following the second. The sixteenth microinstruction has a column address of "15", immediately following the fifteenth ("14"). The 497th microinstruction has a column address of "496", immediately following the 496th ("495"). The 498th microinstruction has a column address of "497", immediately following the 497th ("496"). Finally, the 512th microinstruction has a column address of "511", immediately following the 511th ("510").

[0145] For reference Figure 5 The channel masks included in the first to the 512th microinstructions can be classified into thirty-two groups, for example, groups one to thirty-two, each group including sub-channel masks one to sixteenth. The first group includes the sub-channel masks one to sixteenth included in the first to sixteenth microinstructions, serving as sub-channel masks one to sixteenth. Although Figure 15 Not explicitly shown, but the second group includes the seventeenth to thirty-second channel masks included in the seventeenth to thirty-second microinstructions, respectively, as the first to sixteenth sub-channel masks. Similarly, the thirty-second group includes the four hundred and ninety-seventh to five hundred and twelveth channel masks included in the four hundred and ninety-seventh to five hundred and twelve microinstructions, respectively, as the first to sixteenth sub-channel masks.

[0146] In this example, since the number of channels "j" is "16" and the number of iterations "m" is "32", the "i"th sub-channel mask (where "i" is a natural number from "1" to "16") in the first to thirty-second groups are all configured using the same binary stream. Furthermore, in each "i"th sub-channel mask included in the first to thirty-second groups, only the "i"th bit designated as the channel bit has a binary value of "1", and all other bits have a binary value of "0".

[0147] like Figure 15As shown, in the first sub-channel masks of groups 1 to 32 (i.e., the channel masks included in microinstructions 1, 17, 33, 49, ..., 481, and 497), only the first bit designated as the channel bit has a binary value of "1", while the second to sixteenth bits all have a binary value of "0". Therefore, the first sub-channel masks of groups 1 to 32 are configured using the binary stream "0000 0000 0000 0001". In the second sub-channel masks of groups 1 to 32 (i.e., the channel masks included in microinstructions 2, 18, 34, 50, ..., 482, and 498), only the second bit designated as the channel bit has a binary value of "1", while the first bit and the third to sixteenth bits have a binary value of "0". Therefore, the second sub-channel masks of groups 1 to 32 are configured using the binary stream "0000 0000 0000 0010". Similarly, in the sixteenth sub-channel masks of groups one through thirty-two (i.e., the channel masks included in the sixteenth, thirty-second, forty-eighth, sixty-fourth, ..., four hundred and ninety-sixth, and five hundred and twelve microinstructions), only the sixteenth bit designated as the channel bit has a binary value of "1", while the first through fifteenth bits have a binary value of "0". Therefore, the sixteenth sub-channel masks of groups one through thirty-two are configured using the binary stream "1000 0000 0000 0000".

[0148] Reference Figure 16 When the local memory 230 receives the first to the fifth hundred and twelfth local memory instructions from the instruction decoder and sequencer 220, the local memory 230 sequentially outputs the first to the fifth hundred and twelfth local memory data DA0 to DA511 in response to these local memory instructions and transmits them to the multicast interconnect 250. Specifically, the first local memory data DA0 output from the local memory 230 corresponds to the data stored in the local memory 230 in the first region specified by the local memory address "0" included in the first local memory instruction. Subsequently, the second local memory data DA1 output from the local memory 230 corresponds to the data stored in the local memory 230 in the second region specified by the local memory address "1" included in the second local memory instruction. Similarly, the fifth hundred and twelfth local memory data DA511 output from the local memory 230 corresponds to the data stored in the local memory 230 in the fifth hundred and twelfth region specified by the local memory address "511" included in the fifth hundred and twelfth local memory instruction. Therefore, local memory 230 transmits the first to the fifth hundred and twelve local memory data DA0 to DA511 to multicast interconnect 250.

[0149] Reference Figure 17The multicast interconnect 250 receives first to fifth hundred and twelve local memory data DA0 to DA511 from local memory 230 and first to fifth hundred and twelve microinstructions from instruction decoder and sequencer 220. Since the broadcast bits included in the first to fifth hundred and twelve microinstructions are set to the binary value "0", the multicast interconnect 250 generates and outputs one or more sub-microinstruction sets based on the first to fifth hundred and twelve microinstructions and the first to fifth hundred and twelve local memory data DA0 to DA511. The number of sub-microinstruction sets output from the multicast interconnect 250 is the same as the number of microinstructions input to the multicast interconnect 250. Because the first to fifth hundred and twelve microinstructions are input to the multicast interconnect 250, the multicast interconnect 250 generates and outputs the first to fifth hundred and twelve sub-microinstruction sets.

[0150] Each of the first to 512 sub-micro instruction sets includes an operation type, local memory data, and a column address. The operation type included in each of the first to 512 sub-micro instruction sets is designated as a second operation type "WRGB," identical to the operation types included in the first to 512 microinstructions. The local memory data included in each of the first to 512 sub-micro instruction sets is identical to the local memory data DA0 to DA511 transferred from local memory 230 to multicast interconnect 250. Therefore, as... Figure 17 As shown, the first submicron instruction set includes first local memory data DA0. The second submicron instruction set includes second local memory data DA1. Similarly, the sixteenth submicron instruction set includes sixteenth local memory data DA15. The seventeenth submicron instruction set includes seventeenth local memory data DA16. The eighteenth submicron instruction set includes eighteenth local memory data DA17. Likewise, the thirty-second submicron instruction set includes thirty-second local memory data DA31. Similarly, the four hundred and ninety-seventh submicron instruction set includes four hundred and ninety-seventh local memory data DA496. The four hundred and ninety-eighth submicron instruction set includes four hundred and ninety-eighth local memory data DA497. Finally, the five hundred and twelve submicron instruction set includes five hundred and twelve local memory data DA511.

[0151] The column addresses included in the first to 512 sub-micro instruction sets are the same as those included in the first to 512 micro instructions. For example... Figure 17As shown, the first submicro instruction set includes operation type "WRGB", local memory data DA0, and column address "0". The second submicro instruction set includes operation type "WRGB", local memory data DA1, and column address "1". The sixteenth submicro instruction set includes operation type "WRGB", local memory data DA15, and column address "15". The seventeenth submicro instruction set includes operation type "WRGB", local memory data DA16, and column address "16". The eighteenth submicro instruction set includes operation type "WRGB", local memory data DA17, and column address "17". Similarly, the thirty-second submicro instruction set includes operation type "WRGB", local memory data DA31, and column address "31". Similarly, the four hundred and ninety-seventh submicro instruction set includes operation type "WRGB", local memory data DA496, and column address "496". The four hundred and ninety-eighth submicro instruction set includes operation type "WRGB", local memory data DA497, and column address "497". Similarly, the 512th submicro instruction set includes operation type "WRGB", local memory data DA511, and column address "511".

[0152] Since the broadcast bits included in the first to the 512th microinstructions are set to the binary value "0", the multicast interconnect 250 determines the channel for transmitting each of the first to the 512th sub-microinstruction sets based on the corresponding channel masks included in the first to the 512th microinstructions. Specifically, the multicast interconnect 250 transmits the "(n-1)×j+i"th sub-microinstruction set to the i-th PIM controller 260 (i-1) through the i-th channel CH"i-1". In this example, n represents a natural number from 1 to 32, indicating the group number, the channel count j is 16, and "i" is a natural number from 1 to 16.

[0153] like Figure 17 As shown, when i is "1", the multicast interconnect 250 transmits the first sub-micro instruction set corresponding to "n=1" to the first PIM controller 260(0) via the first channel CH0. Subsequently, the multicast interconnect 250 transmits the seventeenth sub-micro instruction set corresponding to n=2 to the first PIM controller 260(0) via the first channel CH0. In the same manner, the multicast interconnect 250 transmits the "(n-1)×16+1"th sub-micro instruction sets corresponding to n=3 to n=31 sequentially to the first PIM controller 260(0) via the first channel CH0. Finally, the multicast interconnect 250 transmits the four hundred and ninety-seventh sub-micro instruction set corresponding to n=32 to the first PIM controller 260(0) via the first channel CH0.

[0154] When i is "2", the multicast interconnect 250 transmits the second sub-micro instruction set corresponding to n=1 to the second PIM controller 260 (1) via the second channel CH1. Next, the multicast interconnect 250 transmits the eighteenth sub-micro instruction set corresponding to n=2 to the second PIM controller 260 (1) via the second channel CH1. In the same manner, the multicast interconnect 250 transmits the "(n-1)×16+2"th sub-micro instruction sets corresponding to n=3 to n=31 sequentially to the second PIM controller 260 (1) via the second channel CH1. Finally, the multicast interconnect 250 transmits the four hundred and ninety-eighth sub-micro instruction set corresponding to n=32 to the second PIM controller 260 (1) via the second channel CH1.

[0155] Similarly, when i is "16", the multicast interconnect 250 transmits the sixteenth submicro instruction set corresponding to n=1 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. Subsequently, the multicast interconnect 250 transmits the thirty-second submicro instruction set corresponding to n=2 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. In the same manner, the multicast interconnect 250 sequentially transmits the "(n-1)×16+16" submicro instruction sets corresponding to n=3 to n=31 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. Finally, the multicast interconnect 250 transmits the five hundred and twelfth submicro instruction set corresponding to n=32 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15.

[0156] Reference Figure 18 The first to sixteenth PIM controllers 260(0)-260(15) generate the first to five hundred and twelve PIM command sets based on the first to five hundred and twelve sub-micro instruction sets, respectively. The first to sixteenth PIM controllers 260(0)-260(15) transmit the first to five hundred and twelve PIM command sets to the first to sixteenth PIM devices 110(0)-110(15), respectively. The execution method of transmitting the first to five hundred and twelve PIM command sets from the first to sixteenth PIM controllers 260(0)-260(15) to the first to sixteenth PIM devices 110(0)-110(15) is the same as the execution method of transmitting the first to five hundred and twelve sub-micro instruction sets from the multicast interconnect 250 to the first to sixteenth PIM controllers 260(0)-260(15). Therefore, the i-th PIM controller 260 (i-1) transmits the "(n-1)×j+i" PIM command set to the i-th PIM device 110 (i-1) through the i-th channel CH (i-1).

[0157] like Figure 18As shown, when i is "1", the first PIM controller 260(0) transmits the first PIM command set corresponding to n=1 to the first PIM device 110(0) through the first channel CH0. Subsequently, the first PIM controller 260(0) transmits the seventeenth PIM command set corresponding to n=2 to the first PIM device 110(0) through the first channel CH0. In the same manner, the first PIM controller 260(0) transmits the "(n-1)×16+1"th PIM command sets corresponding to n=3 to n=31 sequentially to the first PIM device 110(0) through the first channel CH0. Finally, the first PIM controller 260(0) transmits the four hundred and ninety-seventh PIM command set corresponding to n=32 to the first PIM device 110(0) through the first channel CH0.

[0158] When i is "2", the second PIM controller 260 (1) transmits the second PIM command set corresponding to n=1 to the second PIM device 110 (1) through the second channel CH1. Subsequently, the second PIM controller 260 (1) transmits the eighteenth PIM command set corresponding to n=2 to the second PIM device 110 (1) through the second channel CH1. In the same manner, the second PIM controller 260 (1) transmits the "(n-1)×16+2"th PIM command sets corresponding to n=3 to n=31 sequentially to the second PIM device 110 (1) through the second channel CH1. Finally, the second PIM controller 260 (1) transmits the four hundred and ninety-eighth PIM command set corresponding to n=32 to the second PIM device 110 (1) through the second channel CH1.

[0159] Similarly, when i is "16", the sixteenth PIM controller 260 (15) transmits the sixteenth PIM command set corresponding to n=1 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15. Subsequently, the sixteenth PIM controller 260 (15) transmits the thirty-second PIM command set corresponding to n=2 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15. In the same manner, the sixteenth PIM controller 260 (15) transmits the "(n-1)×16+16" PIM command sets corresponding to n=3 to n=31 sequentially to the sixteenth PIM device 110 (15) via the sixteenth channel CH15. Finally, the sixteenth PIM controller 260 (15) transmits the five hundred and twelfth PIM command set corresponding to n=32 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15.

[0160] In one implementation, each of the first to the 512th PIM command sets includes an operation type, local memory data, and a column address. The operation type, local memory data, and column address included in each of the first to the 32nd PIM command sets are the same as those included in each of the first to the 512th submicro instruction sets.

[0161] like Figure 18 As shown, the first PIM command set includes an operation type set to "WRGB", local memory data set to "DA0", and a column address set to "0". The second PIM command set includes an operation type set to "WRGB", local memory data set to "DA1", and a column address set to "1". The sixteenth PIM command set includes an operation type set to "WRGB", local memory data set to "DA15", and a column address set to "15". The seventeenth PIM command set includes an operation type set to "WRGB", local memory data set to "DA16", and a column address set to "16". The eighteenth PIM command set includes an operation type set to "WRGB", local memory data set to "DA17", and a column address set to "17". Similarly, the thirty-second PIM command set includes an operation type set to "WRGB", local memory data set to "DA31", and a column address set to "31". Similarly, PIM command set 497 includes an operation type set to "WRGB", local memory data set to "DA496", and a column address set to "496". PIM command set 498 includes an operation type set to "WRGB", local memory data set to "DA497", and a column address set to "497". Likewise, PIM command set 512 includes an operation type set to "WRGB", local memory data set to "DA511", and a column address set to "511".

[0162] Although not shown in the figure, when transmitting the first to the 512th PIM command sets, the first to the sixteenth PIM devices 110(0)-110(15) store the first to the 512th local memory data DA0-DA511 as vector data in the storage location of the global buffer specified by the column address included in the corresponding PIM command set. Specifically, when transmitting the first to the sixteenth PIM command sets, the first to the sixteenth PIM devices 110(0)-110(15) store the first to the sixteenth local memory data DA0-DA15 as vector data in the storage location of the global buffer specified by the column address included in the corresponding first to sixteenth PIM command sets, respectively. Subsequently, when transmitting the seventeenth to the thirty-second PIM command sets, the first to the sixteenth PIM devices 110(0)-110(15) store the seventeenth to the thirty-second local memory data DA16-DA31 as vector data in the storage location of the global buffer specified by the corresponding column address, respectively. In the same manner, the thirty-third to the four hundred and ninety-sixth PIM command sets are processed in a similar way. Finally, when transmitting PIM command sets 497 to 512, the first to sixteenth PIM devices 110(0)-110(15) respectively store the local memory data DA496-DA511 of 497 to 512 as vector data in the storage location specified by the corresponding column address in the global buffer.

[0163] Therefore, the global buffer of the first PIM device 110 (0) stores local memory data corresponding to column addresses “0”, “16”, ..., and “496”, namely DA0, DA16, ..., and DA496. The global buffer of the second PIM device 110 (1) stores local memory data corresponding to column addresses “1”, “17”, ..., and “497”, namely DA1, DA17, ..., and DA497. Similarly, the global buffer of the sixteenth PIM device 110 (15) stores local memory data corresponding to column addresses “15”, “31”, ..., and “511”, namely DA15, DA31, ..., and DA511.

[0164] Figure 19 This is a diagram illustrating the third macro instruction used in the PIM system according to this disclosure.

[0165] Reference Figure 19The third macro instruction 530 may include an operation type, iteration count, channel mask, local memory address, column address, broadcast bits, and local memory increment size. In one embodiment, the local memory increment size, broadcast bits, column address, local memory address, channel mask, iteration count, and operation type may be arranged in the third macro instruction 530 in order from LSB to MSB. The operation type, channel mask, local memory address, column address, and broadcast bits included in the third macro instruction 530 may be consistent with reference to... Figure 11 The operation type, channel mask, local memory address, column address, and broadcast bits included in the second macro instruction 520 are configured identically. The local memory increment size included in the third macro instruction 530 specifies the increment size of the local memory address.

[0166] Figures 20 to 23 It is shown in Figure 1 Execution in the PIM system Figure 19 A diagram illustrating an example process of the third macro instruction. In this embodiment, it is assumed that the PIM system 10 includes channels CH0 to CH15, from the first to the sixteenth. Furthermore, it is assumed, for example, that the operation type, iteration count, channel mask, local memory address, column address, broadcast bit, and local memory increment size included in the third macro instruction are set to "WRGB", "64", "1111 1111 1111 1111", "0", "0", "1", and "2", respectively.

[0167] Reference Figure 20 Upon receiving the third macro instruction, the instruction decoder and sequencer 220 decode the third macro instruction and generate the same number of local memory instructions and microinstructions as the number of iterations specified in the third macro instruction. Since the number of iterations is set to "64", the instruction decoder and sequencer 220 generate 64 local memory instructions (i.e., the first to the sixty-fourth local memory instructions) and 64 microinstructions (i.e., the first to the sixty-fourth microinstructions). The instruction decoder and sequencer 220 transmits the first to the sixty-fourth local memory instructions to the local memory 230 and transmits the first to the sixty-fourth microinstructions to the multicast interconnect 250.

[0168] Each of the first through sixty-fourth local memory instructions includes a local memory command and a local memory address. The local memory command is set to "RD_LM", which indicates a read operation on local memory. The local memory addresses included in the first through sixty-fourth local memory instructions are all different from each other. Specifically, the local memory address starts from the local memory address "0" specified in the third macro instruction and is sequentially incremented by the size specified in the local memory increment size field, i.e., sequentially incremented by "2".

[0169] like Figure 20As shown, the first local memory instruction includes a local memory address "0", which is the same as the starting local memory address specified in the third macro instruction. The second local memory instruction includes a local memory address "2", which is obtained by incrementing "2" from the address of the first local memory instruction. The third local memory instruction includes a local memory address "4", which is obtained by further incrementing "2" from the address of the second local memory instruction. Similarly, the sixty-third local memory instruction includes a local memory address "124", which is obtained by incrementing "2" from the address "122" (not shown) included in the sixty-second local memory instruction. The sixty-fourth local memory instruction includes a local memory address "126", which is obtained by incrementing "2" from the address "124" included in the sixty-third local memory instruction.

[0170] Each of the first through sixty-four microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit. The operation type, channel mask, and broadcast bit included in each of the first through sixty-four microinstructions are the same as those included in the third macroinstruction. That is, the channel mask included in each of the first through sixty-four microinstructions is configured using the same binary stream "1111 1111 1111 1111", which is the same as the channel mask included in the third macroinstruction. On the other hand, the column addresses included in the first through sixty-four microinstructions have different values ​​from each other.

[0171] Specifically, the column address included in the first microinstruction is the same as the starting column address included in the third macroinstruction, i.e., "0". The column address included in the second microinstruction is the next column address value "1" that increments from the column address "0" of the first microinstruction. The column address included in the third microinstruction is the next column address value "2" that increments from the column address "1" of the second microinstruction. Similarly, the column address included in the sixty-fourth microinstruction is the next column address value "63" that increments from the column address "62" of the sixty-third microinstruction. Therefore, the column addresses included in the first to sixty-fourth microinstructions are sequentially incremented by "1" starting from the starting column address "0" included in the third macroinstruction.

[0172] Reference Figure 21The local memory 230, having received the first to sixty-fourth local memory instructions from the instruction decoder and sequencer 220, sequentially outputs the first to sixty-fourth local memory data DA0, DA2, ..., DA126 in response to the local memory instructions, and transmits the data to the multicast interconnect 250. First, the first local memory data DA0 output from the local memory 230 is data stored in the first region of the local memory 230 specified by the local memory address "0" included in the first local memory instruction. Subsequently, the second local memory data DA2 output from the local memory 230 is data stored in the second region of the local memory 230 specified by the local memory address "2" included in the second local memory instruction. Then, the third local memory data DA4 output from the local memory 230 is data stored in the third region of the local memory 230 specified by the local memory address "4" included in the third local memory instruction. Similarly, the sixty-third local memory data DA124, output from local memory 230 as the sixty-third data, is data stored in the sixty-third region of local memory 230 specified by the local memory address "124" included in the sixty-third local memory instruction. Finally, the sixty-fourth local memory data DA126, output from local memory 230, is data stored in the sixty-fourth region of local memory 230 specified by the local memory address "126" included in the sixty-fourth local memory instruction.

[0173] Reference Figure 22 The multicast interconnect 250 generates and outputs one or more sub-micro-instruction sets based on the first to sixty-fourth data DA0, DA2, ..., DA126 transmitted from local memory 230 and the first to sixty-fourth micro-instructions transmitted from the instruction decoder and sequencer 220. The number of sub-micro-instruction sets output by the multicast interconnect 250 can be determined based on the bit values ​​of any channel mask included in the first to sixty-fourth micro-instructions. Specifically, the number of sub-micro-instruction sets output by the multicast interconnect 250 corresponds to the number of bits in the first to sixteenth bits of the channel mask that are set to the binary value "1". In this example, because all the channel masks included in the first to sixty-fourth micro-instructions have the value "1111 1111 1111 1111" specifying all channels from the first to the sixteenth, the multicast interconnect 250 outputs the first to sixteenth sub-micro-instruction sets.

[0174] Each of the first to sixteenth submicro-instruction sets includes the first to sixty-fourth submicro-instructions. Each of the first to sixty-fourth submicro-instructions includes an operation type, data, and a column address. The operation type included in each of the first to sixty-fourth submicro-instructions is the same as the operation type included in the first to sixty-fourth micro-instructions. The data included in the first to sixty-fourth submicro-instructions is the same as the local memory data transferred from local memory 230 to multicast interconnect 250. The column address included in the first to sixty-fourth submicro-instructions is the same as the column address included in the first to sixty-fourth micro-instructions. Therefore, each first submicro-instruction included in the first to sixteenth submicro-instruction sets includes the second operation type "WRGB", data DA0, and column address "0". Each second submicro-instruction included in the first to sixteenth submicro-instruction sets includes "WRGB", data DA2, and column address "1". Similarly, each sixty-fourth submicro-instruction included in the first to sixteenth submicro-instruction sets includes "WRGB", data DA126, and column address "63".

[0175] Multicast interconnect 250 transmits the first to sixteenth sub-micro instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15), respectively. Specifically, multicast interconnect 250 transmits the first to sixty-fourth sub-micro instructions included in the first sub-micro instruction set sequentially to the first PIM controller 260(0). Multicast interconnect 250 transmits the first to sixty-fourth sub-micro instructions included in the second sub-micro instruction set sequentially to the second PIM controller 260(1). Similarly, multicast interconnect 250 transmits the first to sixty-fourth sub-micro instructions included in the sixteenth sub-micro instruction set sequentially to the sixteenth PIM controller 260(15).

[0176] The transmission of the first to sixteenth submicro-instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15) can be performed in parallel. Specifically, the multicast interconnect 250 simultaneously transmits the first submicro-instructions included in the first to sixteenth submicro-instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15). Next, the multicast interconnect 250 simultaneously transmits the second submicro-instructions included in the first to sixteenth submicro-instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15). Similarly, the third to sixty-third submicro-instructions included in the first to sixteenth submicro-instruction sets are transmitted to the corresponding PIM controllers in the same manner. Finally, the multicast interconnect 250 transmits the sixty-fourth submicro-instruction included in the first to sixteenth submicro-instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15). The terms "simultaneous" and "simultaneously" used in this document to refer to processes occurring within overlapping time intervals. For example, if the first process occurs within a first time interval, and the second process occurs simultaneously within a second time interval, then the first and second intervals at least partially overlap, such that there exists a time when both the first and second processes are occurring.

[0177] Reference Figure 23 The first to sixteenth PIM controllers 260(0) to 260(15) generate the first to sixteenth PIM command sets based on the first to sixteenth sub-micro instruction sets, respectively. The first to sixteenth PIM controllers 260(0) to 260(15) transmit the first to sixteenth PIM command sets to the first to sixteenth PIM devices 110(0) to 110(15) through the first to sixteenth channels CH0 to CH15, respectively. Specifically, the first PIM controller 260(0) generates the first PIM command set based on the first sub-micro instruction set and transmits the generated first PIM command set to the first PIM device 110(0). The second PIM controller 260(1) generates the second PIM command set based on the second sub-micro instruction set and transmits the generated second PIM command set to the second PIM device 110(1). Similarly, the sixteenth PIM controller 260 (15) generates the sixteenth PIM command set based on the sixteenth submicro instruction set and transmits the generated sixteenth PIM command set to the sixteenth PIM device 110 (15).

[0178] In one implementation, each of the first to sixteenth PIM command sets may include the first to sixty-fourth PIM commands. Each of the first to sixty-fourth PIM commands includes an operation type, local memory data, and a column address. The operation type, local memory data, and column address included in each of the first to sixty-fourth PIM commands are the same as those included in the first to sixty-fourth submicro-instructions. Therefore, each first PIM command included in the first to sixteenth PIM command sets includes the operation type "WRGB", local memory data DA0, and column address 0. Each second PIM command included in the first to sixteenth PIM command sets includes the operation type "WRGB", local memory data DA2, and column address 1. Similarly, each sixty-fourth PIM command included in the first to sixteenth PIM command sets includes the operation type "WRGB", local memory data DA126, and column address 63.

[0179] The transmission of the first to sixteenth PIM command sets from the first to sixteenth PIM controllers 260(0) to 260(15) to the first to sixteenth PIM devices 110(0) to 110(15) is performed in parallel. Specifically, the first to sixteenth PIM controllers 260(0) to 260(15) transmit the first PIM commands included in the first to sixteenth PIM command sets to the first to sixteenth PIM devices 110(0) to 110(15) respectively. Subsequently, the first to sixteenth PIM controllers 260(0) to 260(15) transmit the second PIM commands included in the first to sixteenth PIM command sets to the first to sixteenth PIM devices 110(0) to 110(15) respectively. The third to sixty-third PIM commands included in the first to sixteenth PIM command sets are transmitted to the first to sixteenth PIM devices 110(0) to 110(15) in the same manner. Finally, the first to sixteenth PIM controllers 260(0) to 260(15) respectively transmit the sixty-fourth sub-micro instruction included in the first to sixteenth sub-micro instruction set to the first to sixteenth PIM devices 110(0) to 110(15).

[0180] Although not shown in the figure, each of the first to sixteenth PIM devices 110(0) to 110(15) receiving the first to sixteenth PIM command sets stores the first to sixty-fourth data DA0, DA2, ..., DA126 in sixty-four storage locations in a global buffer specified by the column addresses included in the first to sixty-fourth PIM commands. The first to sixty-fourth data DA0, DA2, ..., DA126 stored in the global buffer of the first to sixteenth PIM devices 110(0) to 110(15) can be used as operand data, i.e., vector data, during operations performed by the processing elements included in the first to sixteenth PIM devices 110(0) to 110(15).

[0181] Figures 24 to 27 It is shown in Figure 1 Execution in the PIM system Figure 19 A diagram illustrating another example of the third macro instruction's process. In this example, assume that PIM system 10 includes channels CH0 through CH15, numbered one through sixteenth. The operation type, iteration count, channel mask, local memory address, column address, broadcast bits, and local memory increment size included in the third macro instruction are set to "WRGB", "64", "1111 1111 1111 1111", "0", "0", "0", and "2", respectively. (Refer to reference...) Figures 20 to 23 The example described above (where the broadcast bit of the third macro instruction is set to the binary value "1") differs from this example, where the broadcast bit of the third macro instruction is set to the binary value "0".

[0182] Reference Figure 24 When a third macro instruction with a broadcast bit set to a binary value of "0" is transmitted, the instruction decoder and sequencer 220 decode the third macro instruction and generate local memory instructions and micro instructions equal to the product of the iteration number and the number of bits with a binary value of "1" in the channel mask. Since the iteration number in the third macro instruction is set to "32" and the number of bits with a binary value of "1" in the channel mask is "16", the instruction decoder and sequencer 220 generates 512 local memory instructions (i.e., the first to the 512th local memory instructions) and 512 micro instructions (i.e., the first to the 512th micro instructions). The instruction decoder and sequencer 220 transmits the first to the 512th local memory instructions to local memory 230 and transmits the first to the 512th micro instructions to multicast interconnect 250.

[0183] The process of generating the first through 512 local memory instructions can be compared with the reference. Figure 15The described process is executed in essentially the same manner. Therefore, each of the first through 512 local memory instructions includes a local memory command (i.e., a read command for local memory (RD_LM)) and a local memory address. From the first to the 512th local memory instructions, the local memory address increments sequentially from the local memory address "0" included in the third macro instruction, by a local memory increment size of "2".

[0184] like Figure 24 As shown, the local memory address included in the first local memory instruction has the same value as the local memory address included in the third macro instruction, namely "0". The local memory address included in the second local memory instruction has the value "2", which is obtained by incrementing the first local memory address "0" by the local memory increment size "2". The local memory address included in the third local memory instruction has the value "4", which is obtained by incrementing the second local memory address "2" by the local memory increment size "2". In the same way, the local memory address included in the 511th local memory instruction has the value "1020", which is obtained by incrementing the 510th local memory address "1018" (not shown) by "2". The local memory address included in the 512th local memory instruction has the value "1022", which is obtained by incrementing the 511th local memory address "1020" by "2".

[0185] The process for generating the first through 512 microinstructions can be compared with reference to Figure 15 The described process is executed in essentially the same way. Therefore, each of the first through 512 microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit. The operation type and broadcast bit included in the first through 512 microinstructions are set to the second operation type "WRGB" and the binary value "0", respectively.

[0186] From the first microinstruction to the 512th microinstruction, the column address increments sequentially by 1, starting from the column address "0" included in the third macroinstruction. Therefore, the column address included in the first microinstruction has the same value as the starting column address, i.e., "0". The column address included in the second microinstruction has the value "1", and it is the next column address after the column address "0" included in the first microinstruction. Although from... Figure 24The column address in the third microinstruction is omitted, but it has the value "2", immediately following the column address "1" of the second microinstruction. Similarly, the column address in the sixteenth microinstruction has the value "15", immediately following the column address "14" of the fifteenth microinstruction (not shown). In the same way, the column address in the 497th microinstruction has the value "496", immediately following the column address "495" of the 496th microinstruction (not shown). The column address in the 498th microinstruction has the value "497", immediately following the column address "496" of the 497th microinstruction. Finally, the column address in the 512th microinstruction has the value "511", immediately following the column address "510" of the 511th microinstruction.

[0187] For reference Figure 5 The channel masks included in the first to 512 microinstructions can be divided into 32 groups, for example, groups one to thirty-second, each group including sub-channel masks one to sixteenth. The first group includes sub-channel masks one to sixteenth, which correspond to the sub-channel masks one to sixteenth included in the first to sixteenth microinstructions. Although in Figure 24 The first group is omitted, but the second group includes the first to sixteenth sub-channel masks, which correspond to the seventeenth to thirty-second channel masks included in the seventeenth to thirty-second microinstructions. Similarly, the thirty-second group includes the first to sixteenth sub-channel masks, which correspond to the 497th to 512th channel masks included in the 497th to 512th microinstructions.

[0188] In this embodiment, since the number of channels "j" is "16" and the number of iterations "m" is "32", the "i"th sub-channel mask (where "i" is a natural number from 1 to 16) in the first to sixteenth sub-channel masks of each of the first to thirty-second groups is configured using the same binary stream. Specifically, the "i"th sub-channel mask has a binary stream in which only the bit of the "i"th channel is set to the binary value "1", and all other bits are set to the binary value "0".

[0189] like Figure 24As shown, in the first sub-channel masks of groups 1 to 32 (i.e., the channel masks included in microinstructions 1, 17, 33, 49, ..., 481, and 497), only the first channel bit has a binary value of "1", while the second to sixteenth channel bits have a binary value of "0". That is, the first sub-channel masks of groups 1 to 32 are all configured using the binary stream "0000 0000 0000 0001". In the second sub-channel masks of groups 1 to 32 (i.e., the channel masks included in microinstructions 2, 18, 34, 50, ..., 482, and 498), only the second channel bit has a binary value of "1", while the first channel bit and the third to sixteenth channel bits have a binary value of "0". That is, the second sub-channel masks of groups 1 to 32 are all configured using the binary stream "0000 0000 0000 0010". Similarly, in the sixteenth sub-channel masks of groups one through thirty-two (i.e., the channel masks included in microinstructions sixteen, thirty-second, forty-eighth, sixty-fourth, ..., 496, and 512), only the sixteenth channel bit has a binary value of "1", while the first through fifteenth channel bits have a binary value of "0". Therefore, the sixteenth sub-channel masks of groups one through thirty-two are all configured using the binary stream "1000 0000 0000 0000".

[0190] Reference Figure 25The local memory 230, having received the first to the 512th local memory instructions from the instruction decoder and sequencer 220, sequentially outputs the first to the 512th data DA0, DA2, ..., DA1022 in response to the corresponding local memory instructions. The local memory 230 transmits the first to the 512th data DA0, DA2, ..., DA1022 to the multicast interconnect 250. The first data DA0 output from the local memory 230 corresponds to data stored in the local memory 230 in the first region specified by the local memory address "0" included in the first local memory instruction. The second data DA2 output from the local memory 230 corresponds to data stored in the local memory 230 in the second region specified by the local memory address "2" included in the second local memory instruction. Similarly, the third data DA4 output from the local memory 230 corresponds to data stored in the local memory 230 in the third region specified by the local memory address "4" included in the third local memory instruction. Similarly, the 511th data DA1020 output from local memory 230 corresponds to the data stored in local memory 230 in the 511th region specified by the local memory address "1020" included in the 511th local memory instruction. Finally, the 512th data DA1022 output from local memory 230 corresponds to the data stored in local memory 230 in the 512th region specified by the local memory address "1022" included in the 512th local memory instruction.

[0191] Reference Figure 26 The multicast interconnect 250 receives first to fifth-numbered data DA0, DA2, ..., DA1022 from local memory 230 and first to fifth-numbered microinstructions from instruction decoder and sequencer 220. Since the broadcast bits included in the first to fifth-numbered microinstructions are set to the binary value "0", the multicast interconnect 250 generates and outputs one or more sub-microinstruction sets based on the first to fifth-numbered microinstructions and the first to fifth-numbered data DA0, DA2, ..., DA1022. The number of sub-microinstruction sets output from the multicast interconnect 250 is the same as the number of microinstructions input to the multicast interconnect 250. Because the first to fifth-numbered microinstructions are input to the multicast interconnect 250, the multicast interconnect 250 generates and outputs the first to fifth-numbered sub-microinstruction sets.

[0192] Each of the first to 512 sub-microinstruction sets includes an operation type, local memory data, and a column address. The operation type included in each of the first to 512 sub-microinstruction sets is set to the second operation type "WRGB," the same as the operation types included in the first to 512 microinstructions. The local memory data included in each of the first to 512 sub-microinstruction sets corresponds to the first to 512 data DA0, DA2, ..., DA1022 transferred from local memory 230 to multicast interconnect 250. For example... Figure 26 As shown, the first submicro instruction set includes first local memory data DA0, the second submicro instruction set includes second local memory data DA2, and similarly, the 16th submicro instruction set includes 16th local memory data DA30. The 17th submicro instruction set includes 17th local memory data DA32, the 18th submicro instruction set includes 18th local memory data DA34, and similarly, the 32nd submicro instruction set includes 32nd local memory data DA62. In the same manner, the 497th submicro instruction set includes 497th local memory data DA992, the 498th submicro instruction set includes 498th local memory data DA994, and the 512th submicro instruction set includes 512th local memory data DA1022.

[0193] The column addresses included in the first to 512 sub-micro instruction sets are the same as those included in the first to 512 micro instructions. For example... Figure 26 As shown, the first submicro instruction set includes column address "0", the second submicro instruction set includes column address "1", and the 16th submicro instruction set includes column address "15". The 17th submicro instruction set includes column address "16", the 18th submicro instruction set includes column address "17", and similarly, the 32nd submicro instruction set includes column address "31". The 33rd submicro instruction set includes column address "32". In the same manner, the 497th submicro instruction set includes column address "496", the 498th submicro instruction set includes column address "497", and the 512th submicro instruction set includes column address "511".

[0194] Since the broadcast bits included in the first to the 512th microinstructions are set to the binary value "0", the multicast interconnect 250 determines the transmission channel for each of the first to the 512th sub-microinstruction sets based on the channel mask included in the corresponding microinstruction. Specifically, the multicast interconnect 250 transmits the "(n-1)×j+i"th sub-microinstruction set to the i-th PIM controller 260 (i-1) through the i-th channel CH (i-1), where n represents a natural number from 1 to 32, "j" represents the number of channels (which is 16), and "i" represents a natural number from 1 to 16.

[0195] like Figure 26As shown, when "i" equals 1, the multicast interconnect 250 transmits the first sub-micro instruction set corresponding to "n" equal to 1 to the first PIM controller 260(0) via the first channel CH0. Subsequently, the multicast interconnect 250 transmits the 17th sub-micro instruction set corresponding to "n" equal to 2 to the first PIM controller 260(0) via the first channel CH0. In the same manner, the multicast interconnect 250 transmits the "(n-1)×16+1"th sub-micro instruction set corresponding to "n" ranging from 3 to 31 to the first PIM controller 260(0) via the first channel CH0. Finally, the multicast interconnect 250 transmits the 497th sub-micro instruction set corresponding to "n" equal to 32 to the first PIM controller 260(0) via the first channel CH0.

[0196] When "i" equals 2, the multicast interconnect 250 transmits the second sub-micro instruction set corresponding to "n" equal to 1 to the second PIM controller 260 (1) via the second channel CH1. Next, the multicast interconnect 250 transmits the eighteenth sub-micro instruction set corresponding to "n" equal to 2 to the second PIM controller 260 (1) via the second channel CH1. Similarly, the multicast interconnect 250 transmits the "(n-1)×16+2"th sub-micro instruction set corresponding to "n" ranging from 3 to 31 to the second PIM controller 260 (1) via the second channel CH1. Finally, the multicast interconnect 250 transmits the 498th sub-micro instruction set corresponding to "n" equal to 32 to the second PIM controller 260 (1) via the second channel CH1.

[0197] Similarly, when "i" equals 16, the multicast interconnect 250 transmits the sixteenth submicro instruction set corresponding to "n" equal to 1 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. Subsequently, the multicast interconnect 250 transmits the thirty-second submicro instruction set corresponding to "n" equal to 2 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. Likewise, the multicast interconnect 250 transmits the "(n-1)×16+16" submicro instruction set corresponding to "n" ranging from 3 to 31 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. Finally, the multicast interconnect 250 transmits the 512th submicro instruction set corresponding to "n" equal to 32 to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15.

[0198] Reference Figure 27The first to sixteenth PIM controllers 260(0) to 260(15) generate the first to 512 PIM command sets based on the first to 512 sub-micro instruction sets, respectively. The first to sixteenth PIM controllers 260(0) to 260(15) transmit the first to 512 PIM command sets to the first to sixteenth PIM devices 110(0) to 110(15), respectively. The method of transmitting the first to 512 PIM command sets from the first to sixteenth PIM controllers 260(0) to 260(15) to the first to sixteenth PIM devices 110(0) to 110(15) can be performed in the same manner as the method of transmitting the first to 512 sub-micro instruction sets from the multicast interconnect 250 to the first to sixteenth PIM controllers 260(0) to 260(15). Therefore, the "i"th PIM controller 260 (i-1) transmits the "(n-1)×j+i"th PIM command set to the "i"th PIM device 110 (i-1) through the "i"th channel CH (i-1).

[0199] like Figure 27 As shown, when "i" equals 1, the first PIM controller 260(0) transmits the first PIM command set corresponding to "n" equal to 1 to the first PIM device 110(0) via the first channel CH0. Next, the first PIM controller 260(0) transmits the 17th PIM command set corresponding to "n" equal to 2 to the first PIM device 110(0) via the first channel CH0. Similarly, the first PIM controller 260(0) transmits the "(n-1)×16+1"th PIM command set corresponding to "n" ranging from 3 to 31 to the first PIM device 110(0) via the first channel CH0. Finally, the first PIM controller 260(0) transmits the 497th PIM command set corresponding to "n" equal to 32 to the first PIM device 110(0) via the first channel CH0.

[0200] When "i" equals 2, the second PIM controller 260 (1) transmits the second PIM command set corresponding to "n" equal to 1 to the second PIM device 110 (1) via the second channel CH1. Next, the second PIM controller 260 (1) transmits the 18th PIM command set corresponding to "n" equal to 2 to the second PIM device 110 (1) via the second channel CH1. Similarly, the second PIM controller 260 (1) transmits the "(n-1)×16+2"th PIM command set corresponding to "n" ranging from 3 to 31 to the second PIM device 110 (1) via the second channel CH1. Finally, the second PIM controller 260 (1) transmits the 498th PIM command set corresponding to "n" equal to 32 to the second PIM device 110 (1) via the second channel CH1.

[0201] In the same manner, when "i" equals 16, the sixteenth PIM controller 260 (15) transmits the sixteenth PIM command set corresponding to "n" equal to 1 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15. Next, the sixteenth PIM controller 260 (15) transmits the 32nd PIM command set corresponding to "n" equal to 2 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15. Similarly, the sixteenth PIM controller 260 (15) transmits the "(n-1)×16+16"th PIM command set corresponding to "n" ranging from 3 to 31 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15. Finally, the sixteenth PIM controller 260 (15) transmits the 512th PIM command set corresponding to "n" equal to 32 to the sixteenth PIM device 110 (15) via the sixteenth channel CH15.

[0202] In one implementation, each of the first through 512 PIM command sets includes an operation type, local memory data, and a column address. The operation types included in the first through 512 PIM command sets are the same as those included in the first through 512 sub-micro instruction sets. The local memory data included in the first through 512 PIM command sets is the same as that included in the first through 512 sub-micro instruction sets. The column addresses included in the first through 512 PIM command sets are the same as those included in the first through 512 sub-micro instruction sets.

[0203] like Figure 27 As shown, the operation types included in PIM command sets 1 through 512 are all set to "WRGB". The first PIM command set includes data and column addresses set to "DA0" and "0" respectively. The second PIM command set includes data and column addresses set to "DA2" and "1" respectively. Similarly, the sixteenth PIM command set includes data and column addresses set to "DA30" and "15" respectively. The seventeenth PIM command set includes data and column addresses set to "DA32" and "16" respectively. The eighteenth PIM command set includes data and column addresses set to "DA34" and "17" respectively. Likewise, the thirty-second PIM command set includes data and column addresses set to "DA62" and "31" respectively. In the same manner, the 497th PIM command set includes operation types, local memory data, and column addresses set to "WRGB", "DA992", and "496" respectively. The 498th PIM command set includes operation types, local memory data, and column addresses set to "WRGB", "DA994", and "497" respectively. Similarly, the 512PIM command set includes operation types, local memory data, and column addresses set to "WRGB", "DA1022", and "511", respectively.

[0204] Although not shown in the figure, when transmitting the first to the 512th PIM command sets, the first to the sixteenth PIM devices 110(0) to 110(15) respectively store the first to the 512th local memory data DA0, DA2, ..., DA1022 specified by the column addresses included in the first to the 512th PIM command sets as vector data in the storage location of the global buffer.

[0205] Specifically, when transmitting the first to sixteenth PIM command sets, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the first to sixteenth local memory data DA0, DA2, ..., DA30 specified by the column addresses included in the first to sixteenth PIM command sets as vector data in the corresponding storage locations of the global buffer. Subsequently, when transmitting the seventeenth to thirty-second PIM command sets, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the seventeenth to thirty-second local memory data DA32, DA34, ..., DA62 specified by the column addresses included in the seventeenth to thirty-second PIM command sets as vector data. In the same manner, the thirty-third to 496th PIM command sets are processed. Finally, when transmitting PIM command sets 497 to 512, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the local memory data DA992, DA994, ..., DA1022 specified by the column addresses included in the PIM command sets 497 to 512 as vector data.

[0206] Therefore, in the first PIM device 110 (0), local memory data DA0, DA32, ..., DA992 are stored in the global buffer at the storage locations specified by column addresses "0", "16", ..., and "496", respectively. In the second PIM device 110 (1), local memory data DA2, DA34, ..., DA994 are stored in the global buffer at the storage locations specified by column addresses "1", "17", ..., and "497", respectively. Similarly, in the sixteenth PIM device 110 (15), local memory data DA30, DA62, ..., DA1022 are stored in the global buffer at the storage locations specified by column addresses "15", "31", ..., and "511", respectively.

[0207] Figure 28 This is a diagram illustrating the fourth macro instruction used in the PIM system according to this disclosure.

[0208] Reference Figure 28The fourth macro instruction 540 may include an operation type, a channel mask, a local memory address, a MAC latch ID, and a broadcast bit. In one embodiment, the broadcast bit may be optionally omitted from the fourth macro instruction 540. In one embodiment, the broadcast bit, MAC latch ID, local memory address, channel mask, and operation type in the fourth macro instruction 540 may be arranged in LSB to MSB order.

[0209] In one implementation, the operation type can be set to "WRBIAS," which specifies the operation of latching data (such as bias data) into latching circuitry included in the processing element of the target PIM device. The channel mask can include bits corresponding to the channels included in the PIM system. Based on the binary values ​​of the bits included in the channel mask, the channels to which the submicron instruction set and PIM command set are to be transmitted can be specified. The local memory address can specify the starting address of the local memory storing the bias data to be latched into the latching circuitry of the PIM device. The MAC latch ID can specify the specific latching circuit to which the bias data is latched within the processing element of the PIM device. The broadcast bit can be set to a first binary value, such as "1," or a second binary value, such as "0." When the broadcast bit is set to the first binary value "1," the instruction and data transmission method can be specified as a broadcast transmission method, which transmits data to all channels in the same manner. Conversely, when the broadcast bit is set to the second binary value "0," the instruction and data transmission method can be specified as a unicast transmission method or a multicast transmission method, where transmission is performed differently for each channel.

[0210] Figures 29 to 31 It is shown in Figure 1 Execution in the PIM system Figure 28 A diagram illustrating the process of the fourth macro instruction. In this example, assume that the PIM system 10 includes channels CH0-CH15 from the first to the sixteenth. Furthermore, assume, for example, that the operation type, channel mask, local memory address, MAC latch ID, and broadcast bit included in the fourth macro instruction are set to “WRBIAS”, “1111 1111 1111 1111”, “0”, “0”, and “0”, respectively.

[0211] Reference Figure 29When transmitting the fourth macro instruction, the instruction decoder and sequencer 220 decode the fourth macro instruction to generate one or more local memory instructions and micro instructions. The number of local memory instructions and micro instructions generated by the instruction decoder and sequencer 220 corresponds to the number of bits with binary values ​​"1" in the channel mask included in the fourth macro instruction. Since the channel mask "1111 1111 1111 1111" included in the fourth macro instruction has sixteen bits, all with binary values ​​"1", the instruction decoder and sequencer 220 generates sixteen local memory instructions, namely the first to sixteenth local memory instructions, and 16 micro instructions, namely the first to sixteenth micro instructions. The instruction decoder and sequencer 220 transmits the first to sixteenth local memory instructions to local memory 230 and transmits the first to sixteenth micro instructions to multicast interconnect 250.

[0212] Each of the first through sixteenth local memory instructions includes a read command "RD_LM" for local memory and a local memory address. The local memory addresses included in the first through sixteenth local memory instructions have different values ​​from each other. Specifically, the local memory address of the first local memory instruction has the same value as the starting address of the local memory included in the fourth macro instruction, i.e., "0". The local memory address of the second local memory instruction has the address value "1" following the address "0" included in the first local memory instruction. Although not shown in the figure, the local memory address of the third local memory instruction is "2", which is the address following the address "1" of the second local memory instruction. Similarly, the local memory address of the sixteenth local memory instruction is "15", which is the address following the address "14" of the fifteenth local memory instruction.

[0213] Each of the first through sixteenth microinstructions includes an operation type, a channel mask, a MAC latch ID, and a broadcast bit. The operation type, MAC latch ID, and broadcast bit included in each of the first through sixteenth microinstructions are the same as those included in the fourth macroinstruction. Therefore, in the first through sixteenth microinstructions, the operation type, MAC latch ID, and broadcast bit are set to "WRBIAS", "0", and "0", respectively.

[0214] Each channel mask included in the first through sixteenth microinstructions consists of a binary stream of sixteen bits corresponding to the number of channels, i.e., the number of bits in the channel mask included in the fourth macroinstruction. Since the broadcast bit included in the fourth macroinstruction is set to "0", see reference... Figure 6 Therefore, in each of the first to sixteenth channel masks, only one bit is set to "1", and all other bits are set to "0".

[0215] like Figure 29 As shown, the first channel mask included in the first microinstruction has only the first bit (LSB) set to "1", while the second to sixteenth bits are all set to "0". In other words, the channel mask of the first microinstruction consists of the binary stream "0000 0000 0000 0001". The second channel mask included in the second microinstruction has only the second bit set to "1", while the first bit (LSB) and the third to sixteenth bits are all set to "0". Therefore, the channel mask of the second microinstruction consists of the binary stream "0000 0000 0000 0010". Similarly, the sixteenth channel mask included in the sixteenth microinstruction has only the sixteenth bit (MSB) set to "1", while the first to fifteenth bits are all set to "0". Therefore, the channel mask of the sixteenth microinstruction consists of the binary stream "1000 0000 0000 0000".

[0216] After receiving the first to sixteenth local memory instructions from the instruction decoder and sequencer 220, the local memory 230 sequentially outputs the first to sixteenth local memory data DA0 to DA15 in response to the corresponding local memory instructions, and transmits the output data to the multicast interconnect 250. Specifically, the first local memory data DA0 output from the local memory 230 corresponds to the data stored in the local memory 230 in the first region specified by the local memory address "0" included in the first local memory instruction. Next, the second local memory data DA1 output from the local memory 230 corresponds to the data stored in the second region specified by the local memory address "1" included in the second local memory instruction. Similarly, the sixteenth local memory data DA15 output from the local memory 230 last corresponds to the data stored in the sixteenth region specified by the local memory address "15" included in the sixteenth local memory instruction.

[0217] Reference Figure 30 The multicast interconnect 250 receives first to sixteenth data DA0 to DA15 from local memory 230 and first to sixteenth microinstructions from instruction decoder and sequencer 220. Based on the first to sixteenth microinstructions and the first to sixteenth data DA0 to DA15, the multicast interconnect 250 generates and outputs one or more sub-microinstruction sets. The number of sub-microinstruction sets output from the multicast interconnect 250 is the same as the number of microinstructions input to the multicast interconnect 250. In this example, since the first to sixteenth microinstructions are input to the multicast interconnect 250, the multicast interconnect 250 outputs first to sixteenth sub-microinstruction sets, each corresponding to a corresponding first to sixteenth microinstruction.

[0218] Each of the first to sixteenth sub-microinstruction sets includes an operation type, local memory data, and a MAC latch ID. The operation type included in each of the first to sixteenth sub-microinstruction sets is set to "WRBIAS," which is the same as the operation type included in the corresponding microinstruction. The local memory data included in each of the first to sixteenth sub-microinstruction sets corresponds to the first to sixteenth data DA0 to DA15 transferred from local memory 230 to multicast interconnect 250. Furthermore, the MAC latch ID included in each of the first to sixteenth sub-microinstruction sets is the same as the MAC latch ID included in the corresponding microinstruction.

[0219] like Figure 30 As shown, the first submicro instruction set includes operation type, data, and MAC latch ID set to "WRBIAS", "DA0", and "0", respectively. The second submicro instruction set includes operation type, data, and MAC latch ID set to "WRBIAS", "DA1", and "0", respectively. Similarly, the sixteenth submicro instruction set includes operation type, data, and MAC latch ID set to "WRBIAS", "DA15", and "0", respectively. Since the broadcast bits included in the first to sixteenth microinstructions have a value of "0", the multicast interconnect 250 transmits the first to sixteenth submicro instruction sets to the first to sixteenth PIM controllers 260(0) to 260(15), respectively. Specifically, the multicast interconnect 250 transmits the first submicro instruction set to the first PIM controller 260(0) via the first channel CH0. The multicast interconnect 250 transmits the second submicro instruction set to the second PIM controller 260(1) via the second channel CH1. Similarly, the multicast interconnect 250 transmits the sixteenth submicro instruction set to the sixteenth PIM controller 260 (15) via the sixteenth channel CH15. The transmission of the first to sixteenth submicro instruction sets to the corresponding first to sixteenth PIM controllers 260 (0) to 260 (15) is performed in parallel.

[0220] Reference Figure 31The first to sixteenth PIM controllers 260(0) to 260(15) generate the first to sixteenth PIM command sets based on the first to sixteenth sub-micro instruction sets, respectively. The first to sixteenth PIM controllers 260(0) to 260(15) transmit the corresponding PIM command sets to the corresponding PIM devices 110(0) to 110(15) in the first to sixteenth PIM devices 110(0) via the first to sixteenth channels, respectively. Specifically, the first PIM controller 260(0) transmits the first PIM command set to the first PIM device 110(0) via the first channel CH0. The second PIM controller 260(1) transmits the second PIM command set to the second PIM device 110(1) via the second channel CH1. Similarly, the sixteenth PIM controller 260(15) transmits the sixteenth PIM command set to the sixteenth PIM device 110(15) via the sixteenth channel CH15.

[0221] The transmission of the first to sixteenth PIM command sets to the corresponding PIM devices 110(0) to 110(15) is performed in parallel. In one embodiment, each of the first to sixteenth PIM command sets includes an operation type, local memory data, and a MAC latch ID. The operation type, local memory data, and MAC latch ID included in each of the first to sixteenth PIM command sets are the same as those included in the corresponding first to sixteenth submicro instruction sets.

[0222] Although not explicitly shown in the figure, each of the first to sixteenth PIM devices 110(0) to 110(15), upon receiving the corresponding first to sixteenth PIM command sets, stores the first to sixteenth local memory data DA0 to DA15 included in the corresponding PIM command set into the latch circuit specified by the MAC latch ID included in the corresponding PIM command set. Therefore, the first PIM device 110(0) latches the first local memory data DA0 as bias data into the latch circuit specified by MAC latch ID "0". The second PIM device 110(1) latches the second local memory data DA1 as bias data into the latch circuit specified by MAC latch ID "0". Similarly, the sixteenth PIM device 110(15) latches the sixteenth local memory data DA15 into the latch circuit specified by MAC latch ID "0".

[0223] Figure 32 This is a block diagram illustrating another embodiment of the PIM system according to the present disclosure.

[0224] Reference Figure 32The PIM system 20 includes multiple PIM devices, such as first to j-th PIM devices 110(0) to 110(j-1), and a PIM central system 600. Here, j is a natural number greater than or equal to 2. In one embodiment, the first to j-th PIM devices 110(0) to 110(j-1) are coupled to the PIM central system 600 via corresponding first to j-th channels CH0 to CH"j-1. Figure 32 As shown, the first PIM device 110(0) is coupled to the PIM central system 600 through the first channel CH0. The second PIM device 110(1) is coupled to the PIM central system 600 through the second channel CH1. The (j-1)th PIM device 110(j-2) is coupled to the PIM central system 600 through the (j-1)th channel CH"j-2", while the jth PIM device 110(j-1) is coupled to the PIM central system 600 through the jth channel CH"j-1".

[0225] Although Figure 32 Not explicitly shown, but in another embodiment, two or more PIM devices may share a single channel to be coupled to the PIM central system 600. In this case, the PIM system 20 may include a multiple of j of PIM devices. It should be noted that, referring to... Figure 1 The provided descriptions of the first to j-th PIM devices 110(0) to 110(j-1), and references Figure 2 and Figure 3 The descriptions provided regarding PIM devices and processing circuitry also apply to... Figure 32 The first to j-th PIM devices 110(0) to 110(j-1) are shown.

[0226] The PIM central system 600 controls the operation of the first to j-th PIM devices 110(0) to 110(j-1). The PIM central system 600 can be coupled to a host computer. Furthermore, the PIM central system 600 can be coupled to another PIM central system included in a different PIM system. The PIM central system 600 can receive macro instructions from the host computer. The PIM central system 600 can convert the received macro instructions into multiple sub-macro instructions. Furthermore, the PIM central system 600 can convert the multiple sub-macro instructions into multiple micro-instruction sets. The PIM central system 600 can generate multiple PIM command sets corresponding to the multiple micro-instruction sets and transmit the generated PIM command sets to the first to j-th PIM devices 110(0) to 110(j-1).

[0227] In one embodiment, the PIM central system 600 may include a multicast interconnect 610, first to j instruction decoders and sequencers (IDS0 to IDS"j-1") 620(0) to 620(j-1), first to j local memories (LM0 to LM"j-1") 630(0) to 630(j-1) and first to j PIM controllers (PIMC0 to PIMC"j-1") 640(0) to 640(j-1).

[0228] The multicast interconnect 610 is coupled to the first to j-th instruction decoders and sequencers 620(0) to 620(j-1) via corresponding first to j-th channels CH0 to CH"j-1. That is, the multicast interconnect 610 is coupled to the i-th instruction decoder and sequencer 620(i-1) via the i-th channel CH"i-1. Each of the first to j-th instruction decoders and sequencers 620(0) to 620(j-1) is coupled to the corresponding local memory in the first to j-th local memory 630(0) to 630(j-1). In addition, each of the first to j-th instruction decoders and sequencers 620(0) to 620(j-1) is also coupled to the corresponding PIM controller in the first to j-th PIM controller 640(0) to 640(j-1). Specifically, the i-th instruction decoder and sequencer 620 (i-1) are coupled to the i-th local memory 630 (i-1) and the i-th PIM controller 640 (i-1).

[0229] Each of the first to j-th local memories 630(0) to 630(j-1) is coupled to the corresponding PIM controller among the first to j-th PIM controllers 640(0) to 640(j-1). Specifically, among the first to j-th local memories 630(0) to 630(j-1), the i-th local memory 630(i-1) is coupled to the i-th PIM controller 640(i-1). Each of the first to j-th PIM controllers 640(0) to 640(j-1) is coupled to the corresponding PIM device among the first to j-th PIM devices 110(0) to 110(j-1) through the corresponding first to j-th channels CH0 to CH"j-1". That is, among the first to j-th PIM controllers 640(0) to 640(j-1), the i-th PIM controller 640(i-1) is coupled to the i-th PIM device 110(i-1) through the i-th channel CH"i-1". Although not shown in the diagram, the PIM center system 600 may also include a host interface, a network router, and a computing unit, similar to the reference. Figure 1 The PIM center system 200 is described.

[0230] The multicast interconnect 610 can receive macro instructions transmitted from the host. The multicast interconnect 610 can generate and output one or more sub-macro instructions based on the received macro instructions. The number of sub-macro instructions generated by the multicast interconnect 610 can be determined based on the bit values ​​included in the channel mask of the macro instructions. In one embodiment, the number of bits included in the channel mask of the macro instructions can be equal to the number of channels "j" included in the PIM system 20. Each bit of the "j" bits of the channel mask, specifically the first to the j-th bits, corresponds to the first to the j-th channels CH0 to CH"j-1, respectively. That is, when counting from LSB to MSB, the i-th bit of the channel mask corresponds to the i-th channel CH"i-1.

[0231] The multicast interconnect 610 can generate and output a number of submacro instructions corresponding to the number of bits with a value of "1" in the channel mask of the macro instruction. Specifically, when the i-th bit of the j-th bit of the channel mask has a binary value of "1", the multicast interconnect 610 generates and outputs the i-th submacro instruction. Conversely, when the i-th bit has a binary value of "0", the multicast interconnect 610 does not generate the corresponding submacro instruction. For example, when the channel mask of the macro instruction is set to "0000 0000 11111111", the multicast interconnect 610 generates and outputs the first through eighth submacro instructions. In another example, when the channel mask is set to "1111 1111 0000 0000", the multicast interconnect 610 generates and outputs the ninth through sixteenth submacro instructions. In yet another example, when the channel mask is set to “1010 1010 1010 1010”, the multicast interconnect 610 generates and outputs the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth submacro instructions.

[0232] When the i-th submacro instruction is generated by the multicast interconnect 610, the multicast interconnect 610 transmits the i-th submacro instruction to the i-th instruction decoder and sequencer 620 (i-1) through the i-th channel CH (i-1). For example, when the channel mask of the macro instruction is set to "0000 0000 1111 1111", the multicast interconnect 610 generates the first to eighth submacro instructions and transmits them to the first to eighth instruction decoders and sequencers, respectively. In another example, when the channel mask of the macro instruction is set to "1111 1111 0000 0000", the multicast interconnect 610 generates the ninth to sixteenth submacro instructions and transmits them to the ninth to sixteenth instruction decoders and sequencers, respectively. In another example, when the channel mask of the macro instruction is set to "1010 1010 1010 1010", the multicast interconnect 610 generates the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth sub-macro instructions, and transmits them to the second, fourth, sixth, eighth, tenth, twelfth, fourteenth and sixteenth instruction decoders and sequencers, respectively.

[0233] In the first example, assume that the macro instruction transmitted to the multicast interconnect 610 includes an operation type designated as "MAC", an iteration count, a channel mask, a row address, and a starting column address. When transmitting a macro instruction that includes a channel mask in which the i-th bit is set to "1", the multicast interconnect 610 generates and outputs the i-th sub-macro instruction. The i-th sub-macro instruction output from the multicast interconnect 610 may include an operation type, an iteration count, a row address, and a starting column address. In the first example, the operation type, iteration count, row address, and starting column address included in the i-th sub-macro instruction may be the same as those included in the macro instruction.

[0234] In the second example, assume that the macro instruction transmitted to the multicast interconnect 610 includes an operation type specified as "WRGB", an iteration count, a channel mask, a local memory address, a starting column address, and a broadcast bit. When transmitting a macro instruction that includes a channel mask in which the i-th bit is set to "1", the multicast interconnect 610 generates and outputs the i-th sub-macro instruction. The i-th sub-macro instruction output from the multicast interconnect 610 may include the operation type, iteration count, local memory start address, start column address, and broadcast bit. In the second example, the operation type, iteration count, local memory start address, start column address, and broadcast bit included in the i-th sub-macro instruction can be the same as those included in the macro instruction. Furthermore, in the second example, the macro instruction transmitted to the multicast interconnect 610 may also include a local memory increment size. In this case, the i-th sub-macro instruction output from the multicast interconnect 610 may also include a local memory increment size, which may be the same as those included in the macro instruction.

[0235] In the third example, assume that the macro instruction transmitted to the multicast interconnect 610 includes an operation type specified as "WRGB", an iteration count, a channel mask, a local memory address, a starting column address, a broadcast bit, and a local memory increment size. When transmitting a macro instruction that includes a channel mask in which the i-th bit is set to "1", the multicast interconnect 610 generates and outputs the i-th sub-macro instruction. The i-th sub-macro instruction output from the multicast interconnect 610 may include an operation type, an iteration count, a local memory start address, a start column address, a broadcast bit, and a local memory increment size. In the third example, the operation type, iteration count, local memory start address, start column address, broadcast bit, and local memory increment size included in the i-th sub-macro instruction may be the same as those included in the macro instruction.

[0236] In the fourth example, assume that the macro instruction transmitted to the multicast interconnect 610 includes an operation type specified as "WRBIAS", a channel mask, a local memory address, and a MAC latch ID. The macro instruction may also include broadcast bits. When transmitting a macro instruction that includes a channel mask in which the i-th bit is set to "1", the multicast interconnect 610 generates and outputs the i-th sub-macro instruction. The i-th sub-macro instruction output from the multicast interconnect 610 may include the operation type, the local memory address, and the MAC latch ID. In the fourth example, the operation type and MAC latch ID included in the i-th sub-macro instruction may be the same as the operation type and MAC latch ID included in the macro instruction. The local memory address included in the i-th sub-macro instruction can be determined by incrementing the starting local memory address included in the macro instruction by a size specified by the local memory increment size.

[0237] The first through j instruction decoders and sequencers 620(0)-620(j-1) can receive submacro instructions output from the multicast interconnect 610. In one embodiment, when a submacro instruction is transmitted from the multicast interconnect 610, each of the first through j instruction decoders and sequencers 620(0)-620(j-1) can decode the submacro instruction and generate a microinstruction set for output. For example, when the i-th submacro instruction is transmitted from the multicast interconnect 610, the i-th instruction decoder and sequencer 620(i-1) can generate and output the i-th microinstruction set. The i-th instruction decoder and sequencer 620(i-1) can transmit the i-th microinstruction set to the i-th PIM controller 640(i-1).

[0238] In another embodiment, when a submacro instruction is transmitted from the multicast interconnect 610, each of the first to j-th instruction decoders and sequencers 620(0)-620(j-1) can decode the submacro instruction and generate a local memory instruction set and a microinstruction set. Specifically, when the i-th submacro instruction is transmitted from the multicast interconnect 610, the i-th instruction decoder and sequencer 620(i-1) can generate the i-th local memory instruction set and the i-th microinstruction set. The i-th instruction decoder and sequencer 620(i-1) can transmit the i-th local memory instruction set and the i-th microinstruction set to the i-th local memory 630(i-1) and the i-th PIM controller 640(i-1), respectively.

[0239] In another embodiment, when a submacro instruction is transmitted from the multicast interconnect 610, each of the first to j-th instruction decoders and sequencers 620(0)-620(j-1) can decode the submacro instruction and generate multiple local memory instructions and multiple micro instructions. Specifically, when the i-th submacro instruction is transmitted from the multicast interconnect 610, the i-th instruction decoder and sequencer 620(i-1) can generate the "(n-1)×j+i"-th local memory instruction and the "(n-1)×j+i"-th micro instruction. Here, n is a natural number from 1 to m / j. The i-th instruction decoder and sequencer 620(i-1) can transmit the "(n-1)×j+i"-th local memory instruction and the "(n-1)×j+i"-th micro instruction to the i-th local memory 630(i-1) and the i-th PIM controller 640(i-1), respectively.

[0240] In another embodiment, when a submacro instruction is transmitted from the multicast interconnect 610, each of the first to j-th instruction decoders and sequencers 620(0)-620(j-1) can decode the submacro instruction and generate local memory instructions and micro-instructions. Specifically, when the i-th submacro instruction is transmitted from the multicast interconnect 610, the i-th instruction decoder and sequencer 620(i-1) can generate the i-th local memory instruction and the i-th micro-instruction. The i-th instruction decoder and sequencer 620(i-1) can transmit the i-th local memory instruction and the i-th micro-instruction to the i-th local memory 630(i-1) and the i-th PIM controller 640(i-1), respectively.

[0241] In the first example (where the macro instruction transmitted to the multicast interconnect 610 includes an operation type designated as "MAC", an iteration number, a channel mask, a row address, and a starting column address), the i-th instruction decoder and sequencer 620(i-1) receiving the i-th sub-macro instruction can generate and output the i-th microinstruction set. In this case, the i-th microinstruction set can include first to m-th microinstructions, where m represents the iteration number. Each of the first to m-th microinstructions can include an operation type, a row address, and a column address. The operation type and row address included in the first to m-th microinstructions can be the same as those included in the i-th sub-macro instruction. The column addresses included in the first to m-th microinstructions can be sequentially incremented starting from the starting column address included in the i-th sub-macro instruction.

[0242] In the second example (where the macro instruction transmitted to the multicast interconnect 610 includes an operation type specified as "WRGB", iteration count, channel mask, local memory address, column address, and broadcast bit), when the broadcast bit is set to "1", the i-th instruction decoder and sequencer 620(i-1) receiving the i-th sub-macro instruction can generate and output the first to m-th local memory instructions and the i-th micro-instruction set. In this case, each of the first to m-th local memory instructions output from the i-th instruction decoder and sequencer 620(i-1) can include a local memory command and a local memory address. The local memory command can be specified as "RD_LM", indicating a read operation on the i-th local memory. The local memory address can be sequentially incremented starting from the local memory address included in the i-th sub-macro instruction. The i-th micro-instruction set output from the i-th instruction decoder and sequencer 620(i-1) can include the first to m-th micro-instructions. Each of the first to m-th micro-instructions can include an operation type and a column address. The operation type included in the first to m-th micro-instructions can be the same as the operation type included in the i-th sub-macro instruction. The column addresses included in the first to mth microinstructions can be sequentially incremented starting from the starting column address included in the i-th submacro instruction.

[0243] In the second example, when the broadcast bit value is set to "0", the i-th instruction decoder and sequencer 620(i-1) receiving the i-th submacro instruction can generate and output the "(n-1)×j+i"th local memory instruction and the "(n-1)×j+i"th micro instruction. In this case, each "(n-1)×j+i"th local memory instruction output from the i-th instruction decoder and sequencer 620(i-1) can include a local memory command and a local memory address. The local memory command can be specified as "RD_LM", indicating a read operation on the i-th local memory. The local memory address can be specified as (n-1)×j+i+c1, where c1 represents the local memory address included in the i-th submacro instruction. Each "(n-1)×j+i"th micro instruction output from the i-th instruction decoder and sequencer 620(i-1) can include an operation type and a column address. The operation type included in the "(n-1)×j+i" microinstruction can be the same as the operation type included in the i-th submacro instruction. The column address instruction included in the "(n-1)×j+i" microinstruction can be specified as (n-1)×j+i+c2, where c2 represents the starting column address included in the i-th submacro instruction.

[0244] In the third example, when the broadcast bit value is set to "1" in the macro instruction transmitted to the multicast interconnect 610, the i-th instruction decoder and sequencer 620 (i-1) receiving the i-th sub-macro instruction can generate and output the first to m-th local memory instruction sets and the i-th micro-instruction set. Each of the first to m-th local memory instructions output from the i-th instruction decoder and sequencer 620 (i-1) can include a local memory command and a local memory address. The local memory command can be specified as "RD_LM" to indicate a read operation on the i-th local memory. The local memory address can be sequentially incremented starting from the starting local memory address included in the i-th sub-macro instruction, with the increment step size limited by the local memory increment size. The i-th micro-instruction set output from the i-th instruction decoder and sequencer 620 (i-1) can include the first to m-th micro-instructions. Each of the first to m-th micro-instructions can include an operation type and a column address. The operation type included in the first to m-th micro-instructions can be the same as the operation type included in the i-th sub-macro instruction. The column addresses included in the first to mth microinstructions can be sequentially incremented starting from the column addresses included in the i-th submacro instruction.

[0245] In the third example, when the broadcast bit value is set to "0", the i-th instruction decoder and sequencer 620(i-1) receiving the i-th submacro instruction can generate and output the "(n-1)×j+i"th local memory instruction and the "(n-1)×j+i"th micro instruction. Each "(n-1)×j+i"th local memory instruction output from the i-th instruction decoder and sequencer 620(i-1) can include a local memory command and a local memory address. The local memory command can be specified as "RD_LM", indicating a read operation on the i-th local memory. The local memory address can be specified as [(n-1)×j+i+c1]×s, where c1 represents the local memory address included in the i-th submacro instruction, and s represents the local memory increment size. Each "(n-1)×j+i"th micro instruction output from the i-th instruction decoder and sequencer 620(i-1) can include an operation type and a column address. The operation type included in the "(n-1)×j+i" microinstruction can be the same as the operation type included in the i-th submacro instruction. The column address included in the "(n-1)×j+i" microinstruction can be specified as (n-1)×j+i+c2, where c2 represents the column address included in the i-th submacro instruction.

[0246] In the fourth example (where the macro instruction transmitted to the multicast interconnect 610 includes an operation type designated as "WRBIAS", a channel mask, a local memory address, and a MAC latch ID), the i-th instruction decoder and sequencer 620(i-1) receiving the i-th sub-macro instruction can generate and output the i-th local memory instruction and the i-th micro instruction. In this case, the i-th local memory instruction output from the i-th instruction decoder and sequencer 620(i-1) may include a local memory command and a local memory address. The local memory command may be designated as "RD_LM", indicating a read operation on the i-th local memory. The local memory address may be sequentially incremented starting from the local memory address included in the i-th sub-macro instruction. The i-th micro instruction output from the i-th instruction decoder and sequencer 620(i-1) may include an operation type and a MAC latch ID. The operation type and MAC latch ID included in the i-th micro instruction may be the same as the operation type and MAC latch ID included in the i-th sub-macro instruction.

[0247] In the first to j-th local memories 630(0)-630(j-1), the i-th local memory 630(i-1) can receive the first to m-th local memory instructions from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoders and sequencers 620(0)-620(j-1). After receiving the first to m-th local memory instructions from the i-th instruction decoder and sequencer 620(i-1), the i-th local memory 630(i-1) sequentially performs the first to m-th read operations based on the first to m-th local memory instructions. Specifically, the i-th local memory 630(i-1) transfers the data stored at the storage location specified by the local memory address included in the first to m-th local memory instructions to the i-th PIM controller 640(i-1).

[0248] In the first to j-th local memories 630(0)-630(j-1), the i-th local memory 630(i-1) can also receive the "(n-1)×j+i" local memory instruction from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoders and sequencers 620(0)-620(j-1). After receiving the "(n-1)×j+i" local memory instruction from the i-th instruction decoder and sequencer 620(i-1), the i-th local memory 630(i-1) sequentially executes the "(n-1)×j+i" read operation based on the "(n-1)×j+i" local memory instruction. Therefore, the i-th local memory 630(i-1) transfers the data stored at the storage location specified by the local memory address included in the "(n-1)×j+i" local memory instruction to the i-th PIM controller 640(i-1).

[0249] In the first to j-th local memories 630(0)-630(j-1), the i-th local memory 630(i-1) can also receive the i-th local memory instruction from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoders and sequencers 620(0)-620(j-1). After receiving the i-th local memory instruction from the i-th instruction decoder and sequencer 620(i-1), the i-th local memory 630(i-1) executes the i-th read operation sequentially based on the i-th local memory instruction. Specifically, the i-th local memory 630(i-1) transfers the data stored at the storage location specified by the local memory address included in the i-th local memory instruction to the i-th PIM controller 640(i-1).

[0250] In the first to j-th PIM controllers 640(0)-640(j-1), the i-th PIM controller 640(i-1) can receive the i-th microinstruction set from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoders and sequencers 620(0)-620(j-1). In this case, the i-th PIM controller 640(i-1) generates and outputs the i-th PIM command set based on the first to m-th microinstructions included in the i-th microinstruction set. The i-th PIM command set may include an activation PIM command and first to m-th PIM commands corresponding to the first to m-th microinstructions respectively. The activation PIM command may include the “ACT” command for activating a row and a row address. Each of the first to m-th PIM commands may include an operation type, a row address, and a column address. The operation type, row address, and column address included in the first to m-th PIM commands may be the same as the operation type, row address, and column address included in the first to m-th microinstructions of the i-th microinstruction set. The i-th PIM controller 640 (i-1) transmits the i-th PIM command set to the i-th PIM device through the i-th channel CH (i-1).

[0251] In the first to j-th PIM controllers 640(0)-640(j-1), the i-th PIM controller 640(i-1) can receive first to m-th data from the i-th local memory 630(i-1) in the first to j-th local memories 630(0)-630(j-1), and can also receive the i-th microinstruction set from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoder and sequencer 620(0)-620(j-1). In this case, the i-th PIM controller 640(i-1) generates and outputs the i-th PIM command set based on the first to m-th data and the first to m-th microinstructions included in the i-th microinstruction set. The i-th PIM command set may include the first to m-th PIM commands, each PIM command corresponding to each of the first to m-th data and each of the first to m-th microinstructions. Each of the first to m-th PIM commands may include an operation type, local memory data, and a column address. The local memory data included in each of the first to m-th PIM commands can be the same as the corresponding first to m-th data. The operation type and column address included in the first to m-th PIM commands can be the same as the operation type and column address included in the first to m-th microinstructions of the i-th microinstruction set. The i-th PIM controller 640 (i-1) transmits the i-th PIM command set to the i-th PIM device through the i-th channel CH (i-1).

[0252] In the first to j-th PIM controllers 640(0)-640(j-1), the i-th PIM controller 640(i-1) can receive the "(n-1)×j+i"th data from the i-th local memory 630(i-1) in the first to j-th local memories 630(0)-630(j-1), and can also receive the "(n-1)×j+i"th microinstruction from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoder and sequencer 620(0)-620(j-1). In this case, the i-th PIM controller 640(i-1) generates and outputs the "(n-1)×j+i"th PIM command based on the "(n-1)×j+i"th data and the "(n-1)×j+i"th microinstruction. Each "(n-1)×j+i"th PIM command may include an operation type, local memory data, and column address. The local memory data included in each "(n-1)×j+i" PIM command can be the same as the corresponding "(n-1)×j+i" data. The operation type and column address included in each "(n-1)×j+i" PIM command can be the same as the operation type and column address included in the corresponding "(n-1)×j+i" microinstruction. The i-th PIM controller 640 (i-1) transmits the "(n-1)×j+i" PIM command to the i-th PIM device through the i-th channel CH (i-1).

[0253] In the first to j-th PIM controllers 640(0)-640(j-1), the i-th PIM controller 640(i-1) can receive i-th data from the i-th local memory 630(i-1) in the first to j-th local memories 630(0)-630(j-1), and can also receive the i-th microinstruction from the i-th instruction decoder and sequencer 620(i-1) in the first to j-th instruction decoders and sequencers 620(0)-620(j-1). In this case, the i-th PIM controller 640(i-1) generates and outputs the i-th PIM command based on the i-th data and the i-th microinstruction. The i-th PIM command may include an operation type, local memory data, and a MAC latch ID. The local memory data included in the i-th PIM command may be the same as the corresponding i-th data. The operation type and MAC latch ID included in the i-th PIM command may be the same as the operation type and MAC latch ID included in the i-th microinstruction. The i-th PIM controller 640 (i-1) transmits the i-th PIM command to the i-th PIM device through the i-th channel CH (i-1).

[0254] In the first to j-th PIM devices 110(0)-110(j-1), the i-th PIM device 110(i-1) can receive the i-th PIM command set from the i-th PIM controller 640(i-1). When the i-th PIM command set includes the first to m-th PIM commands, and the operation type of the first to m-th PIM commands is specified as "MAC", the i-th PIM device 110(i-1) activates a row in the memory bank specified by the row address included in the i-th activated PIM command. Subsequently, the processing element included in the i-th PIM device 110(i-1) receives weight data stored in the column specified by the column address in the activated row of the memory bank, and vector data stored in the global buffer at the storage location specified by the same column address. Then, the processing element performs a MAC operation using the weight data and vector data received from the memory bank and the global buffer.

[0255] When the i-th PIM command set transmitted from the i-th PIM controller 640 (i-1) includes the first to m-th PIM commands, and the operation type of the first to m-th PIM commands is specified as "WRGB", the i-th PIM device 110 (i-1) stores the first to m-th local memory data as vector data in the first to m-th storage locations of the global buffer specified by the column addresses included in the first to m-th PIM commands.

[0256] In the first to j-th PIM devices 110(0)-110(j-1), the i-th PIM device 110(i-1) can also receive the i-th PIM command from the i-th PIM controller 640(i-1). When the operation type of the i-th PIM command is specified as "WRBIAS", the i-th PIM device 110(i-1) latches the local memory data included in the i-th PIM command as bias data into the latch circuit in the MAC latch circuit, which is specified by the MAC latch ID included in the i-th PIM command.

[0257] Figures 33 to 35 It is shown in Figure 32 Execution in the PIM system Figure 7 The diagram illustrates the process of the first macro instruction. In this example, it is assumed that the PIM system (20) includes channels 1 through 16 (CH0-CH15). Furthermore, it is assumed, for example, that the operation type, operation repetition count, channel mask, row address, and column address of the first macro instruction are set to “MAC”, “64”, “1111 11111111 1111”, “0”, and “0”, respectively.

[0258] Reference Figure 33After receiving the first macro instruction, the multicast interconnect 610 generates and outputs one or more sub-macro instructions based on the first macro instruction. Since the first to sixteenth bits of the channel mask included in the first macro instruction all have a binary value of "1", the multicast interconnect 610 generates the first to sixteenth sub-macro instructions. The multicast interconnect 610 transmits the first to sixteenth sub-macro instructions to the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) through the first channel CH0 to the sixteenth channel CH15 respectively. Each of the first to sixteenth sub-macro instructions may include an operation type, an iteration number, a row address, and a starting column address. The operation type, iteration number, row address, and starting column address included in the first to sixteenth sub-macro instructions are the same as those included in the first macro instruction. Therefore, each of the first to sixteenth sub-macro instructions includes an operation type set to "MAC", an iteration number set to "64", a row address set to "0", and a column address set to "0".

[0259] Reference Figure 34 The first to sixteenth instruction decoders and sequencers 620(0) to 620(15) generate the first to sixteenth microinstruction sets based on the first to sixteenth submacro instructions, respectively. The first to sixteenth instruction decoders and sequencers 620(0) to 620(15) transmit the first to sixteenth microinstruction sets to the first to sixteenth PIM controllers 640(0) to 640(15), respectively. Figure 34 As shown, the first instruction decoder and sequencer 620(0) generate a first microinstruction set based on a first submacro instruction. The first instruction decoder and sequencer 620(0) transmit the first microinstruction set to the first PIM controller 640(0) through the first channel CH0. Similarly, the second instruction decoder and sequencer 620(1) generate a second microinstruction set based on a second submacro instruction and transmits the second microinstruction set to the second PIM controller 640(1) through the second channel CH1. The sixteenth instruction decoder and sequencer 620(15) generate a sixteenth microinstruction set based on a sixteenth submacro instruction and transmits the sixteenth microinstruction set to the sixteenth PIM controller 640(15) through the sixteenth channel CH15.

[0260] The first to sixteenth microinstruction sets output from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) all include the first to sixty-fourth microinstructions. For example... Figure 34As shown, the first microinstruction set includes microinstructions one through sixty-four. Similarly, the second and sixteenth microinstruction sets also include microinstructions one through sixty-four. Each of the first through sixty-four microinstructions includes an operation type, a row address, and a column address. The operation type and row address included in the first through sixty-four microinstructions are the same as those included in the corresponding first through sixteenth submacro instructions. The column address included in each of the first through sixty-four microinstructions increments sequentially from the starting column address included in the corresponding first through sixteenth submacro instructions. Figure 34 As shown, the first microinstruction in the first to sixteenth microinstruction sets all includes an operation type set to "MAC", a row address set to "0", and a column address set to "0". The second microinstruction in the first to sixteenth microinstruction sets all includes an operation type set to "MAC", a row address set to "0", and a column address set to "1". Similarly, the sixty-fourth microinstruction in the first to sixteenth microinstruction sets all includes an operation type set to "MAC", a row address set to "0", and a column address set to "63".

[0261] Reference Figure 35 The first to sixteenth PIM controllers 640(0) to 640(15) generate and output the first to sixteenth PIM command sets based on the first to sixteenth microinstruction sets, respectively. Each of the first to sixteenth PIM command sets includes an activation PIM command and the first to sixty-fourth PIM commands. For example, the first PIM controller 640(0) generates the first PIM command set based on the first to sixty-fourth microinstructions included in the first microinstruction set, and the first PIM command set includes an activation PIM command and the first to sixty-fourth PIM commands. Similarly, the second PIM controller 640(1) generates the second PIM command set based on the first to sixty-fourth microinstructions included in the second microinstruction set, and the second PIM command set includes an activation PIM command and the first to sixty-fourth PIM commands. Likewise, the sixteenth PIM controller 640(15) generates the sixteenth PIM command set based on the sixteenth microinstruction set.

[0262] Each activation PIM command in the first through sixteenth PIM command sets includes an activation command specified as "ACT" and a row address specified as "0". Each first PIM command in the first through sixteenth PIM command sets includes an operation type set to "MAC" and a column address set to "0". Each second PIM command in the first through sixteenth PIM command sets includes an operation type set to "MAC" and a column address set to "1". Similarly, each sixty-fourth PIM command in the first through sixteenth PIM command sets includes an operation type set to "MAC" and a column address set to "63".

[0263] Although not shown in the figure, after receiving the first to sixteenth PIM command sets respectively, the first to sixteenth PIM devices 110(0)-110(15) activate the row in the memory specified by the row address "0" included in the activation PIM command. Subsequently, the processing element included in each of the first to sixteenth PIM devices 110(0)-110(15) receives weight data in the column specified by the column address in the activated row stored in the memory, and vector data in the storage location specified by the column address in the storage location of the global buffer. In addition, the processing element included in each of the first to sixteenth PIM devices 110(0)-110(15) performs MAC operation using the weight data received from the memory and the vector data received from the global buffer.

[0264] Figures 36 to 39 It is shown in Figure 32 Execution in the PIM system Figure 11 A diagram illustrating an example process of the second macro instruction. In this example, it is assumed that the PIM system 20 includes channels CH0 through CH15, numbered from the first to the sixteenth. It is further assumed that the operation type, iteration count, channel mask, local memory address, column address, and broadcast bit of the second macro instruction are set to “WRGB”, “64”, “1111 1111 1111 1111”, “0”, “0”, and “1”, respectively.

[0265] Reference Figure 36 After receiving the second macro instruction, the multicast interconnect 610 generates and outputs one or more sub-macro instructions based on the second macro instruction. Since the first to sixteenth bits of the channel mask included in the second macro instruction all have a binary value of "1", the multicast interconnect 610 generates the first to sixteenth sub-macro instructions. The multicast interconnect 610 transmits the first to sixteenth sub-macro instructions to the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) respectively through the first to sixteenth channels CH0 to CH15. Figure 36 As shown, the multicast interconnect 610 transmits the first submacro instruction to the first instruction decoder and sequencer 620 (0) via the first channel CH0. The multicast interconnect 610 transmits the second submacro instruction to the second instruction decoder and sequencer 620 (1) via the second channel CH1. Similarly, the multicast interconnect 610 transmits the sixteenth submacro instruction to the sixteenth instruction decoder and sequencer 620 (15) via the sixteenth channel CH15.

[0266] Each of the first through sixteenth submacro instructions may include an operation type, iteration count, local memory address, starting column address, and broadcast bit. The operation type, iteration count, local memory address, column address, and broadcast bit included in each of the first through sixteenth submacro instructions are the same as those included in the second macro instruction. Therefore, each of the first through sixteenth submacro instructions includes an operation type set to "WRGB", an iteration count set to "64", a local memory address set to "0", a column address set to "0", and a broadcast bit set to "1".

[0267] Reference Figure 37 The first to sixteenth instruction decoders and sequencers 620(0) to 620(15) generate and output the first to sixteenth local memory instruction sets based on the first to sixteenth sub-macro instructions, respectively. Furthermore, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) generate and output the first to sixteenth micro-instruction sets based on the first to sixteenth sub-macro instructions, respectively. The first to sixteenth instruction decoders and sequencers 620(0) to 620(15) transmit the first to sixteenth local memory instruction sets to the first to sixteenth local memories 630(0) to 630(15), respectively, and transmit the first to sixteenth micro-instruction sets to the first to sixteenth PIM controllers 640(0) to 640(15), respectively.

[0268] like Figure 37 As shown, the first instruction decoder and sequencer 620(0) generates a first local memory instruction set and a first microinstruction set based on a first submacro instruction. The first instruction decoder and sequencer 620(0) transmits the first local memory instruction set to the first local memory 630(0) and also transmits the first microinstruction set to the first PIM controller 640(0) through the first channel CH0. Similarly, the second instruction decoder and sequencer 620(1) generates a second local memory instruction set and a second microinstruction set based on a second submacro instruction. The second instruction decoder and sequencer 620(1) transmits the second local memory instruction set to the second local memory 630(1) and transmits the second microinstruction set to the second PIM controller 640(1) through the second channel CH1. The sixteenth instruction decoder and sequencer 620(15) generates a sixteenth local memory instruction set and a sixteenth microinstruction set based on a sixteenth submacro instruction. Similarly, the sixteenth instruction decoder and sequencer 620 (15) transmits the sixteenth local memory instruction set to the sixteenth local memory 630 (15) and transmits the sixteenth microinstruction set to the sixteenth PIM controller 640 (15) through the sixteenth channel CH15.

[0269] Each of the first to sixteenth local memory instruction sets generated by the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) includes the first to sixty-fourth local memory instructions. Each of the first to sixty-fourth local memory instructions includes a local memory command and a local memory address. The local memory command is designated as "RD_LM" and its instruction is a read operation on local memory. The local memory address is sequentially incremented from the starting address (which is the local memory address included in the corresponding submacro instruction) across the first to sixty-fourth local memory instructions.

[0270] like Figure 37 As shown, the first local memory instruction included in the first to sixteenth local memory instruction sets all includes a local memory command specified as "RD_LM" and a local memory address specified as "0". The second local memory instruction included in the first to sixteenth local memory instruction sets all includes a local memory command specified as "RD_LM" and a local memory address specified as "1". Similarly, the sixty-fourth local memory instruction included in the first to sixteenth local memory instruction sets all includes a local memory command specified as "RD_LM" and a local memory address specified as "63".

[0271] Each of the first to sixteenth microinstruction sets output from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) comprises the first to sixty-fourth microinstructions. Each of the first to sixty-fourth microinstructions comprises an operation type and a column address. The operation type is specified as "WRGB", which is an instruction for writing to the global buffer. The column address is sequentially incremented starting from the starting column address (which is the column address included in the corresponding submacro instruction) across the first to sixty-fourth microinstructions.

[0272] like Figure 37 As shown, the first microinstruction in the first to sixteenth microinstruction sets all includes an operation type specified as "WRGB" and a column address specified as "0". The second microinstruction in the first to sixteenth microinstruction sets all includes an operation type specified as "WRGB" and a column address specified as "1". Similarly, the sixty-fourth microinstruction in the first to sixteenth microinstruction sets all includes an operation type specified as "WRGB" and a column address specified as "63".

[0273] Reference Figure 38 Each of the first to sixteenth local memories, LM0 630(0) to LM15 630(15), outputs the corresponding first to sixteenth local memory dataset after receiving the corresponding first to sixteenth local memory instruction set. Each of the first to sixteenth local memory datasets includes data from the first to sixty-fourth local memories. Figure 38As shown, the first local memory 630(0) outputs first local memory data DA0_0 stored in the first local memory 630(0) at the storage location specified by local memory address "0" included in the first local memory instruction of the first local memory instruction set. Subsequently, the first local memory 630(0) outputs second local memory data DA0_1 stored in the first local memory 630(0) at the storage location specified by local memory address "1" included in the second local memory instruction of the first local memory instruction set. Finally, the first local memory 630(0) outputs sixty-fourth local memory data DA0_63 stored in the first local memory 630(0) at the storage location specified by local memory address "63" included in the sixty-fourth local memory instruction of the first local memory instruction set.

[0274] In the same manner, the second local memory 630(1) outputs the first local memory data DA1_0 stored in the second local memory 630(1) at the storage location specified by the local memory address "0" included in the first local memory instruction of the second local memory instruction set. Subsequently, the second local memory 630(1) outputs the second local memory data DA1_1 stored in the second local memory 630(1) at the storage location specified by the local memory address "1" included in the second local memory instruction of the second local memory instruction set. Finally, the second local memory 630(1) outputs the sixty-fourth local memory data DA1_63 stored in the second local memory 630(1) at the storage location specified by the local memory address "63" included in the sixty-fourth local memory instruction of the second local memory instruction set.

[0275] Similarly, the sixteenth local memory 630 (15) outputs the first local memory data DA15_0 stored in the sixteenth local memory 630 (15) at the storage location specified by the local memory address "0" included in the first local memory instruction of the sixteenth local memory instruction set. Subsequently, the sixteenth local memory 630 (15) outputs the second local memory data DA15_1 stored in the sixteenth local memory 630 (15) at the storage location specified by the local memory address "1" included in the second local memory instruction of the sixteenth local memory instruction set. Finally, the sixteenth local memory 630 (15) outputs the sixty-fourth local memory data DA15_63 stored in the sixty-fourth local memory instruction of the sixteenth local memory instruction set at the storage location specified by the local memory address "63" included in the sixty-fourth local memory instruction of the sixteenth local memory instruction set.

[0276] Reference Figure 39The first to sixteenth PIM controllers 640(0) to 640(15) receive corresponding local memory datasets from the first to sixteenth local memories 630(0) to 630(15), respectively. Specifically, the first PIM controller 640(0) sequentially receives local memory data DA0_0 to DA0_63, which are included in the first local memory dataset, from the first local memory 630(0). The second PIM controller 640(1) sequentially receives local memory data DA1_0 to DA1_63, which are included in the second local memory dataset, from the second local memory 630(1). Similarly, the sixteenth PIM controller 640(15) sequentially receives local memory data DA15_0 to DA15_63, which are included in the sixteenth local memory dataset, from the sixteenth local memory 630(15).

[0277] The first to sixteenth PIM controllers 640(0) to 640(15) also receive the first to sixteenth microinstruction sets from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15), respectively. Specifically, the first PIM controller 640(0) sequentially receives the first to sixty-fourth microinstructions included in the first microinstruction set from the first instruction decoder and sequencer 620(0). The second PIM controller 640(1) sequentially receives the first to sixty-fourth microinstructions included in the second microinstruction set from the second instruction decoder and sequencer 620(1). Similarly, the sixteenth PIM controller 640(15) sequentially receives the first to sixty-fourth microinstructions included in the sixteenth microinstruction set from the sixteenth instruction decoder and sequencer 620(15).

[0278] Each of the first to sixteenth PIM controllers 640(0) to 640(15) generates and outputs the corresponding first to sixteenth PIM command sets. Each of the first to sixteenth PIM command sets includes the first to sixty-fourth PIM commands. Each of the first to sixty-fourth PIM commands includes an operation type, local memory data, and a column address. The operation type included in each of the first to sixty-fourth PIM commands is specified as "WRGB". The local memory data included in each of the first to sixty-fourth PIM commands corresponds to the local memory data included in the corresponding local memory dataset. The column address included in each of the first to sixty-fourth PIM commands corresponds to the column address included in the corresponding microinstruction set.

[0279] like Figure 39As shown, the first PIM controller 640(0) outputs a first PIM command, which includes an operation type specified as "WRGB", local memory data "DA0_0", and column address "0". Subsequently, the first PIM controller 640(0) outputs a second PIM command, which includes an operation type specified as "WRGB", local memory data "DA0_1", and column address "1". In the same manner, the first PIM controller 640(0) sequentially outputs the third to the sixty-third PIM commands. Finally, the first PIM controller 640(0) outputs the sixty-fourth PIM command, which includes an operation type specified as "WRGB", local memory data "DA0_63", and column address "63". Similarly, the second PIM controller 640(1) outputs a first PIM command, which includes an operation type specified as "WRGB", local memory data "DA1_0", and column address "0". Subsequently, the second PIM controller 640(1) outputs a second PIM command, which includes an operation type specified as "WRGB", local memory data "DA1_1", and column address "1". In the same manner, the second PIM controller 640(1) sequentially outputs the third to the sixty-third PIM commands. Finally, the second PIM controller 640(1) outputs the sixty-fourth PIM command, which includes an operation type specified as "WRGB", local memory data "DA1_63", and column address "63". Similarly, the sixteenth PIM controller 640(15) outputs a first PIM command, which includes an operation type specified as "WRGB", local memory data "DA15_0", and column address "0". Subsequently, the sixteenth PIM controller 640(15) outputs a second PIM command, which includes an operation type specified as "WRGB", local memory data "DA15_1", and column address "1". In the same manner, the sixteenth PIM controller 640(15) sequentially outputs the third to the sixty-third PIM commands. Finally, the sixteenth PIM controller 640 (15) outputs the sixty-fourth PIM command, which includes the operation type specified as "WRGB", the local memory data "DA15_63", and the column address "63".

[0280] Although not shown in the figures, each of the first to sixteenth PIM devices 110(0) to 110(15), upon receiving the first to sixteenth PIM command sets, stores the first to sixty-fourth local memory data included in the first to sixty-fourth PIM commands into sixty-four storage locations in the global buffer specified by the column addresses included in the first to sixty-fourth PIM commands. For example, the first PIM device 110(0) stores the first local memory data “DA0_0” into the storage location in the global buffer specified by the column address “0” included in the first PIM command of the first PIM command set. Subsequently, the first PIM device 110(0) stores the second local memory data “DA0_1” into the storage location in the global buffer specified by the column address “1” included in the second PIM command of the first PIM command set. In the same manner, the first PIM device 110(0) stores the third to sixty-third local memory data into the storage locations in the global buffer specified by the column addresses included in the third to sixty-third PIM commands of the first PIM command set. Finally, the first PIM device 110 (0) stores the sixty-fourth local memory data “DA0_63” into the storage location specified by the column address “63” included in the sixty-fourth PIM command of the first PIM command set in the global buffer.

[0281] Figures 40 to 42 It is shown in Figure 32 Execution in the PIM system Figure 11 A diagram illustrating another example of the second macro instruction's process is provided. In this example, it is assumed that the PIM system 20 includes channels CH0 through CH15, numbered one through sixteenth. Further, it is assumed that the operation type, iteration count, channel mask, local memory address, column address, and broadcast bit of the second macro instruction are set to "WRGB", "32", "1111 1111 1111 1111", "0", "0", and "0", respectively. (Refer to...) Figures 36 to 39 In the case of the second macro instruction described, the iteration count is "64" and the broadcast bit has a value of "1". In contrast, in this example, the second macro instruction differs in that the iteration count is "32" and the broadcast bit has a value of "0".

[0282] Reference Figure 40 After receiving the second macro instruction, the multicast interconnect 610 generates and outputs one or more sub-macro instructions based on the second macro instruction. Since the first to sixteenth bits of the channel mask included in the second macro instruction all have the binary value "1", the multicast interconnect 610 generates the first to sixteenth sub-macro instructions. The multicast interconnect 610 transmits the first to sixteenth sub-macro instructions to the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) respectively through the first to sixteenth channels CH0 to CH15. Specifically, as Figure 40 As shown, the first submacro instruction is transmitted from the multicast interconnect 610 to the first instruction decoder and sequencer 620 (0) via the first channel CH0. The second submacro instruction is transmitted from the multicast interconnect 610 to the second instruction decoder and sequencer 620 (1) via the second channel CH1. Similarly, the sixteenth submacro instruction is transmitted from the multicast interconnect 610 to the sixteenth instruction decoder and sequencer 620 (15) via the sixteenth channel CH15.

[0283] Each of the first through sixteenth submacro instructions may include an operation type, iteration count, local memory address, column address, and broadcast bit. The operation type, iteration count, local memory address, column address, and broadcast bit included in each of the first through sixteenth submacro instructions are the same as those included in the second macro instruction. Therefore, each of the first through sixteenth submacro instructions includes an operation type set to "WRGB", an iteration count set to "32", a local memory address set to "0", a column address set to "0", and a broadcast bit set to "0".

[0284] Reference Figure 41 Since the broadcast bit included in each of the first to sixteenth submacro instructions is set to the binary value "0", each of the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) generates and outputs the first to thirty-second local memory instructions and the first to thirty-second micro instructions. Specifically, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the first to sixteenth local memory instructions respectively. The first to sixteenth local memory instructions are respectively transferred to the first to sixteenth local memories 630(0) to 630(15). Subsequently, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the seventeenth to thirty-second local memory instructions respectively. The seventeenth to thirty-second local memory instructions are respectively transferred to the first to sixteenth local memories 630(0) to 630(15).

[0285] Each of the first through thirty-second local memory instructions includes a local memory command and a local memory address. The local memory command included in each of the first through thirty-second local memory instructions is specified as "RD_LM", and its instruction performs a read operation on local memory. The local memory address included in the first through thirty-second local memory instructions increments sequentially from the local memory address "0" included in each of the first through sixteenth submacro instructions.

[0286] like Figure 41As shown, the local memory address included in the first local memory instruction output from the first instruction decoder and sequencer 620 (0) is specified as "0". The local memory address included in the second local memory instruction output from the second instruction decoder and sequencer 620 (1) is specified as "1". Similarly, the local memory address included in the sixteenth local memory instruction output from the sixteenth instruction decoder and sequencer 620 (15) is specified as "15". Subsequently, the local memory address included in the seventeenth local memory instruction output from the first instruction decoder and sequencer 620 (0) is specified as "16", while the local memory address included in the eighteenth local memory instruction output from the second instruction decoder and sequencer 620 (1) is specified as "17". In the same manner, the local memory address included in the thirty-second local memory instruction output from the sixteenth instruction decoder and sequencer 620 (15) is specified as "31".

[0287] When transmitting the first to sixteenth local memory instructions, the first to sixteenth local memory units 630(0) to 630(15) output the first to sixteenth local memory data DA0 to DA15 respectively. Subsequently, when transmitting the seventeenth to thirty-second local memory instructions, the first to sixteenth local memory units 630(0) to 630(15) output the seventeenth to thirty-second local memory data DA16 to DA31 respectively. The first to sixteenth local memory data DA0 to DA15 output from the first to sixteenth local memory units 630(0) to 630(15) are data stored in the storage locations specified by local memory addresses "0" to "15". Similarly, the seventeenth to thirty-second local memory data DA16 to DA31 output from the first to sixteenth local memory units 630(0) to 630(15) are data stored in the storage locations specified by local memory addresses "16" to "31".

[0288] Additionally, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the first to sixteenth microinstructions respectively. The first to sixteenth microinstructions are output through channels CH0 to CH15 respectively. Subsequently, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the seventeenth to thirty-second microinstructions respectively. The seventeenth to thirty-second microinstructions are also output through channels CH0 to CH15 respectively. Each of the first to thirty-second microinstructions includes an operation type and a column address. The operation type included in each of the first to thirty-second microinstructions is specified as "WRGB". The column addresses included in the first to thirty-second microinstructions are sequentially incremented starting from column address "0" included in each of the first to sixteenth submacro instructions.

[0289] like Figure 41 As shown, the column address included in the first microinstruction output from the first instruction decoder and sequencer 620(0) is specified as "0", while the column address included in the second microinstruction output from the second instruction decoder and sequencer 620(1) is specified as "1". Similarly, the column address included in the sixteenth microinstruction output from the sixteenth instruction decoder and sequencer 620(15) is specified as "15". Subsequently, the column address included in the seventeenth microinstruction output from the first instruction decoder and sequencer 620(0) is specified as "16", while the column address included in the eighteenth microinstruction output from the second instruction decoder and sequencer 620(1) is specified as "17". In the same manner, the column address included in the thirty-second microinstruction output from the sixteenth instruction decoder and sequencer 620(15) is specified as "31".

[0290] Reference Figure 42 The first to sixteenth PIM controllers 640(0) to 640(15) receive first to sixteenth local memory data DA0 to DA15 from the first to sixteenth local memory 630(0) to 630(15), respectively, and also receive first to sixteenth micro-instructions from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15), respectively. Subsequently, the first to sixteenth PIM controllers 640(0) to 640(15) receive seventeenth to thirty-second local memory data DA16 to DA31 from the first to sixteenth local memory 630(0) to 630(15), respectively, and also receive seventeenth to thirty-second micro-instructions from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15), respectively.

[0291] Upon receiving the first to sixteenth local memory data DA0 to DA15 and the first to sixteenth microinstructions, the first to sixteenth PIM controllers 640(0) to 640(15) generate and output the first to sixteenth PIM commands respectively. Subsequently, upon receiving the seventeenth to thirty-second local memory data DA16 to DA31 and the seventeenth to thirty-second microinstructions, the first to sixteenth PIM controllers 640(0) to 640(15) generate and output the seventeenth to thirty-second PIM commands respectively. The first to sixteenth PIM commands are transmitted to the first to sixteenth PIM devices 110(0) to 110(15) through the first to sixteenth channels CH0 to CH15 respectively. Similarly, the seventeenth to thirty-second PIM commands are transmitted to the first to sixteenth PIM devices 110(0) to 110(15) through the first to sixteenth channels CH0 to CH15 respectively.

[0292] Each of the first to thirty-second PIM commands includes an operation type, local memory data, and a column address. The operation type included in each of the first to thirty-second PIM commands is specified as "WRGB". The first to thirty-second local memory data included in the first to thirty-second PIM commands correspond to the first to thirty-second local memory data DA0 to DA31 transferred from the first to sixteenth local memories 630(0) to 630(15). The first to sixteenth column addresses included in the first to sixteenth PIM commands correspond to the first to sixteenth column addresses included in the first to sixteenth microinstructions. Similarly, the seventeenth to thirty-second column addresses included in the seventeenth to thirty-second PIM commands correspond to the seventeenth to thirty-second column addresses included in the seventeenth to thirty-second microinstructions.

[0293] like Figure 42 As shown, the first PIM controller 640(0) outputs a first PIM command, which includes an operation type specified as "WRGB", first local memory data "DA0", and a first column address "0". Subsequently, the first PIM controller 640(0) outputs a seventeenth PIM command, which includes an operation type specified as "WRGB", seventeenth local memory data "DA16", and seventeenth column address "16". Similarly, the second PIM controller 640(1) outputs a second PIM command, which includes an operation type specified as "WRGB", second local memory data "DA1", and second column address "1". Subsequently, the second PIM controller 640(1) outputs an eighteenth PIM command, which includes an operation type specified as "WRGB", eighteenth local memory data "DA17", and eighteenth column address "17". In the same manner, the sixteenth PIM controller 640(15) outputs a sixteenth PIM command, which includes an operation type specified as "WRGB", sixteenth local memory data "DA15", and sixteenth column address "15". Subsequently, the sixteenth PIM controller 640 (15) outputs the thirty-second PIM command, which includes the operation type specified as "WRGB", the thirty-second local memory data "DA31" and the thirty-second column address "31".

[0294] Although not shown in the figure, after receiving the first to sixteenth PIM commands, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the first to sixteenth local memory data DA0 to DA15 into the storage location of the global buffer specified by the corresponding column address included in the first to sixteenth PIM commands. Similarly, after receiving the seventeenth to thirty-second PIM commands, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the seventeenth to thirty-second local memory data DA16 to DA31 into the storage location of the global buffer specified by the corresponding column address included in the seventeenth to thirty-second PIM commands.

[0295] For example, the first PIM device 110(0) stores the first local memory data “DA0” into the storage location of the global buffer specified by column address “0” included in the first PIM command. The second PIM device 110(1) stores the second local memory data “DA1” into the storage location of the global buffer specified by column address “1” included in the second PIM command. In the same manner, the sixteenth PIM device 110(15) stores the sixteenth local memory data “DA15” into the storage location of the global buffer specified by column address “15” included in the sixteenth PIM command. Subsequently, the first PIM device 110(0) stores the seventeenth local memory data “DA16” into the storage location of the global buffer specified by column address “16” included in the seventeenth PIM command. The second PIM device 110(1) stores the eighteenth local memory data “DA17” into the storage location of the global buffer specified by column address “17” included in the eighteenth PIM command. Similarly, the sixteenth PIM device 110 (15) stores the thirty-second local memory data “DA31” into the storage location specified by the column address “31” included in the thirty-second PIM command in the global buffer.

[0296] Figures 43 to 46 It is shown in Figure 32 Execution in the PIM system Figure 19 A diagram illustrating an example process of the third macro instruction. In this example, it is assumed that the PIM system 20 includes channels CH0 through CH15, numbered 1 through 16. It is further assumed that the operation type, iteration count, channel mask, local memory address, column address, broadcast bit, and local memory increment size of the third macro instruction are set to “WRGB”, “64”, “1111 1111 1111 1111”, “0”, “0”, “1”, and “2”, respectively.

[0297] Reference Figure 43After receiving the third macro instruction, the multicast interconnect 610 generates and outputs one or more sub-macro instructions based on the third macro instruction. Since the first to sixteenth bits of the channel mask included in the third macro instruction all have the binary value "1", the multicast interconnect 610 generates the first to sixteenth sub-macro instructions. The multicast interconnect 610 transmits the first to sixteenth sub-macro instructions to the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) respectively through the first to sixteenth channels CH0 to CH15. Each of the first to sixteenth sub-macro instructions may include an operation type, iteration number, local memory address, column address, broadcast bit, and local memory increment size. The operation type, iteration number, local memory address, column address, broadcast bit, and local memory increment size included in each of the first to sixteenth sub-macro instructions are the same as those included in the third macro instruction. Therefore, each of the first to sixteenth submacro instructions includes an operation type set to "WRGB", an iteration number set to "64", a local memory address set to "0", a column address set to "0", a broadcast bit set to "1", and a local memory increment size set to "2".

[0298] Reference Figure 44 Each of the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) generates and outputs the first to sixteenth local memory instruction set and the first to sixteenth microinstruction set based on the corresponding first to sixteenth submacro instructions. The first to sixteenth instruction decoders and sequencers 620(0) to 620(15) respectively transmit the first to sixteenth local memory instruction set to the first to sixteenth local memory 630(0) to 630(15). In addition, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) respectively transmit the first to sixteenth microinstruction set to the first to sixteenth PIM controller 640(0) to 640(15).

[0299] like Figure 44As shown, the first instruction decoder and sequencer 620(0) generates a first local memory instruction set and a first microinstruction set based on a first submacro instruction. The first instruction decoder and sequencer 620(0) transmits the first local memory instruction set to the first local memory 630(0) and transmits the first microinstruction set to the first PIM controller 640(0) through the first channel CH0. Similarly, the second instruction decoder and sequencer 620(1) generates a second local memory instruction set and a second microinstruction set based on a second submacro instruction. The second instruction decoder and sequencer 620(1) transmits the second local memory instruction set to the second local memory 630(1) and transmits the second microinstruction set to the second PIM controller 640(1) through the second channel CH1. Similarly, the sixteenth instruction decoder and sequencer 620 (15) generates the sixteenth local memory instruction set and the sixteenth micro instruction set based on the sixteenth submacro instruction, and transmits the sixteenth local memory instruction set to the sixteenth local memory 630 (15) and transmits the sixteenth micro instruction set to the sixteenth PIM controller 640 (15) through the sixteenth channel CH15.

[0300] Each of the first to sixteenth local memory instruction sets generated by the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) includes the first to sixty-fourth local memory instructions. Each of the first to sixty-fourth local memory instructions includes a local memory command and a local memory address. The local memory command is specified as "RD_LM", which instructs a read operation on local memory. The local memory address is sequentially incremented starting from the starting address included in the submacro instruction, incrementing by a local memory increment size "2" for each instruction. Figure 44 As shown, the first local memory instruction in the first to sixteenth local memory instruction sets all includes a local memory command specified as "RD_LM" and a local memory address specified as "0". The second local memory instruction all includes the local memory command "RD_LM" and a local memory address specified as "2". Similarly, the sixty-fourth local memory instruction all includes the local memory command "RD_LM" and a local memory address specified as "126".

[0301] Each of the first to sixteenth microinstruction sets output from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) comprises the first to sixty-fourth microinstructions. Each of the first to sixty-fourth microinstructions includes an operation type and a column address. The operation type is specified as "WRGB", which is a write operation to the global buffer. The column address is sequentially incremented starting from the starting column address included in the submacro instruction. Figure 44As shown, the first microinstruction includes an operation type specified as "WRGB" and a column address specified as "0". The second microinstruction includes an operation type specified as "WRGB" and a column address specified as "1". Similarly, the sixty-fourth microinstruction includes an operation type specified as "WRGB" and a column address specified as "63".

[0302] Reference Figure 45 After receiving the instruction sets from the first to the sixteenth local memories, LM0 630(0) to LM15 630(15) output the first to sixteenth local memory datasets respectively. Each of the first to sixteenth local memory datasets includes data from the first to the sixty-fourth local memories. Figure 45 As shown, the first local memory 630(0) outputs the first local memory data DA0_0 stored at the storage location specified by the local memory address "0" included in the first local memory instruction of the first local memory instruction set. Subsequently, the first local memory 630(0) outputs the second local memory data DA0_2 stored at the storage location specified by the local memory address "2" included in the second local memory instruction of the first local memory instruction set. Finally, the first local memory 630(0) outputs the sixty-fourth local memory data DA0_126 stored at the storage location specified by the local memory address "126" included in the sixty-fourth local memory instruction of the first local memory instruction set.

[0303] In the same manner, the second local memory 630(1) outputs the first local memory data DA1_0 stored at the memory location specified by the local memory address "0" included in the first local memory instruction of the second local memory instruction set. Subsequently, the second local memory 630(1) outputs the second local memory data DA1_2 stored at the memory location specified by the local memory address "2" included in the second local memory instruction of the second local memory instruction set. Finally, the second local memory 630(1) outputs the sixty-fourth local memory data DA1_126 stored at the memory location specified by the local memory address "126" included in the sixty-fourth local memory instruction of the second local memory instruction set.

[0304] In the same manner, the sixteenth local memory 630 (15) outputs the first local memory data DA15_0 stored at the memory location specified by the local memory address "0" included in the first local memory instruction of the sixteenth local memory instruction set. Subsequently, the sixteenth local memory 630 (15) outputs the second local memory data DA15_2 stored at the memory location specified by the local memory address "2" included in the second local memory instruction of the sixteenth local memory instruction set. Finally, the sixteenth local memory 630 (15) outputs the sixty-fourth local memory data DA15_126 stored at the memory location specified by the local memory address "126" included in the sixty-fourth local memory instruction of the sixteenth local memory instruction set.

[0305] Reference Figure 46 The first to sixteenth PIM controllers 640(0) to 640(15) receive the first to sixteenth local memory datasets from the first to sixteenth local memories 630(0) to 630(15), respectively. Specifically, the first PIM controller 640(0) sequentially receives the first to sixty-fourth local memory data DA0_0 to DA0_126 included in the first local memory dataset from the first local memory 630(0). Similarly, the second PIM controller 640(1) sequentially receives the first to sixty-fourth local memory data DA1_0 to DA1_126 included in the second local memory dataset from the second local memory 630(1). Likewise, the sixteenth PIM controller 640(15) sequentially receives the first to sixty-fourth local memory data DA15_0 to DA15_126 included in the sixteenth local memory dataset from the sixteenth local memory 630(15).

[0306] The first to sixteenth PIM controllers 640(0) to 640(15) also receive the first to sixteenth microinstruction sets from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15), respectively. Specifically, the first PIM controller 640(0) sequentially receives the first to sixty-fourth microinstructions included in the first microinstruction set from the first instruction decoder and sequencer 620(0). Similarly, the second PIM controller 640(1) sequentially receives the first to sixty-fourth microinstructions included in the second microinstruction set from the second instruction decoder and sequencer 620(1). Likewise, the sixteenth PIM controller 640(15) sequentially receives the first to sixty-fourth microinstructions included in the sixteenth microinstruction set from the sixteenth instruction decoder and sequencer 620(15).

[0307] The first to sixteenth PIM controllers 640(0) to 640(15) generate and output the first to sixteenth PIM command sets, respectively. Each of the first to sixteenth PIM command sets includes the first to sixty-fourth PIM commands. Each of the first to sixty-fourth PIM commands includes an operation type, local memory data, and a column address. The operation type included in each of the first to sixty-fourth PIM commands is specified as "WRGB". The local memory data included in each of the first to sixty-fourth PIM commands corresponds to the local memory data included in the corresponding local memory dataset. The column address included in each of the first to sixty-fourth PIM commands corresponds to the column address included in the corresponding microinstruction set.

[0308] like Figure 46As shown, the first PIM controller 640(0) outputs a first PIM command, which includes an operation type specified as "WRGB", first local memory data "DA0_0", and a first column address "0". Subsequently, the first PIM controller 640(0) outputs a second PIM command, which includes an operation type specified as "WRGB", second local memory data "DA0_2", and a second column address "1". In the same manner, the first PIM controller 640(0) sequentially outputs the third to the sixty-third PIM commands. Finally, the first PIM controller 640(0) outputs the sixty-fourth PIM command, which includes an operation type specified as "WRGB", sixty-fourth local memory data "DA0_126", and a column address "63". Similarly, the second PIM controller 640(1) outputs a first PIM command, which includes an operation type specified as "WRGB", first local memory data "DA1_0", and a first column address "0". Subsequently, the second PIM controller 640(1) outputs a second PIM command, which includes an operation type specified as "WRGB", second local memory data "DA1_2", and second column address "1". In the same manner, the second PIM controller 640(1) sequentially outputs the third to the sixty-third PIM commands. Finally, the second PIM controller 640(1) outputs the sixty-fourth PIM command, which includes an operation type specified as "WRGB", sixty-fourth local memory data "DA1_126", and column address "63". Similarly, the sixteenth PIM controller 640(15) outputs a first PIM command, which includes an operation type specified as "WRGB", first local memory data "DA15_0", and first column address "0". Subsequently, the sixteenth PIM controller 640(15) outputs a second PIM command, which includes an operation type specified as "WRGB", second local memory data "DA15_2", and second column address "1". In the same manner, the sixteenth PIM controller 640(15) sequentially outputs the third to the sixty-third PIM commands. Finally, the sixteenth PIM controller 640 (15) outputs the sixty-fourth PIM command, which includes the operation type specified as "WRGB", the sixty-fourth local memory data "DA15_126", and the column address "63".

[0309] Although not shown in the figures, each of the first to sixteenth PIM devices 110(0) to 110(15), upon receiving the corresponding first to sixteenth PIM command set, stores the first to sixty-fourth local memory data corresponding to the column addresses specified by the first to sixty-fourth PIM commands into the sixty-fourth storage locations of the global buffer. For example, the first PIM device 110(0) stores the first local memory data “DA0_0” into the storage location of the global buffer specified by the column address “0” included in the first PIM command. Subsequently, the first PIM device 110(0) stores the second local memory data “DA0_2” into the storage location specified by the column address “1” included in the second PIM command. In the same manner, the first PIM device 110(0) stores the third to sixty-third local memory data into the corresponding storage locations specified by the third to sixty-third PIM commands. Finally, the first PIM device 110 (0) stores the sixty-fourth local memory data “DA0_126” into the storage location specified by the column address “63” included in the sixty-fourth PIM command.

[0310] Figures 47 to 49 It is shown in Figure 32 Execution in the PIM system Figure 19 A diagram illustrating another example of the third macro instruction's process. In this example, assume that the PIM system 20 includes channels CH0 through CH15, numbered from the first to the sixteenth. Further assume that the operation type, iteration count, channel mask, local memory address, column address, broadcast bit, and local memory increment size of the third macro instruction are set to "WRGB", "32", "1111 1111 1111 1111", "0", "0", "0", and "2", respectively.

[0311] Reference Figure 47 After receiving the third macro instruction, the multicast interconnect 610 generates and outputs one or more sub-macro instructions based on the third macro instruction. Since the first to sixteenth bits of the channel mask included in the third macro instruction all have the binary value "1", the multicast interconnect 610 generates the first to sixteenth sub-macro instructions. The multicast interconnect 610 transmits the first to sixteenth sub-macro instructions to the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) respectively through the first to sixteenth channels CH0 to CH15. Specifically, as Figure 47 As shown, the multicast interconnect 610 transmits the first submacro instruction to the first instruction decoder and sequencer 620 (0) via the first channel CH0. The second submacro instruction is transmitted from the multicast interconnect 610 to the second instruction decoder and sequencer 620 (1) via the second channel CH1. Similarly, the sixteenth submacro instruction is transmitted from the multicast interconnect 610 to the sixteenth instruction decoder and sequencer 620 (15) via the sixteenth channel CH15.

[0312] Each of the first through sixteenth submacro instructions may include an operation type, iteration count, local memory address, column address, broadcast bits, and local memory increment size. The operation type, iteration count, local memory address, column address, broadcast bits, and local memory increment size included in each of the first through sixteenth submacro instructions are the same as those included in the third macro instruction. Therefore, each of the first through sixteenth submacro instructions includes an operation type set to "WRGB", an iteration count set to "32", a local memory address set to "0", a column address set to "0", a broadcast bit set to "0", and a local memory increment size set to "2".

[0313] Reference Figure 48 Since the broadcast bit in each of the first to sixteenth submacro instructions is set to the binary value "0", the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) generate and output the first to thirty-second local memory instructions and the first to thirty-second micro instructions, respectively. Specifically, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the first to sixteenth local memory instructions. The first to sixteenth local memory instructions are transferred to the first to sixteenth local memories 630(0) to 630(15), respectively. Subsequently, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the seventeenth to thirty-second local memory instructions, respectively. The seventeenth to thirty-second local memory instructions are also transferred to the first to sixteenth local memories 630(0) to 630(15), respectively.

[0314] The first through thirty-second local memory instructions each include a local memory command and a local memory address. The local memory command included in each of the first through thirty-second local memory instructions is designated as "RD_LM," indicating a read operation on local memory. The local memory addresses included in the first through thirty-second local memory instructions sequentially increment from local memory address "0" included in the first through sixteenth submacro instructions, with increments of local memory increment size "2."

[0315] like Figure 48As shown, the first local memory address included in the first local memory instruction output from the first instruction decoder and sequencer 620(0) is designated as "0". The second local memory address included in the second local memory instruction output from the second instruction decoder and sequencer 620(1) is designated as "2". Similarly, the sixteenth local memory address included in the sixteenth local memory instruction output from the sixteenth instruction decoder and sequencer 620(15) is designated as "30". Subsequently, the seventeenth local memory address included in the seventeenth local memory instruction output from the first instruction decoder and sequencer 620(0) is designated as "32". The eighteenth local memory address included in the eighteenth local memory instruction output from the second instruction decoder and sequencer 620(1) is designated as "34". Likewise, the thirty-second local memory address included in the thirty-second local memory instruction output from the sixteenth instruction decoder and sequencer 620(15) is designated as "62".

[0316] When the first to sixteenth local memory instructions are transmitted, the first to sixteenth local memory 630(0) to 630(15) respectively output the corresponding first to sixteenth local memory data DA0, DA2, ..., DA30. Subsequently, when the seventeenth to thirty-second local memory instructions are transmitted, the first to sixteenth local memory 630(0) to 630(15) respectively output the corresponding seventeenth to thirty-second local memory data DA32, DA34, ..., DA62. The first to sixteenth local memory data DA0, DA2, ..., DA30 output from the first to sixteenth local memory 630(0) to 630(15) are data stored in the storage locations specified by local memory addresses "0", "2", ..., "30". Similarly, the seventeenth to thirty-second local memory data DA32, DA34, ..., DA62 output from the first to sixteenth local memory 630(0) to 630(15) are data stored in the storage locations specified by the local memory addresses “32”, “34”, ..., “62”.

[0317] In addition, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the first to sixteenth microinstructions respectively. The first to sixteenth microinstructions are output through channels CH0 to CH15 respectively. Subsequently, the first to sixteenth instruction decoders and sequencers 620(0) to 620(15) output the seventeenth to thirty-second microinstructions respectively. The seventeenth to thirty-second microinstructions are also output through channels CH0 to CH15 respectively. Each of the first to thirty-second microinstructions includes an operation type specified as "WRGB", a column address, and a broadcast bit specified as "0". The column addresses included in the first to thirty-second microinstructions are sequentially incremented starting from column address "0" included in the first to sixteenth submacro instructions.

[0318] like Figure 48 As shown, the column address included in the first microinstruction output from the first instruction decoder and sequencer 620(0) is specified as "0". The column address included in the second microinstruction output from the second instruction decoder and sequencer 620(1) is specified as "1". Similarly, the column address included in the sixteenth microinstruction output from the sixteenth instruction decoder and sequencer 620(15) is specified as "15". Subsequently, the column address included in the seventeenth microinstruction output from the first instruction decoder and sequencer 620(0) is specified as "16". The column address included in the eighteenth microinstruction output from the second instruction decoder and sequencer 620(1) is specified as "17". Similarly, the column address included in the thirty-second microinstruction output from the sixteenth instruction decoder and sequencer 620(15) is specified as "31".

[0319] Reference Figure 49 The first PIM controller 640(0) to the sixteenth PIM controller 640(15) sequentially receive first to sixteenth local memory data DA0, DA2, ..., DA30 from the first local memory 630(0) to the sixteenth local memory 630(15), and also receive first to sixteenth micro-instructions from the first instruction decoder and sequencer 620(0) to the sixteenth instruction decoder and sequencer 620(15). Subsequently, the first PIM controller 640(0) to the sixteenth PIM controller 640(15) sequentially receive seventeenth to thirty-second local memory data DA32, DA34, ..., DA62 from the first local memory 630(0) to the sixteenth local memory 630(15), and also receive seventeenth to thirty-second micro-instructions from the first instruction decoder and sequencer 620(0) to the sixteenth instruction decoder and sequencer 620(15).

[0320] When the first to sixteenth local memory data DA0, DA2, ..., DA30 and the first to sixteenth microinstructions are received, the first PIM controller 640(0) to the sixteenth PIM controller 640(15) generate and output the first to sixteenth PIM commands respectively. Subsequently, when the seventeenth to thirty-second local memory data DA32, DA34, ..., DA62 and the seventeenth to thirty-second microinstructions are received, the first PIM controller 640(0) to the sixteenth PIM controller 640(15) generate and output the seventeenth to thirty-second PIM commands respectively.

[0321] The first to sixteenth PIM commands are transmitted to the first to sixteenth PIM devices 110(0) to 110(15) via channels CH0 to CH15, respectively. Similarly, the seventeenth to thirty-second PIM commands are transmitted to the first to sixteenth PIM devices 110(0) to 110(15) via channels CH0 to CH15, respectively. Each of the first to thirty-second PIM commands includes an operation type, local memory data, and a column address. The operation type included in each of the first to thirty-second PIM commands is specified as "WRGB". The first to thirty-second local memory data DA0, DA2, ..., DA30, DA32, DA34, ..., DA62 included in the first to thirty-second PIM commands correspond to the first to thirty-second local memory data transmitted from the first to sixteenth local memories 630(0) to 630(15), respectively. The first to sixteenth column addresses included in the first to sixteenth PIM commands correspond to the first to sixteenth column addresses included in the first to sixteenth microinstructions, respectively. Similarly, the addresses in columns 17 to 32 included in PIM commands 17 to 32 correspond to the addresses in columns 17 to 32 included in microinstructions 17 to 32, respectively.

[0322] like Figure 49As shown, the first PIM controller 640(0) outputs a first PIM command, which includes an operation type specified as "WRGB", first local memory data DA0, and a first column address "0". Subsequently, the first PIM controller 640(0) outputs a seventeenth PIM command, which includes an operation type specified as "WRGB", seventeenth local memory data DA32, and seventeenth column address "16". Similarly, the second PIM controller 640(1) outputs a second PIM command, which includes an operation type specified as "WRGB", second local memory data DA2, and a second column address "1". Subsequently, the second PIM controller 640(1) outputs an eighteenth PIM command, which includes an operation type specified as "WRGB", eighteenth local memory data DA34, and eighteenth column address "17". Likewise, the sixteenth PIM controller 640(15) outputs a sixteenth PIM command, which includes an operation type specified as "WRGB", sixteenth local memory data DA30, and sixteenth column address "15". Subsequently, the sixteenth PIM controller 640 (15) outputs the thirty-second PIM command, which includes the operation type specified as "WRGB", the thirty-second local memory data DA62, and the thirty-second column address "31".

[0323] Although not explicitly shown in the figure, after receiving the first to sixteenth PIM commands, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the first to sixteenth local memory data DA0, DA2, ..., DA30 in the storage location of the global buffer specified by the corresponding column address included in the corresponding PIM command. Similarly, after receiving the seventeenth to thirty-second PIM commands, the first to sixteenth PIM devices 110(0) to 110(15) respectively store the seventeenth to thirty-second local memory data DA32, DA34, ..., DA62 in the storage location of the global buffer specified by the corresponding column address included in the corresponding PIM command.

[0324] For example, the first PIM device 110 (0) stores the first local memory data DA0 in the storage location specified by the column address "0" of the first PIM command in the global buffer. The second PIM device 110 (1) stores the second local memory data DA2 in the storage location specified by the column address "1" of the second PIM command in the global buffer. Similarly, the sixteenth PIM device 110 (15) stores the sixteenth local memory data DA30 in the storage location specified by the column address "15" of the sixteenth PIM command in the global buffer. Next, the first PIM device 110 (0) stores the seventeenth local memory data DA32 in the storage location specified by the column address "16" of the seventeenth PIM command in the global buffer. The second PIM device 110 (1) stores the eighteenth local memory data DA34 in the storage location specified by the column address "17" of the eighteenth PIM command in the global buffer. Similarly, the sixteenth PIM device 110 (15) stores the thirty-second local memory data DA62 in the storage location specified by the column address "31" of the thirty-second PIM command in the global buffer.

[0325] Figures 50 to 52 It is shown in Figure 32 Execution in the PIM system Figure 28 A diagram illustrating the process of the fourth macro instruction. In this example, assume that the PIM system 20 includes channels CH0 through CH15, numbered 1 through 16. Further assume that the operation type, channel mask, local memory address, MAC latch ID, and broadcast bit of the fourth macro instruction are set to “WRBIAS”, “11111111 1111 1111”, “0”, “0”, and “0”, respectively.

[0326] Reference Figure 50 After receiving the fourth macro instruction, the multicast interconnect 610 generates and outputs one or more sub-macro instructions based on the fourth macro instruction. Since the first to sixteenth bits of the channel mask included in the fourth macro instruction all have the binary value "1", the multicast interconnect 610 generates the first to sixteenth sub-macro instructions. The multicast interconnect 610 transmits the first to sixteenth sub-macro instructions to the first instruction decoder and sequencer 620 (0) to the sixteenth instruction decoder and sequencer 620 (15) respectively through the first channel CH0 to the sixteenth channel CH15. Specifically, as Figure 50 As shown, the first submacro instruction is transmitted from the multicast interconnect 610 to the first instruction decoder and sequencer 620 (0) via the first channel CH0. Similarly, the second submacro instruction is transmitted to the second instruction decoder and sequencer 620 (1) via the second channel CH1, while the sixteenth submacro instruction is transmitted to the sixteenth instruction decoder and sequencer 620 (15) via the sixteenth channel CH15.

[0327] Each of the first through sixteenth submacro instructions may include an operation type, a local memory address, a MAC latch ID, and a broadcast bit. The operation type, local memory address, MAC latch ID, and broadcast bit included in each of the first through sixteenth submacro instructions are the same as those included in the fourth macro instruction. Therefore, each of the first through sixteenth submacro instructions includes an operation type set to "WRBIAS", a local memory address set to "0", a MAC latch ID set to "0", and a broadcast bit set to "0". In some cases, the broadcast bit in the first through sixteenth submacro instructions may also be omitted when the broadcast bit set to a binary value of "0" in the fourth macro instruction is omitted.

[0328] Reference Figure 51 The first instruction decoder and sequencer 620(0) to the sixteenth instruction decoder and sequencer 620(15) generate and output the first to sixteenth local memory instructions and the first to sixteenth micro-instructions, respectively. Specifically, the first instruction decoder and sequencer 620(0) to the sixteenth instruction decoder and sequencer 620(15) output the first to sixteenth local memory instructions, respectively. The first to sixteenth local memory instructions are respectively transmitted to the first local memory 630(0) to the sixteenth local memory 630(15). Each of the first to sixteenth local memory instructions includes a local memory command and a local memory address. The local memory command included in each local memory instruction is specified as "RD_LM", which indicates a read operation on the local memory. The local memory addresses included in the first to sixteenth local memory instructions are sequentially incremented starting from the local memory address "0" included in the corresponding submacro instruction. Figure 51 As shown, the first local memory address output from the first instruction decoder and sequencer 620 (0) is designated as "0", the second local memory address output from the second instruction decoder and sequencer 620 (1) is designated as "1", and similarly, the sixteenth local memory address output from the sixteenth instruction decoder and sequencer 620 (15) is designated as "15".

[0329] When the first to sixteenth local memory instructions are transmitted, the first local memory 630(0) to the sixteenth local memory 630(15) output the first to sixteenth local memory data DA0 to DA15 respectively. The first to sixteenth local memory data DA0 to DA15 output from the local memory 630(0) to 630(15) correspond to the data stored at the storage locations specified by the local memory addresses "0" to "15".

[0330] Additionally, the first instruction decoder and sequencer 620(0) to the sixteenth instruction decoder and sequencer 620(15) output the first to sixteenth microinstructions respectively. The first to sixteenth microinstructions are transmitted through channels CH0 to CH15 respectively. Each of the first to sixteenth microinstructions includes an operation type designated as "WRBIAS" and a MAC latch ID. The column addresses included in the first to sixteenth microinstructions are sequentially incremented starting from the column address "0" of the corresponding submacro instruction. For example... Figure 51 As shown, the column address of the first microinstruction output from the first instruction decoder and sequencer 620 (0) is “0”, the column address of the second microinstruction output from the second instruction decoder and sequencer 620 (1) is “1”, and similarly, the column address of the sixteenth microinstruction output from the sixteenth instruction decoder and sequencer 620 (15) is “15”.

[0331] Reference Figure 52 Each of the first PIM controllers 640(0) to the sixteenth PIM controllers 640(15) sequentially receives first to sixteenth local memory data DA0 to DA15 from the corresponding first to sixteenth local memories 630(0) to 630(15), and also sequentially receives first to sixteenth micro-instructions from the first to sixteenth instruction decoders and sequencers 620(0) to 620(15). When the first to sixteenth local memory data DA0 to DA15 and the first to sixteenth micro-instructions are transmitted, the first to sixteenth PIM controllers 640(0) to 640(15) respectively generate and output the corresponding first to sixteenth PIM commands. The first to sixteenth PIM commands are transmitted to the first to sixteenth PIM devices 110(0) to 110(15) respectively through the corresponding first to sixteenth channels CH0 to CH15.

[0332] Each of the first through sixteenth PIM commands includes an operation type, local memory data, and a MAC latch ID. The operation type included in each PIM command is specified as "WRBIAS". The local memory data included in each PIM command corresponds to local memory data DA0 through DA15 received from local memory 630(0) through 630(15). The MAC latch IDs included in the first through sixteenth PIM commands are the same as the MAC latch IDs included in the corresponding first through sixteenth microinstructions. Figure 52As shown, the first PIM controller 640 (0) outputs a first PIM command, which includes an operation type specified as "WRBIAS", first local memory data DA0, and MAC latch ID "0". Similarly, the second PIM controller 640 (1) outputs a second PIM command, which includes an operation type specified as "WRBIAS", second local memory data DA1, and MAC latch ID "0". In the same manner, the sixteenth PIM controller 640 (15) outputs a sixteenth PIM command, which includes an operation type specified as "WRBIAS", sixteenth local memory data DA15, and MAC latch ID "0".

[0333] Although not shown in the figure, each of the first PIM devices 110(0) to the sixteenth PIM devices 110(15), upon receiving the corresponding PIM command in the first to sixteenth PIM commands, latches the corresponding local memory data from the first to sixteenth local memory data DA0 to DA15 into the latching circuit specified by the corresponding MAC latch ID in the first to sixteenth MAC latch IDs included in the corresponding PIM command. For example, the first PIM device 110(0) latches the first local memory data DA0 into the latching circuit specified by the first MAC latch ID "0" included in the first PIM command. The second PIM device 110(1) latches the second local memory data DA1 into the latching circuit specified by the second MAC latch ID "0" included in the second PIM command. In the same manner, the sixteenth PIM device 110(15) latches the sixteenth local memory data DA15 into the latching circuit specified by the MAC latch ID "0" included in the sixteenth PIM command.

[0334] Figure 53 This is a block diagram illustrating yet another embodiment of the PIM system according to the present disclosure.

[0335] Reference Figure 53The PIM system 10 includes multiple PIM devices, such as first to j-th PIM devices (PIM0 to PIM"j-1") 110(0) to 110(j-1), and a PIM central system 700. The first to j-th PIM devices 110(0) to 110(j-1) are coupled to the PIM central system 700 via first to j-th channels CH0 to CH"j-1, respectively. Here, first to j-th channels CH0 to CH"j-1 represent the physical connection between the first to j-th PIM devices 110(0) to 110(j-1) and the PIM central system 700. Each of the first to j-th channels CH0 to CH"j-1 has an independent data bus. Therefore, signal transmission between the first to j-th PIM devices 110(0) to 110(j-1) and the PIM central system 700 can be performed simultaneously via the first to j-th channels CH0 to CH"j-1. Figure 53 As shown, the first PIM device 110(0) is coupled to the PIM central system 700 via the first channel CH0. The second PIM device 110(1) is coupled to the PIM central system 700 via the second channel CH1. The third PIM device 110(2) is coupled to the PIM central system 700 via the third channel CH2. The "(j-1)" PIM device 110(j-2) is coupled to the PIM central system 700 via the "(j-1)" channel CH"j-2", while the j-th PIM device 110(j-1) is coupled to the PIM central system 700 via the j-th channel CH"j-1". Although Figure 53 Not shown in the diagram, but in another embodiment, two or more PIM devices may share a single channel to be coupled to the PIM central system 700. In this case, the PIM system 30 may include a number of PIM devices that are multiples of "j". The structure and operation of the first to jth PIM devices 110(0) to 110(j-1) can be compared with those in the reference diagram. Figures 1 to 3 The descriptions are the same.

[0336] PIM central system 700 controls the operation of the first to j-th PIM devices 110(0) to 110(j-1). PIM central system 700 can be coupled to a host computer. PIM central system 700 can also be coupled to another PIM central system included in a different PIM system. PIM central system 700 can receive macro instructions from the host computer. Based on the macro instructions transmitted from the host computer, PIM central system 700 can generate one or more PIM command sets. PIM central system 700 can transmit one or more PIM commands or one or more PIM command sets to one or more of the first to j-th PIM devices 110(0) to 110(j-1).

[0337] The PIM central system 700 may include a first-level instruction decoder and sequencer 711, a second-level instruction decoder and sequencer 712, a local memory 720, a multicast interconnect 730, and first to j-th PIM controllers 740(0) to 740(j-1). The first-level instruction decoder and sequencer 711 is coupled to the second-level instruction decoder and sequencer 712. The second-level instruction decoder and sequencer 712 is coupled to the local memory 720 and the multicast interconnect 730. The multicast interconnect 730 is coupled to the local memory 720. In addition, the multicast interconnect 730 is coupled to the first to j-th PIM controllers 740(0) to 740(j-1). The first to j-th PIM controllers 740(0) to 740(j-1) are coupled to the first to j-th PIM devices 110(0) to 110(j-1) via the first to j-th channels CH0 to CH"j-1".

[0338] although Figure 53 Not shown in the image, but related to the reference. Figure 1 Similar to the PIM center system 200 of the described PIM system 10, the PIM center system 700 may include a host interface, a network router, and a computing unit. In this case, the host interface may be coupled to the first-level instruction decoder and sequencer 711, the network router may be coupled to the multicast interconnect 730, and the computing unit may be coupled to the second-level instruction decoder and sequencer 712 and the multicast interconnect 730.

[0339] The first-level instruction decoder and sequencer 711 can receive macro instructions transmitted from the host to the PIM central system 700. In one example, the macro instructions transmitted to the first-level instruction decoder and sequencer 711 may include operation type, matrix row count, matrix column count, starting bias address, starting input vector address, starting row address, starting column address, starting memory address, and starting channel. The operation type can be specified as a command specifying a matrix-vector multiplication operation, such as "GEMV". The matrix row count indicates the number of rows in the weight matrix used for the matrix-vector multiplication operation. The matrix column count indicates the number of columns in the weight matrix used for the matrix-vector multiplication operation. The starting bias address indicates the starting address in local memory where the bias data is stored. The starting input vector address indicates the starting address in local memory where the input vector data is stored. The starting row address indicates the row address in memory where the weight data used for the matrix-vector multiplication operation is stored. The starting column address indicates the starting column address in memory where the weight data is stored. The starting memory address indicates the starting memory address in memory where the weight data is stored. The starting channel indicates the starting channel among multiple channels.

[0340] The first-level instruction decoder and sequencer 711 can generate and output one or more first-level micro-instructions based on macro instructions. The first-level instruction decoder and sequencer 711 can transmit the first-level micro-instructions to the second-level instruction decoder and sequencer 712. The first-level micro-instruction output from the first-level instruction decoder and sequencer 711 can be a low-level macro instruction corresponding to a received macro instruction. For example, the operation specified by the macro instruction can be implemented by sequentially executing multiple sub-operations. The first-level micro-instruction output from the first-level instruction decoder and sequencer 711 specifies the first sub-operation to be executed among the multiple sub-operations. The next first-level micro-instruction output specifies the second sub-operation to be executed after the first sub-operation. The final first-level micro-instruction output specifies the last sub-operation to be executed among the multiple sub-operations.

[0341] In one implementation, the first-level microinstruction output from the first-level instruction decoder and sequencer 711 can correspond to a reference. Figure 7 The first macro instruction described is 510, see reference. Figure 11 The second macro instruction 520 described, see reference. Figure 19 The third macro instruction described is 530 or refer to Figure 28 The fourth macro instruction 540 is described. In one embodiment, the first-level instruction decoder and sequencer 711 may first output the first-level instruction corresponding to the fourth macro instruction, then output the first-level instruction corresponding to the second macro instruction, and finally output the first-level instruction corresponding to the first macro instruction. In another embodiment, the first-level instruction decoder and sequencer 711 may first output the first-level instruction corresponding to the fourth macro instruction, then output the first-level instruction corresponding to the third macro instruction, and finally output the first-level instruction corresponding to the first macro instruction.

[0342] The second-level instruction decoder and sequencer 712 can output a second-level microinstruction set based on the first-level microinstructions. The second-level instruction decoder and sequencer 712 can also output the local memory instruction set together with the second-level microinstruction set. In one embodiment, when the first-level microinstruction corresponds to a first macroinstruction, the second-level instruction decoder and sequencer 712 can output only the second-level microinstruction set without outputting the local memory instruction set. In another embodiment, when the first-level microinstruction corresponds to a second, third, or fourth macroinstruction, the second-level instruction decoder and sequencer 712 can output the second-level microinstruction set together with the local memory instruction set. The second-level instruction decoder and sequencer 712 can transmit the second-level microinstruction set to the multicast interconnect 730. The second-level instruction decoder and sequencer 712 can transmit the local memory instruction set to the local memory 720.

[0343] In one implementation, when a first-level microinstruction corresponding to a first macroinstruction in which the operation type is specified as "MAC" is transmitted, the second-level instruction decoder and sequencer 712 generate and output a second-level microinstruction set including the first to the "m"th microinstructions. Here, "m" represents the number of iterations included in the first-level microinstructions. In this case, the process of generating the first to the "m"th microinstructions included in the second-level microinstruction set can be similar to that described in the reference... Figure 8 The process for generating the first through sixty-fourth microinstructions is the same. Therefore, the first through "m" microinstructions included in the second-level microinstruction set may include operation type, channel mask, row address, and column address.

[0344] In one implementation, when transmitting a first-level microinstruction corresponding to a second or third macroinstruction whose operation type is specified as "WRGB" and whose broadcast bit has a binary value of "1", the second-level instruction decoder and sequencer 712 generate and output a second-level microinstruction set including the first to "m"th microinstructions and a local memory instruction set including the first to "m"th local memory instructions. In this case, each of the first to "m"th microinstructions may include an operation type, a channel mask, a column address, and a broadcast bit. Each of the first to "m"th local memory instructions may include a local memory command and a local memory address. When transmitting a first-level microinstruction corresponding to a second or third macroinstruction whose operation type is specified as "WRGB" and whose broadcast bit has a binary value of "0", the second-level instruction decoder and sequencer 712 generate and output a second-level microinstruction set including "m×t" microinstructions and a local memory instruction set including "m×t" local memory instructions. Here, "t" represents the number of bits with a binary value of "1" in the channel mask bits included in the first-level microinstruction. In this context, each of the "m×t" microinstructions included in the Level 2 microinstruction set may include an operation type, channel mask, column address, and broadcast bit. Each of the "m×t" local memory instructions included in the local memory instruction set may include a local memory command and a local memory address.

[0345] When the broadcast bit included in the first-level microinstruction set has a binary value of "1", the process of generating the first to the "m"th microinstructions included in the second-level microinstruction set and the first to the "m"th local memory instructions included in the local memory instruction set can be compared with the reference. Figure 12The process for generating the first to sixty-fourth microinstructions and the first to sixty-fourth local memory instructions is the same as described. When the first-level microinstruction includes both a broadcast bit with a binary value of "1" and a local memory increment size, the process for generating the first to "m"th microinstructions included in the second-level microinstruction set and the first to "m"th local memory instructions included in the local memory instruction set can be the same as described in the reference. Figure 20 The process for generating the first through sixty-fourth microinstructions and the first through sixty-fourth local memory instructions is identical. Therefore, the first through "m"th microinstructions included in the second-level microinstruction set may include operation type, channel mask, column address, and broadcast bit. Furthermore, the first through "m"th local memory instructions included in the local memory instruction set may include local memory commands and local memory addresses.

[0346] When the broadcast bit included in the first-level microinstruction set has a binary value of "0", the process of generating the "m×t" microinstructions included in the second-level microinstruction set and the "m×t" local memory instructions included in the local memory instruction set can be compared with the reference. Figure 15 The process for generating 512 microinstructions and 512 local memory instructions is the same as described. When the first-level microinstruction set includes both a broadcast bit with a binary value of "0" and a local memory increment size, the process for generating the "m×t" microinstructions in the second-level microinstruction set and the "m×t" local memory instructions in the local memory instruction set can be the same as described in the reference. Figure 24 The process for generating 512 microinstructions and 512 local memory instructions is the same.

[0347] In one implementation, when the second-level microinstruction set and the local memory instruction set are generated based on first-level microinstructions corresponding to a fourth macroinstruction in which the operation type is specified as "WRBIAS", the second-level microinstruction set output from the second-level instruction decoder and sequencer 712 may include "t" microinstructions, and the local memory instruction set may include "t" local memory instructions. In this case, each of the "t" microinstructions included in the second-level microinstruction set may include an operation type, a channel mask, a MAC latch ID, and a broadcast bit. Each of the "t" local memory instructions included in the local memory instruction set may include a local memory command and a local memory address. The process of generating the "t" microinstructions included in the second-level microinstruction set and the "t" local memory instructions included in the local memory instruction set can be compared with the referenced Figure 29 The process for generating the first through sixteenth microinstructions and the first through sixteenth local memory instructions is the same.

[0348] When a local memory instruction set is transmitted from the second-level instruction decoder and sequencer 712, the local memory 720 performs local memory operations based on the local memory instruction set. In one embodiment, when the local memory instruction set is generated based on a first-level microinstruction corresponding to a second or third macroinstruction, the local memory 720 outputs vector data stored in the memory location specified by the local memory address included in the first to "m"th local memory instructions and transmits the vector data to the multicast interconnect 730. In another embodiment, when the local memory instruction set is generated based on a first-level microinstruction corresponding to a fourth macroinstruction, the local memory 720 outputs bias data stored in the memory location specified by the local memory address included in the first to jth local memory instructions and transmits the bias data to the multicast interconnect 730.

[0349] When the second-level microinstruction set is transmitted from the second-level instruction decoder and sequencer 712 to the multicast interconnect 730, the multicast interconnect 730 can generate one or more sub-microinstruction sets based on the second-level microinstruction set. When the second-level microinstruction set and local memory data are transmitted from the second-level instruction decoder and sequencer 712 and local memory 720 to the multicast interconnect 730, respectively, the multicast interconnect 730 can generate one or more sub-microinstruction sets based on the second-level microinstruction set and local memory data.

[0350] When a first-level microinstruction corresponds to a first macroinstruction in which the operation type is specified as "MAC", the multicast interconnect 730 generates and outputs at least one of the first to j-th sub-microinstruction sets based on the first to "m"-th microinstructions transmitted from the second-level instruction decoder and sequencer 712. Each sub-microinstruction set may include the first to "m"-th sub-microinstructions. Each of the first to "m"-th sub-microinstructions may include an operation type specified as "MAC", a row address, and a column address. The process of generating at least one of the first to j-th sub-microinstruction sets can be described with reference to... Figure 9 The process for generating the first through sixteenth submicro instruction sets is performed in the same manner.

[0351] When a first-level microinstruction corresponds to a second or third macroinstruction in which the operation type is specified as "WRGB" and the broadcast bit has a binary value of "1", the multicast interconnect 730 generates and outputs at least one of the first to j sub-microinstruction sets based on the first to "m" microinstructions and the first to "m" local memory data transmitted from the second-level instruction decoder and sequencer 712. Each sub-microinstruction set may include the first to "m" sub-microinstructions. Each of the first to "m" sub-microinstructions may include an operation type specified as "WRGB", local memory data, and a column address. The process of generating at least one of the first to j sub-microinstruction sets can be compared with reference to... Figure 13 or Figure 22The process for generating the first through sixteenth submicro instruction sets is performed in the same manner.

[0352] When a first-level microinstruction corresponds to a second or third macroinstruction whose operation type is specified as "WRGB" and whose broadcast bit has a binary value of "0", the multicast interconnect 730 generates and outputs "m×t" sub-microinstruction sets based on "m×t" microinstructions and "m×t" local memory data transmitted from the second-level instruction decoder and sequencer 712. The process of generating "m×t" sub-microinstruction sets can be compared with... Figure 17 or Figure 26 The process for generating the first through 512 submicro instruction sets is performed in the same manner.

[0353] When a first-level microinstruction corresponds to a fourth macroinstruction in which the operation type is specified as "WRBIAS", the multicast interconnect 730 generates and outputs "t" sub-microinstruction sets. Specifically, when the "i"th microinstruction is transmitted to the multicast interconnect 730, the multicast interconnect 730 generates the "i"th sub-microinstruction set. Conversely, when the "i"th microinstruction is not transmitted to the multicast interconnect 730, the multicast interconnect 730 does not generate the "i"th sub-microinstruction set. In one embodiment, the "i"th sub-microinstruction set may include an operation type specified as "WRGB", local memory data, and a MAC latch ID. The process of generating at least one of the first to jth sub-microinstruction sets can be described with reference to... Figure 30 The process for generating the first through sixteenth submicro instruction sets is performed in the same manner.

[0354] The multicast interconnect 730 transmits the sub-micro instruction set to the PIM controller. In one embodiment, when the first-level microinstruction has an operation type specified as "MAC" or "WRGB", and the broadcast bit has a binary value of "1", the "i"th sub-micro instruction set generated by the multicast interconnect 730 is transmitted to the "i"th PIM controller 740 (i-1) via the "i"th channel CH (i-1). In this case, the multicast interconnect 730 transmits the first to the "m"th sub-micro instructions included in the "i"th sub-micro instruction set sequentially to the "i"th PIM controller 740 (i-1). The process of transmitting the "i"th sub-micro instruction set to the "i"th PIM controller 740 (i-1) can be described with reference to... Figure 9 or Figure 13 The process of transmitting the first to sixteenth submicro instruction sets to the first to sixteenth PIM controllers 260(0)-260(15) is performed in the same manner as described.

[0355] In another embodiment, when the first-level microinstruction has an operation type specified as "WRGB" and a broadcast bit with a binary value of "0", the "(n-1)×j+i"th sub-microinstruction set generated by the multicast interconnect 730 is transmitted to the "i"th PIM controller 740 (i-1) through the "i"th channel CH (i-1), where n is a natural number from 1 to "m". Specifically, firstly, when "n"=1, the "i"th sub-microinstruction set is transmitted to the "i"th PIM controller 740 (i-1) through the "i"th channel CH (i-1). Next, when "n"=2, the "j+i"th sub-microinstruction set is transmitted to the "i"th PIM controller 740 (i-1) through the "i"th channel CH (i-1). Then, when "n"=3, the "2×j+i"th submicro instruction set is transmitted to the "i"th PIM controller 740 (i-1) through the "i"th channel CH (i-1). Finally, when "n"=="m", the "(m-1)×j+i"th submicro instruction set is transmitted to the "i"th PIM controller 740 (i-1) th...

Claims

1. A PIM system, wherein PIM is in-memory processing, the PIM system comprising: Multiple PIM devices; as well as The PIM central system controls the multiple PIM devices. The PIM center system includes: An instruction decoder and sequencer that receives macro instructions and generates and outputs multiple micro instructions based on the macro instructions; Multicast interconnection, which outputs one or more sub-microinstruction sets based on the plurality of microinstructions; and Multiple PIM controllers, each PIM controller being coupled to the multiple PIM devices via multiple channels, the multiple PIM controllers generating and outputting one or more PIM command sets based on the one or more submicro instruction sets.

2. The PIM system according to claim 1, in, Each of the plurality of PIM devices includes: Multiple storage volumes store weight data used as the first operand in the GEMV operation, which is a general matrix-vector multiplication. A global buffer that stores vector data used as a second operand in the GEMV operation; and Multiple processing elements perform MAC operations on the weight data and the vector data, where MAC stands for multiplication and accumulation.

3. The PIM system according to claim 2, in, Each of the plurality of processing elements includes: A multiplication circuit that performs a multiplication operation on the weight data and the vector data to output multiplied data; An adder circuit that performs an addition operation on the multiplication data output from the multiplication circuit to output addition data; and An accumulator that performs an accumulation operation on the addition data and the latched data.

4. The PIM system according to claim 3, in, The accumulator includes: An accumulator adder that performs an accumulation operation on the addition data and the latched data to output accumulated data; and A MAC latch circuit that latches the accumulated data output from the accumulator adder.

5. The PIM system according to claim 1, in, The plurality of channels includes channels 1 through j, where "j" is a natural number of 2 or greater; The plurality of PIM devices include first to j-th PIM devices; The plurality of PIM controllers include first to j-th PIM controllers; The multicast interconnects are respectively coupled to the first to the j-th PIM controllers via the first to the j-th channels; and The first to j PIM controllers are respectively coupled to the first to j PIM devices through the first to j channels.

6. The PIM system according to claim 5, in, The macro instruction is a first macro instruction, a second macro instruction, a third macro instruction, or a fourth macro instruction. The first macro instruction includes a first operation type, which specifies that a MAC operation is performed in the plurality of PIM devices. The second and third macro instructions include a second operation type, which specifies a global buffer write operation to store vector data in the global buffer of the plurality of PIM devices. The fourth macro instruction includes a third operation type, which specifies a bias data write operation that stores bias data into the latch circuit of the plurality of PIM devices.

7. The PIM system according to claim 6, in, The first macro instruction also includes the number of iterations, the channel mask, the row address, and the column address. In this macro instruction, the number of iterations is set to a number "m" indicating the number of times the MAC operation is performed, where "m" is a natural number of 2 or greater. The channel mask included in the first macro instruction includes the first to j bits corresponding to the first to j channels. Wherein, the row address included in the first macro instruction specifies the row of the memory bank storing the weight data used for the MAC operation, and The column address included in the first macro instruction specifies the column in the memory that stores the weight data.

8. The PIM system according to claim 7, in, When the first macro instruction is transmitted, the instruction decoder and sequencer output the first to the mth micro instructions. Each of the first to m microinstructions includes an operation type, a channel mask, a row address, and a column address.

9. The PIM system according to claim 8, in, The operation type included in each of the first to m-th microinstructions is the first operation type. Wherein, the channel mask and the row address included in each of the first to m-th microinstructions are the same as those included in the first macroinstruction, and The column address included in each of the first to m microinstructions is sequentially incremented starting from the starting column address included in the first macroinstruction.

10. The PIM system according to claim 9, in, The first to the mth microinstructions each include the first to the mth channel masks. Each of the first to m-th channel masks includes the first to j-th bits, and Wherein, the first to the j bits included in the first to the m-th channel mask are the same as the first to the j bits included in the channel mask in the first macro instruction.

11. The PIM system according to claim 10, in, The number of the one or more submicro instruction sets output from the multicast interconnect is determined based on the first to j bits included in each of the first to m-th channel masks.

12. The PIM system according to claim 10, in, When the i-th bit of the first to j-th bits included in each of the first to m-th channel masks has a first binary value, the multicast interconnect generates the i-th sub-micro instruction set, where "i" is a natural number from 1 to j, and Wherein, when the i-th bit of the first to j-th bits included in each of the first to m-th channel masks has a second binary value, the multicast interconnect does not generate the i-th submicro instruction set.

13. The PIM system according to claim 12, in, The i-th submicro-instruction set includes the first to the m-th submicro-instructions. Each of the first to m sub-micro instructions includes an operation type, a row address, and a column address.

14. The PIM system according to claim 13, in, The operation type included in each of the first to m-th sub-micro instructions is designated as the first operation type. Wherein, the row address included in the first to mth sub-micro instructions is the same as the row address included in the first to mth micro instructions, and Wherein, the column address included in the first to the mth sub-micro instructions is the same as the column address included in the first to the mth micro instructions.

15. The PIM system according to claim 13, in, The multicast interconnect sequentially transmits the first to m sub-micro instructions included in the i-th sub-micro instruction set to the i-th PIM controller among the first to j-th PIM controllers via the i-th channel among the first to j-th channels.

16. The PIM system according to claim 15, in, The i-th PIM controller generates the i-th PIM command set based on the first to m-th sub-micro instructions included in the i-th sub-micro instruction set. The i-th PIM command set includes: the PIM activation command and the first to m-th PIM commands.

17. The PIM system according to claim 16, in, The i-th PIM controller transmits the i-th PIM command set to the i-th PIM device among the first to j-th PIM devices through the i-th channel.

18. The PIM system according to claim 16, in, The PIM activation command includes an activation command and a row address, and Each of the first to m PIM commands includes an operation type and a column address. The activation command included in the activation PIM command is specified as the command included in the activation PIM command for activating the row indicated by the row address in the memory. The row address included in the PIM activation command is the same as the row address included in the first to m sub-micro instructions of the i-th sub-micro instruction set. Wherein, the operation type included in each of the first to m PIM commands is specified as the first operation type, and The column addresses included in the first to m PIM commands are the same as the column addresses included in the first to m sub-micro instructions in the i-th sub-micro instruction set.

19. The PIM system of claim 6, further comprising: a local memory coupled to the instruction decoder and sequencer and the multicast interconnect.

20. The PIM system according to claim 19, in, The second macro instruction also includes the iteration count, channel mask, local memory address, column address, and broadcast bit. In this second macro instruction, the number of iterations is set to a number "m" indicating the number of times the global buffer write operation is performed, where m is a natural number of 2 or greater. The channel mask included in the second macro instruction comprises the first to the j-th bits corresponding to the first to the j-th channels, respectively. The local memory address included in the second macro instruction specifies the storage location accessed in the local memory. Wherein, the column address included in the second macro instruction specifies the storage location of the vector data stored in the global buffer, and The broadcast bit included in the second macro instruction is set to a first binary value for indicating a broadcast operation or a second binary value for indicating a non-broadcast operation.

21. The PIM system according to claim 20, in, When the second macro instruction is transmitted and the broadcast bit included in the second macro instruction has the first binary value, the instruction decoder and sequencer output the first to m-th local memory instructions and the first to m-th micro instructions. Wherein, each of the first to m-th local memory instructions includes a local memory command and a local memory address, and Each of the first to m microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit.

22. The PIM system according to claim 21, in, Each of the first to m-th local memory instructions includes a local memory command that is a read command for the local memory. Wherein, the local memory address included in each of the first to m-th local memory instructions is sequentially incremented starting from the local memory address included in the second macro instruction. Wherein, the operation type included in each of the first to m-th microinstructions is the second operation type. Wherein, the channel mask and the broadcast bit included in each of the first to m-th micro-instructions are the same as the channel mask and the broadcast bit included in the second macro-instruction, and The column address included in each of the first to m microinstructions is sequentially incremented starting from the column address included in the second macroinstruction.

23. The PIM system according to claim 22, in, The first to the m-th microinstructions each include the first to the j-th channel masks. Each of the first to m-th channel masks includes the first to j-th bits, and In this embodiment, the first to the j bits included in each of the first to the m-th channel masks have the same binary value as the first to the j bits included in the channel mask of the second macro instruction.

24. The PIM system according to claim 23, in, The local memory outputs the data stored at the storage location specified by the local memory address included in the first to m local memory instructions as the first to m local memory data, and transmits the first to m local memory data to the multicast interconnect.

25. The PIM system according to claim 24, in, The multicast interconnect generates and outputs one or more sub-microinstruction sets based on the first to m-th microinstructions and the first to m-th local memory data. The number of the one or more submicro instruction sets output from the multicast interconnect is determined by the first to the j bits included in each of the first to m-th channel masks.

26. The PIM system according to claim 25, in, When the i-th bit of the first to j-th bits included in each of the first to m-th channel masks has a first binary value, the multicast interconnect generates the i-th sub-micro instruction set, where i is a natural number from 1 to j, and Wherein, when the i-th bit of the first to j-th bits included in each of the first to m-th channel masks has a second binary value, the multicast interconnect does not generate the i-th submicro instruction set.

27. The PIM system according to claim 26, in, The i-th submicro-instruction set includes the first to the m-th submicro-instructions. Each of the first to m submicro-instructions includes an operation type, local memory data, and column address.

28. The PIM system according to claim 27, in, The operation type included in each of the first to m-th sub-micro instructions is designated as the second operation type. Wherein, the local memory data included in each of the first to m-th submicro-instructions is the same as the corresponding local memory data in the first to m-th local memory data, and Wherein, the column address included in each of the first to m sub-micro instructions is the same as the corresponding column address included in the first to m micro instructions.

29. The PIM system according to claim 26, in, The multicast interconnect sequentially transmits the first to m sub-micro instructions included in the i-th sub-micro instruction set to the i-th PIM controller among the first to j-th PIM controllers via the i-th channel among the first to j-th channels.

30. The PIM system according to claim 29, in, The i-th PIM controller generates the i-th PIM command set based on the first to m-th sub-micro instructions included in the i-th sub-micro instruction set. Wherein, the i-th PIM command set includes the first to m-th PIM commands, and The i-th PIM controller transmits the i-th PIM command set to the i-th PIM device among the first to j-th PIM devices via the i-th channel.

31. The PIM system according to claim 30, in, Each of the first to m PIM commands includes an operation type, local memory data, and a column address. Wherein, the operation type included in each of the first to m PIM commands is designated as the second operation type. Wherein, the local memory data included in each of the first to m PIM commands is the same as the local memory data included in the first to m submicro-instructions of the i-th submicro-instruction set, and The column address included in each of the first to m PIM commands is the same as the column address included in the first to m sub-micro instructions of the i-th sub-micro instruction set.

32. The PIM system according to claim 20, in, When the second macro instruction is transmitted and t bits of the channel mask included in the second macro instruction have the first binary value and the broadcast bits included in the second macro instruction have the second binary value, the instruction decoder and sequencer output m×t local memory instructions and m×t micro instructions. Each of the m×t local memory instructions includes a local memory command and a local memory address, and Each of the m×t microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit.

33. The PIM system according to claim 32, in, Each of the m×t local memory instructions includes a local memory command that is a read command for the local memory. The local memory addresses included in the m×t local memory instructions are sequentially incremented starting from the local memory addresses included in the second macro instruction. Wherein, the operation type included in each of the m×t microinstructions is designated as the second operation type. Wherein, the column addresses included in the m×t microinstructions are sequentially incremented starting from the column addresses included in the second macroinstruction, and The broadcast bit included in each of the m×t microinstructions is the same as the broadcast bit included in the second macroinstruction.

34. The PIM system according to claim 33, in, The m×t microinstructions include m×t channel masks. The m×t channel masks are divided into the first to the mth groups. Each of the first to the mth groups includes t channel masks, and each channel mask has the first to the jth bits.

35. The PIM system according to claim 34, in, In each of the t channel masks included in the first to m groups, each i-th channel mask has the same binary stream, where i is a natural number from 1 to j.

36. The PIM system according to claim 35, in, In the first to j bits included in the i-th channel mask of each of the first to m groups, the i-th bit, which is a channel bit, has the first binary value, and all other bits except the channel bit are set to the second binary value.

37. The PIM system according to claim 36, in, The local memory will output the data stored at the storage location specified by the local memory address included in the m×t local memory instructions as m×t local memory data, and transmit the m×t local memory data to the multicast interconnect.

38. The PIM system according to claim 37, in, The multicast interconnect generates one or more sub-microinstruction sets based on the m×t local memory data and the m×t microinstructions. The number of the one or more sub-microinstruction sets generated by the multicast interconnect is the same as the number of the m×t microinstructions.

39. The PIM system according to claim 38, in, When transmitting the m×t microinstructions and the m×t local memory data, the multicast interconnect generates m×t sub-microinstruction sets. The m×t submicro instruction sets include the "(n-1)×j+i"th submicro instruction set, where n is a natural number from 1 to m.

40. The PIM system according to claim 39, in, Each instruction in the "(n-1)×j+i" submicro instruction set includes an operation type, local memory data, and column address.

41. The PIM system according to claim 40, in, The operation type included in each of the "(n-1)×j+i" submicro-instruction sets is designated as the second operation type. The local memory data included in the "(n-1)×j+i"th submicro instruction set is the same as the "(n-1)×j+i"th local memory data in the first to mth local memory data, and The column address included in the "(n-1)×j+i" sub-microinstruction set is the same as the column address included in the "(n-1)×j+i" microinstruction in the first to m microinstructions.

42. The PIM system according to claim 39, in, The multicast interconnect transmits the "(n-1)×j+i" submicro instruction set to the i-th PIM controller among the first to j PIM controllers via the i-th channel of the first to j-th channels.

43. The PIM system according to claim 42, in, The i-th PIM controller generates the (n-1)×j+i" PIM command set based on the (n-1)×j+i" submicro instruction set, and transmits the (n-1)×j+i" PIM command set to the i-th PIM device among the first to j-th PIM devices via the i-th channel.

44. The PIM system according to claim 42, in, Each of the "(n-1)×j+i"th PIM command set includes an operation type, local memory data, and column address. Wherein, the operation type included in each of the "(n-1)×j+i" PIM command sets is designated as the second operation type. Wherein, the local memory data included in the "(n-1)×j+i" PIM command set is the same as the local memory data included in the "(n-1)×j+i" sub-micro instruction set, and The column address included in the "(n-1)×j+i" PIM command set is the same as the column address included in the "(n-1)×j+i" submicro instruction set.

45. The PIM system according to claim 19, in, The third macro instruction also includes the number of iterations, channel mask, local memory address, column address, broadcast bits, and local memory increment size. The iteration count included in the third macro instruction is specified as "m", which indicates the number of times the global buffer write operation is performed, where m is a natural number of 2 or greater. The channel mask included in the third macro instruction includes the first to j bits corresponding to the first to j channels. The local memory address included in the third macro instruction specifies the storage location used for data access in the local memory. The column address included in the third macro instruction specifies the storage location of the vector data in the global buffer. The broadcast bit included in the third macro instruction is set to a first binary value indicating a broadcast operation or a second binary value indicating a non-broadcast operation, and The local memory increment size included in the third macro instruction specifies the increment size of the local memory address.

46. ​​The PIM system according to claim 45, in, When the third macro instruction is transmitted and the broadcast bit included in the third macro instruction has the first binary value, the instruction decoder and sequencer output the first to m-th local memory instructions and the first to m-th micro instructions. Wherein, each of the first to m-th local memory instructions includes a local memory command and a local memory address, and Each of the first to m microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit.

47. The PIM system according to claim 46, in, Each of the first to m-th local memory instructions includes a local memory command that is a read command for the local memory. Wherein, the local memory addresses included in the first to m-th local memory instructions are sequentially incremented by the size indicated by the local memory increment size, starting from the local memory address included in the third macro instruction. Wherein, the operation type included in each of the first to m-th microinstructions is designated as the second operation type. Wherein, the channel mask and the broadcast bit included in each of the first to m micro-instructions are the same as the channel mask and the broadcast bit included in the third macro instruction, and The column addresses included in the first to m microinstructions are sequentially incremented starting from the column addresses included in the third macroinstruction.

48. The PIM system according to claim 47, in, The first to the mth microinstructions each include the first to the mth channel masks. Each of the first to m-th channel masks includes the first to j-th bits, and Wherein, the first to the j bits included in each of the first to the m-th channel masks are the same as the first to the j bits included in the channel mask in the third macro instruction.

49. The PIM system according to claim 48, in, The local memory will output the data stored at the location specified by the local memory address included in the first to m local memory instructions as the first to m local memory data, and transmit the first to m local memory data to the multicast interconnect.

50. The PIM system according to claim 49, in, The multicast interconnect generates and outputs one or more sub-microinstruction sets based on the first to m-th microinstructions and the first to m-th local memory data. The number of the one or more submicro instruction sets output from the multicast interconnect is determined by the first to the j bits included in each of the first to m-th channel masks.

51. The PIM system according to claim 50, in, When the i-th bit of the first to j-th bits included in each of the first to m-th channel masks has the first binary value, the multicast interconnect generates the i-th sub-micro instruction set, where i is a natural number from 1 to j, and Wherein, when the i-th bit of the first to j-th bits included in each of the first to m-th channel masks has the second binary value, the multicast interconnect does not generate the i-th submicro instruction set.

52. The PIM system according to claim 51, in, The i-th submicro-instruction set includes the first to the m-th submicro-instructions. Each of the first to m submicro-instructions includes an operation type, local memory data, and column address.

53. The PIM system according to claim 52, in, The operation type included in each of the first to m-th sub-micro instructions is designated as the second operation type. Wherein, the local memory data included in each of the first to m-th submicro-instructions is the same as the corresponding local memory data in the first to m-th local memory data, and Wherein, the column address included in each of the first to m sub-micro instructions is the same as the corresponding column address included in the first to m micro instructions.

54. The PIM system according to claim 51, in, The multicast interconnect sequentially transmits the first to m sub-micro instructions included in the i-th sub-micro instruction set to the i-th PIM controller among the first to j-th PIM controllers via the i-th channel among the first to j-th channels.

55. The PIM system according to claim 54, in, The i-th PIM controller generates the i-th PIM command set based on the first to m-th sub-micro instructions included in the i-th sub-micro instruction set. The i-th PIM command set includes the first to m-th PIM commands.

56. The PIM system according to claim 55, in, The i-th PIM controller transmits the i-th PIM command set to the i-th PIM device among the first to j-th PIM devices through the i-th channel.

57. The PIM system according to claim 56, in, Each of the first to m PIM commands includes an operation type, local memory data, and a column address. Wherein, the operation type included in the first to m PIM commands is designated as the second operation type. Wherein, the local memory data included in the first to m-th PIM commands is the same as the local memory data included in the first to m-th sub-micro instructions of the i-th sub-micro instruction set, and The column addresses included in the first to m PIM commands are the same as the column addresses included in the first to m sub-micro instructions in the i-th sub-micro instruction set.

58. The PIM system according to claim 45, in, When the third macro instruction is transmitted, and t bits of the channel mask included in the third macro instruction have the first binary value and the broadcast bits included in the third macro instruction have the second binary value, the instruction decoder and sequencer output m×t local memory instructions and m×t micro instructions. Each of the m×t local memory instructions includes a local memory command and a local memory address, and Each of the m×t microinstructions includes an operation type, a channel mask, a column address, and a broadcast bit.

59. The PIM system according to claim 58, in, Each of the m×t local memory instructions includes a local memory command that is a read command for the local memory. Wherein, the local memory addresses included in the m×t local memory instructions are sequentially incremented using the local memory address included in the third macro instruction as the starting address, and the increment is limited by the local memory increment size. Wherein, the operation type included in each of the m×t microinstructions is the second operation type. Wherein, the column addresses included in the m×t microinstructions are sequentially incremented using the column addresses included in the third macroinstruction as the starting column addresses, and The broadcast bit included in each of the m×t microinstructions is the same as the broadcast bit included in the third macroinstruction.

60. The PIM system according to claim 59, in, Each of the m×t microinstructions also includes a channel mask. The m×t channel masks are divided into the first to the mth groups, and Each of the first to the mth groups includes t channel masks, and each channel mask has the first to the jth bits.

61. The PIM system according to claim 60, in, In each of the t channel masks included in the first to m groups, the i-th channel mask included in each of the first to m groups consists of the same binary stream, where i is a natural number from 1 to j.

62. The PIM system according to claim 61, in, In each of the first to m groups, the channel bit corresponding to the i-th channel mask includes the first to j-th bits, and the channel bit has the first binary value. In each of the first to m groups, the remaining bits in the i-th channel mask, excluding the channel bits, are set to the second binary value.

63. The PIM system according to claim 62, in, The local memory will output the data stored at the storage location specified by the local memory address included in the m×t local memory instructions as m×t local memory data, and transmit the m×t local memory data to the multicast interconnect.

64. The PIM system according to claim 63, in, The multicast interconnect generates one or more sub-microinstruction sets based on the m×t local memory data and the m×t microinstructions. The number of sub-microinstruction sets generated from the multicast interconnect is the same as the number of m×t microinstructions.

65. The PIM system according to claim 64, in, When transmitting the m×t microinstructions and the m×t local memory instructions, the multicast interconnect generates m×t sub-microinstruction sets. The m×t submicro instruction sets include the "(n-1)×j+i"th submicro instruction set, where n is a natural number from 1 to m.

66. The PIM system according to claim 65, in, Each of the "(n-1)×j+i"th submicro instruction set includes an operation type, local memory data, and column address.

67. The PIM system according to claim 66, in, The operation type included in each of the "(n-1)×j+i"th submicro-instruction sets is designated as the second operation type. Wherein, the local memory data included in each of the "(n-1)×j+i"th submicro instruction sets is the same as the "(n-1)×j+i"th local memory data in the first to mth local memory data, and The column address included in each of the "(n-1)×j+i" sub-microinstruction sets is the same as the column address included in the "(n-1)×j+i" microinstruction among the first to m microinstructions.

68. The PIM system according to claim 65, in, The multicast interconnect transmits the "(n-1)×j+i" submicro instruction set to the i-th PIM controller among the first to j PIM controllers via the i-th channel of the first to j-th channels.

69. The PIM system according to claim 68, in, The i-th PIM controller generates the (n-1)×j+i"-th PIM command set based on the (n-1)×j+i"-th submicro instruction set, and transmits the (n-1)×j+i"-th PIM command set to the i-th PIM device among the first to j-th PIM devices through the i-th channel.

70. The PIM system according to claim 68, in, Each of the "(n-1)×j+i"th PIM command set includes an operation type, local memory data, and column address. Wherein, the operation type included in each of the "(n-1)×j+i" PIM command sets is designated as the second operation type. Wherein, the local memory data included in each of the "(n-1)×j+i" PIM command sets is the same as the local memory data included in the "(n-1)×j+i" submicro instruction sets, and The column address included in each of the "(n-1)×j+i" PIM command sets is the same as the column address included in the "(n-1)×j+i" submicro instruction set.

71. The PIM system according to claim 19, in, The fourth macro instruction includes the third operation type, channel mask, local memory address, and MAC latch ID. The channel mask included in the fourth macro instruction comprises the first to the j-th bits corresponding to the first to the j-th channels, respectively. The fourth macro instruction includes a local memory address specifying the starting storage location of the local memory where the bias data is stored, and... The MAC latch ID included in the fourth macro instruction specifies the latch circuit in which the bias data is latched.

72. The PIM system according to claim 71, in, When transmitting the fourth macro instruction, the instruction decoder and sequencer output the first to j-th local memory instructions and the first to j-th micro instructions. Each of the first to j-th local memory instructions includes a local memory command and a local memory address, and Each of the first to jth microinstructions includes an operation type, a channel mask, and a MAC latch ID.

73. The PIM system according to claim 72, in, Each of the first to j-th local memory instructions includes a local memory command that is a read command for the local memory. Wherein, the local memory addresses included in the first to j-th local memory instructions are sequentially incremented starting from the local memory addresses included in the fourth macro instruction. Wherein, the operation type included in each of the first to j-th microinstructions is the third operation type, and Wherein, the MAC latch ID included in each of the first to j-th microinstructions is the same as the MAC latch ID included in the fourth macroinstruction.

74. The PIM system according to claim 73, in, The first to the j-th microinstructions each include the first to the j-th channel masks. Each of the first to j-th channel masks includes the first to j-th bits. Wherein, in the i-th channel mask among the first to j-th channel masks, the i-th bit among the first to j-th bit bits has the same binary value as the i-th bit of the channel mask included in the fourth macro instruction, and In this case, all bits from the first to the j-th bit except for the i-th bit are set to the second binary value.

75. The PIM system according to claim 74, in, The local memory outputs the bias data stored in the storage location specified by the local memory address included in the first to j local memory instructions as the first to j local memory data, and transmits the data to the multicast interconnect.

76. The PIM system according to claim 75, in, The multicast interconnect generates and outputs one or more sub-microinstruction sets based on the first to j-th microinstructions and the first to j-th local memory data. The number of sub-microinstruction sets output from the multicast interconnect is the same as the number of channel masks in the first to j-th microinstructions that have channel bits set to the first binary value.

77. The PIM system according to claim 76, in, When the channel bit of the channel mask included in the i-th microinstruction among the first to j-th microinstructions has the first binary value, the multicast interconnect generates the i-th sub-microinstruction set, and Wherein, when the channel bit of the channel mask included in the i-th microinstruction among the first to j-th microinstructions has the second binary value, the multicast interconnect does not generate the i-th sub-microinstruction set.

78. The PIM system according to claim 77, in, The i-th submicro instruction set includes operation type, local memory data, and MAC latch ID.

79. The PIM system according to claim 78, in, The operation type included in the i-th submicro-instruction is designated as the third operation type. Wherein, the local memory data included in the i-th submicro instruction is the same as the i-th local memory data in the first to j-th local memory data, and Wherein, the MAC latch ID included in the i-th sub-micro instruction is the same as the MAC latch ID included in the i-th micro instruction.

80. The PIM system according to claim 77, in, When the i-th submicro instruction set is generated from the multicast interconnect, the multicast interconnect transmits the i-th submicro instruction set to the i-th PIM controller among the first to j PIM controllers through the i-th channel of the first to j channels.

81. The PIM system according to claim 80, in, The i-th PIM controller generates the i-th PIM command set based on the i-th submicro instruction set, and transmits the i-th PIM command set to the i-th PIM device among the first to j-th PIM devices through the i-th channel.

82. The PIM system according to claim 80, in, The i-th PIM command set includes the operation type, local memory data, and MAC latch ID. Wherein, the operation type included in the i-th PIM command set is designated as the third operation type. Wherein, the local memory data included in the i-th PIM command set is the same as the local memory data included in the i-th submicro instruction set, and Wherein, the MAC latch ID included in the i-th PIM command set is the same as the MAC latch ID included in the i-th submicro instruction set.

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