A method, system, device, medium and product for verifying a knowledge base construction

Abstract

The application relates to the chip verification technical field and provides a verification knowledge base construction method, system, device, medium and product. The method automatically captures multi-modal error information at the time of simulation failure, including simulation logs, simulation waveforms and simulation environments, when the current simulation case fails. Based on the obtained multi-modal information, corresponding semantic feature vectors, waveform feature vectors and topology feature vectors are respectively extracted, the vectors are fused according to predetermined rules, a structured fusion feature vector is generated, the fusion feature vector is mapped with a solution when the current simulation case passes, knowledge entries are formed and stored in a verification knowledge base. The application realizes a complete automatic verification knowledge base construction process from automatic triggering at the time of simulation failure, to feature generation, to automatic binding with a solution, and overcomes the defects of the original error information recording which depends on manual work.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a method, system, device, medium and product for constructing a verification knowledge base. Background Technology

[0002] In chip verification, debugging after simulation failure is one of the most time-consuming aspects for engineers. After a simulation failure, verification engineers manually observe logs and waveforms, recording the error phenomenon, possible causes, and final solutions in text form in documents, wikis (a hypertext system for collaborative creation), or simple databases (such as Excel). This process relies entirely on the engineer's conscientiousness, memory, and summarization abilities. Existing methods of recording these findings suffer from at least the following problems: First, it is inefficient and cannot be scaled. The entire process is manual, and this method cannot be systematically applied to thousands of simulation cases, becoming an additional burden on engineers. Second, the knowledge representation is incomplete and not objective. Manual recording inevitably involves subjective selection, which will miss a lot of key contextual information that can be read by machines (such as specific waveform patterns, complete signal interactions, and precise design topologies), resulting in limited value of the recorded knowledge. Third, it cannot be deeply processed by computers. The recorded text information is unstructured, and computers cannot understand its deep semantics and relationships, making it difficult to support subsequent intelligent retrieval and matching; they can only perform simple keyword searches. Summary of the Invention

[0003] The purpose of this application is to provide a method, system, device, medium and product for constructing a verification knowledge base, so as to improve the above-mentioned problems in the prior art.

[0004] For the purposes mentioned above, this application provides the following technical solution: The first aspect of this application provides a method for constructing a verification knowledge base, including: When the current simulation test case fails, error information is automatically captured. The error information includes the simulation log, simulation waveform, and simulation environment at the time of simulation failure. Based on the error information, a semantic feature vector corresponding to the simulation log, a waveform feature vector corresponding to the simulation waveform, and a topological feature vector corresponding to the simulation environment are generated respectively. The semantic feature vector, the waveform feature vector, and the topological feature vector are fused to generate a structured fused feature vector. The fused feature vector is then mapped to the solution obtained when the current simulation use case is passed, forming a knowledge entry. The knowledge entry is then stored in the verification knowledge base.

[0005] Further, the semantic feature vector, the waveform feature vector, and the topological feature vector are respectively subjected to dimensionality reduction processing and then vector fusion to obtain the fused feature vector. The structure of the structured fused feature vector is as follows: The fused feature vector = [topological feature vector, semantic feature vector, waveform feature vector] The topological feature vector has a first weight, the semantic feature vector has a second weight, and the waveform feature vector has a third weight; the first weight, the second weight, and the third weight are dynamically determined based on the error information.

[0006] Further, generating the semantic feature vector corresponding to the simulation log includes: The simulation logs are parsed using natural language processing, and then segmented and filtered for stop words to obtain a keyword sequence. The keyword sequence is matched sequentially with each index word in the predefined validation domain vocabulary, and the semantic feature vector is generated based on the matching results. The semantic feature vector is a binary vector whose elements include "0" or "1". Wherein, the "0" element represents that the current index word is not in the keyword sequence, and the "1" element represents that the current index word is in the keyword sequence.

[0007] Furthermore, the waveform feature vector corresponding to the simulated waveform includes: Identify the key signals when the current simulation use case fails; Statistical features and sequence features are calculated for the waveforms corresponding to each of the key signals, and specific pattern detection is performed on each of them. The specific pattern detection includes detecting a predefined "protocol handshake violation" pattern and detecting a predefined "reset recovery violation" pattern. The waveform feature vector is determined based on the calculation results of the statistical features and the sequence features, and the detection results of the specific pattern detection, respectively.

[0008] Optionally, the method for identifying the key signal includes: The design code is parsed to identify all modules connected to predefined standard interfaces, and the interface signals of each module are marked as key signals; Receive a list of key module names input by the user, and automatically mark the interface signals of all key modules in the list as the key signals.

[0009] Optionally, the method for identifying the key signal includes: A predefined key signal library is used to determine each key signal; or, based on the key signal library, each of the currently determined key signals is added to or deleted.

[0010] Optionally, the method for identifying the key signal includes: The instantiated verification components and assertions in the simulation environment are parsed, and the signals monitored by the verification components and assertions are extracted and added as the key signals.

[0011] Further, generating the topological feature vector corresponding to the simulation environment includes: The design code is analyzed to determine the module hierarchy where the simulation error occurs, and the module hierarchy is encoded into a hierarchical path string; The hierarchical path string is hashed and then truncated to a fixed length of bytes to obtain the topological feature vector.

[0012] The second aspect of this application provides a verification knowledge base construction system for implementing the verification knowledge base construction method described in the first aspect of this application, including: The error information capture module is used to automatically capture error information when the current simulation test case fails. The error information includes the simulation log, simulation waveform and simulation environment when the simulation fails. The feature vector generation module is used to generate, based on the error information, the semantic feature vector corresponding to the simulation log, the waveform feature vector corresponding to the simulation waveform, and the topological feature vector corresponding to the simulation environment. The feature fusion storage module is used to fuse the semantic feature vector, the waveform feature vector, and the topological feature vector to generate a structured fused feature vector, map the fused feature vector to the solution when the current simulation use case passes and form a knowledge entry, and store the knowledge entry in the verification knowledge base.

[0013] A third aspect of this application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a verification knowledge base construction method as described in the first aspect of this application.

[0014] The fourth aspect of this application provides a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the verification knowledge base construction method described in the first aspect of this application.

[0015] The fifth aspect of this application provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of a verification knowledge base construction method as described in the first aspect of this application.

[0016] This application, through the above-described method for constructing a verification knowledge base, can achieve at least the following technical effects: This application overcomes the shortcomings of relying entirely on manual methods by automatically extracting and fusing multimodal information (logs, waveforms, topology) of verification errors into a unified multidimensional feature vector. The generated multidimensional feature vector contains multidimensional information of the errors, and its representation ability far exceeds that of plain text, laying a solid foundation for subsequent intelligent applications. At the same time, it realizes a complete automated construction process from automatic triggering of simulation failure to feature generation and automatic binding with the solution. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for constructing a verification knowledge base, as provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the steps of a verification knowledge base construction method provided in this application embodiment; Figure 3 A schematic diagram of a verification knowledge base construction system provided in this application embodiment; Figure 4 This is a schematic diagram of a computer device provided in an embodiment of this application.

[0019] Reference numerals: 300, a verification knowledge base construction system; 301, error information capture module; 302, feature vector generation module; 303, feature fusion storage module; 401, memory; 402, processor. Detailed Implementation

[0020] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] This embodiment overcomes the shortcomings of relying entirely on manual methods by automatically extracting and fusing multimodal information (logs, waveforms, topology) of verification errors into a unified multidimensional feature vector. The generated multidimensional feature vector contains multidimensional information of the errors, and its representation capability far exceeds that of plain text, laying a solid foundation for subsequent intelligent applications. At the same time, it realizes a complete automated construction process from automatic triggering of simulation failure to feature generation and automatic binding with the solution.

[0022] like Figure 1 and Figure 2 As shown, the method for constructing a verification knowledge base provided in this embodiment specifically includes the following steps: Step S100: When the current simulation test case fails, automatically capture error information, including simulation logs, simulation waveforms, and simulation environment when the simulation fails.

[0023] Specifically, in regression testing for chip verification, when a simulation test case fails and an assertion failure message is received, the system automatically triggers (without manual intervention) to capture a complete snapshot of the simulation test case failure, including: Simulation logs may contain messages such as "Error: AXI write response timeout at address 0x1000". Assertion failure message: An error message containing information about simulation failures; Automatic dump (to storage) of simulation waveform files: The system automatically saves the waveforms before and after the error occurred, such as the read and write transaction waveforms of axi_arvalid, axi_arready, axi_rvalid, and axi_rready at address 0x1000; Simulation environment: The relevant parameters of the test environment, such as the simulation design topology, occur in the top.soc_design.dra.axi_slave_interface module.

[0024] Step S200: Based on the error information, generate the semantic feature vector corresponding to the simulation log, the waveform feature vector corresponding to the simulation waveform, and the topological feature vector corresponding to the simulation environment.

[0025] Further, the unstructured data captured in step S100 is processed to generate three types of structured feature vectors: semantic feature vector, waveform feature vector, and topological feature vector. First, based on the error information of the test case failures automatically captured in step S100, simulation logs and assertion failure information are parsed using natural language processing technology to extract features such as error type, key signal name, and data value, which are then encoded into a numerical vector as the semantic feature vector. Second, near the time point of the error occurrence, the waveforms of the identified key signals are analyzed, their statistical and sequence features are calculated, and specific pattern detection is performed. A vector representing the waveform pattern is generated using a preset algorithm (such as statistical features and frequency domain transform features), obtaining the aforementioned waveform feature vector. Finally, by parsing the top-level design code, the module hierarchy where the error root cause resides (e.g., top.dut.sub_module.inst_a) is determined and encoded into a vector representing the design location, i.e., the topological feature vector.

[0026] Further, in step S200, the semantic feature vector corresponding to the simulation log is generated, and the method includes: Simulation logs are parsed using natural language processing, and word segmentation and stop word filtering are performed to obtain a keyword sequence. This keyword sequence is then matched sequentially with each index word in a predefined validation domain vocabulary, generating a semantic feature vector based on the matching results. This semantic feature vector is a binary vector containing either "0" or "1" elements; where "0" represents that the current index word is not in the keyword sequence, and "1" represents that the current index word is in the keyword sequence.

[0027] For example, the following are examples of methods for generating semantic feature vectors: S1. The predefined validation domain vocabulary is as follows: [length=10]: ["timeout", "AXI", "protocol", "violation", "address", "data", "mismatch", "assertion", "failed", "null_pointer"] S2. When simulation fails, the captured error simulation log is as follows: "Error: AXI protocol violation detected. Read data mismatch ataddress 0x1000. Assertion 'check_data_valid' failed." S3. Perform word segmentation and stop word filtering on the simulation logs: Tokenization (breaking the above simulation log sentence into words): [“Error:”, “AXI”, “protocol”, “violation”, “detected.”, “Read”, “data”, “mismatch”, “at”, “address”, “0x1000.”, “Assertion”, “'check_data_valid'”, “failed.”] Stop word filtering: Remove meaningless stop words (such as "at", ".") and overly generalized words (such as "Error", "detected", "Read") to obtain a keyword sequence. ["AXI", "protocol", "violation", "data", "mismatch", "address", "Assertion", "failed"] S4. Match the keyword sequence obtained in step S3 with the predefined validation domain vocabulary in S1 to obtain the matching results shown in Table 1: Table 1: Keyword Sequence Matching Results

[0028] S5. Based on the matching results described in S4 above, generate a semantic feature vector (a binary vector containing "0" or "1"): [0, 1, 1, 1, 1, 1, 1, 1, 1, 0]. Each vector's position (index) corresponds to an indexed word in the validation vocabulary. If the current indexed word exists in the keyword sequence, the corresponding position is set to 1; otherwise, it is set to 0.

[0029] Further, in step S200, the waveform feature vector corresponding to the simulated waveform is generated, including: S210. Identify the key signals when the current simulation use case fails; S220. Calculate statistical features and sequence features for the waveforms corresponding to each of the key signals, and perform specific pattern detection for each. The specific pattern detection includes detecting a predefined "protocol handshake violation" pattern and detecting a predefined "reset recovery violation" pattern. S230. The calculation results of the statistical features and the sequence features, and the detection results of the specific pattern detection are sequentially concatenated to obtain the waveform feature vector.

[0030] Specifically, the waveform segment is extracted according to a preset time window length, centered on the time point where the simulation error occurs, and the waveforms of key signals are analyzed. For example, the preset time window length can be selected as 2. (Unit: microseconds), 5 (Unit: microsecond), 100ns (unit: nanosecond), etc. First, identify and extract key signals within the preset time window. Optionally, key signals include, but are not limited to, the following: interface protocol signals, clock reset signals, data path control signals, error and status indication signals, etc. Optionally, key signals can be identified using one of the following methods: 1. Automatic identification based on design hierarchy and module importance: The system automatically parses the RTL (Register Transfer Level) top-level design code, identifies all modules connected to predefined standard interfaces (such as AXI, APB), and automatically adds these interface signals to the critical signal list. And / or, it receives a user-input list of critical module names (such as video_encoder, ISP) and automatically marks the port signals corresponding to all modules in that list as critical signals.

[0031] 2. Signal library reuse based on historical debugging experience: The system maintains an extensible, inter-project shared "critical signal library" to record signal types that have been frequently proven to be relevant to debugging in historical projects (such as the full / empty signal of a FIFO (First In, First Out) and the grant signal of an arbitrator). Current simulation projects can directly inherit from this critical signal library to determine critical signals, or add or delete currently identified critical signals based on this library.

[0032] 3. Reverse derivation based on validation components and assertions: The process involves parsing the instantiated verification components (VIPs, Verification IPs) and assertion information within the verification environment, extracting these assertions and all signals monitored by the verification components, and incorporating these signals into a critical signal list. These verification components and assertions are specifically configured and written by verification engineers based on functional verification requirements, and the signals they monitor directly reflect the engineer's judgment and focus on key design functionalities. Therefore, they constitute an important candidate source of critical signals.

[0033] Furthermore, based on the extracted key signals, a "signal value sequence" is extracted from the waveform data of each key signal, and statistical features and sequence features are calculated respectively. Statistical features involve calculating the number of transitions; sequence feature extraction refers to secondary processing and calculation of the original signal value sequence to generate a set of statistical or numerical features that characterize its temporal dynamics. This signal value sequence is treated as a time series, and its trend, periodicity, peak values, and other features are extracted. For example, bandwidth can be analyzed by detecting the changing trend of the buffer water level. Finally, specific pattern detection is performed on the waveform data of each key signal, including: Detects predefined 'protocol handshake violation' patterns, where the master device's request signal undergoes undesirable changes before the slave device is ready. Detects predefined 'reset recovery violation' patterns, where critical control signals or state machines fail to return to their specified initial states after the reset signal is released.

[0034] Furthermore, the detection of the above two modes is achieved through the following steps: S11, Pattern Rule Base: A predefined, extensible pattern rule base. Each rule uses a temporal logic-based expression or pseudocode to describe an error pattern as described above.

[0035] S12. Sequence Scanning and Matching: A sliding time window is used to scan the signal value sequence. For each sequence segment within the window, it is matched against rules in the pattern rule base.

[0036] S13, Generating Pattern Flag: If the current sequence segment matches a certain rule, then the corresponding position in the feature vector is 1; otherwise, it is 0.

[0037] Further, in step S200, the topological feature vector corresponding to the simulated waveform is generated, including: Step S240: Parse the design code to determine the module hierarchy where the simulation error is located, and encode the module hierarchy into a hierarchical path string; Step S250: After hashing the hierarchical path string, extract a fixed length of bytes to obtain the topological feature vector.

[0038] Specifically, by parsing the top-level design code of the RTL, the module hierarchy of the module containing the root cause of the error (e.g., top.dut.sub_module.inst_a) is determined and encoded into a vector representing the design location. Next, the complete hierarchical path is treated as a string, its hash value is calculated, and the first N bytes are extracted as a vector representing the topology, thus obtaining the aforementioned topology vector. Using the method provided in this embodiment, any unique path can be mapped to a fixed-length topology vector.

[0039] Step S300: Fuse the semantic feature vector, the waveform feature vector, and the topological feature vector to generate a structured fused feature vector. Map the fused feature vector to the solution when the current simulation use case is passed to form a knowledge entry. Store the knowledge entry in the verification knowledge base.

[0040] Specifically, based on the semantic feature vector, waveform feature vector, and topological feature vector obtained in step S200, a fused feature vector is formed through vector concatenation and fusion to comprehensively and objectively describe the simulation error. First, vector concatenation is performed by joining the three vectors end-to-end to obtain: The fused feature vector = [topological feature vector, semantic feature vector, waveform feature vector] Secondly, dimensionality reduction is performed on each sub-vector to ensure a controllable final vector length and remove redundant information. Finally, vector fusion is performed through dynamic weight allocation based on an attention mechanism. The weights of each sub-vector and even key dimensions within the vector are dynamically calculated based on the specific context of the current error. Specifically, topological feature vectors are assigned a first weight, semantic feature vectors a second weight, and waveform feature vectors a third weight. These first, second, and third weights are dynamically determined based on the context of the current error information.

[0041] Specifically, based on the characteristics of the chip verification field, targeted dimensionality reduction processing is performed on the feature vectors. Preferably, for semantic feature sub-vectors, a "keyword selective retention" strategy is adopted, retaining only the feature dimensions with the highest matching degree to the predefined verification error keyword library, and eliminating noise from common words. For waveform feature sub-vectors, "Principal Component Analysis (PCA)" is used for dimensionality reduction, retaining the principal component components that best distinguish different error waveform patterns. For topological feature sub-vectors, since they are already high-information-density hash codes, their dimensions are kept unchanged to retain unique location information. Through dimensionality reduction processing, the information most relevant to defect diagnosis is purposefully retained.

[0042] Furthermore, the fused feature vector in this embodiment adopts a "hierarchical fusion structure based on debugging priority." This structure is based on the debugging logic of chip verification engineers: first, locate the problem (where it is), then characterize the problem (what it is), and finally analyze the waveform behavior (why it occurs). Therefore, the first level (location layer) is determined first: the topological feature sub-vector, which is placed at the beginning of the fused feature vector, so that the model first focuses on the physical or logical location of the error. The second level (characterization layer) is determined second: the semantic feature sub-vector, which is placed after the topological vector to provide the model with a textual semantic description of the error type. Finally, the third level (analysis layer) is determined third: the waveform feature sub-vector, which is placed at the end of the vector as in-depth corroboration and detailed supplementation of the information from the first two layers. Based on the above method, the structured fused feature vector is obtained as described above: [topological feature vector, semantic feature vector, waveform feature vector]. By fusing through the above method, the fused feature vector can adaptively focus on the features most relevant to the current error, thereby achieving more accurate similarity matching.

[0043] For example, when semantic features strongly indicate a 'protocol violation', the system automatically assigns higher attention weights to timing-related dimensions (such as signal setup and hold times, and specific protocol handshake sequences) in the waveform feature subvectors. When topology features indicate an error occurring in the 'clock domain crossover (CDC)' module, the system assigns higher weights to dimensions in the waveform features related to clock synchronization and metastability.

[0044] Furthermore, the system monitors the failure status of the simulation test case. When the simulation test case is finally repaired and passed, the system automatically binds the generated fusion feature vector with the solution obtained when the test case passed (including the reason for failure and the corresponding repair suggestions) to form a mapping relationship, forming a complete case knowledge entry, and stores it in the structured verification knowledge base. When a new simulation failure occurs, the system can automatically retrieve several historical cases with the closest vector distance in the verification knowledge base. If a match is successful, the system directly recommends the most similar error and its known solution to the engineer; if a match fails, the error information is manually repaired until the simulation passes. The error information from the time the simulation passed is extracted and a new fusion feature vector is generated. The fusion feature vector generated before the simulation passed is bound with the solution to generate a knowledge entry and stored in the verification knowledge base. This embodiment realizes the leap from "keyword matching" to "semantic-level intelligent matching", significantly accelerating the debugging and convergence process.

[0045] This application describes a verification knowledge base construction method as described above in conjunction with the following embodiments.

[0046] Example 1 During simulation, an assertion failure error was detected, with the log message: "Assertion failure: AXIprotocol violation on archannel at time 100ns." The root cause of this error was traced to the signal `top.dut.axi_interconnect.master_bridge.arbiter.fsm_state` in the design.

[0047] I. Feature Vector Generation 1. Topological feature vector generation: The topological feature vector is used to uniquely encode the hierarchical location of error root causes in the design.

[0048] Path acquisition: By parsing the simulation report and design netlist, the complete hierarchical path of the error signal is automatically extracted: "top.dut.axi_interconnect.master_bridge.arbiter.fsm_state".

[0049] Hash encoding: The path string is calculated using the MD5 Message-Digest Algorithm to obtain a 128-bit (16-byte) hash value, such as a1b2c3d4e5f6....

[0050] Vector generation: Take the first 4 bytes a1b2c3d4 of the hash value and convert them into a 4-dimensional byte vector as the topological feature vector.

[0051] The final generated topological feature vector V_topo is: [0xa1, 0xb2, 0xc3, 0xd4].

[0052] 2. Semantic Feature Vector Generation The semantic feature vector is used to transform unstructured error log text into structured, machine-readable identifiers. The generation method includes: Vocabulary definition: The predefined validation domain vocabulary contains 8 entries: ["timeout", "AXI", "protocol", "violation", "assertion", "failed", "data", "mismatch"].

[0053] Text processing: The error log is segmented and filtered for stop words to obtain the core keyword sequence: ["AXI", "protocol", "violation", "assertion"].

[0054] Binary encoding: The core keyword sequence is matched against the vocabulary to generate an 8-dimensional binary vector. The matching rule is: if a word in the vocabulary exists in the keyword sequence, the corresponding position is set to 1; otherwise, it is set to 0.

[0055] The final generated semantic feature vector V_semantic is [0, 1, 1, 1, 1, 0, 0, 0]. This vector indicates that the error is highly correlated with AXI, protocol, violation, and assertion.

[0056] 3. Waveform Feature Vector Generation The waveform feature vector is used to quantify the timing behavior of key signals near the point of error occurrence.

[0057] Taking the error signal fsm_state and the associated signal axi_arready as examples, the analysis is performed within a time window near the error time point: a. Statistical feature extraction: AXI write channel handshake count: 10 fsm_state transition count: 4 axi_arready high-level percentage: 0.10 b. Sequence feature extraction: fsm_state sequence coefficients 4 axi_arready sequence coefficient 0.1 c. Specific pattern detection: Scan and match according to 3 predefined rules.

[0058] Rule 1 (Protocol Violation): Detected ->1 Rule 2 (Deadlock): Not detected -> 0 All the above features are concatenated in a predetermined order to form a waveform feature vector: V_waveform: [10, 4, 0.10, 4, 0.1, 1, 0].

[0059] II. Vector Fusion The three sub-vectors generated in the first part are concatenated according to a fixed structure of [topological feature vector, semantic feature vector, waveform feature vector] to generate the final fused feature vector.

[0060] The final fused feature vector V_unified: V_unified = [V_topo, V_semantic, V_waveform] V_unified = [0xa1, 0xb2, 0xc3, 0xd4, 0, 1, 1, 1, 1, 0, 0, 0, 10, 4,0.10, 4, 0.1, 1, 0] III. Constructing Knowledge Entries The system monitors the status of the failed simulation test case. If the current simulation test case is eventually fixed and passed, the system automatically binds the previously generated fusion feature vector with the final solution to form a complete "case knowledge entry," which is then stored in the structured verification knowledge base. If the current simulation test case fails, the system extracts the multimodal information (logs, waveforms, topology) at the time of the simulation failure and automatically extracts feature vectors to form a new fusion feature vector, until the current simulation test case passes. The last generated fusion feature vector before the current simulation test case passes replaces the previously generated fusion feature vector, and it is bound to the corresponding solution to generate a knowledge entry, which is then stored in the verification knowledge base.

[0061] Based on the same inventive concept, this invention also provides a verification knowledge base construction system 300, as described in the following embodiments. Since the verification knowledge base construction system 300 is implemented based on the verification knowledge base construction method described above, the implementation of the verification knowledge base construction system 300 can refer to the implementation of the verification knowledge base construction method, and repeated details will not be elaborated further. Figure 3 This is a structural block diagram of a verification knowledge base construction system 300 according to an embodiment of this application, such as... Figure 3 As shown, the system specifically includes: The error information capture module 301 is used to automatically capture error information when the current simulation test case fails. The error information includes the simulation log, simulation waveform and simulation environment when the simulation fails. The feature vector generation module 302 is used to generate, based on the error information, the semantic feature vector corresponding to the simulation log, the waveform feature vector corresponding to the simulation waveform, and the topological feature vector corresponding to the simulation environment. The feature fusion storage module 303 is used to fuse the semantic feature vector, the waveform feature vector and the topological feature vector to generate a structured fused feature vector, map the fused feature vector to the solution when the current simulation use case is passed to form a knowledge entry, and store the knowledge entry in the verification knowledge base.

[0062] In this embodiment, an electronic device is also provided, such as... Figure 4 As shown, it includes: a processor 402; and a memory 401 for storing executable instructions of the processor 402; wherein the processor 402 is used for the instructions to implement a verification knowledge base construction method as described above in this embodiment.

[0063] Specifically, the computer device can be a computer terminal, a server, or a similar computing device.

[0064] In this embodiment, a storage medium is provided, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the verification knowledge base construction method described above in this embodiment.

[0065] In this embodiment, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, it implements the steps of the verification knowledge base construction method described above in this embodiment.

[0066] In this embodiment, a computer-readable storage medium is provided, which stores a computer program that executes any of the above-described methods for constructing a verification knowledge base.

[0067] Specifically, computer-readable storage media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, and optical disc read-only memory (CD-ROM). ROM, digital multifunction optical disc (DVD) or other optical storage, magnetic cassette tape, magnetic magnetic disk storage or other magnetic storage devices or any other non-transfer medium, may be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media does not include transient media such as modulated data signals and carrier waves.

[0068] The embodiments of the present invention achieve the following technical effects: 1. This application transforms the accumulation of debugging experience from "manual summarization" to "automatic machine coding" by automatically triggering data capture, automatically identifying key signals, and automatically extracting multi-dimensional feature vectors. It can fully cover all failed test cases in regression testing, significantly improve efficiency, eliminate the extra burden on engineers, and realize a complete automated construction process from automatic triggering of simulation failures to feature generation and automatic binding with the solution. 2. This application extracts topological and semantic features directly from the design netlist and log text, and automatically calculates statistical and sequence features from waveform data, thus fully preserving the aforementioned machine-readable key information. Furthermore, it combines a weight allocation method based on an attention mechanism for vector fusion, enabling the fused vector to adaptively focus according to the error context. The resulting multidimensional feature vector contains multidimensional information about the error, and its representational ability far exceeds that of pure text, laying a solid foundation for subsequent intelligent applications. 3. This application sets up a structured fusion vector structure, which corresponds to the debugging thinking level of engineers: "first locate where the problem is, then define what the problem is, and finally analyze why the waveform is". This makes the fusion vector naturally have a progressive information organization method, which is conducive to the efficient processing of subsequent models according to the priority of "position → type → details".

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for constructing a verification knowledge base, characterized in that, include: When the current simulation test case fails, error information is automatically captured. The error information includes the simulation log, simulation waveform, and simulation environment at the time of simulation failure. Based on the error information, a semantic feature vector corresponding to the simulation log, a waveform feature vector corresponding to the simulation waveform, and a topological feature vector corresponding to the simulation environment are generated respectively. The semantic feature vector, the waveform feature vector, and the topological feature vector are fused to generate a structured fused feature vector. The fused feature vector is then mapped to the solution obtained when the current simulation use case is passed, forming a knowledge entry. The knowledge entry is then stored in the verification knowledge base.

2. The method for constructing a verification knowledge base according to claim 1, characterized in that, After dimensionality reduction processing of the semantic feature vector, the waveform feature vector, and the topological feature vector, vector fusion is performed to obtain the fused feature vector. The structure of the structured fused feature vector is as follows: The fused feature vector = [topological feature vector, semantic feature vector, waveform feature vector] The topological feature vector has a first weight, the semantic feature vector has a second weight, and the waveform feature vector has a third weight; the first weight, the second weight, and the third weight are dynamically determined based on the error information.

3. The method for constructing a verification knowledge base according to claim 1, characterized in that, The generation of the semantic feature vector corresponding to the simulation log includes: The simulation logs are parsed using natural language processing, and then segmented and filtered for stop words to obtain a keyword sequence. The keyword sequence is matched sequentially with each index word in the predefined validation domain vocabulary, and the semantic feature vector is generated based on the matching results. The semantic feature vector is a binary vector whose elements include "0" or "1". Wherein, the "0" element represents that the current index word is not in the keyword sequence, and the "1" element represents that the current index word is in the keyword sequence.

4. The method for constructing a verification knowledge base according to claim 1, characterized in that, Generating the waveform feature vector corresponding to the simulated waveform includes: Identify the key signals when the current simulation use case fails; Statistical features and sequence features are calculated for the waveforms corresponding to each of the key signals, and specific pattern detection is performed on each. The specific pattern detection includes detecting a predefined "protocol handshake violation" pattern and a predefined "reset recovery violation" pattern. The waveform feature vector is determined based on the calculation results of the statistical features and the sequence features, and the detection results of the specific pattern detection, respectively.

5. The method for constructing a verification knowledge base according to claim 4, characterized in that, The method for identifying the key signals includes: The design code is parsed to identify all modules connected to predefined standard interfaces, and the interface signals of each module are marked as key signals; Receive a list of key module names input by the user, and automatically mark the interface signals of all key modules in the list as the key signals.

6. The method for constructing a verification knowledge base according to claim 4, characterized in that, The method for identifying the key signals includes: A predefined key signal library is used to determine each key signal; or, based on the key signal library, each of the currently determined key signals is added to or deleted.

7. The method for constructing a verification knowledge base according to claim 4, characterized in that, The method for identifying the key signals includes: The instantiated verification components and assertions in the simulation environment are parsed, and the signals monitored by the verification components and assertions are extracted and added as the key signals.

8. The method for constructing a verification knowledge base according to claim 1, characterized in that, Generating the topological feature vector corresponding to the simulation environment includes: The design code is parsed to determine the module hierarchy where the simulation error occurs, and the module hierarchy is encoded into a hierarchical path string; The hierarchical path string is hashed and then truncated to a fixed length of bytes to obtain the topological feature vector.

9. A verification knowledge base construction system, characterized in that, A method for constructing a verification knowledge base according to any one of claims 1 to 8 includes: The error information capture module is used to automatically capture error information when the current simulation test case fails. The error information includes the simulation log, simulation waveform and simulation environment when the simulation fails. The feature vector generation module is used to generate, based on the error information, the semantic feature vector corresponding to the simulation log, the waveform feature vector corresponding to the simulation waveform, and the topological feature vector corresponding to the simulation environment. The feature fusion storage module is used to fuse the semantic feature vector, the waveform feature vector, and the topological feature vector to generate a structured fused feature vector, map the fused feature vector to the solution when the current simulation use case passes and form a knowledge entry, and store the knowledge entry in the verification knowledge base.

10. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is used to execute the instructions to implement a verification knowledge base construction method as described in any one of claims 1 to 8.

11. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of a verification knowledge base construction method as described in any one of claims 1 to 8.

12. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of a verification knowledge base construction method as described in any one of claims 1 to 8.

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