Virtual simulation training task intelligent evaluation method and system based on neural-symbolic architecture

Abstract

The present application relates to the technical field of virtual simulation training teaching and skill evaluation, and discloses a virtual simulation training task intelligent evaluation method and system based on a neural symbol architecture, a global device dictionary is constructed for a digital twin object; based on the global device dictionary, a large language model is used to compile natural language form training examination standards to obtain a standardized field-specific language rule configuration file; high-frequency time series data output by a virtual simulation platform is received, atomic fact extraction is performed on the high-frequency time series data to obtain an atomic fact set; according to an industrial control evaluation specification defined in the standardized field-specific language rule configuration file, logical assertion is performed on the atomic fact set to obtain an assertion result; exception information is captured from the assertion result, and intelligent diagnosis reasoning is performed in combination with a fault diagnosis code in the standardized field-specific language rule configuration file to obtain exception diagnosis information and a training evaluation result.

Description

Technical Field

[0001] This invention relates to the field of virtual simulation training and skills evaluation technology, specifically to an intelligent evaluation method and system for virtual simulation training tasks based on neural symbolic architecture. Background Technology

[0002] With the rapid development of digital twin technology and virtual-real integration technology, industrial virtual simulation platforms have become the core carrier of vocational education's work-study integration teaching reform, and are widely used in practical training scenarios such as electrical engineering, industrial robot operation, and automated production line debugging. While virtual simulation technology is now relatively mature, intelligent evaluation technology for practical training tasks is still in the exploratory stage. Existing evaluation methods are mainly divided into two categories: hard-coded rule tree evaluation and direct large-model evaluation. The former relies on writing conditional logic in the underlying code, while the latter inputs time-series data and scoring criteria into a large model to complete the scoring.

[0003] Both existing evaluation technologies have serious flaws and are unable to meet the high accuracy, low cost, and easy scalability requirements of industrial-grade and competition-grade practical training evaluation.

[0004] The main problems are: it is impossible to simultaneously achieve flexible expression of rules and deterministic and precise evaluation logic; hard-coded rule trees lack the flexibility of rule configuration; and direct evaluation of large models lacks the deterministic nature of logical judgment. Therefore, all of the above problems urgently require new technical solutions. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes an intelligent evaluation method and system for virtual simulation training tasks based on neural symbolic architecture, which solves the aforementioned technical problems.

[0006] Firstly, an intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture is provided, including: Construct a global device dictionary for digital twin objects; Based on the global device dictionary, a large language model is used to compile the training and assessment standards in natural language form to obtain a standardized domain-specific language rule configuration file. Receive high-frequency time-series data output from a virtual simulation platform, extract atomic facts from the high-frequency time-series data, and obtain a set of atomic facts; Logical assertions are performed on the atomic fact set according to the industrial control evaluation criteria defined in the standardized domain-specific language rule configuration file to obtain the assertion results; The assertion results are subjected to anomaly information capture, and intelligent diagnostic reasoning is performed in combination with the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain anomaly diagnosis information and training evaluation results.

[0007] Furthermore, a global device dictionary for digital twin objects is constructed, including: The hierarchical path addressing specification is used to map the logical addresses of virtual devices to obtain the correspondence between virtual devices and logical addresses; The physical rendering state attributes of the virtual device are mapped to obtain the logical address of the physical rendering state attributes; The logical state attributes of the virtual device are mapped to obtain the logical addresses of the logical state attributes; By integrating the correspondence between the virtual devices and logical addresses, the logical addresses of the physical rendering state attributes, and the logical addresses of the logical state attributes, a global device dictionary for digital twin objects is obtained.

[0008] Furthermore, based on the global device dictionary, a large language model is used to compile the training and assessment standards in natural language form, resulting in a standardized domain-specific language rule configuration file, including: A large language model is used to perform semantic recognition on natural language assessment criteria to obtain temporal constraints and causal relationships. Align the devices and actions described in natural language with the global device dictionary to obtain the logical address mapping of devices and actions; The global device dictionary and the preset domain-specific language standard specifications are injected into the large language model as a system prompt word whitelist, and the large language model is used to perform restricted semantic recognition on natural language assessment standards. The logical address mapping is constrained and matched according to the industrial signal type to obtain data constraint rules; The timing constraints, causal relationships, logical address mappings between devices and actions, and data constraint rules are assembled to obtain a standardized domain-specific language rule configuration file. The compilation process implements strict zero-illusion rule constraints: the generated logical operators must be extracted from the preset core operator library, the addressing path must be within the global device dictionary whitelist, and the large language model is prohibited from fabricating device layers or changing the JSON structure skeleton.

[0009] Furthermore, the timing constraints and causal relationships, the logical address mapping between devices and actions, and the data constraint rules are assembled to obtain a standardized domain-specific language rule configuration file, including: When generating the standardized abstract syntax tree configuration file, industrial-grade fault diagnostic codes corresponding to each assertion logic are generated simultaneously. The standardized abstract syntax tree configuration file and the corresponding industrial-grade fault diagnosis code are solidified to obtain a standardized domain-specific language rule configuration file.

[0010] Furthermore, the system receives high-frequency time-series data output from the virtual simulation platform, extracts atomic facts from the high-frequency time-series data, and obtains a set of atomic facts, including: Edge detection is performed on the high-frequency time-series data based on the matrix difference algorithm to obtain instantaneous action facts; Perform state hold verification on discrete switching signals to obtain the continuous state facts of discrete switching signals; By introducing the dead zone tolerance parameter into the analog signal for anti-jitter filtering, the steady state of the analog signal is obtained. By introducing a scan cycle delay compensation parameter, the network communication delay of the virtual simulation platform is filtered out, and the delay-compensated data is used for subsequent fact extraction. By integrating the instantaneous action facts, the continuous state facts of discrete switching quantities, and the steady state facts of analog quantities, a set of atomic facts is obtained.

[0011] Furthermore, based on the industrial control evaluation specifications defined in the standardized domain-specific language rule configuration file, logical assertions are performed on the atomic fact set to obtain assertion results, including: The set of atomic facts is processed using a vectorized computation method to perform data processing on the entire simulation time axis, resulting in vectorized time series data; Matrix slicing is performed on the vectorized time series data within a preset time window to obtain data slices within the time window; Logical verification is performed on the data shards to obtain the logical verification results. The logical verification is performed with a built-in defensive exception interception mechanism: when a corrupted rule configuration file or a non-existent signal feature is parsed, the system outputs a format corruption alarm, sets the judgment to a failure state and records the runtime error code, and then safely skips the current error node to ensure the continuity of subsequent concurrent rule judgments and anti-crash capability. Based on the logical verification results, logical assertion results are generated, and the success and failure states of the logical assertions are obtained.

[0012] Furthermore, logical verification is performed on the data fragments to obtain the logical verification results, including: The trigger-response monitoring paradigm is used to perform logical verification on the data shards to obtain the trigger-response verification results. The data fragments are logically verified using a limit and safety protection paradigm to obtain the limit and safety protection verification results. The data shards are logically verified using the state linkage and global consistency paradigm to obtain the state linkage and global consistency verification results. The data shards are logically verified using a full-process time-series state machine paradigm to obtain the full-process time-series verification results. The trigger-response verification results, limit and safety protection verification results, state linkage and global consistency verification results, and full-process timing verification results are integrated to obtain the logical verification results.

[0013] Furthermore, anomaly information is captured from the assertion results, and intelligent diagnostic reasoning is performed by combining the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain anomaly diagnosis information and training evaluation results, including: The failure status in the logical assertion result is identified, and the timestamp of the corresponding violation data frame is captured to obtain the violation timestamp. The standardized domain-specific language rule configuration file is parsed to extract the corresponding industrial-grade fault diagnosis codes; Extract the device identifier involved from the logical assertion result, extract the state slices 3 seconds before and after the violation timestamp from the high-frequency time series data, and integrate the violation timestamp, device identifier and state slices to obtain a structured error data packet; The structured error data packet is sent back to the large language model for diagnostic reasoning to obtain abnormal diagnostic information and training evaluation results.

[0014] Secondly, a smart evaluation system for virtual simulation training tasks based on neural symbolic architecture is provided, based on the smart evaluation method for virtual simulation training tasks based on neural symbolic architecture described above, including: The module is configured to build a global device dictionary for digital twin objects; The compilation module is configured to compile the training and assessment standards in natural language form based on the global device dictionary and using a large language model to obtain a standardized domain-specific language rule configuration file. The extraction module is configured to receive high-frequency time-series data output by the virtual simulation platform, extract atomic facts from the high-frequency time-series data, and obtain a set of atomic facts. The logical assertion module is configured to perform logical assertions on the set of atomic facts according to the industrial control evaluation specifications defined in the standardized domain-specific language rule configuration file, and obtain assertion results; The intelligent diagnostic reasoning module is configured to capture abnormal information from the assertion results and perform intelligent diagnostic reasoning by combining the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain abnormal diagnostic information and training evaluation results.

[0015] Thirdly, a terminal is provided, including a processor, an input device, an output device, and a memory, wherein the processor, input device, output device, and memory are interconnected, wherein the memory is used to store a computer program, the computer program including program instructions, and the processor is configured to invoke the program instructions to execute the intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture as described in any of the preceding claims.

[0016] The invention employing the above technical solution has the following advantages: 1. This invention restricts the large model to the role of a "text-to-JSON translator" and completely entrusts all hard logic decisions involving time difference, floating-point comparison, and high-frequency sampling to a vectorized computing engine built on program code and structured rules.

[0017] 2. The NLP to DSL link provided by this invention empowers front-line training teachers to directly define the scoring criteria for complex processes; users only need to input natural language, and the system can automatically map it to the underlying sensor logic chain, thereby improving the reusability and lifespan of the training platform.

[0018] 3. This invention adopts matrix vectorization processing technology in modern data science, and uses low-level C language mathematical operations such as index offset and Boolean mask to process fact extraction, thereby avoiding the overhead of Python's native loop as much as possible; for half-hour level training tasks containing hundreds of thousands of frames of records, the engine can complete the judgment of dozens of strict concurrency rules within tens to hundreds of milliseconds.

[0019] 4. When the assertion component in this invention performs interception, it will forcibly capture and record the timestamp and exception code of the specific violation; this "accident slice" can not only provide teachers and students with absolutely objective review evidence, but also cluster these structured error features into systematic knowledge blind spot prompts through the feedback module. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention, the accompanying drawings used in the specific embodiments will be briefly described below. In all the drawings, the elements or parts are not necessarily drawn to scale.

[0021] Figure 1 The flowchart shows the intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to the present invention. Figure 2 The flowchart of the intelligent evaluation system for virtual simulation training tasks based on neural symbolic architecture of the present invention is shown below; Figure 3 This is a schematic diagram of the terminal structure in the intelligent evaluation method and system for virtual simulation training tasks based on neural symbolic architecture of the present invention. Detailed Implementation

[0022] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are merely illustrative of the technical solution of the present invention and are therefore intended to limit the scope of protection of the present invention.

[0023] like Figures 1-3 As shown, the intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture of the present invention includes: Step S01: Construct a global device dictionary for digital twin objects; Step S02: Based on the global device dictionary, the training assessment standards in natural language form are compiled using a large language model to obtain a standardized domain-specific language rule configuration file. Step S03: Receive high-frequency time series data output by the virtual simulation platform, extract atomic facts from the high-frequency time series data, and obtain a set of atomic facts; Step S04: Perform logical assertions on the atomic fact set according to the industrial control evaluation specifications defined in the standardized domain-specific language rule configuration file, and obtain the assertion results; Step S05: Capture abnormal information from the assertion results and perform intelligent diagnostic reasoning by combining the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain abnormal diagnostic information and training evaluation results.

[0024] In this embodiment, a global device dictionary for digital twin objects is constructed, including: The hierarchical path addressing specification is used to map the logical addresses of virtual devices to obtain the correspondence between virtual devices and logical addresses; Map the physical rendering state attributes of the virtual device to obtain the logical address of the physical rendering state attributes; The logical state attributes of the virtual device are mapped to obtain the logical address of the logical state attribute; By integrating the mapping between virtual devices and logical addresses, the logical addresses of physical rendering state attributes, and the logical addresses of logical state attributes, a global device dictionary for digital twin objects is obtained.

[0025] Specifically, the system adopts a strict dot-notation hierarchical path addressing specification, with the format "device code.attribute name", to achieve accurate mapping of variables within the virtual device.

[0026] For example, the material handling trolley module 001 is defined as X1, its floating-point attributes corresponding to its physical rendering state (such as the X-axis velocity in 3D space) are mapped to X1.Speed_X, and its boolean attributes corresponding to its logical state (such as whether it is on the track) are mapped to X1.On_Rail; the operation box module is defined as X5, and its subordinate forward rotation button is mapped to X5.B1. The final generated global device dictionary serves as the sole data interaction interface between the virtual simulation software and the rule evaluation engine, ensuring that all collected time-series data has a clear industrial physical meaning.

[0027] In this embodiment, based on a global device dictionary, a large language model is used to compile the training assessment standards in natural language form, resulting in a standardized domain-specific language rule configuration file, including: A large language model is used to perform semantic recognition on natural language assessment criteria to obtain temporal constraints and causal relationships. Align the devices and actions described in natural language with the global device dictionary to obtain the logical address mapping of devices and actions; The global device dictionary and the preset domain-specific language standard specifications are injected into the large language model as a system prompt word whitelist, and the large language model is used to perform restricted semantic recognition on natural language assessment standards. Constraint matching is performed on the logical address mapping based on the industrial signal type to obtain data constraint rules; By assembling timing constraints and causal relationships, logical address mappings between devices and actions, and data constraint rules, a standardized domain-specific language rule configuration file is obtained.

[0028] Specifically, the steps encapsulate the large language model as a "rule compilation agent" to achieve automatic conversion from natural language scoring standards to machine-executable logic, limiting the large model to the role of semantic understanding and translation, and preventing it from participating in hard logic judgment.

[0029] First, a large language model is used to identify the temporal constraints and causal relationships in the natural language assessment criteria to determine the industrial control paradigm type to which they belong. Then, a search and matching is performed in the global device dictionary to accurately align the device names described in natural language (such as "front electromagnetic limit switch") to the corresponding logical addresses (such as X2.Detection_State) and the action descriptions (such as "hopper bottom door open") to the corresponding logical expressions (such as X4.Gate_State==1). Next, strict constraints are applied according to the industrial signal type. For switch signals such as indicator light status, 1 / 0 Boolean values ​​are strictly matched. For analog signals such as speed, the Range operator is introduced by default and tolerance logic boundaries are reserved. Finally, all the above logical elements are assembled into a standardized JSON abstract syntax tree, which includes two parts: trigger block and assertion block.

[0030] To prevent large language models from generating illusions during compilation, this embodiment implements strict zero-illusion rule constraints.

[0031] Specifically, the system pre-builds a core operator library (including: existence quantifier operator, universal quantifier operator, negation quantifier operator, conditional implication operator, strong mutual exclusion lock operator, strict sequential evolution operator, time-limited flow operator, continuous duration measurement operator, pulse jump counting operator, etc.), and sets the global device dictionary as an addressing whitelist.

[0032] During compilation, the large language model must and can only extract logical operators from the core operator library. All device addressing paths must be within the global device dictionary whitelist. The large language model is prohibited from fabricating device layers or modifying the JSON structure skeleton. Any generated content outside the whitelist will be rejected by the system and trigger an alarm.

[0033] The above constraints ensure the determinism and reliability of the DSL rule configuration file.

[0034] In this embodiment, timing constraints and causal relationships, logical address mappings between devices and actions, and data constraint rules are assembled to obtain a standardized domain-specific language rule configuration file, including: When generating the standardized abstract syntax tree configuration file, industrial-grade fault diagnostic codes corresponding to each assertion logic are generated simultaneously. By solidifying the standardized abstract syntax tree configuration file with the corresponding industrial-grade fault diagnostic codes, a standardized domain-specific language rule configuration file is obtained.

[0035] Specifically, the principle behind this step is to provide a standardized error identification system for subsequent anomaly diagnosis.

[0036] During the generation of the JSON abstract syntax tree, the system automatically assigns a unique industrial-grade fault diagnostic code to each independent assertion logic. For example, for the assertion logic of "overtravel or braking failure", the OVERTRAVEL_LIMIT_FAILED diagnostic code is generated, and for the assertion logic of "signal and motion mismatch", the SIGNAL_MISMATCH_WITH_MOTION diagnostic code is generated.

[0037] Finally, the complete JSON configuration file containing fault diagnostic codes is solidified into an offline executable file, so that it can run independently without relying on a large model.

[0038] For ease of understanding, the standardized domain-specific language (DSL) rule configuration file generated above can also be called a "domain symbolization rule configuration file".

[0039] The name reflects its role as the core carrier of the "symbolic" part in the "neuro-symbolic" architecture, which realizes the transformation from natural language to deterministic symbolic logic and serves as a bridge connecting the large language model (neuro) and the vectorized assertion engine (symbolic).

[0040] In this embodiment, high-frequency time-series data output by a virtual simulation platform is received, and atomic facts are extracted from the high-frequency time-series data to obtain a set of atomic facts, including: Edge detection is performed on the high-frequency time-series data based on the matrix difference algorithm to obtain instantaneous action facts; Perform state hold verification on discrete switching signals to obtain the continuous state facts of discrete switching signals; By introducing the dead zone tolerance parameter into the analog signal for anti-jitter filtering, the steady state of the analog signal is obtained. By introducing a scan cycle delay compensation parameter, the network communication delay of the virtual simulation platform is filtered out, and the delay-compensated data is used for subsequent fact extraction. By integrating the instantaneous action facts, the continuous state facts of discrete switching quantities, and the steady state facts of analog quantities, a set of atomic facts is obtained.

[0041] Specifically, the principle of this step is to overcome computational glitches in the physics engine and latency in the virtual network, and to extract absolutely reliable "atomic facts" from the original high-frequency time-series data, providing a deterministic input basis for subsequent logical assertions.

[0042] First, edge detection is performed based on the matrix difference algorithm. The underlying simulation logic is similar to the scanning cycle of a PLC. The rising edge corresponds to the signal changing from 0 to 1, which is used to capture the extremely short moment when a student clicks a button or a photoelectric sensor is blocked. The falling edge corresponds to the signal changing from 1 to 0, which is used to capture the moment when a button is released or a material leaves the sensor. Then, the state holding verification is performed on discrete switching signals such as contactor engagement and indicator light staying on, and their continuous stable state facts are extracted. Finally, in response to the floating-point precision jitter generated when the 3D physics engine simulates the friction of mechanical motion (for example, the car is visually stopped, but the speed value of the physics engine is 0.0001), a dead zone parameter ε is forcibly introduced into the analog signal. By using matrix operations to determine |V_actual-V_target|<ε, the continuous variable is abstracted into a deterministic Boolean stable state fact.

[0043] Considering the unavoidable network communication delays in linkage signals (such as PLC output to virtual device response) within the virtual simulation platform, this system introduces a scan cycle delay compensation parameter ΔT. This parameter allows linkage signals to achieve state synchronization within a specified network delay grace period.

[0044] Specifically, when extracting trigger-response facts, the system does not require the response to occur precisely at a moment infinitely close to zero after the trigger. Instead, it allows matching within a time window of [t_trigger, t_trigger+ΔT]. This parameter effectively filters out false positives caused by normal virtual network communication latency, making the evaluation results closer to the actual response characteristics in real industrial scenarios.

[0045] Finally, by integrating the above three types of facts, a complete set of atomic facts is obtained.

[0046] In this embodiment, logical assertions are performed on the set of atomic facts according to the industrial control evaluation specifications defined in the standardized domain-specific language rule configuration file, and the assertion results are obtained, including: The set of atomic facts is processed using a vectorized computation method to perform data processing on the entire simulation time axis, resulting in vectorized time series data. Matrix slicing is performed on vectorized time-series data within a preset time window to obtain data slices within the time window; Perform logical verification on the data shards and obtain the logical verification results; The logical assertion result is generated based on the logical verification result, and the success and failure states of the logical assertion are obtained.

[0047] Specifically, matrix vectorization processing technology from modern data science is adopted, and low-level C language mathematical operations are used to replace Python's native loops, thereby improving the processing efficiency of massive time-series data.

[0048] The system first converts the extracted atomic fact set into vectorized time-series data in Pandas / NumPy format. Then, based on the time window parameters defined in the DSL rules, it extracts corresponding data slices along the entire simulation time axis using index offset operations. Next, it performs corresponding logical verification operations on each data slice. Finally, based on the Boolean results of the logical verification, it generates the success or failure status of the logical assertion. For a half-hour-level training task containing hundreds of thousands of frames, this vectorized computing engine can complete the judgment of dozens of stringent concurrency rules within tens to hundreds of milliseconds.

[0049] In this embodiment, logical verification is performed on the data shards to obtain the logical verification results, including: The trigger-response monitoring paradigm is used to perform logical verification on data shards, and the trigger-response verification results are obtained. The limit and safety protection paradigm is used to perform logical verification on data fragments, and the limit and safety protection verification results are obtained. The state linkage and global consistency paradigm is used to perform logical verification on data sharding, and the state linkage and global consistency verification results are obtained. Performing logical verification on data shards using the full-process sequential state machine paradigm to obtain a full-process sequential verification result; Integrating the trigger-response verification result, the limit and safety protection verification result, the state linkage and global consistency verification result, and the full-process sequential verification result to obtain a logical verification result.

[0050] Specifically, this step constructs a logical verification system based on the four core evaluation paradigms in the industrial control field, covering all common assessment scenarios in industrial training evaluation: Trigger-response monitoring paradigm: Used to assess the connectivity of electrical circuits and the response of drivers.

[0051] The engine first searches for all timestamp sets where a trigger event (such as the rising edge of a button press (X5.B1)) occurs. For each trigger point t0, it intercepts the data shard within the time window [t0, t0+T], and uses matrix operations to verify whether the target condition (such as the trolley speed X1.Speed_X crossing the start threshold) has at least one satisfied instant within this shard. If the entire shard does not satisfy the condition, the assertion fails.

[0052] Limit and safety protection paradigm: Used to assess the emergency stop mechanism and mechanical limit protection of the system.

[0053] After the engine captures a limit sensor trigger event (such as (J1)), it intercepts the data shard for the entire subsequent limit period, and uses the matrix all() operation to verify that the target condition (such as the speed being within the dead band range) is always true for the entire period within this window. Once an abnormal speed fluctuation frame appears, it is determined as "overtravel or braking failure".

[0054] State linkage and global consistency paradigm: Used to assess the signal interlock and indication logic of the industrial control system.

[0055] The engine performs a global vectorized comparison on all data throughout the entire training cycle to verify the strong correlation between the physical object state (such as X1.Running_State=="Forward") and the logical control signal (such as X5.L1==1). Once a state mismatch is found in any time frame, a violation is recorded.

[0056] Full-process sequential state machine paradigm: Used to assess the sequential logic of complex process flows.

[0057] The system abstracts the complex process into a series of key state nodes. The engine extracts the timestamp when each state node is first satisfied one by one, and establishes a strict incremental time assertion chain (such as t_arrive at J1 < t_open door < t_close door < t_return). It not only verifies whether the action has occurred, but also forcibly checks the sequence of actions. Out-of-sequence actions are determined to have process loopholes.

[0058] In addition to the four basic evaluation paradigms mentioned above, this system can also be extended to other industrial control evaluation paradigms as needed to adapt to more complex assessment requirements.

[0059] The following are examples: (5) Time window quantifier paradigm: This includes the existence quantifier test (EXPECT_EXIST), the universal quantifier test (EXPECT_ALWAYS), and the negation quantifier test (EXPECT_NEVER). The existence quantifier test is used to determine whether there is at least one time within a specified time window that satisfies the condition; the universal quantifier test is used to determine whether all times within a specified time window satisfy the condition; and the negation quantifier test is used to determine whether there are no times within a specified time window that satisfy the condition.

[0060] (6) Global constraint paradigm: including conditional implication test (GLOBAL_IMPLICATION) and strong mutex test (GLOBAL_MUTEX). Conditional implication test is used to verify the global logical relationship of "if A then B" (e.g., "as long as the trolley is in forward rotation, the forward indicator light must be on"); strong mutex test is used to verify that two states cannot be true at the same time (e.g., "the forward contactor and the reverse contactor cannot be engaged at the same time").

[0061] (7) Temporal Evolution Paradigm: This includes the Strict Sequential Evolution Test (STRICT_SEQUENCE) and the Time-Limited Flow Test (BOUNDED_SEQUENCE). The Strict Sequential Evolution Test is used to verify the order in which multiple critical state nodes occur (e.g., "first reach limit switch J1, then open the door, then close the door, and finally return to the origin"); the Time-Limited Flow Test adds a time limit constraint on top of the sequence.

[0062] (8) Quantitative and cumulative paradigms: including continuous duration measurement (EXPECT_DURATION) and pulse transition counting (EXPECT_COUNT). Continuous duration measurement is used to determine whether a certain state must last for at least a specified time; pulse transition counting is used to count whether the number of signal transitions meets the requirements.

[0063] All of the above paradigms can be efficiently implemented using time window slicing and matrix operations in a vectorized computation engine. The specific implementation methods are similar to the four basic paradigms mentioned above, and will not be elaborated further.

[0064] To improve the robustness of the system, the logic assertion engine has a built-in defensive exception interception mechanism.

[0065] When a corrupted DSL rule configuration file is encountered (e.g., incomplete JSON structure, mismatched operator names) or a rule references a non-existent signal feature (e.g., an undefined variable name in the device dictionary), the system will not crash or abort the evaluation process. Instead, it will output a corrupted format alarm through a secure call mechanism, set the rule to a failed state and record the runtime error code, and then safely skip the current error node and continue to execute concurrent assertions of other rules.

[0066] This mechanism ensures system continuity and crash prevention when dealing with large-scale concurrent grading or incomplete configurations.

[0067] In this embodiment, anomaly information is captured from the assertion results, and intelligent diagnostic reasoning is performed by combining the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain anomaly diagnosis information and training evaluation results, including: The failure status in the logical assertion result is identified, and the timestamp of the corresponding violation data frame is captured to obtain the violation timestamp; The standardized domain-specific language rule configuration file is parsed to extract the corresponding industrial-grade fault diagnosis codes; Extract the device identifiers involved from the logical assertion results, extract the state slices 3 seconds before and after the violation timestamp from the high-frequency time series data, and integrate the violation timestamp, device identifiers and state slices to obtain the structured error data packet; The structured error data packets are sent back to the large language model for diagnostic reasoning to obtain abnormal diagnostic information and training evaluation results.

[0068] Specifically, the principle of this step is to use the deterministic error data output by the vectorization engine to guide the large model to generate accurate diagnostic suggestions without illusions, thus solving the illusion problem of direct evaluation by the large model.

[0069] When the vectorization engine fails to execute any assertion, it immediately triggers an interrupt mechanism to capture the millisecond-level timestamp of the data frame that caused the violation. Then, it parses the DSL rule configuration file to extract the industrial-grade fault diagnosis code corresponding to the assertion logic. At the same time, it extracts the device ID involved from the logic assertion result and extracts a complete state slice of 3 seconds before and after the violation timestamp from the original high-frequency time series data. The above information is integrated into an absolutely real and illusory "crime scene data packet". Finally, the structured error data packet is sent back to the large language model diagnostic agent. Based on the structured error context and combined with the engineering-integrated teaching concept, the large model automatically infers the systemic physical fault or operational shortcoming and generates targeted rich text troubleshooting suggestions.

[0070] For example, “When the simulation runs for 260ms, it is detected that the forward rotation command of the control box has been issued, but the trolley traction motor does not respond. Please check whether the motor power harness connection is correct or whether the inverter parameters are configured correctly”, thus realizing a closed loop of industrial training evaluation from automated grading to intelligent tutoring.

[0071] In other embodiments, an intelligent evaluation system for virtual simulation training tasks based on neural symbolic architecture is provided, and an intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture based on any of the preceding embodiments is provided, including: The module is configured to build a global device dictionary for digital twin objects; The compilation module is configured to compile the training and assessment standards in natural language form based on a global device dictionary and a large language model, resulting in a standardized domain-specific language rule configuration file. The extraction module is configured to receive high-frequency time-series data output by the virtual simulation platform, extract atomic facts from the high-frequency time-series data, and obtain a set of atomic facts. The logical assertion module is configured to perform logical assertions on the set of atomic facts according to the industrial control evaluation specifications defined in the standardized domain-specific language rule configuration file, and obtain the assertion results. The intelligent diagnostic reasoning module is configured to capture abnormal information from assertion results and perform intelligent diagnostic reasoning by combining the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain abnormal diagnostic information and training evaluation results.

[0072] In other embodiments, a terminal is provided, including a processor, an input device, an output device, and a memory, which are interconnected. The memory is used to store a computer program, which includes program instructions. The processor is configured to invoke the program instructions to execute the intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture as described above.

[0073] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. An intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture, characterized in that, include: Construct a global device dictionary for digital twin objects; Based on the global device dictionary, a large language model is used to compile the training and assessment standards in natural language form to obtain a standardized domain-specific language rule configuration file. Receive high-frequency time-series data output from a virtual simulation platform, extract atomic facts from the high-frequency time-series data, and obtain a set of atomic facts; Logical assertions are performed on the atomic fact set according to the industrial control evaluation criteria defined in the standardized domain-specific language rule configuration file to obtain the assertion results; The assertion results are subjected to anomaly information capture, and intelligent diagnostic reasoning is performed in combination with the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain anomaly diagnosis information and training evaluation results.

2. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 1, characterized in that, Construct a global device dictionary for digital twin objects, including: The hierarchical path addressing specification is used to map the logical addresses of virtual devices to obtain the correspondence between virtual devices and logical addresses; The physical rendering state attributes of the virtual device are mapped to obtain the logical address of the physical rendering state attributes; The logical state attributes of the virtual device are mapped to obtain the logical addresses of the logical state attributes; By integrating the correspondence between the virtual devices and logical addresses, the logical addresses of the physical rendering state attributes, and the logical addresses of the logical state attributes, a global device dictionary for digital twin objects is obtained.

3. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 1, characterized in that, Based on the global device dictionary, a large language model is used to compile the training and assessment standards in natural language form, resulting in a standardized domain-specific language rule configuration file, including: A large language model is used to perform semantic recognition on natural language assessment criteria to obtain temporal constraints and causal relationships. Align the devices and actions described in natural language with the global device dictionary to obtain the logical address mapping of devices and actions; The global device dictionary and the preset domain-specific language standard specifications are injected into the large language model as a system prompt word whitelist, and the large language model is used to perform restricted semantic recognition on natural language assessment standards. The logical address mapping is constrained and matched according to the industrial signal type to obtain data constraint rules; The timing constraints, causal relationships, logical address mappings between devices and actions, and data constraint rules are assembled to obtain a standardized domain-specific language rule configuration file. The compilation process implements strict zero-illusion rule constraints: the generated logical operators must be extracted from the preset core operator library, the addressing path must be within the global device dictionary whitelist, and the large language model is prohibited from fabricating device layers or changing the JSON structure skeleton.

4. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 3, characterized in that, The timing constraints and causal relationships, the logical address mapping between devices and actions, and the data constraint rules are assembled to obtain a standardized domain-specific language rule configuration file, including: When generating the standardized abstract syntax tree configuration file, industrial-grade fault diagnostic codes corresponding to each assertion logic are generated simultaneously. The standardized abstract syntax tree configuration file and the corresponding industrial-grade fault diagnosis code are solidified to obtain a standardized domain-specific language rule configuration file.

5. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 1, characterized in that, The system receives high-frequency time-series data output from a virtual simulation platform, extracts atomic facts from the high-frequency time-series data, and obtains a set of atomic facts, including: Edge detection is performed on the high-frequency time-series data based on the matrix difference algorithm to obtain instantaneous action facts; Perform state hold verification on discrete switching signals to obtain the continuous state facts of discrete switching signals; By introducing the dead zone tolerance parameter into the analog signal for anti-jitter filtering, the steady state of the analog signal is obtained. By introducing a scan cycle delay compensation parameter, the network communication delay of the virtual simulation platform is filtered out, and the delay-compensated data is used for subsequent fact extraction. By integrating the instantaneous action facts, the continuous state facts of discrete switching quantities, and the steady state facts of analog quantities, a set of atomic facts is obtained.

6. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 1, characterized in that, According to the industrial control evaluation criteria defined in the standardized domain-specific language rule configuration file, logical assertions are performed on the atomic fact set to obtain assertion results, including: The set of atomic facts is processed using a vectorized computation method to perform data processing on the entire simulation time axis, resulting in vectorized time series data; Matrix slicing is performed on the vectorized time series data within a preset time window to obtain data slices within the time window; Logical verification is performed on the data shards to obtain the logical verification results. The logical verification is performed with a built-in defensive exception interception mechanism: when a corrupted rule configuration file or a non-existent signal feature is parsed, the system outputs a format corruption alarm, sets the judgment to a failure state and records the runtime error code, and then safely skips the current error node to ensure the continuity of subsequent concurrent rule judgments and anti-crash capability. Based on the logical verification results, logical assertion results are generated, and the success and failure states of the logical assertions are obtained.

7. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 6, characterized in that, Perform logical verification on the data shards to obtain the logical verification results, including: The trigger-response monitoring paradigm is used to perform logical verification on the data shards to obtain the trigger-response verification results. The data fragments are logically verified using a limit and safety protection paradigm to obtain the limit and safety protection verification results. The data shards are logically verified using the state linkage and global consistency paradigm to obtain the state linkage and global consistency verification results. The data shards are logically verified using a full-process time-series state machine paradigm to obtain the full-process time-series verification results. The trigger-response verification results, limit and safety protection verification results, state linkage and global consistency verification results, and full-process timing verification results are integrated to obtain the logical verification results.

8. The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to claim 1, characterized in that, The assertion results are subjected to anomaly information capture, and intelligent diagnostic reasoning is performed in conjunction with the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain anomaly diagnosis information and training evaluation results, including: The failure status in the logical assertion result is identified, and the timestamp of the corresponding violation data frame is captured to obtain the violation timestamp. The standardized domain-specific language rule configuration file is parsed to extract the corresponding industrial-grade fault diagnosis codes; Extract the device identifier involved from the logical assertion result, extract the state slices 3 seconds before and after the violation timestamp from the high-frequency time series data, and integrate the violation timestamp, device identifier and state slices to obtain a structured error data packet; The structured error data packet is sent back to the large language model for diagnostic reasoning to obtain abnormal diagnostic information and training evaluation results.

9. An intelligent evaluation system for virtual simulation training tasks based on neural symbolic architecture, characterized in that, The intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture according to any one of claims 1 to 8 includes: The module is configured to build a global device dictionary for digital twin objects; The compilation module is configured to compile the training and assessment standards in natural language form based on the global device dictionary and using a large language model to obtain a standardized domain-specific language rule configuration file. The extraction module is configured to receive high-frequency time-series data output by the virtual simulation platform, extract atomic facts from the high-frequency time-series data, and obtain a set of atomic facts. The logical assertion module is configured to perform logical assertions on the set of atomic facts according to the industrial control evaluation specifications defined in the standardized domain-specific language rule configuration file, and obtain assertion results; The intelligent diagnostic reasoning module is configured to capture abnormal information from the assertion results and perform intelligent diagnostic reasoning by combining the fault diagnosis codes in the standardized domain-specific language rule configuration file to obtain abnormal diagnostic information and training evaluation results.

10. A terminal, characterized in that, The system includes a processor, an input device, an output device, and a memory, which are interconnected. The memory stores a computer program, which includes program instructions. The processor is configured to invoke the program instructions to execute the intelligent evaluation method for virtual simulation training tasks based on neural symbolic architecture as described in any one of claims 1 to 8.

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