A DDR4 memory module row activation disturbance attack detection and mitigation system

Abstract

The application discloses a DDR4 memory module row activation disturbance attack detection and mitigation system and belongs to the technical field of memory security. The system comprises three layers: a row activation fingerprint layer L1 generates a row activation fingerprint through probability sampling and counting Bloom filter aggregation, and generates a first alarm when a threshold is met; a module side independent observation layer L2 samples CA bus commands in real time through a programmable logic device, performs activation density and row activation time length statistics through a microcontroller, identifies a row activation disturbance attack, and generates a second alarm; and a hierarchical response layer L3 is deployed in a system management controller and a host operating system, and triggers a hierarchical response after cross verification of the two alarms. A degradation execution mechanism is triggered when any layer fails, and the system makes adaptive adjustment based on the remaining available layers. The application does not need to modify DRAM chips and RCDs, has after-installation protection capability for existing DDR4 modules, and realizes high-reliability row activation disturbance attack detection and mitigation through three-layer cooperation and a degradation path.

Description

Technical Field

[0001] This invention relates to the field of memory security technology, and in particular to a system for detecting and mitigating row activation disturbance attacks on DDR4 memory modules. Background Technology

[0002] Row Hammer vulnerability in Dynamic Random Access Memory (DRAM) is a widely studied hardware security threat in recent years: by repeatedly activating a physical row (aggressor row) at high speed, bit flips can occur in its adjacent rows (victim rows), thus breaching the operating system's memory isolation protection. RowPress attack, proposed in 2023, is a variant of RowHammer, which significantly reduces the number of activations required to achieve bit flips by keeping the aggressor row active for an extended period. Both of these attacks are collectively referred to as row activation perturbation attacks.

[0003] In the DDR4 memory module field, the industry-standard Targeted Row Refresh (TRR) mechanism is implemented internally by DRAM manufacturers. It mitigates attacks by tracking suspected aggressor rows and performing additional refreshes on adjacent rows during refresh operations. However, the industry has discovered attack patterns such as TRRespass (2020), Blacksmith (2021), Half-Double (2021), and ZenHammer (2024) that can bypass mainstream DDR4 TRR implementations. The solutions mentioned at the USENIX Security 2025 conference further demonstrate that even if DDR4 servers are equipped with Error Correction Code (ECC), ECC is insufficient to prevent bit flip propagation after TRR is compromised.

[0004] DDR4's command encoding method differs from DDR3: DDR4 introduces a separate ACT_n pin (active-low) to distinguish the Activate command from other commands. Other commands, such as Precharge, are encoded using ACT_n=H combined with A16 (corresponding to RAS_n function), A15 (corresponding to CAS_n function), and A14 (corresponding to WE_n function). In a DDR4 RDIMM, the CA signal from the host memory controller first reaches the RCD (Register Clock Driver), which then re-drives it before sending it to the DRAM chip. The CA signal uses the SSTL (Stub Series Terminated Logic) single-ended level standard, and the clock signals CK / CK# are differential.

[0005] The DDR5 generation introduced RFM (Refresh Management), DRFM (Directed RFM) commands at the JEDEC level, and some manufacturers implemented PRAC (Per-Row Activation Counting) to provide stronger RowHammer mitigation; the DDR4 generation did not have corresponding standard commands.

[0006] The following solutions exist in the existing technology: Existing Solution 1: Integrating a row activation counter circuit within the RCD chip on the module: This circuit receives ACT commands from the host memory controller via the CA interface and counts the number of row activations; when the activation count for a row reaches a threshold, it sends an alarm message to the host memory controller. The counter is housed within the RCD chip itself.

[0007] Existing Solution 2: By setting up a row hammer protection circuit in the buffer chip on the module, including a history storage circuit, an address storage circuit, a reference address storage circuit and a control circuit, a reference address is provided in the refresh command response to perform additional refresh on the word lines adjacent to the target word line.

[0008] Existing Solution 3: Send an additional refresh command to the DRAM device through the host memory controller, so that the DRAM can use this extra time period to perform adjacent row refresh, thus forming a host-to-DRAM two-way cooperative RowHammer mitigation.

[0009] The existing solution has the following drawbacks: Disadvantage 1: Since both the existing solution and the DDR5 PRAC mechanism require the addition of circuitry inside the DRAM chip, the DDR4 modules that have already been shipped cannot obtain their protection capabilities without replacing the DRAM chip, thus making it impractical for the hundreds of millions of existing DDR4 modules.

[0010] Disadvantage 2: Since the counter of the existing solution 1 is located inside the RCD, (a) the counter is bound to the firmware / ECO cycle of the RCD, and the upgrade of the new protection strategy is subject to the RCD manufacturer; (b) the RCD has limited on-chip logic resources, making it difficult to achieve efficient tracking of all rows in low threshold (such as 500 times) scenarios; (c) once the RCD is compromised by an attacker through the side channel, the protection of the entire module is lost.

[0011] Disadvantage 3: Since the protection circuit of the existing Scheme 2 focuses on address history storage and adjacent row refresh during refresh response, it is not capable of identifying RowPress attacks (which depend on the duration of row activation rather than the number of activations).

[0012] Disadvantage 4: Since the existing solution 3 is limited to host-DRAM binary collaboration and does not introduce an independent observation channel on the module side, when the host memory controller itself is bypassed (as shown by ECC.fail), there is no second opinion on the module side that can provide cross-verification. Therefore, the defense chain is broken at a single point in the TRR failure scenario.

[0013] Disadvantage 5: Since the above solutions generally do not introduce a response layer between the system management controller and the host operating system, there is a lack of software-level actions (process isolation, memory page migration, module entering hardened mode, etc.) that can increase the cost to the attacker after the attack is detected. Therefore, even if it is detected, it can only be passively refreshed once.

[0014] Disadvantage 6: Since none of the above solutions define a degradation path when any layer fails, the entire protection chain will fail if a single component fails or a compatibility issue occurs during field deployment.

[0015] Therefore, a technical solution is needed that can be applied to both existing and new DDR4 modules without modifying the DDR4 DRAM chip itself or the module RCD chip, and can effectively detect and mitigate RowHammer and RowPress row activation perturbation attacks. Summary of the Invention

[0016] The purpose of this invention is to overcome the shortcomings of the prior art and provide a DDR4 memory module row activation perturbation attack detection and mitigation system. Without modifying the DDR4 DRAM chip itself or the module RCD chip, it achieves a three-layer collaborative system of row activation fingerprinting on the host memory controller side, independent observation unit on the module side (using programmable logic devices as high-speed sampling front-ends), and hierarchical response of the system management controller and host operating system. It also defines a degradation execution path when any layer fails. It is applicable to existing DDR4 modules and can be continuously upgraded as the algorithm evolves. It is also effective against both RowHammer and RowPress attacks.

[0017] The objective of this invention is achieved through the following technical solution: a DDR4 memory module row activation perturbation attack detection and mitigation system, comprising a row activation fingerprint layer L1, wherein the row activation fingerprint layer L1 is connected to a module-side independent observation layer L2, and the module-side independent observation layer L2 is connected to a hierarchical response layer L3;

[0018] The row activation fingerprint layer L1 is deployed on the host memory controller. It performs nondeterministic sampling of row activation commands through probability sampling, aggregates the sampled row address information using a counting Bloom filter to generate a row activation fingerprint, and generates a first alarm when a first threshold condition is met.

[0019] The module-side independent observation layer L2 is an independent management unit deployed on the DDR4 memory module PCB, independent of the DRAM chip array and the register clock driver RCD on the module. The management unit includes a logic sampling front-end and a microcontroller. The logic sampling front-end operates at the DDR4 clock frequency and is used to sample and decode the module's CA bus signals in real time. The microcontroller is used to perform activation density statistics and row activation duration statistics based on the decoded command events, and generate a second alarm when a second threshold condition is met.

[0020] The hierarchical response layer L3 is deployed on the system management controller and host operating system on the host side. It is used to receive the first alarm and the second alarm, perform cross-verification on the first alarm and the second alarm, and trigger hierarchical response based on the verification result.

[0021] When any one of the row activation fingerprint layer L1, module-side independent observation layer L2, and hierarchical response layer L3 fails, a degradation execution mechanism is triggered. The system makes adaptive adjustments based on the remaining available layers and continues to perform attack detection and mitigation functions.

[0022] Preferably, in the row activation fingerprint layer L1, when the host memory controller processes a memory request from the CPU, it uses a hardware pseudo-random number generator to perform nondeterministic sampling on each ACT command with an online adjustable sampling probability p, where 0 < p ≤ 1.

[0023] The triplet of the sampled hit command is mapped to h positions in a counter array of length M using h independent hash functions. The count value at the corresponding position is incremented by 1. Each count Bloom filter has a bit width of b bits. When the count Bloom filter reaches its maximum value of 2... b When the value is -1, saturation does not overflow.

[0024] At the end of each predetermined aggregation window, that is, after every W counter groups are updated, the count value of all positions in the count Bloom filter is compared with the first threshold Th1. If the minimum count value among the h hash positions exceeds Th1, it is determined that the corresponding area may be suffering from a row activation perturbation attack, and a first alarm is generated along with the area identifier of the area.

[0025] After the aggregation window ends, reset all count Bloom filters to zero and begin the next round of aggregation.

[0026] Preferably, the sampling probability p and the first threshold Th1 are adjusted online by the hierarchical response layer L3 according to the current alarm frequency and system load through a policy template or BIOS reload mechanism.

[0027] Preferably, in the independent observation layer L2 on the module side, the logic sampling front end bypasses the CA signal subset from the output of the register clock driver RCD through a high-impedance input buffer; the logic sampling front end uses the DDR4 clock CK as the sampling clock, latches the CA signal subset on each rising edge of CK, and combines and decodes the latched results to identify the Activate command and the Precharge command, while extracting the bank address and the row address.

[0028] The logic sampling front end writes the decoded command events into the FIFO buffer of the on-chip dual-port SRAM for command event transmission;

[0029] The microcontroller reads command events from the FIFO buffer, maintains an activation density table in the microcontroller's internal SRAM using a Count-MinSketch structure, and performs activation density statistics.

[0030] The logic sampling front end maintains a current active row register and ACT timestamp for each bank. When a Precharge command is detected, it calculates the row activation duration of the bank and performs row activation duration statistics. The microcontroller maintains a sliding window statistic for the row activation duration and identifies rows with consistently large row activation durations as an additional criterion for RowPress-type attacks.

[0031] When the frequency estimate of a row region in the activation density table exceeds the second threshold Th2, or the row activation duration of a row exceeds the RowPress threshold Th... RP At that time, the microcontroller generates a second alarm and transmits the second alarm to the system management controller via the system management bus in an OEM-customized command format. At the same time, it writes to the onboard EEPROM to form a persistent evidence chain. The onboard EEPROM adopts a cyclic writing strategy, and the storage area is divided into fixed-size entry slots. When the slots are full, the oldest entry is overwritten.

[0032] Preferably, the logic sampling front end uses a CPLD, a small-scale FPGA, or a custom ASIC, and the microcontroller uses an ARM Cortex-M0+.

[0033] The module-side independent observation layer L2 receives a policy template from the system management controller via the system management bus. The policy template includes settings for the second threshold Th2 and the RowPress threshold Th. RP The microcontroller provides an online adjustment command for at least one of the following parameters: Count-Min Sketch row and column configuration or sliding window length; the microcontroller updates the parameters using atomic operations, first writing the new parameters to the EEPROM temporary storage area, and then switching to the new parameters after verification.

[0034] Preferably, in the hierarchical response layer L3, the system management controller receives the first alarm and the second alarm, and compares whether the areas pointed to by the first alarm and the second alarm overlap within a predetermined time window. When they overlap, double-signed evidence is formed. The alarm confidence of the double-signed evidence is higher than that of the evidence of a single-layer alarm.

[0035] Based on the alarm confidence and severity, trigger at least one or a combination of the following three-level responses:

[0036] Conservative Level R1: The system management controller instructs the host memory controller to inject additional refresh commands into the alarm area, shorten the local refresh interval of the alarm area, and perform inspection and erasure / write.

[0037] Aggressive R2: The system management controller issues memory safety events to the host operating system through ACPI GHES entries. The host operating system kernel module performs isolation, freezing, or memory page migration on the process occupying the alerted region based on the reverse lookup from physical address to virtual address.

[0038] Level 3 R3: The system management controller sends a hardening mode command to the management unit. The management unit writes the status flag to the EEPROM and notifies the host memory controller through the SMBALERT# signal. The host memory controller adjusts the global refresh rate of the alarm memory module and continues for a predetermined duration.

[0039] The hierarchical response layer L3 implements hierarchical response state management through a finite state machine. After an alarm event is absent for a predetermined time, the response state regresses to the next level.

[0040] Preferably, the degradation execution mechanism includes at least one of the following degradation paths:

[0041] First degradation path D-1: When the row activation fingerprint layer L1 fails, the software module in the BIOS or hypervisor on the host side effectively implements the function of the row activation fingerprint layer L1, collects memory access events through the performance monitoring unit, and performs probability sampling and count Bloom filter aggregation in software.

[0042] The second degradation path D-2: When the independent observation layer L2 on the module side is missing, the system degenerates into a two-layer collaboration of row activation fingerprint layer L1 and hierarchical response layer L3. The hierarchical response layer L3 reduces the response threshold of a single-layer alarm by one level to compensate for the risk of missed detection caused by the lack of independent verification.

[0043] The third degradation path D-3: When the hierarchical response layer L3 is temporarily unreachable, the host memory controller executes a conservative response locally after the row activation fingerprint layer L1 is hit. The module-side independent observation layer L2 persists the alarm to EEPROM. After the hierarchical response layer L3 is restored, the system management controller actively polls, reads, and supplements the processing.

[0044] Fourth degradation path D-4: When the row activation fingerprint layer L1, the module-side independent observation layer L2, and the hierarchical response layer L3 are all unavailable, the system degrades to DDR4 standard behavior, without causing the original JEDEC-defined TRR mechanism to fail.

[0045] The beneficial effects of this invention are:

[0046] 1) Due to the adoption of a three-layer collaborative architecture, the host-side fingerprint of L1 and the independent observation of the module-side of L2 are physically and mathematically independent (L1 uses CBF, L2 uses Count-Min Sketch). Together with the hierarchical response of L3, they form a "detection-crossover-response" chain. This architecture requires attackers to simultaneously bypass two independent detection layers deployed in different physical locations and using different mathematical structures in order to evade detection and enter the response layer. Let the false negative rate of L1 be P. miss1 The L2 single-layer false negative rate is P miss2 Since the two detection algorithms are mathematically independent (different families of hash functions and different data structures), the joint false negative rate under the dual-signature mode is P. miss1 ×P miss2 This is far lower than the false negative rate of any single layer. This product effect is a nonlinear synergistic gain generated by the combination of layers, which cannot be obtained by simple superposition—this false negative rate level cannot be achieved by deploying any single layer alone.

[0047] 2) By adopting a dual-chip architecture of L2 logic sampling front-end + microcontroller and high-impedance bypass access, this invention provides a post-installation observation path for shipped DDR4 modules without modifying the DRAM chip or relying on RCD manufacturer ECO, thus solving the problem of drawback 1. The logic sampling front-end operates in real time at the DDR4 clock frequency while the microcontroller processes asynchronously. This division of labor architecture of "high-speed front-end + low-speed back-end" makes the hardware cost (small-scale CPLD / FPGA + low-end MCU) controllable. At the same time, the management unit can receive policy templates through SMBus to realize runtime threshold adjustment and algorithm upgrade.

[0048] 3) Because L2 adds additional RowPress observations, the logical sampling front end accurately measures the duration of each row activation at a resolution of 0.625 ns. The conventional understanding in the art is that RowHammer detection only needs to focus on the number of activations (frequency). However, this invention, by incorporating the activation duration dimension into the detection criterion, forms a dedicated identification path for RowPress-type attacks, solving shortcoming 3. This is a detection dimension not addressed by existing solutions 1-3 and their simple combinations.

[0049] 4) By introducing L3 hierarchical response and dual-signature evidence chain, after detection, the operating system can be linked to process isolation, memory page migration, or the module can be placed into enhanced refresh mode. Through cross-hardware and system software collaboration, the attacker's cost is increased from "bypassing DRAM-side TRR" to "simultaneously bypassing MC-side detection + module-side detection + operating system-level isolation", thus solving the problem of drawback 5.

[0050] 5) Because a degraded execution path is defined, L3 automatically lowers its response threshold to compensate for L2 failure, rather than causing a complete system failure. This "adaptive threshold tightening during degrade" compensation strategy allows the system to maintain a controllable level of protection even under partial failure conditions, thus addressing drawback 6. Attached Figure Description

[0051] Figure 1 This is a system principle block diagram of the present invention. Detailed Implementation

[0052] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] First, here is a definition of some of the technical terms involved in this invention:

[0054] RowHammer: A perturbation attack that causes adjacent row bits to flip by rapidly and repeatedly activating the same DRAM row.

[0055] RowPress: An attack variant that reduces the number of hammer attacks required by extending the activation time of the aggressor row.

[0056] TRR (Targeted Row Refresh): A RowHammer mitigation mechanism implemented by DDR4 generation vendors.

[0057] RFM (Refresh Management): A refresh management command introduced by the JEDEC standard for DDR5 generation.

[0058] PRAC (Per-Row Activation Counting): A per-row activation counting mechanism implemented in the DDR5 generation.

[0059] CBF (Counting Bloom Filter): A probabilistic data structure that replaces bits with counters to support counting and deletion, based on the standard Bloom filter.

[0060] Count-Min Sketch: A streaming frequency estimation data structure consisting of a d-row × w-column counter matrix. Each row uses an independent hash function, and the minimum value at the corresponding position in each row is retrieved during the query.

[0061] ACT_n: The Activate command signal pin (active-low) in DDR4. It is a new independent pin added in DDR4 to distinguish the Activate command from other commands.

[0062] PRE command: The Precharge command defined by JEDEC is implemented in DDR4 through the combination of ACT_n=H and A16 / A15 / A14 encoding. There is no independent PRE pin.

[0063] CA (Command / Address) bus: The bus on the module used to transmit command and address signals. DDR4 uses the SSTL single-ended level standard.

[0064] RCD (Register Clock Driver): A buffer chip on DDR4 RDIMM, responsible for receiving the CA signal from the MC and re-driving it to the DRAM chip.

[0065] MC (Memory Controller): The host-side controller responsible for interacting with DRAM.

[0066] BMC (Baseboard Management Controller): A management controller on the server motherboard that operates independently of the CPU.

[0067] CPLD (Complex Programmable Logic Device): A non-volatile programmable logic chip that operates immediately upon power-up and is suitable for low-power, high-speed sampling front-ends.

[0068] FPGA (Field-Programmable Gate Array): A type of programmable logic chip with abundant logic resources, but usually requires external configuration.

[0069] SSTL (Stub Series Terminated Logic): The single-ended level standard used by DDR4 CA signals.

[0070] LFSR (Linear Feedback Shift Register): A hardware pseudo-random number generator.

[0071] ACPI (Advanced Configuration and Power Interface): A standard for power management and hardware configuration.

[0072] GHES (Generic Hardware Error Source): An interface in ACPI used for reporting generic hardware errors.

[0073] SMBIOS (System Management BIOS): System Management Information Table Standard.

[0074] SMBus (System Management Bus): A low-speed management bus based on I2C, used for DIMM SPD reading and management communication.

[0075] ECC (Error-Correcting Code): A memory-based encoding mechanism used to detect and correct bit flips.

[0076] tREFI: The refresh interval defined by the DDR4 standard, which is 7.8μs under normal temperature.

[0077] tCK: DDR4 clock cycle, 0.625ns for DDR4-3200.

[0078] tRAS: The minimum time interval between Activate and Precharge in DDR4, approximately 32 ns for DDR4-3200.

[0079] See Figure 1The present invention provides a technical solution: a DDR4 memory module row activation disturbance attack detection and mitigation system, including a row activation fingerprint layer L1, wherein the row activation fingerprint layer L1 is connected to a module-side independent observation layer L2, and the module-side independent observation layer L2 is connected to a hierarchical response layer L3;

[0080] The row activation fingerprint layer L1 is deployed on the host memory controller. It performs nondeterministic sampling of row activation commands through probability sampling, aggregates the sampled row address information using a counting Bloom filter to generate a row activation fingerprint, and generates a first alarm when a first threshold condition is met.

[0081] The module-side independent observation layer L2 is an independent management unit deployed on the DDR4 memory module PCB, independent of the DRAM chip array and the register clock driver RCD on the module. The management unit includes a logic sampling front-end and a microcontroller. The logic sampling front-end operates at the DDR4 clock frequency and is used to sample and decode the module's CA bus signals in real time. The microcontroller is used to perform activation density statistics and row activation duration statistics based on the decoded command events, and generate a second alarm when a second threshold condition is met.

[0082] The hierarchical response layer L3 is deployed on the system management controller and host operating system on the host side. It is used to receive the first alarm and the second alarm, perform cross-verification on the first alarm and the second alarm, and trigger hierarchical response based on the verification result.

[0083] When any one of the row activation fingerprint layer L1, module-side independent observation layer L2, and hierarchical response layer L3 fails, a degradation execution mechanism is triggered. The system makes adaptive adjustments based on the remaining available layers and continues to perform attack detection and mitigation functions.

[0084] In this embodiment, three collaborative layers are set up: the first layer is deployed on the host memory controller, which generates row activation fingerprints through probability sampling and counting Bloom filters; the second layer is deployed on the module PCB, in a management unit independent of RCD and DRAM, which uses a logic sampling front-end (programmable logic device) to decode CA commands in real time at the DDR4 clock frequency, and the microcontroller performs activation density statistics and row activation duration statistics; the third layer is deployed on the system management controller and operating system, which cross-validates alarms from the two layers and triggers a tiered response of local enhanced refresh, process isolation, or module hardening mode. If any of the three layers fails, it degrades to the remaining available layers through a degradation path. This scheme is suitable for RowHammer and RowPress attack protection of existing DDR4 modules.

[0085] In some embodiments, in the row activation fingerprint layer L1, when the host memory controller processes a memory request from the CPU, it performs nondeterministic sampling on each ACT command with an online adjustable sampling probability p through a hardware pseudo-random number generator, where 0 < p ≤ 1.

[0086] The triplet of the sampled hit command is mapped to h positions in a counter array of length M using h independent hash functions. The count value at the corresponding position is incremented by 1. Each count Bloom filter has a bit width of b bits. When the count Bloom filter reaches its maximum value of 2... b When the value is -1, saturation does not overflow.

[0087] At the end of each predetermined aggregation window, that is, after every W counter groups are updated, the count value of all positions in the count Bloom filter is compared with the first threshold Th1. If the minimum count value among the h hash positions exceeds Th1, it is determined that the corresponding area may be suffering from a row activation perturbation attack, and a first alarm is generated along with the area identifier of the area.

[0088] After the aggregation window ends, reset all count Bloom filters to zero and begin the next round of aggregation.

[0089] In this embodiment, the first L1-row activation fingerprint layer is:

[0090] Nondeterministic sampling: When processing memory requests from the CPU, the host memory controller samples each ACT command with probability p (0 < p ≤ 1, and p can be adjusted online by the policy template). For commands that are sampled and matched, their (rank, bank, row) triples are fed into subsequent aggregation. Sampling is driven by a hardware pseudo-random number generator within the memory controller: the output of the linear feedback shift register (LFSR) is compared with a preset threshold register; a match is achieved when the output is below the threshold.

[0091] Filter aggregation: The (rank, bank, row) triple is mapped through h independent hash functions to h positions in a counter array of length M (i.e., CBF, Counting Bloom Filter), with the count value at each position incremented by 1. Each counter has a bit width of b bits (typically 4 bits), and the count increases when the counter reaches its maximum value of 2. b -1 prevents saturation and overflow. The hash function can be an H3-type linear hash (implemented with XOR operation, low hardware cost).

[0092] Threshold Comparison: At the end of each predetermined aggregation window (after every W CBF updates), the count values ​​of all positions in the CBF are compared with the first threshold Th1. If the minimum count value among the h hash positions exceeds Th1, it is determined that the corresponding (rank, bank, row region) may be being hammered, and a first alarm is generated along with the region's identifier. After the window ends, all CBF counters are reset to zero, and the next round of aggregation begins.

[0093] Threshold Adaptation: The threshold Th1 and sampling probability p can be adjusted online by the third layer via policy templates or BIOS reload mechanisms. L3 selects parameter combinations from predefined policy templates and writes them into the MC's configuration register based on the current alarm frequency and system load.

[0094] Let the sampling probability be p, and the number of ACTs within a window be N. Then the expected number of samples per unit window is p⋅N. CBF uses h independent hash functions and a counter array of length M. Its single-position false positive rate (misclassifying a non-attack line as an attack line) is approximately: Where h is the number of hash functions, M is the length of the counter array, and p⋅N is the expected number of samples within the window. When h=4, M=4096, p=0.05, and N=4×10^6, the expected number of samples is 200,000. Substituting these values ​​into the formula, we can obtain P. fp A value close to 1 indicates that the CBF is nearing saturation under this parameter. In actual deployment, M should be adjusted according to the number of different rows in a single window (rather than the total number of ACTs) to control the false positive rate within an acceptable range.

[0095] In some embodiments, the sampling probability p and the first threshold Th1 are adjusted online by the hierarchical response layer L3 according to the current alarm frequency and system load through a policy template or BIOS reload mechanism.

[0096] In some embodiments, the logic sampling front-end in the module-side independent observation layer L2 bypasses the CA signal subset from the output of the register clock driver RCD through a high-impedance input buffer; the logic sampling front-end uses the DDR4 clock CK as the sampling clock, latches the CA signal subset on each rising edge of CK, and combines and decodes the latched results to identify the Activate command and the Precharge command, while extracting the bank address and the row address.

[0097] The logic sampling front end writes the decoded command events into the FIFO buffer of the on-chip dual-port SRAM for command event transmission;

[0098] The microcontroller reads command events from the FIFO buffer, maintains an activation density table in the microcontroller's internal SRAM using a Count-MinSketch structure, and performs activation density statistics.

[0099] The logic sampling front end maintains a current active row register and ACT timestamp for each bank. When a Precharge command is detected, it calculates the row activation duration of the bank and performs row activation duration statistics. The microcontroller maintains a sliding window statistic for the row activation duration and identifies rows with consistently large row activation durations as an additional criterion for RowPress-type attacks.

[0100] When the frequency estimate of a row region in the activation density table exceeds the second threshold Th2, or the row activation duration of a row exceeds the RowPress threshold Th... RP At that time, the microcontroller generates a second alarm and transmits the second alarm to the system management controller via the system management bus in an OEM-customized command format. At the same time, it writes to the onboard EEPROM to form a persistent evidence chain. The onboard EEPROM adopts a cyclic writing strategy, and the storage area is divided into fixed-size entry slots. When the slots are full, the oldest entry is overwritten.

[0101] In this embodiment, the second layer L2 is an independent observation layer on the module side:

[0102] High-speed command sampling: An independent management unit located on the module PCB, whose programmable logic device (hereinafter referred to as the logic sampling front end) bypasses the CA signal subset from the RCD output terminal through PCB traces. The subset includes at least CS_n, ACT_n, and some address pins (A16 / A15 / A14 and bank / row address bits). The logic sampling front end uses the DDR4 clock CK as the sampling clock (for DDR4-3200, the CK frequency is 1600 MHz), latches the signal subset on each rising edge of CK, and performs combined decoding on the latched results: when CS_n=L and ACT_n=L, it is identified as an Activate command, and the bank address and row address are extracted simultaneously; when CS_n=L and ACT_n=H and A16=L and A15=H and A14=L, it is identified as a Precharge command.

[0103] The bypass connection employs a high-impedance input buffer (input impedance ≥ 10 kΩ, input capacitance ≤ 2 pF) to minimize the load impact on the CA signal at the RCD output. The bypass trace is led out from the RCD output rather than directly from the gold finger, in order to utilize the signal after the RCD is redriven, reducing the impact on the signal integrity of the MC→RCD segment.

[0104] The management unit is independent of the DRAM chip array and the RCD; it is completely decoupled on the data path and does not undertake any forwarding or buffering functions for reading and writing data.

[0105] Command event delivery: The logic sampling front end writes the decoded command events (event type, bank address, row address, timestamp) into the FIFO buffer of the on-chip dual-port SRAM. The microcontroller reads the events sequentially from the FIFO read end. The FIFO depth is designed for the worst-case scenario (continuous ACT command stream) to ensure that the microcontroller's processing speed can keep up with the average event arrival rate. The logic sampling front end internally maintains a free-running counter with CK as the clock source as the timestamp, with a resolution of 1 tCK (0.625 ns under DDR4-3200).

[0106] Activation density statistics: The microcontroller maintains an activation density table in its internal SRAM with a granularity of (rank, bank, row region). The incrementing method of its entries differs mathematically from L1 (using a Count-Min Sketch structure), thus forming an independent chain of evidence. The Count-Min Sketch uses a d-row, w-column counter matrix, with each row corresponding to an independent hash function; during a query, the minimum value at the corresponding position in the d-row is taken as the frequency estimate.

[0107] 1. Meaning of Activation Density Table: Activation density table refers to a data structure in which the management unit, based on row activation events observed on the DDR4 command bus, performs correlation statistics on repeated activations, inter-row round-trip switching, activation time intervals, and row opening durations of logical rows within the same bank. Combined with the pre-configured adjacency relationships between logical rows and candidate disturbed rows, it accumulates the disturbance contribution generated by each intruding row into the candidate disturbed row according to the source direction, disturbance weight, and time decay rules. It does not record the simple total number of activations of a row since system startup, but rather the disturbance exposure intensity experienced by the candidate disturbed row within the current continuous time range. When this intensity reaches a preset threshold, the system outputs the corresponding candidate disturbed row or row region and attack mode.

[0108] Perturbation density = activation contribution after time decay + gain from multiple sources combined + optional long open line contribution.

[0109] 2. Composition of the Activation Density Table: As shown in Table 1, the activation density table consists of the Row Migration Admission Table (TAD), the Disturbance Exposure Table (VED), and the Adjacent Disturbance Configuration (APC). TAD is responsible for filtering row migration paths with dangerous timing characteristics from the high-bandwidth command stream; VED only records the filtered candidate disturbed objects with precise labels; and APC is responsible for connecting logical row addresses with candidate disturbed objects.

[0110] Table 1

[0111] Row activation duration statistics: The logical sampling front end maintains a "currently active row" register and the corresponding ACT timestamp for each bank. When a Precharge command is detected, the row activation duration t for that bank is calculated. AggON =PRE timestamp - ACT timestamp (resolution 0.625 ns). The microcontroller assigns a timestamp to each (bank, row) t. AggON Maintain sliding window statistics (p99 quantiles) to identify t. AggON A persistently large number of rows is used as an additional criterion for RowPress-type attacks.

[0112] A second alarm is generated when the estimated frequency of a region in a row of the activation density table exceeds the second threshold Th2, or the t value of a certain row exceeds the threshold Th2. AggON The p99 value exceeds the RowPress threshold. RP At this time, the microcontroller generates a second alarm. The second alarm is transmitted to the BMC via SMBus (System Management Bus) in an OEM-defined command format, and simultaneously written to the management unit's onboard EEPROM (8KB capacity) to form a persistent chain of evidence. The EEPROM employs a circular write strategy: the storage area is divided into fixed-size entry slots (each slot is 16 bytes, including a 4-byte timestamp, a 4-byte rank / bank / row address, a 1-byte alarm type, and a density value or t). AggON (Value is 4 bytes, checksum is 3 bytes), and when full, the oldest entry is overwritten.

[0113] In some embodiments, the logic sampling front-end uses a CPLD, a small-scale FPGA, or a custom ASIC, and the microcontroller uses an ARM Cortex-M0+.

[0114] The module-side independent observation layer L2 receives a policy template from the system management controller via the system management bus. The policy template includes settings for the second threshold Th2 and the RowPress threshold Th. RP The microcontroller provides an online adjustment command for at least one of the following parameters: Count-Min Sketch row and column configuration or sliding window length; the microcontroller updates the parameters using atomic operations, first writing the new parameters to the EEPROM temporary storage area, and then switching to the new parameters after verification.

[0115] In some embodiments, the system management controller in the hierarchical response layer L3 receives a first alarm and a second alarm, and compares whether the areas pointed to by the first alarm and the second alarm overlap within a predetermined time window. When they overlap, double-signature evidence is formed. The alarm confidence of the double-signature evidence is higher than that of the evidence of a single-layer alarm.

[0116] Based on the alarm confidence and severity, trigger at least one or a combination of the following three-level responses:

[0117] Conservative Level R1: The system management controller instructs the host memory controller to inject additional refresh commands into the alarm area, shorten the local refresh interval of the alarm area, and perform inspection and erasure / write.

[0118] Aggressive R2: The system management controller issues memory safety events to the host operating system through ACPI GHES entries. The host operating system kernel module performs isolation, freezing, or memory page migration on the process occupying the alerted region based on the reverse lookup from physical address to virtual address.

[0119] Level 3 R3: The system management controller sends a hardening mode command to the management unit. The management unit writes the status flag to the EEPROM and notifies the host memory controller through the SMBALERT# signal. The host memory controller adjusts the global refresh rate of the alarm memory module and continues for a predetermined duration.

[0120] The hierarchical response layer L3 implements hierarchical response state management through a finite state machine. After an alarm event is absent for a predetermined time, the response state regresses to the next level.

[0121] In this embodiment, the third layer L3-hierarchical response layer:

[0122] Alarm aggregation: The BMC receives the first alarm (from the MC, transmitted via PCI Express in-band message or platform event interruption) and the second alarm (from the L2 management unit, transmitted via SMBus), and compares whether the (rank, bank, row) areas pointed to by the two alarms overlap. When both alarms point to the same area within a predetermined time window (e.g., 100 ms), "double-signature" evidence is formed with high confidence; when only a single alarm is detected, it is processed according to the degradation rules with low confidence.

[0123] Tiered Response: Trigger at least one or a combination of the following three levels of response based on alarm confidence and severity:

[0124] Conservative R1: The BMC instruction injects additional refresh commands into the bank / row area of ​​the alarm, shortening the local refresh interval of that area from the standard tREFI (7.8μs) to tREFI / 2 (3.9μs), and performs a patrol scrub in the indicated area. The DDR4 standard allows the MC to independently schedule REF commands by rank, and the DRAM chip supports 2× refresh rate (the high-temperature mode defined by the DDR4 specification is 2× refresh).

[0125] Aggressive R2: The BMC issues memory safety events to the host operating system through ACPI GHES (Generic Hardware Error Source) entries. The OS kernel module performs isolation, freezing, or memory page migration on the process occupying the alerted region based on the reverse lookup from physical address to virtual address.

[0126] Level 3 R3: The BMC sends a "hardening mode" command to the management unit via SMBus. The management unit writes the status flag to the EEPROM and notifies the MC via the SMBALERT# signal. The MC adjusts the global refresh rate of the DIMM to 2× and continues for a predetermined duration (e.g., 60 seconds).

[0127] State Machine and Decline: Hierarchical response is implemented using a finite state machine: NORMAL → ELEVATED (triggered R1) → AGGRESSIVE (triggered R2) → HARDENED (triggered R3). After an event remains absent for a predetermined time (e.g., no new alarms for 30 seconds in the ELEVATED state), the state declines by one level.

[0128] In some embodiments, the degradation execution mechanism includes at least one of the following degradation paths:

[0129] First degradation path D-1: When the row activation fingerprint layer L1 fails, the software module in the BIOS or hypervisor on the host side effectively implements the function of the row activation fingerprint layer L1, collects memory access events through the performance monitoring unit, and performs probability sampling and count Bloom filter aggregation in software.

[0130] The second degradation path D-2: When the independent observation layer L2 on the module side is missing, the system degenerates into a two-layer collaboration of row activation fingerprint layer L1 and hierarchical response layer L3. The hierarchical response layer L3 reduces the response threshold of a single-layer alarm by one level to compensate for the risk of missed detection caused by the lack of independent verification.

[0131] The third degradation path D-3: When the hierarchical response layer L3 is temporarily unreachable, the host memory controller executes a conservative response locally after the row activation fingerprint layer L1 is hit. The module-side independent observation layer L2 persists the alarm to EEPROM. After the hierarchical response layer L3 is restored, the system management controller actively polls, reads, and supplements the processing.

[0132] Fourth degradation path D-4: When the row activation fingerprint layer L1, the module-side independent observation layer L2, and the hierarchical response layer L3 are all unavailable, the system degrades to DDR4 standard behavior, without causing the original JEDEC-defined TRR mechanism to fail.

[0133] In this embodiment, the downgrade execution path includes: D-1: When activating the fingerprint layer L1 (e.g., if the MC does not support a hardware fingerprint module), L1 is equivalently implemented by a software module within the host BIOS or hypervisor: memory access events are collected through the PMU (Performance Monitoring Unit), and probability sampling and CBF aggregation are performed in software. The time resolution of the software implementation is weaker than that of the hardware implementation, but it can still achieve effective interception.

[0134] D-2: When the independent observation layer L2 on the module side is missing (for example, the module does not contain the independent management unit described in this invention), the system degenerates into a "L1 + L3" two-layer collaboration, losing only the "dual signature" and module-side evidence chain capabilities. At this time, L3 lowers the response threshold of single-layer alarms by one level (originally requiring dual signatures to trigger R2, now triggering R2 with a single-layer alarm (L1 alarm)) to compensate for the risk of missed detection caused by the lack of independent verification.

[0135] D-3: When the hierarchical response layer L3 is temporarily unreachable (e.g., BMC is undergoing firmware upgrade), the MC performs conservative level R1 (refresh + inspection and write) locally after L1 hit. The L2 management unit persists the alarm to EEPROM, and when L3 recovers, the BMC actively polls and reads it and performs supplementary processing.

[0136] D-4: If all three layers are unavailable at the same time, this invention degenerates into DDR4 standard behavior, without invalidating the original JEDEC-defined TRR mechanism.

[0137] The following is an example of a complete three-tier deployment of DDR4 RDIMM servers in a financial data center:

[0138] Implementation environment: Xeon Scalable server platform in a financial data center, configured with DDR4-3200 ECCRDIMM, MC supports the fingerprint module extended by this invention (added by BIOS through MRC microcode), BMC runs OpenBMC custom firmware, the operating system is Linux 6.5 kernel and loaded with the memory security kernel module that is compatible with this invention.

[0139] L1 parameter configuration: Each channel maintains an independent CBF. The hash function uses four independent H3 linear hashes (implemented via an XOR matrix), the counter array length M=4096, each counter is 4 bits wide (saturation counting, maximum value 15), the sampling probability p=0.05, the aggregation window W is set to 64ms (aligned with DDR4 tREFW), and the threshold Th1=8. The CBF is reset to zero after the window ends. Sampling is driven by the MC's internal 16-bit LFSR.

[0140] L2 hardware implementation: The independent management unit on the module consists of the following components:

[0141] Logic sampling front end: High-speed FPGA / ASIC / dedicated sampler, using the module CK clock (1600 MHz) as the sampling clock, bypassing the CS_n, ACT_n, A16, A15, A14 and row addresses A0-A13 (a total of 19 signals) of the RCD output. The input buffer adopts the high-impedance LVCMOS input mode inside the CPLD (input capacitance approximately 2 pF / pin). The CPLD internally implements the command decoding state machine and per-bank active row register (16 banks × 14-bit row address + 32-bit timestamp). Decoded events are written to a dual-port SRAM FIFO (depth 256 entries) through an 8-bit parallel interface.

[0142] Microcontroller: MCU@48 MHz, reads events from FIFO via an 8-bit parallel interface, maintains a Count-Min Sketch (d=4 rows × w=512 columns, 8 bits per counter, 2 KB total) and per-bank t in internal SRAM. AggON p99 Sliding window statistics. Th2 and Th RP It is distributed online by BMC via SMBus.

[0143] Storage: 8 KB EEPROM (e.g., AT24C64) for persistent alarm evidence chain.

[0144] Power supply: Power is drawn from the VDD (1.2V) rail of the DIMM via an LDO. The total power consumption of the management unit is approximately 50 mW.

[0145] PCB layout: The management unit is placed on the back of the module PCB (either on the same side as the DRAM chip or on the back side). Bypass traces are led out from the RCD output terminal, and the trace length is controlled within 15mm to ensure signal quality at 1600 MHz.

[0146] L3 Implementation: The BMC receives the first alarm from the MC (via PCI Express platform event interrupt) and the second alarm reported by the management unit via the SMBus OEM protocol, and maintains a hierarchical response state machine internally. The dual-signature time window is set to 100ms. When entering the conservative level R1, the BMC instructs the MC to shorten the tREFI of the alarm rank from 7.8μs to 3.9μs; when entering the aggressive level R2, the BMC notifies the OS via the ACPI GHES entry, and the OS kernel module performs a reverse lookup from physical address to virtual address and isolates or migrates the relevant processes; when entering the third level R3, the BMC instructs the marked DIMM to enter hardened mode via SMBus instructions, which lasts for 60 seconds.

[0147] Policy template distribution mechanism: The BMC sends OEM-defined commands (command codes 0xC0-0xCF reserved) to the microcontroller of the L2 management unit via SMBus. The command payload includes the target parameter identifier (1 byte) and parameter values ​​(2-4 bytes). Upon receiving the command, the microcontroller updates its internal parameters and writes them to the EEPROM for backup. Supported parameters include: Th2, Th... RP The parameters include: Count-Min Sketch row and column configuration, and sliding window length. Parameter updates are performed atomically: the microcontroller first writes the new parameters to the EEPROM temporary storage area, and then switches to the new parameters after verification.

[0148] Verification scenario: Four known attack modes—TRRespass, Blacksmith, Half-Double, and ZenHammer—were deployed for 24 hours each on a target machine with identical laboratory configurations. Bit flip counts were compared between the scenarios with and without this invention enabled. Results are shown in Report 2:

[0149] Table 2

[0150]

[0151] In this embodiment, L2 simultaneously affects t AggON The statistics are used for RowPress bypass observation. When the t of a certain aggressor row... AggON p99 value exceeds Th RP An additional second alarm will be generated at that time.

[0152] In other implementations, L1 can also adopt a software fallback path: replacing the hardware CBF in the MRC microcode with software sampling and CBF implementation within the hypervisor, which can be deployed as a "software SKU" on early platforms that do not have a hardware fingerprint module. A comparison of the degradation effects is shown in Table 3.

[0153] Table 3

[0154]

[0155] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A system for detecting and mitigating row activation disturbance attacks in DDR4 memory modules, characterized in that: It includes a row activation fingerprint layer L1, which is connected to a module-side independent observation layer L2, and the module-side independent observation layer L2 is connected to a hierarchical response layer L3; The row activation fingerprint layer L1 is deployed on the host memory controller. It performs nondeterministic sampling of row activation commands through probability sampling, aggregates the sampled row address information using a counting Bloom filter to generate a row activation fingerprint, and generates a first alarm when a first threshold condition is met. The module-side independent observation layer L2 is an independent management unit deployed on the DDR4 memory module PCB, independent of the DRAM chip array and the register clock driver RCD on the module. The management unit includes a logic sampling front-end and a microcontroller. The logic sampling front-end operates at the DDR4 clock frequency and is used to perform real-time sampling and command decoding of the module CA bus signal. The microcontroller is used to perform activation density statistics and row activation duration statistics based on the decoded command events, and generate a second alarm when the second threshold condition is met. The hierarchical response layer L3 is deployed on the system management controller and host operating system on the host side. It is used to receive the first alarm and the second alarm, perform cross-verification on the first alarm and the second alarm, and trigger hierarchical response based on the verification result. When any one of the row activation fingerprint layer L1, module-side independent observation layer L2, and hierarchical response layer L3 fails, a degradation execution mechanism is triggered. The system makes adaptive adjustments based on the remaining available layers and continues to perform attack detection and mitigation functions.

2. The DDR4 memory module row activation disturbance attack detection and mitigation system according to claim 1, characterized in that: In the row activation fingerprint layer L1, when the host memory controller processes a memory request from the CPU, it uses a hardware pseudo-random number generator to perform nondeterministic sampling on each ACT command with an online adjustable sampling probability p, where 0 < p ≤ 1. The triplet of the sampled hit command is mapped to h positions in a counter array of length M using h independent hash functions. The count value at the corresponding position is incremented by 1. Each count Bloom filter has a bit width of b bits. When the count Bloom filter reaches its maximum value of 2... b When the value is -1, saturation does not overflow. At the end of each predetermined aggregation window, that is, after every W counter groups are updated, the count value of all positions in the count Bloom filter is compared with the first threshold Th1. If the minimum count value among the h hash positions exceeds Th1, it is determined that the corresponding area may be suffering from a row activation perturbation attack, and a first alarm is generated along with the area identifier of the area. After the aggregation window ends, reset all count Bloom filters to zero and begin the next round of aggregation.

3. The DDR4 memory module row activation disturbance attack detection and mitigation system according to claim 2, characterized in that: The sampling probability p and the first threshold Th1 are adjusted online by the hierarchical response layer L3 according to the current alarm frequency and system load through policy templates or BIOS reload mechanisms.

4. The DDR4 memory module row activation disturbance attack detection and mitigation system according to claim 1, characterized in that: The logic sampling front end in the module-side independent observation layer L2 bypasses the CA signal subset from the output of the register clock driver RCD through a high-impedance input buffer; the logic sampling front end uses the DDR4 clock CK as the sampling clock, latches the CA signal subset on each rising edge of CK, and combines and decodes the latched results to identify the Activate command and the Precharge command, while extracting the bank address and the row address. The logic sampling front end writes the decoded command events into the FIFO buffer of the on-chip dual-port SRAM for command event transmission; The microcontroller reads command events from the FIFO buffer, maintains an activation density table in the microcontroller's internal SRAM using a Count-MinSketch structure, and performs activation density statistics. The logical sampling front end maintains a current active row register and ACT timestamp for each bank. When a Precharge command is detected, it calculates the duration of row activation for the bank and performs row activation duration statistics. The microcontroller maintains sliding window statistics on the duration of row activation and identifies rows with consistently long durations of row activation as an additional criterion for RowPress-type attacks. When the frequency estimate of a row region in the activation density table exceeds the second threshold Th2, or the row activation duration of a row exceeds the RowPress threshold Th... RP At that time, the microcontroller generates a second alarm and transmits the second alarm to the system management controller via the system management bus in an OEM-customized command format. At the same time, it writes to the onboard EEPROM to form a persistent evidence chain. The onboard EEPROM adopts a cyclic writing strategy, and the storage area is divided into fixed-size entry slots. When the slots are full, the oldest entry is overwritten.

5. The DDR4 memory module row activation disturbance attack detection and mitigation system according to claim 4, characterized in that: The logic sampling front end uses a CPLD, a small-scale FPGA, or a custom ASIC, and the microcontroller uses an ARM Cortex-M0+. The module-side independent observation layer L2 receives a policy template from the system management controller via the system management bus. The policy template includes settings for the second threshold Th2 and the RowPress threshold Th. RP The microcontroller provides an online adjustment command for at least one of the following parameters: Count-Min Sketch row and column configuration or sliding window length; the microcontroller updates the parameters using atomic operations, first writing the new parameters to the EEPROM temporary storage area, and then switching to the new parameters after verification.

6. The DDR4 memory module row activation disturbance attack detection and mitigation system according to claim 1, characterized in that: In the hierarchical response layer L3, the system management controller receives the first alarm and the second alarm, and compares whether the areas pointed to by the first alarm and the second alarm overlap within a predetermined time window. When they overlap, double-signed evidence is formed. The alarm confidence of the double-signed evidence is higher than that of the evidence of a single-layer alarm. Based on the alarm confidence and severity, trigger at least one or a combination of the following three-level responses: Conservative Level R1: The system management controller instructs the host memory controller to inject additional refresh commands into the alarm area, shorten the local refresh interval of the alarm area, and perform inspection and erasure / write. Aggressive R2: The system management controller issues memory safety events to the host operating system through ACPI GHES entries. The host operating system kernel module performs isolation, freezing, or memory page migration on the process occupying the alerted region based on the reverse lookup from physical address to virtual address. Level 3 R3: The system management controller sends a hardening mode command to the management unit. The management unit writes the status flag to the EEPROM and notifies the host memory controller through the SMBALERT# signal. The host memory controller adjusts the global refresh rate of the alarm memory module and continues for a predetermined duration. The hierarchical response layer L3 implements hierarchical response state management through a finite state machine. After an alarm event is absent for a predetermined time, the response state regresses to the next level.

7. The DDR4 memory module row activation disturbance attack detection and mitigation system according to claim 1, characterized in that: The aforementioned degradation execution mechanism includes at least one of the following degradation paths: First degradation path D-1: When the row activation fingerprint layer L1 fails, the software module in the BIOS or hypervisor on the host side effectively implements the function of the row activation fingerprint layer L1, collects memory access events through the performance monitoring unit, and performs probability sampling and count Bloom filter aggregation in software. The second degradation path D-2: When the independent observation layer L2 on the module side is missing, the system degenerates into a two-layer collaboration of row activation fingerprint layer L1 and hierarchical response layer L3. The hierarchical response layer L3 reduces the response threshold of a single-layer alarm by one level to compensate for the risk of missed detection caused by the lack of independent verification. The third degradation path D-3: When the hierarchical response layer L3 is temporarily unreachable, the host memory controller executes a conservative response locally after the row activation fingerprint layer L1 is hit. The module-side independent observation layer L2 persists the alarm to EEPROM. After the hierarchical response layer L3 is restored, the system management controller actively polls, reads, and supplements the processing. Fourth degradation path D-4: When the row activation fingerprint layer L1, the module-side independent observation layer L2, and the hierarchical response layer L3 are all unavailable, the system degrades to DDR4 standard behavior, without causing the original JEDEC-defined TRR mechanism to fail.

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