Simulator and simulation method

Abstract

The application discloses an emulator and a simulation method. The emulator comprises a debugging interface module, which is used for realizing the conduction and disconnection of a debugging channel; a chip function debugging module, which is connected with the debugging interface module; the chip function debugging module comprises an access control unit, the access control unit comprises a configuration subunit, which is used for configuring a debugging permission; a chip function module, which is used for simulating a chip; the chip function module comprises a permission management unit, which is connected with the access control unit, wherein the permission management unit generates an access address and sends the access address to the access control unit; the access control unit configures the configuration subunit according to the access address to output a control signal to the debugging interface module; and the control signal is used for controlling the conduction and disconnection of the debugging channel. The emulator and the simulation method improve the security protection capability in the chip simulation debugging process.

Description

Technical Field

[0001] This application relates to the fields of chip design and verification technology, and in particular to a simulator and simulation method. Background Technology

[0002] In the development of security chips, emulators are used to debug chip programs and download data. With the increasing demands for chip security, emulators must not only support the normal download and debugging of user programs or data, but also consider encryption protection for sensitive data, achieving functions such as anti-debugging and anti-reading protection for secure data.

[0003] The ease of program debugging and security protection are inherently contradictory design requirements. This necessitates emulator designs to incorporate additional usage restrictions or even reduce debugging functionality to meet basic security requirements. In existing technologies, emulators primarily focus on the ease of debugging, with security mechanisms typically employing pure software encryption or simple interface locking. On one hand, pure software encryption schemes are easily intercepted and cracked during the download process, posing a risk of data leakage. On the other hand, simple interface locking lacks dynamic management capabilities; once the debugging interface is enabled, the secure program area and secure data area are threatened with unauthorized reading or modification, failing to achieve differentiated and dynamic access control for different security areas.

[0004] Therefore, there is a need for a new simulator and simulation method that can overcome at least one of the above-mentioned defects. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a simulator and simulation method, and in particular a simulator and method that supports security protection, aiming to improve the security protection capabilities during chip simulation and debugging.

[0006] According to a first aspect of the embodiments of this application, a simulator is provided, comprising:

[0007] A debugging interface module, which is used to enable and disable the debugging path;

[0008] A chip function debugging module, connected to the debugging interface module; the chip function debugging module includes an access control unit, which includes a configuration subunit for configuring debugging permissions; and

[0009] A chip functional module, used for chip simulation; the chip functional module includes a permission management unit, which is connected to the access control unit.

[0010] The access management unit generates an access address and sends the access address to the access control unit. The access control unit configures the configuration subunit according to the access address to output a control signal to the debugging interface module. The control signal is used to control the connection and disconnection of the debugging path.

[0011] Optionally, when the access address is within a preset protected address range, the corresponding control signal controls the debugging path to disconnect.

[0012] Optionally, the configuration subunit is also connected to the CPU unit and / or encryption readout unit of the chip functional module;

[0013] The control signal includes at least one selected from the following signals:

[0014] A debug enable signal is output to the debug interface module to control the opening and closing of the debug interface.

[0015] Access Denied Signal, which is output to the permission management unit to prevent the CPU unit from accessing the memory of the chip functional module through the permission management unit;

[0016] A verification enable signal is output to the encryption readout unit to enable encryption of the data read from the memory;

[0017] A debug disable signal is output to the CPU unit to disable the debugging function of the CPU unit.

[0018] Optionally, the chip functional module further includes a CPU unit and a memory; the CPU unit is connected to the permission management unit; the memory is connected to the permission management unit.

[0019] When the CPU unit accesses the memory through the permission management unit, the permission management unit generates a corresponding access address.

[0020] The control signals are used to allow or disable the debug interface module's debug access to the CPU unit, and to allow or disable read / write access to the memory.

[0021] Optionally, the memory includes a secure program area and a secure data area;

[0022] When the CPU unit accesses the secure program area through the permission management unit, the permission management unit outputs an access address that identifies the access to the secure program area to the access control unit. The access control unit configures the configuration subunit to output a valid debug prohibition signal to the CPU unit to prohibit the CPU unit from debugging the secure program area.

[0023] When the CPU unit accesses the secure data area through the permission management unit, the permission management unit outputs an access address identifying the access to the secure data area to the access control unit. The access control unit configures the configuration subunit to output a valid access prohibition signal to the permission management module to prevent the permission management unit from responding to the CPU unit's read and write access to the secure data area.

[0024] Optionally, the emulator includes an emulator debugging system and an emulator hardware system; the emulator hardware system includes the debugging interface module, the chip function debugging module, and the chip function module;

[0025] The simulator debugging system includes a secure download algorithm module and an encrypted download module, used to encrypt and download programs and data, as well as perform debugging operations on the chip;

[0026] The RAM memory of the chip functional module includes a decryption and download module, which is used to decrypt the downloaded encrypted data.

[0027] Optionally, the chip function debugging module is used for memory access control; the configuration subunit includes a debug register, and the access control unit implements secure management of debugging permissions by configuring the debug register;

[0028] The chip's functional modules also include a CPU unit, an encryption readout unit, RAM memory, and NVM memory;

[0029] The debugging interface module is connected to the simulator debugging system and the chip function debugging module, respectively; the chip function debugging module is connected to the debugging interface module, the CPU unit, the permission management unit and the encryption readout unit, respectively.

[0030] The RAM memory is connected to the permission management unit; the NVM memory is connected to the permission management unit and the encryption readout unit.

[0031] According to a second aspect of this application, a simulation method is provided, comprising:

[0032] The access control unit of the chip's functional modules generates access addresses;

[0033] The access management unit sends the access address to the access control unit of the chip function debugging module;

[0034] The access control unit configures its configuration subunit according to the access address to obtain a control signal;

[0035] The control signal is sent to the debugging interface module.

[0036] The control signal is used to control the opening and closing of the debugging path of the debugging interface module.

[0037] Optionally, the simulation method further includes:

[0038] The configuration subunit is configured through the debugging interface module to obtain the protection address range of the secure program area and the secure data area, and the switching function of the debugging interface module is enabled.

[0039] When the corresponding access address for accessing the secure program area and / or the secure data area falls within the protected address range, the configuration subunit outputs an invalid debug enable signal to the debug interface module to shut down the debug interface module.

[0040] Optionally, the simulation method further includes:

[0041] The emulator debugging system calls the encryption download module to encrypt the program and data to be downloaded, thus obtaining encrypted data;

[0042] The secure download algorithm module of the simulator debugging system sends a secure download command to the chip function debugging module through the debugging interface module; after the access control unit verifies the successful download command, it configures the configuration subunit to output a valid debugging enable signal, so that the debugging interface module is in the enabled state.

[0043] The secure download algorithm module writes the encrypted data into the RAM memory of the chip function module via the debug interface module, the chip function debug module, the CPU unit of the chip function module, and the permission management unit; the decryption download module in the RAM memory decrypts the encrypted data under the control of the CPU unit and writes the decrypted data into the NVM memory of the chip function module.

[0044] The secure download algorithm module sends a data verification command to the chip function debugging module, and the access control unit configures the configuration subunit to output a valid verification enable signal;

[0045] The secure download algorithm module reads the downloaded data from the NVM memory. The read downloaded data is encrypted by the encryption readout unit and then read out to the secure download algorithm module in sequence through the CPU unit, the chip function debugging module, and the debugging interface module. The secure download algorithm module compares the read downloaded data with the encrypted data to complete the download verification.

[0046] The simulator and simulation method according to the embodiments of this application effectively improve the security protection capability during chip simulation and debugging by controlling the opening and closing of the debugging path through the access address.

[0047] Furthermore, dynamic access control for the debugging interface module is achieved based on address recognition technology, enabling differentiated and dynamic access control for different security zones.

[0048] Furthermore, dynamic access control of the debugging interface module is achieved based on address recognition technology. The debugging register is dynamically configured according to the access address to prevent debugging in the secure program area and prevent access in the secure data area. While ensuring the simulation debugging function, efficient and dynamic security protection of chip programs and data is achieved, effectively improving the security protection capability in the chip simulation debugging process.

[0049] Furthermore, a secure download mechanism is implemented through collaboration between the emulator and the chip, ensuring the encryption of data transmission on the physical link and thus guaranteeing data security.

[0050] Furthermore, the data is encrypted by the emulator debugging module, decrypted and downloaded during program execution in RAM, and then read out and verified by the emulator hardware after encryption, ensuring that all data on the entire physical link is encrypted.

[0051] Furthermore, the safe operation includes, but is not limited to, secure downloading from NVM memory, disabling CPU debugging, and controlling the opening and closing of the debugging interface, thus balancing the implementation of simulation functions with security assurance.

[0052] Furthermore, the dynamic on / off function of the debugging interface module allows for flexible delineation of the protected area based on actual security needs. During program execution, the debugging interface is automatically and dynamically turned on or off depending on whether the access address falls within the protected area, achieving a dynamic balance between security protection and debugging convenience. Attached Figure Description

[0053] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0054] Figure 1A schematic diagram of the simulator according to Embodiment 1 of this application is shown;

[0055] Figure 2 A schematic diagram of the simulator according to Embodiment 2 of this application is shown;

[0056] Figure 3 A flowchart of a simulation method according to an embodiment of this application is shown;

[0057] Figure 4 A flowchart illustrating link data encryption and secure download according to an embodiment of this application is shown;

[0058] Figure 5 A flowchart illustrating the dynamic security protection of the debug interface module according to an embodiment of this application is shown. Detailed Implementation

[0059] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. The present application may be presented in various forms; only some examples are described below.

[0060] Figure 1 A schematic diagram of the simulator according to Embodiment 1 of this application is shown. Figure 1 As shown, the (chip) emulator according to Embodiment 1 of this application includes a debug interface module 4, a chip function debug module 5, and a chip function module 6. The chip function debug module 5 includes an access control unit (module) 9, which includes a configuration subunit (debug register) 10; the chip function module 6 includes a permission management unit (module) 12.

[0061] Specifically, the debug interface module 4 is used to enable and disable the debug path.

[0062] The chip function debugging module 5 is connected to the debugging interface module 4. The chip function debugging module 5 includes an access control unit 9, which includes a configuration subunit 10. The configuration subunit 10 is used for configuring debugging permissions.

[0063] Chip function module 6 is used for chip simulation. Chip function module 6 includes a permission management unit 12. The permission management unit 12 is connected to the access control unit 9.

[0064] The access control unit 12 generates an access address and sends it to the access control unit 9. Based on the access address, the access control unit 9 configures the configuration subunit 10 to output control signals to the debugging interface module 4. These control signals are used to control the connection and disconnection of the debugging path.

[0065] In an optional embodiment of this application, when the access address is within a preset protected address range, the corresponding control signal controls the debugging path to disconnect.

[0066] Figure 2 A schematic diagram of the simulator according to Embodiment 2 of this application is shown. Figure 2 As shown, the emulator 1 according to Embodiment 2 of this application includes an emulator debugging module (system) 2 and an emulator hardware module (system) 3. The emulator debugging module 2 includes a secure download algorithm module (unit) 7 and an encrypted download module (unit) 8. The emulator hardware module 3 includes a debug interface module 4, a chip function debugging module 5, and a chip function module 6. The chip function debugging module 5 includes an access control module (unit) 9, which includes a debug register (configuration subunit) 10. The chip function module 6 includes a CPU module (unit) 11, a permission management module (unit) 12, an encrypted read module (unit) 13, a RAM (Random Access Memory) memory 14, and an NVM (Non-Volatile Memory) memory 15. Among them, the RAM memory 14 includes a decryption download module (unit) 18, and the NVM memory 15 includes a secure program area 16 and a secure data area 17.

[0067] In the specific implementation, the simulator debugging module 2 is implemented using host computer software, the secure download algorithm module 7 is implemented using a software algorithm, and the encrypted download module 8 is implemented using a dynamic library program flow. The simulator hardware module 3 is implemented using an FPGA chip. The CPU module 11 executes the decryption download program in the RAM memory. The decryption download program calls the hardware encryption algorithm module in the chip function module 6 to complete the decryption operation of the downloaded encrypted data.

[0068] The emulator debugging module 2 includes a secure download algorithm module 7 and an encrypted download module 8, used for encrypting and downloading programs and data, as well as for debugging operations on the chip. The secure download algorithm module 7 generates download control commands, and the encrypted download module 8 encrypts the downloaded programs and data.

[0069] The debug interface module 4 is used to connect and disconnect the debug path. The emulator debug module 2 implements debug operations on the chip functional module 6 through the debug interface (debug interface module 4).

[0070] The chip function debugging module 5 is used to implement access control to the memory (RAM memory 14 and / or NVM memory 15). The chip function debugging module 5 includes an access control module 9, which includes a debug register 10. The access control module 9 implements secure management of debugging permissions by configuring the debug register 10.

[0071] The chip functional module 6 includes a CPU module 11, a permission management module 12, an encryption readout module 13, a RAM memory 14, and an NVM memory 15, which are used to implement the chip's functional simulation.

[0072] The debugging interface module 4 is connected to the emulator debugging module 2 and the chip function debugging module 5, respectively. The chip function debugging module 5 is connected to the debugging interface module 4, the CPU module 11, the access control module 12, and the encryption readout module 13, respectively. The RAM memory 14 is connected to the access control module 12; the NVM memory 15 is connected to the access control module 12 and the encryption readout module 13.

[0073] CPU module 11 accesses NVM memory 15 and RAM memory 14 through permission management module 12, and can also directly read data in NVM memory 15 through encryption read module 13.

[0074] Optionally, when the CPU module 11 accesses the NVM memory 15 through the access management module 12, the access management module 12 generates an access address and outputs it to the access control module 9. The access control module 9 configures the control signal output by the debug register 10 based on the access address generated by the access management module 12. The control signal is used to disable debug access from the debug interface module 4 to the CPU module 11, and to disable read / write access to the NVM memory 15.

[0075] Optionally, when the CPU module 11 directly accesses the NVM memory 15 through the encryption read module 13, the secure download algorithm module 7 sends a command to the chip function debugging module 5. The access control module 9 in the chip function debugging module 5 configures the debug register 10 to output a valid verification enable signal. When the verification enable signal is valid, the data in the NVM memory 15 is encrypted by the encryption read module 13 and then read out, realizing the function of reading downloaded data from the NVM memory 15 for verification. When the verification enable signal is invalid, data in the NVM memory 15 cannot be read or written.

[0076] In an optional embodiment of this application, the control signals output by the debug register 10 in the access control module 9 include, but are not limited to, at least one of the following: debug enable signal, access denied signal, verification enable signal, and debug denied signal.

[0077] The debug enable signal is output to debug interface module 4 to control the opening and closing of the debug interface.

[0078] An access-prohibited signal is output to the access control module 12 to prevent the CPU module 11 from accessing the NVM memory 15 through the access control module 12. When the CPU module 11 accesses the NVM memory 15, the access control module 12 determines whether the NVM memory 15 can be accessed based on the state of the access-prohibited signal.

[0079] The verification enable signal is output to the encryption read module 13 to enable encryption of the data read from the NVM memory 15. The CPU module 11 reads the data from the NVM memory 15. When the verification enable signal is valid, the data is encrypted by the encryption read module 13 before being read out.

[0080] The debug signal is disabled to be output to CPU module 11, which is used to disable the debug function of CPU module 11. The debug function includes, but is not limited to, at least one of the debug operations such as single-stepping, breakpointing, and stopping the program.

[0081] Optionally, the encryption read-out module 13 in chip functional module 6 is used to encrypt data read from NVM memory 15. RAM memory 14 includes a decryption download module 18, which is used to decrypt the downloaded encrypted data.

[0082] Optionally, the NVM memory 15 includes a secure program area 16 and a secure data area 17. The CPU module 11 accesses the secure program area 16 and secure data area 17 in the NVM memory 15 through the encryption read module 13 or the access control module 12.

[0083] In an optional embodiment of this application, the emulator debugging module 2 configures the debugging register 10 through the debugging interface module 4. The specific operations include: configuring the protection address range of the secure program area 16 and the secure data area 17, and enabling the dynamic switching function of the debugging enable signal; the secure program area 16 and the secure data area 17 implement program and data protection for the specified area by configuring the protection address range, and the area outside the protection address range of the secure program area 16 and the secure data area 17 is unprotected and allowed to be read and written.

[0084] The simulator in this application implements functions to prevent debugging of the secure program area and to prevent access to the secure data area:

[0085] When CPU module 11 accesses the secure program area 16 through access management module 12, access management module 12 outputs the access address identifying the secure program area to access control module 9. If the access address is within the protected address range of secure program area 16, access control module 9 configures debug register 10 to output a valid debug disable signal to CPU module 11, prohibiting CPU module 11 from debugging secure program area 16.

[0086] When CPU module 11 accesses secure data area 17 through access management module 12, access management module 12 outputs the access address identifying the secure data area to access control module 9. If the access address is within the protected address range of secure data area 17, access control module 9 configures debug register 10 to output a valid access denied signal to access management module 12, thereby preventing access management module 12 from responding to read and write access to secure data area 17 by CPU module 11.

[0087] Figure 3 A flowchart illustrating a simulation method according to an embodiment of this application is shown. Figure 3 As shown, the simulation method according to an embodiment of this application includes the following steps:

[0088] In step S101, the permission management unit of the chip functional module generates an access address;

[0089] In step S102, the access management unit sends the access address to the access control unit of the chip function debugging module;

[0090] In step S103, the access control unit configures the configuration subunit of the access control unit according to the access address to obtain the control signal;

[0091] In step S104, the control signal is sent to the debugging interface module, wherein the control signal is used to control the connection and disconnection of the debugging path of the debugging interface module.

[0092] In an optional embodiment of this application, the simulation method further includes:

[0093] The configuration subunit is configured through the debugging interface module to obtain the protection address range of the secure program area and the secure data area, and the switching function of the debugging interface module is enabled.

[0094] When the corresponding access address for accessing the secure program area and / or the secure data area falls within the protected address range, the configuration subunit outputs an invalid debug enable signal to the debug interface module to shut down the debug interface module.

[0095] In an optional embodiment of this application, the simulation method further includes:

[0096] The emulator debugging system calls the encryption download module to encrypt the program and data to be downloaded, thus obtaining encrypted data;

[0097] The secure download algorithm module of the simulator debugging system sends a secure download command to the chip function debugging module through the debugging interface module; after the access control unit verifies the successful download command, it configures the configuration subunit to output a valid debugging enable signal, so that the debugging interface module is in the enabled state.

[0098] The secure download algorithm module writes the encrypted data into the RAM memory of the chip function module via the debug interface module, the chip function debug module, the CPU unit of the chip function module, and the permission management unit; the decryption download module in the RAM memory decrypts the encrypted data under the control of the CPU unit and writes the decrypted data into the NVM memory of the chip function module.

[0099] The secure download algorithm module sends a data verification command to the chip function debugging module, and the access control unit configures the configuration subunit to output a valid verification enable signal;

[0100] The secure download algorithm module reads the downloaded data from the NVM memory. The read downloaded data is encrypted by the encryption readout unit and then read out to the secure download algorithm module in sequence through the CPU unit, the chip function debugging module, and the debugging interface module. The secure download algorithm module compares the read downloaded data with the encrypted data to complete the download verification.

[0101] Figure 4 A flowchart illustrating link data encryption and secure download according to an embodiment of this application is shown. Figure 4 As shown, the method for encrypting and securely downloading link data applied to the simulator of this application implements the functions of encrypting and securely downloading link data, including the following operation steps:

[0102] In step S201, the downloaded program data is encrypted;

[0103] The downloaded program data is encrypted. The emulator debugging module calls the encryption download module to encrypt the program and data to be downloaded, and obtain encrypted data.

[0104] In step S202, the debug interface is authenticated and enabled;

[0105] After authenticating and enabling the debug interface, the secure download algorithm module sends a secure download command to the chip function debug module through the debug interface module. After the access control module verifies the successful download command, it configures the debug register to output a valid debug enable signal, keeping the debug interface module in the enabled state.

[0106] In step S203, the encrypted data is first written to RAM, then decrypted and written to NVM;

[0107] Encrypted data is first written to RAM, then decrypted and written to NVM. The secure download algorithm module writes the encrypted data to RAM memory through the debugging interface module, chip function debugging module, CPU module, and permission management module. The decryption download module in RAM memory decrypts the encrypted data under the control of the CPU module and writes the decrypted data to NVM memory.

[0108] In step S204, a valid verification enable signal is output;

[0109] The secure download algorithm module sends a data verification command to the chip function debugging module by outputting a valid verification enable signal. The access control module in the chip function debugging module configures the debug register to output a valid verification enable signal.

[0110] In step S205, the data is read from the NVM, encrypted, and then transmitted and verified.

[0111] The secure download algorithm module reads the downloaded data from the NVM memory, encrypts it, and then transmits and verifies it. The read data is then encrypted by the encryption reading module and sequentially read through the CPU module, chip function debugging module, and debugging interface module to the secure download algorithm module in the emulator debugging module. The secure download algorithm module compares the read data with the encrypted data to complete the download verification.

[0112] Figure 5 A flowchart illustrating the dynamic security protection of the debug interface module according to an embodiment of this application is shown. After the emulator completes the download of the secure program area and secure data area and configures the protected address range for the debug register, the debug interface module dynamically performs on / off operations based on the configuration of the debug register when the CPU module executes the program. Figure 5 As shown, the simulator performs the following steps to switch the debug interface module on and off, thereby implementing dynamic security protection for the secure program area and secure data area:

[0113] In step S301, dynamic protection is enabled for the protection address range;

[0114] Configure the protected address range and enable dynamic protection. The emulator debugging module configures the debugging register through the debugging interface module. The configuration content is the protected address range of the safe program area and the safe data area, and the dynamic on / off function of the debugging interface module is enabled.

[0115] In step S302, the debug interface module is dynamically switched on and off when the CPU program executes the program.

[0116] When the CPU program executes the program, the debug interface module is dynamically switched on and off. The CPU module accesses the secure program area and secure data area. When the access address falls within the protected address range, the debug register outputs an invalid debug enable signal, disabling the debug interface module to achieve dynamic protection. When the access address is outside the protected address range, the debug register outputs a valid debug enable signal. At this time, the debug interface module is in the enabled state, supporting normal debugging operations. In this case, the address areas corresponding to the secure program area and secure data area are not protected.

[0117] The emulator and simulation method provided in this application implement dynamic debugging permission control based on address identification. According to the address range configuration in the access control module, it achieves dynamic security protection for designated areas in the secure program area and secure data area: during program execution, it dynamically disables debugging in the secure program area and dynamically disables access in the secure data area. The emulator implements a higher level of protection, supporting dynamic on / off operations of the debugging interface module. Simultaneously, it achieves dynamic permission control of the debugging interface based on address identification technology, enabling dynamic configuration of the debugging register according to the access address, thus achieving differentiated and dynamic permission control for different security areas. Furthermore, it supports dynamic on / off operations of the debugging interface module, further enhancing the flexibility of security protection. This application also implements a secure download mechanism through the collaborative cooperation of the emulator and the chip, ensuring the encryption of data transmission on the physical link and effectively preventing the risk of data being intercepted and cracked during the download process.

[0118] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A simulator, comprising: A debugging interface module, which is used to enable and disable the debugging path; A chip function debugging module is connected to the debugging interface module; the chip function debugging module includes an access control unit, which includes a configuration subunit for configuring debugging permissions. as well as A chip functional module, used for chip simulation; the chip functional module includes a permission management unit, which is connected to the access control unit. The access management unit generates an access address and sends the access address to the access control unit; the access control unit configures the configuration subunit according to the access address to output control signals to the debugging interface module. The control signal is used to control the on and off of the debugging path.

2. The simulator according to claim 1, wherein, When the access address is within a preset protected address range, the corresponding control signal controls the debugging path to disconnect.

3. The simulator according to claim 1, wherein, The configuration subunit is also connected to the CPU unit and / or encryption readout unit of the chip functional module; The control signal includes at least one selected from the following signals: A debug enable signal is output to the debug interface module to control the opening and closing of the debug interface. Access Denied Signal, which is output to the permission management unit to prevent the CPU unit from accessing the memory of the chip functional module through the permission management unit; A verification enable signal is output to the encryption readout unit to enable encryption of the data read from the memory; A debug disable signal is output to the CPU unit to disable the debugging function of the CPU unit.

4. The simulator according to claim 1, wherein, The chip functional module further includes a CPU unit and a memory; the CPU unit is connected to the permission management unit; the memory is connected to the permission management unit. When the CPU unit accesses the memory through the permission management unit, the permission management unit generates a corresponding access address. The control signals are used to allow or disable the debug interface module's debug access to the CPU unit, and to allow or disable read / write access to the memory.

5. The simulator according to claim 4, wherein, The memory includes a secure program area and a secure data area; When the CPU unit accesses the secure program area through the permission management unit, the permission management unit outputs an access address that identifies the access to the secure program area to the access control unit. The access control unit configures the configuration subunit to output a valid debug-prohibit signal to the CPU unit to prevent the CPU unit from debugging the secure program area. When the CPU unit accesses the secure data area through the permission management unit, the permission management unit outputs an access address identifying the access to the secure data area to the access control unit. The access control unit configures the configuration subunit to output a valid access prohibition signal to the permission management module to prevent the permission management unit from responding to the CPU unit's read and write access to the secure data area.

6. The simulator according to claim 1, wherein, The simulator includes a simulator debugging system and a simulator hardware system; the simulator hardware system includes the debugging interface module, the chip function debugging module, and the chip function module; The simulator debugging system includes a secure download algorithm module and an encrypted download module, used to encrypt and download programs and data, as well as perform debugging operations on the chip; The RAM memory of the chip functional module includes a decryption and download module, which is used to decrypt downloaded encrypted data.

7. The simulator according to claim 1, wherein, The chip function debugging module is used for memory access control; the configuration subunit includes a debugging register, and the access control unit implements secure management of debugging permissions by configuring the debugging register; The chip's functional modules also include a CPU unit, an encryption readout unit, RAM memory, and NVM memory; The debugging interface module is connected to the simulator debugging system and the chip function debugging module, respectively; the chip function debugging module is connected to the debugging interface module, the CPU unit, the permission management unit and the encryption readout unit, respectively. The RAM memory is connected to the permission management unit; the NVM memory is connected to the permission management unit and the encryption readout unit.

8. A simulation method, comprising: The access control unit of the chip's functional modules generates access addresses; The access management unit sends the access address to the access control unit of the chip function debugging module; The access control unit configures its configuration subunit according to the access address to obtain a control signal; The control signal is sent to the debugging interface module. The control signal is used to control the opening and closing of the debugging path of the debugging interface module.

9. The simulation method according to claim 8, wherein, The simulation method further includes: The configuration subunit is configured through the debugging interface module to obtain the protection address range of the secure program area and the secure data area, and the switching function of the debugging interface module is enabled. When the corresponding access address for accessing the secure program area and / or the secure data area falls within the protected address range, the configuration subunit outputs an invalid debug enable signal to the debug interface module to shut down the debug interface module.

10. The simulation method according to claim 8, wherein, The simulation method further includes: The emulator debugging system calls the encryption download module to encrypt the program and data to be downloaded, thus obtaining encrypted data; The secure download algorithm module of the simulator debugging system sends a secure download command to the chip function debugging module through the debugging interface module; after the access control unit verifies the successful download command, it configures the configuration subunit to output a valid debugging enable signal, so that the debugging interface module is in the enabled state. The secure download algorithm module writes the encrypted data into the RAM memory of the chip function module via the debug interface module, the chip function debug module, the CPU unit of the chip function module, and the permission management unit; the decryption download module in the RAM memory decrypts the encrypted data under the control of the CPU unit and writes the decrypted data into the NVM memory of the chip function module. The secure download algorithm module sends a data verification command to the chip function debugging module, and the access control unit configures the configuration subunit to output a valid verification enable signal; The secure download algorithm module reads the downloaded data from the NVM memory. The read downloaded data is encrypted by the encryption readout unit and then read out to the secure download algorithm module in sequence through the CPU unit, the chip function debugging module, and the debugging interface module. The secure download algorithm module compares the read downloaded data with the encrypted data to complete the download verification.

Images