A security chip, data encryption and decryption method, and digital signature and verification method
Patent Information
- Application Number
- CN202611103451.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-23
- Publication Date
- 2026-10-16
AI Technical Summary
[0003]目前，安全芯片的实现方式包括两类：一类是使用纯软件方案实现芯片的安全启动和信息安全，这类方案由于是纯软件方案，存在被攻破的风险；另一类是纯硬件方案，这类方案芯片的面积大、成本高，且灵活性差，导致后期无法拓展
[0045] Compared with existing technologies, the security chip, data encryption/decryption method, and digital signature/verification method provided by this invention have the following advantages:
Smart Images
Figure CN122926465A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to security chips, specifically to a security chip, a data encryption / decryption method, and a digital signature and verification method. Background Technology
[0002] In the entire chip system, the role of the security chip is to first enable the system to boot securely, and then, during normal system operation, encrypt and decrypt sensitive data to ensure information security. Therefore, the security chip is crucial to the entire system.
[0003] Currently, security chips are implemented in two ways: one is to use a pure software solution to achieve secure boot and information security, which is vulnerable to being compromised; the other is a pure hardware solution, which results in large chip size, high cost, and poor flexibility, making it difficult to expand in the future. Summary of the Invention
[0004] (a) Technical problems to be solved
[0005] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a security chip, a data encryption and decryption method, and a digital signature and verification method, which can effectively overcome the defects of the existing technology in that it is difficult to balance security and scalability.
[0006] (II) Technical Solution
[0007] To achieve the above objectives, the present invention provides the following technical solution:
[0008] A security chip includes the following functional units:
[0009] The processor includes a coprocessor, a processor core, and an interrupt handling unit. The coprocessor is used to extend the functionality of the processor and stores the finite field operation unit, inversion unit, and multiplier required for elliptic curve algorithms to accelerate elliptic curve operations. The processor core contains an instruction storage unit and a data storage unit.
[0010] Direct Memory Access Unit (DMA) allows data to be moved in and out of the security chip via symmetric / asymmetric cryptographic algorithms when data needs to be processed, reducing processor load.
[0011] The symmetric encryption / decryption unit uses a symmetric cryptographic algorithm to encrypt and decrypt data.
[0012] The true random number unit uses an oscillating ring to generate true random numbers.
[0013] Shared storage unit stores register configuration parameters, hash data, and keys for the elliptic curve algorithm;
[0014] The mailbox unit is used for inter-core communication when the external main CPU needs to communicate with the security chip.
[0015] Preferably, it also includes an internal AHB bus network, an ICB to AHBL adapter bridge, and an AHBL to APB adapter bridge;
[0016] The internal AHB bus network enables communication between the processor and various units, as well as between units.
[0017] The ICB to AHBL adapter bridge enables protocol conversion, timing adaptation, and data transfer between the ICB bus and the AHBL bus, facilitating communication between the processor and various units.
[0018] The AHBL to APB converter bridge enables protocol conversion, timing adaptation, and data transfer between the AHBL bus and the APB bus, facilitating communication between the processor and the mailbox unit.
[0019] Preferably, the security chip supports data encryption and decryption using symmetric cryptographic algorithms based on AES / DES / 3-DES / SM4, data compression using one-way hash functions based on SHA-1 / SHA-2 / SHA-3 / SM3, and data signing and verification using asymmetric cryptographic algorithms based on ECC / ECDH / ECDSA / SM2.
[0020] Among them, the functional modules required for the operation of the symmetric cryptographic algorithms AES / DES / 3-DES / SM4 are designed with full hardening to accelerate the operation, and the mode of running AES / DES / 3-DES / SM4 is determined by software scheduling.
[0021] The functional modules required for the operation of the one-way hash functions SHA-1 / SHA-2 / SHA-3 / SM3 are also fully hardened to accelerate computation.
[0022] The elliptic curve algorithms ECC / ECDH / ECDSA / SM2 in asymmetric cryptography have the following operational hierarchy from low to high: finite field arithmetic, elliptic curve point addition and doubling, point multiplication, and protocol. The functional modules required for finite field operations, inversion operations, and multiplication operations in elliptic curve algorithms ECC / ECDH / ECDSA / SM2 are also fully hardened to accelerate the operation, while the protocol layer is implemented in software.
[0023] A data encryption / decryption method includes the following steps:
[0024] S11. The external main CPU writes the register configuration parameters required by the Direct Memory Access Unit (DMA), Symmetric Encryption / Decryption Unit, and True Random Number Unit into the shared memory unit.
[0025] S12. The external main CPU starts the processor through the mailbox unit in the inter-core communication mode. The processor writes the corresponding register configuration parameters into the direct memory access unit (DMA), symmetric encryption / decryption unit, and true random number unit through the peripheral interface and internal AHB bus network, respectively.
[0026] S13. The Direct Memory Access (DMA) unit reads the data to be encrypted or decrypted through the external read data interface and the external AHB bus network according to the configuration parameters, and then writes the data to be encrypted or decrypted into the symmetric encryption / decryption unit through the internal write data interface and the internal AHB bus network.
[0027] S14. The symmetric encryption / decryption unit performs encryption / decryption operations on the data that needs to be encrypted / decrypted.
[0028] S15. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network.
[0029] S16. The processor informs the external main CPU that the data encryption / decryption is complete via inter-core communication through the mailbox unit.
[0030] A digital signature method includes the following steps:
[0031] S21. The external main CPU writes the register configuration parameters required by the coprocessor, direct memory access unit (DMA), and true random number unit into the shared memory unit.
[0032] S22. The external main CPU starts the processor through the mailbox unit in the inter-core communication mode. The processor writes the corresponding register configuration parameters to the coprocessor, direct memory access unit (DMA), and true random number unit through the peripheral interface and internal AHB bus network, respectively.
[0033] S23. The Direct Memory Access Unit (DMA) reads the data that needs to be signed through the external read data interface and the external AHB bus network according to the configuration parameters, and then transmits it to the internal AHB bus network through the internal write data interface.
[0034] S24. The processor reads the data that needs to be signed through the peripheral interface and the internal AHB bus network, and the coprocessor performs the signing operation.
[0035] S25. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network.
[0036] S26. The processor informs the external main CPU that the data signature is complete via inter-core communication through the mailbox unit.
[0037] A digital signature verification method includes the following steps:
[0038] S31. The external main CPU writes the register configuration parameters required by the coprocessor, direct memory access unit (DMA), and true random number unit into the shared memory unit.
[0039] S32. The external main CPU starts the processor via inter-core communication through the mailbox unit. The processor writes the corresponding register configuration parameters to the coprocessor, direct memory access unit (DMA), and true random number unit through the peripheral interface and internal AHB bus network, respectively.
[0040] S33. The Direct Memory Access (DMA) unit reads the data to be verified through the external read data interface and the external AHB bus network according to the configuration parameters, and then transmits it to the internal AHB bus network through the internal write data interface.
[0041] S34. The processor reads the data that needs to be verified through the peripheral interface and the internal AHB bus network, and the coprocessor performs the verification operation.
[0042] S35. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network.
[0043] S36. The processor informs the external main CPU that the data verification is complete via inter-core communication through the mailbox unit.
[0044] (III) Beneficial Effects
[0045] Compared with existing technologies, the security chip, data encryption / decryption method, and digital signature / verification method provided by this invention have the following advantages:
[0046] 1) Adopting a modular design based on the combination of hardware and software, the symmetric cryptography operation is accelerated by hardening the symmetric encryption and decryption unit, and the asymmetric cryptography operation is accelerated by hardening the finite field operation unit, the inversion unit and the multiplier by separating the operation level of the elliptic curve algorithm.
[0047] 2) To address the frequent scheduling required by asymmetric cryptographic algorithms, the finite field operation unit, inversion unit, and multiplier are stored in the coprocessor to accelerate asymmetric cryptographic operations.
[0048] 3) Hardware area was reduced through a combination of hardware and software design. Logic synthesis, based on the GF22nm process library, resulted in a 30% reduction in hardware area.
[0049] 4) The design approach, which combines hardware and software, achieves flexibility and scalability. If new algorithms need to be introduced later, they can be upgraded through software.
[0050] 5) Generating true random numbers using an oscillating ring ensures the unpredictability of random numbers and guarantees the security of key data generated based on random numbers. Attached Figure Description
[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0052] Figure 1 This is a system architecture diagram of the security chip in this invention;
[0053] Figure 2 This is a flowchart illustrating the data encryption / decryption method in this invention;
[0054] Figure 3 This is a schematic diagram of the digital signature process in this invention;
[0055] Figure 4 This is a schematic diagram of the digital signature verification process in this invention;
[0056] Figure 5 This is a schematic diagram of the operational hierarchy of the elliptic curve algorithm in the asymmetric cryptography algorithm of this invention. Detailed Implementation
[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0058] The specific architecture of the security chip provided by this invention is described below with specific examples (e.g.) Figure 1 (as shown) and technical effects.
[0059] The security chip includes the following functional units:
[0060] The processor (using E203, an open-source RISC-V processor) includes a coprocessor, a processor core, and an interrupt handling unit. The coprocessor is used to extend the functionality of the processor and stores the finite field operation unit, inversion unit, and multiplier required for elliptic curve algorithms to accelerate elliptic curve operations. The processor core contains instruction storage unit and data storage unit.
[0061] Direct Memory Access Unit (DMA) allows data to be moved in and out of the security chip via symmetric / asymmetric cryptographic algorithms when data needs to be processed, reducing processor load.
[0062] The symmetric encryption / decryption unit uses a symmetric cryptographic algorithm to encrypt and decrypt data.
[0063] The true random number unit uses an oscillating ring to generate true random numbers.
[0064] Shared storage unit stores register configuration parameters, hash data, and keys for the elliptic curve algorithm;
[0065] The mailbox unit is used for inter-core communication when the external main CPU needs to communicate with the security chip.
[0066] The security chip also includes an internal AHB bus network, an ICB to AHBL adapter bridge, and an AHBL to APB adapter bridge;
[0067] The internal AHB bus network enables communication between the processor and various units, as well as between units.
[0068] The ICB to AHBL adapter bridge enables protocol conversion, timing adaptation, and data transfer between the ICB bus and the AHBL bus, facilitating communication between the processor and various units.
[0069] The AHBL to APB converter bridge enables protocol conversion, timing adaptation, and data transfer between the AHBL bus and the APB bus, facilitating communication between the processor and the mailbox unit.
[0070] In the technical solution of this application, the security chip supports data encryption and decryption based on symmetric cryptographic algorithms such as AES / DES / 3-DES / SM4, data compression based on one-way hash functions such as SHA-1 / SHA-2 / SHA-3 / SM3, and data signing and verification based on asymmetric cryptographic algorithms such as ECC / ECDH / ECDSA / SM2.
[0071] Among them, the functional modules required for the operation of the symmetric cryptographic algorithms AES / DES / 3-DES / SM4 are fully hardened to accelerate the operation, and the mode of operation under AES / DES / 3-DES / SM4 (such as the CFB mode of AES) is determined by software scheduling.
[0072] The functional modules required for the operation of the one-way hash functions SHA-1 / SHA-2 / SHA-3 / SM3 are also fully hardened to accelerate computation.
[0073] The operational hierarchy of elliptic curve cryptography algorithms ECC / ECDH / ECDSA / SM2, from lowest to highest, is: finite field arithmetic, elliptic curve point addition and doubling, point multiplication, and protocols (such as...). Figure 5 As shown in the figure, the functional modules required for the elliptic curve algorithms ECC / ECDH / ECDSA / SM2 in asymmetric cryptography to perform finite field operations, inversion operations, and multiplication operations are also fully hardened to accelerate the operation, and the protocol layer is implemented in software.
[0074] Based on the security chip disclosed above, this invention also discloses a data encryption and decryption method, such as... Figure 2 As shown, it includes the following steps:
[0075] S11. The external main CPU writes the register configuration parameters required by the Direct Memory Access Unit (DMA), Symmetric Encryption / Decryption Unit, and True Random Number Unit into the shared memory unit.
[0076] S12. The external main CPU starts the processor through the mailbox unit in the inter-core communication mode. The processor writes the corresponding register configuration parameters into the direct memory access unit (DMA), symmetric encryption / decryption unit, and true random number unit through the peripheral interface and internal AHB bus network, respectively.
[0077] S13. The Direct Memory Access (DMA) unit reads the data to be encrypted or decrypted through the external read data interface and the external AHB bus network according to the configuration parameters, and then writes the data to be encrypted or decrypted into the symmetric encryption / decryption unit through the internal write data interface and the internal AHB bus network.
[0078] S14. The symmetric encryption / decryption unit performs encryption / decryption operations on the data that needs to be encrypted / decrypted.
[0079] S15. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network.
[0080] S16. The processor informs the external main CPU that the data encryption / decryption is complete via inter-core communication through the mailbox unit.
[0081] Based on the security chip disclosed above, this invention also discloses a digital signature method, such as... Figure 3 As shown, it includes the following steps:
[0082] S21. The external main CPU writes the register configuration parameters required by the coprocessor, direct memory access unit (DMA), and true random number unit into the shared memory unit.
[0083] S22. The external main CPU starts the processor through the mailbox unit in the inter-core communication mode. The processor writes the corresponding register configuration parameters to the coprocessor, direct memory access unit (DMA), and true random number unit through the peripheral interface and internal AHB bus network, respectively.
[0084] S23. The Direct Memory Access Unit (DMA) reads the data that needs to be signed through the external read data interface and the external AHB bus network according to the configuration parameters, and then transmits it to the internal AHB bus network through the internal write data interface.
[0085] S24. The processor reads the data that needs to be signed through the peripheral interface and the internal AHB bus network, and the coprocessor performs the signing operation.
[0086] S25. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network.
[0087] S26. The processor informs the external main CPU that the data signature is complete via inter-core communication through the mailbox unit.
[0088] Based on the security chip disclosed above, this invention also discloses a digital signature verification method, such as... Figure 4 As shown, it includes the following steps:
[0089] S31. The external main CPU writes the register configuration parameters required by the coprocessor, direct memory access unit (DMA), and true random number unit into the shared memory unit.
[0090] S32. The external main CPU starts the processor via inter-core communication through the mailbox unit. The processor writes the corresponding register configuration parameters to the coprocessor, direct memory access unit (DMA), and true random number unit through the peripheral interface and internal AHB bus network, respectively.
[0091] S33. The Direct Memory Access (DMA) unit reads the data to be verified through the external read data interface and the external AHB bus network according to the configuration parameters, and then transmits it to the internal AHB bus network through the internal write data interface.
[0092] S34. The processor reads the data that needs to be verified through the peripheral interface and the internal AHB bus network, and the coprocessor performs the verification operation.
[0093] S35. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network.
[0094] S36. The processor informs the external main CPU that the data verification is complete via inter-core communication through the mailbox unit.
[0095] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A security chip, characterized in that: It includes the following functional units: The processor includes a coprocessor, a processor core, and an interrupt handling unit. The coprocessor is used to extend the functionality of the processor and stores the finite field operation unit, inversion unit, and multiplier required for elliptic curve algorithms to accelerate elliptic curve operations. The processor core contains an instruction storage unit and a data storage unit. Direct Memory Access Unit (DMA) allows data to be moved in and out of the security chip via symmetric / asymmetric cryptographic algorithms when data needs to be processed, reducing processor load. The symmetric encryption / decryption unit uses a symmetric cryptographic algorithm to encrypt and decrypt data. The true random number unit uses an oscillating ring to generate true random numbers. Shared storage unit stores register configuration parameters, hash data, and keys for the elliptic curve algorithm; The mailbox unit is used for inter-core communication when the external main CPU needs to communicate with the security chip.
2. The security chip according to claim 1, characterized in that: It also includes an internal AHB bus network, an ICB to AHBL adapter bridge, and an AHBL to APB adapter bridge; The internal AHB bus network enables communication between the processor and various units, as well as between units. The ICB to AHBL adapter bridge enables protocol conversion, timing adaptation, and data transfer between the ICB bus and the AHBL bus, facilitating communication between the processor and various units. The AHBL to APB converter bridge enables protocol conversion, timing adaptation, and data transfer between the AHBL bus and the APB bus, facilitating communication between the processor and the mailbox unit.
3. The security chip according to claim 2, characterized in that: The security chip supports data encryption and decryption using symmetric cryptographic algorithms based on AES / DES / 3-DES / SM4, data compression using one-way hash functions based on SHA-1 / SHA-2 / SHA-3 / SM3, and data signing and verification using asymmetric cryptographic algorithms based on ECC / ECDH / ECDSA / SM2. Among them, the functional modules required for the operation of the symmetric cryptographic algorithms AES / DES / 3-DES / SM4 are designed with full hardening to accelerate the operation, and the mode of running AES / DES / 3-DES / SM4 is determined by software scheduling. The functional modules required for the operation of the one-way hash functions SHA-1 / SHA-2 / SHA-3 / SM3 are also fully hardened to accelerate computation. The elliptic curve algorithms ECC / ECDH / ECDSA / SM2 in asymmetric cryptography have the following operational hierarchy from low to high: finite field arithmetic, elliptic curve point addition and doubling, point multiplication, and protocol. The functional modules required for finite field operations, inversion operations, and multiplication operations in elliptic curve algorithms ECC / ECDH / ECDSA / SM2 are also fully hardened to accelerate the operation, while the protocol layer is implemented in software.
4. A data encryption / decryption method, applicable to the security chip of claim 3, characterized in that: Includes the following steps: S11. The external main CPU writes the register configuration parameters required by the Direct Memory Access Unit (DMA), Symmetric Encryption / Decryption Unit, and True Random Number Unit into the shared memory unit. S12. The external main CPU starts the processor through the mailbox unit in the inter-core communication mode. The processor writes the corresponding register configuration parameters into the direct memory access unit (DMA), symmetric encryption / decryption unit, and true random number unit through the peripheral interface and internal AHB bus network, respectively. S13. The Direct Memory Access (DMA) unit reads the data to be encrypted or decrypted through the external read data interface and the external AHB bus network according to the configuration parameters, and then writes the data to be encrypted or decrypted into the symmetric encryption / decryption unit through the internal write data interface and the internal AHB bus network. S14. The symmetric encryption / decryption unit performs encryption / decryption operations on the data that needs to be encrypted / decrypted. S15. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network. S16. The processor informs the external main CPU that the data encryption / decryption is complete via inter-core communication through the mailbox unit.
5. A digital signature method, applicable to the security chip of claim 3, characterized in that: Includes the following steps: S21. The external main CPU writes the register configuration parameters required by the coprocessor, direct memory access unit (DMA), and true random number unit into the shared memory unit. S22. The external main CPU starts the processor through the mailbox unit in the inter-core communication mode. The processor writes the corresponding register configuration parameters to the coprocessor, direct memory access unit (DMA), and true random number unit through the peripheral interface and internal AHB bus network, respectively. S23. The Direct Memory Access Unit (DMA) reads the data that needs to be signed through the external read data interface and the external AHB bus network according to the configuration parameters, and then transmits it to the internal AHB bus network through the internal write data interface. S24. The processor reads the data that needs to be signed through the peripheral interface and the internal AHB bus network, and the coprocessor performs the signing operation. S25. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network. S26. The processor informs the external main CPU that the data signature is complete via inter-core communication through the mailbox unit.
6. A digital signature verification method, applicable to the security chip of claim 3, characterized in that: Includes the following steps: S31. The external main CPU writes the register configuration parameters required by the coprocessor, direct memory access unit (DMA), and true random number unit into the shared memory unit. S32. The external main CPU starts the processor via inter-core communication through the mailbox unit. The processor writes the corresponding register configuration parameters to the coprocessor, direct memory access unit (DMA), and true random number unit through the peripheral interface and internal AHB bus network, respectively. S33. The Direct Memory Access (DMA) unit reads the data to be verified through the external read data interface and the external AHB bus network according to the configuration parameters, and then transmits it to the internal AHB bus network through the internal write data interface. S34. The processor reads the data that needs to be verified through the peripheral interface and the internal AHB bus network, and the coprocessor performs the verification operation. S35. The Direct Memory Access (DMA) unit reads the processed data through the internal read data interface and the internal AHB bus network, and then writes the processed data to the external storage space through the external write data interface and the external AHB bus network. S36. The processor informs the external main CPU that the data verification is complete via inter-core communication through the mailbox unit.