Anti-burn write control method for FPGA built-in eFUSE unit
Patent Information
- Application Number
- CN202611064852.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-17
- Publication Date
- 2026-10-16
AI Technical Summary
由于eFUSE烧写过程具有不可逆性和一次性特征，一旦烧写失败或中断，易导致数据写入不完整或错误，致使整个芯片的功能异常或报废，影响芯片良率
本申请公开了一种FPGA内置eFUSE单元的抗误烧写控制方法，该方法在对eFUSE单元烧写之前，首先FPGA通过内部的配置下载控制逻辑下载测试位流进行测试，并将各待修调项的测试值输出至测试引脚，然后根据各待修调项的测试值与目标值的偏差确定目标烧写码点，经由eFUSE控制逻辑对eFUSE单元进行烧写。该方法在烧写eFUSE单元之前加入测试校准流程来确定最终的目标烧写码点，可以实现对FPGA内部eFUSE单元的精准烧写，从而避免误烧写，有利于提高FPGA参数一致性且有利于提升量产良率。
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Figure CN122926513A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of FPGA technology, and in particular to a method for preventing accidental programming of an FPGA built-in eFUSE unit. Background Technology
[0002] As the integration and complexity of FPGA chips continue to increase, the demands for chip configuration, secure key storage, and circuit redundancy repair are becoming increasingly critical. eFUSE (electronic fuse) modules, as one-time programmable non-volatile memory units, have been widely used in FPGA chips due to their advantages such as compatibility with standard CMOS processes, small footprint, low programming voltage, and support for post-package field configuration. They are used to implement core functions such as power-on boot, device configuration, redundancy replacement, AES encryption key programming, and protection against physical attacks.
[0003] The eFUSE programming process is based on the electromigration effect. By applying a programming current, the fuse resistor changes from a low-resistance state to a high-resistance state, thereby permanently writing data. Because the eFUSE programming process is irreversible and one-time, if the programming fails or is interrupted, it can easily lead to incomplete or incorrect data writing, causing the entire chip to malfunction or become unusable, affecting chip yield. Summary of the Invention
[0004] To address the aforementioned problems and technical requirements, this application proposes a method for preventing accidental programming using an FPGA-embedded eFUSE unit. The technical solution of this application is as follows: A method for preventing accidental programming of an FPGA's built-in eFUSE unit, the method comprising: Before programming the eFUSE cell inside the FPGA, the FPGA downloads the test bit stream through its internal configuration download control logic for testing and outputs the test values of each item to be adjusted to the test pin. The host computer reads the test values of each item to be repaired and adjusted through the test pins of the FPGA, and determines the target programming code point based on the deviation between the test value of each item to be repaired and the target value. The host computer sends the programming instruction containing the target programming code point to the eFUSE control logic inside the FPGA; The eFUSE control logic inside the FPGA responds to the programming command and programs the eFUSE cells inside the FPGA according to the target programming code.
[0005] A further technical solution is that the anti-false burning control method also includes: The host computer updates the adjustment value corresponding to the target programming code point to the test bit stream online; The FPGA downloads the updated test bit stream through its internal configuration download control logic and retests it, and outputs the corrected test values of each item to be adjusted to the test pin. The host computer reads the correction test values of each item to be adjusted through the test pins of the FPGA, corrects the target programming code point according to the deviation between the correction test value of the item to be adjusted and the target value, and re-executes the step of updating the correction value corresponding to the target programming code point online to the test bit stream until the deviation between the correction test value of the item to be adjusted and the target value is less than the deviation threshold. Then, the programming instruction containing the target programming code point is sent to the eFUSE control logic inside the FPGA.
[0006] A further technical solution is that this anti-false burning control method also includes: After the eFUSE cell inside the FPGA is programmed, the FPGA downloads the test bit stream through the internal configuration download control logic for testing, and outputs the actual value of each item to be adjusted after being adjusted by the corresponding adjustment value in the eFUSE cell to the test pin. The host computer reads the actual value of each item to be repaired through the test pins of the FPGA, and determines that the burning meets expectations when the deviation between the actual value of the item to be repaired and the target value is less than the deviation threshold; otherwise, it determines that the burning does not meet expectations.
[0007] A further technical solution is that the eFUSE control logic inside the FPGA responds to the programming instruction and programs the eFUSE unit inside the FPGA according to the target programming code, including: The eFUSE control logic inside the FPGA responds to the programming command and simultaneously programs multiple eFUSE units inside the FPGA according to the target programming code; among them, the multiple eFUSE units integrated inside the FPGA are all connected to the eFUSE control logic.
[0008] A further technical solution is that this anti-false burning control method also includes: The eFUSE control logic simultaneously reads the write data of each eFUSE unit corresponding to the same item to be modified, and votes on multiple read data to determine the modification value of the item to be modified.
[0009] A further technical solution involves setting each programming bit in the eFUSE unit to a low level initially, then setting it to a high level after programming. The eFUSE control logic within the FPGA uses multiple readback data to vote on and determine the adjustment value of the item to be adjusted, including: The eFUSE control logic inside the FPGA performs AND logic operations on the readback data of the programming bits of multiple eFUSE cells corresponding to the same item to be adjusted to determine the adjustment value of the item to be adjusted.
[0010] A further technical solution is to ground the input control port PD of the eFUSE unit inside the FPGA so that the input control port PD is always at a low level.
[0011] A further technical solution involves the FPGA's internal eFUSE control logic responding to programming instructions and programming the FPGA's internal eFUSE units according to the target programming code. This also includes: The eFUSE control logic inside the FPGA performs format verification on the received programming command. If the format verification passes, it responds to the programming command and programs the eFUSE cell inside the FPGA according to the target programming code; otherwise, it does not respond to the programming command.
[0012] The further technical solution is that the host computer determines the target programming code point based on the deviation between the test value and the target value of each item to be repaired, including: The host computer calculates the deviation between the test value and the target value of each item to be repaired and adjusts, and determines the repair code corresponding to the deviation value by combining the repair lookup table TRIM_TABLA. It then determines the target programming code point of the programming bit of the eFUSE unit corresponding to the current item to be repaired and adjusts.
[0013] The further technical solution is that the host computer is an automated testing equipment (ATE).
[0014] The beneficial technical effects of this application are: This application discloses a method for preventing incorrect programming of FPGA-built-in eFUSE units. Before programming the eFUSE unit, the FPGA first downloads a test bitstream through its internal configuration download control logic and outputs the test values of each parameter to be adjusted to the test pin. Then, based on the deviation between the test values of each parameter and the target values, the target programming code point is determined. The eFUSE unit is then programmed via the eFUSE control logic. This method incorporates a test calibration process before programming the eFUSE unit to determine the final target programming code point, enabling accurate programming of the FPGA's internal eFUSE unit, thus avoiding incorrect programming, improving FPGA parameter consistency, and increasing mass production yield.
[0015] This method also provides an online closed-loop adjustment mechanism, which further avoids accidental programming by updating the test bitstream dynamics online. In addition, this method introduces post-programming reconfiguration verification to form a full closed-loop calibration, supports real-time verification after programming, and can detect in a timely manner when programming does not meet expectations, avoiding the risk of scrap caused by one-time programming of eFUSE.
[0016] In this application, the FPGA integrates multiple eFUSE units inside the chip. The eFUSE control logic simultaneously programs multiple eFUSE units according to the target programming code point, and determines the adjustment value after voting on the readback data of multiple eFUSE units. This ensures that even if some eFUSE units are mistakenly programmed, the chip will not fail. This control method can avoid the instability of the entire chip system caused by mistaken programming of eFUSE units.
[0017] In this application, the PD port of the eFUSE unit integrated inside the FPGA is directly connected to GND to prevent accidental programming caused by the output signal of the eFUSE control logic being in the state of PS=1 or PD=1 during power-on and power-off.
[0018] The eFUSE control logic performs verification upon receiving the programming command. Only after the verification passes will the eFUSE unit be programmed. This avoids accidental programming caused by external signal interference and further reduces the probability of accidental programming of the eFUSE unit.
[0019] This application combines multiple anti-misprogramming mechanisms, which can determine the programming instructions through the test bit stream before performing eFUSE programming during ATE mass production testing. This not only reduces the impact of one-time programming of the eFUSE unit, but also allows the eFUSE unit to record information such as chip number for traceability. This can improve the anti-misprogramming capability of the eFUSE unit inside the FPGA and help improve the FPGA mass production yield. Attached Figure Description
[0020] Figure 1 This is a flowchart of an anti-miswritten control method in one embodiment of this application.
[0021] Figure 2 This is a block diagram of anti-miswritten control in one embodiment of this application.
[0022] Figure 3 This is a functional block diagram of the eFUSE unit in an example. Figure 4 This is a schematic diagram showing the connection between the eFUSE control logic integrated inside the FPGA and multiple eFUSE units in one example. Detailed Implementation
[0023] The specific embodiments of this application will be further described below with reference to the accompanying drawings.
[0024] This application discloses a method for preventing accidental programming using an FPGA-embedded eFUSE unit. Please refer to [reference needed]. Figure 1 The flowchart shown illustrates that this anti-false burning control method includes the following steps: Step 110: Before programming the eFUSE cell inside the FPGA, the FPGA downloads the test bit stream through the internal configuration download control logic for testing, and outputs the test values of each item to be adjusted to the test pin.
[0025] Please refer to Figure 2 The control framework diagram shown illustrates that the FPGA in this application integrates eFUSE control logic and connected eFUSE units. The eFUSE control logic manages read and write access to the eFUSE units. Operations by the eFUSE control logic on the eFUSE units are mainly divided into programming, readback, and non-working states. In traditional structures, all control ports and readback data ports of the eFUSE unit are connected to the eFUSE control logic. When the internal functional structure of the eFUSE unit differs, its port structure also differs, and the specific connection relationship between the eFUSE control logic and the eFUSE unit also differs. Connections should be made according to the eFUSE unit's design manual. In one example, the functional block diagram of the eFUSE unit is as follows: Figure 3 As shown. The control ports of the eFUSE unit include at least the chip select signal port CSB, the programming high-voltage strobe signal port PS, the address bus A<*:0>, the programming enable signal port PGENB, the programming fuse pulse port STROBE, and the input control port PD. Other control ports are not shown in detail. In one embodiment of this application, the input control port PD of the eFUSE unit is grounded, while other control ports and the data readback port remain connected to the eFUSE control logic. Then, as... Figure 2 As shown, the eFUSE control logic connects to each control port of the eFUSE unit and the data readback port Q<31:0>, while the input control port PD is connected to GND. This ensures that the input control port PD is always at a low level, preventing the eFUSE unit from being accidentally burned during power-on and power-off due to the output signal of the eFUSE control logic being in the state of PS=1 and PD=1.
[0026] The conventional approach is to directly program the eFUSE unit using the eFUSE control logic. In order to avoid incorrect programming of the eFUSE unit, this application adds a test calibration process before programming the eFUSE unit. The test calibration process includes: first, determining the FPGA to be repaired, confirming the programming bits of the eFUSE unit corresponding to each to be repaired item, and determining the value of the corresponding test register. Then, the FPGA test file is modified accordingly to obtain the test bit stream that opens the test pin.
[0027] In addition, the FPGA of this application also integrates configuration download control logic. After the configuration download control logic downloads the test bit stream, it configures and tests the internal test circuit according to the test bit stream configuration, and brings out the test values of each item to be adjusted through the test pins. The test pins here can be implemented using I / O ports.
[0028] Step 120: The host computer reads the test values of each item to be repaired and adjusted through the test pins of the FPGA, and determines the target programming code point based on the deviation between the test value of each item to be repaired and adjusted and the target value.
[0029] The host computer calculates the deviation between the test value and the target value of each item to be repaired, and determines the corresponding repair code based on the repair lookup table TRIM_TABLA. TRIM_TABLA is a factory calibration curve provided by the chip manufacturer, which records the correspondence between repair codes and deviation values. Therefore, the required repair code can be determined by looking up the table. Then, the target programming code point is the programming bit of the eFUSE cell corresponding to the current item to be repaired, which is the programming code point used to implement the repair code.
[0030] In this context, the FPGA's troubleshooting items are the control bits of the FPGA's internal analog circuits, and the target value of the troubleshooting item is the parameter value that the corresponding control bit needs to achieve. Alternatively, the troubleshooting items are the FPGA's internal information storage bits, and the target value of the troubleshooting item is the information content that the corresponding information storage bit needs to store, such as the chip number.
[0031] To further improve the accuracy of programming, after determining the target programming code point through the above process, the process does not directly proceed to the subsequent step 130, but instead incorporates an online verification process, including: The host computer updates the adjustment value corresponding to the currently determined target programming code point to the test bit stream online.
[0032] The FPGA downloads the updated test bit stream through its internal configuration download control logic and retests it, then outputs the corrected test values of each item to be adjusted to the test pin.
[0033] The host computer reads the correction test value of each item to be adjusted through the test pin of the FPGA, corrects the target programming code point according to the deviation between the correction test value of the item to be adjusted and the target value, and re-executes the step of updating the correction value corresponding to the target programming code point online to the test bit stream until the deviation between the correction test value of the item to be adjusted and the target value is less than the deviation threshold, and then proceeds to the subsequent step 130.
[0034] Step 130: The host computer sends the programming instruction containing the target programming code point to the eFUSE control logic inside the FPGA.
[0035] Step 140: The eFUSE control logic inside the FPGA responds to the programming instruction and programs the eFUSE unit inside the FPGA according to the target programming code.
[0036] In one embodiment, the host computer is an ATE (Automatic Test Equipment). The specific implementation of this step is as follows: Write a programming instruction containing the target programming code points; use a script to convert it into a vector file for the ATE; update the ATE's vector file online and send it to the eFUSE control logic; the ATE executes the test to complete the programming. This allows for determining the programming instructions through code stream testing before programming the eFUSE unit during mass production testing of the ATE, reducing the impact of one-time programming of the eFUSE unit.
[0037] To further avoid erroneous programming, in another embodiment, after programming the eFUSE cells inside the FPGA, the FPGA further downloads a test bitstream through its internal configuration download control logic for testing, and outputs the actual values of each item to be adjusted, after being adjusted using the corresponding adjustment values in the eFUSE cells, to the test pins. The host computer reads the actual values of each item to be adjusted through the FPGA's test pins, and determines that the programming is satisfactory if the deviation between the actual value of the item to be adjusted and the target value is less than the deviation threshold; otherwise, it determines that the programming is not satisfactory.
[0038] In another embodiment, after receiving the programming command via the TDI port, the eFUSE control logic inside the FPGA first performs a format verification on the programming command. If the format verification passes, it responds to the programming command and programs the eFUSE unit inside the FPGA according to the target programming code; otherwise, it does not respond to the programming command. This embodiment, by adding command verification logic to the eFUSE control logic and identifying the command tail with a fixed specified format, can avoid incorrect programming caused by external signal interference to the FPGA chip.
[0039] In another embodiment, such as Figure 4 As shown, the FPGA integrates multiple eFUSE units, and these multiple eFUSE units are all connected to the eFUSE control logic. Figure 4 Taking an FPGA with three integrated eFUSE units as an example, when the eFUSE control logic inside the FPGA responds to a programming instruction and programs the eFUSE units according to the target programming code, it simultaneously programs multiple eFUSE units according to the target programming code. Therefore, when determining the adjustment value for each adjustment item, the eFUSE control logic simultaneously reads the readback data of the programming bits corresponding to the same adjustment item from each eFUSE unit, and uses a vote among the multiple readback data to determine the adjustment value for the adjustment item.
[0040] In practical applications, the initial state of each programming bit in the eFUSE unit is low, and it becomes high after programming. Therefore, the above function only needs to add AND logic operation to the eFUSE control logic. That is, after the eFUSE control logic reads the readback data of the programming bits corresponding to the same adjustment item in each eFUSE unit, it performs AND logic operation on the readback data of the programming bits corresponding to the same adjustment item in multiple eFUSE units to determine the adjustment value of the adjustment item.
[0041] The above are merely preferred embodiments of this application, and this application is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of this application should be considered to be included within the protection scope of this application.
Claims
1. A method for preventing accidental programming of an FPGA with a built-in eFUSE unit, characterized in that, The anti-false burning control method includes: Before programming the eFUSE cell inside the FPGA, the FPGA downloads the test bit stream through its internal configuration download control logic for testing and outputs the test values of each item to be adjusted to the test pin. The host computer reads the test values of each item to be repaired and adjusted through the test pins of the FPGA, and determines the target programming code point based on the deviation between the test value of each item to be repaired and the target value. The host computer sends the programming instruction containing the target programming code point to the eFUSE control logic inside the FPGA; The eFUSE control logic inside the FPGA responds to the programming instruction and programs the eFUSE unit inside the FPGA according to the target programming code.
2. The anti-false burning control method according to claim 1, characterized in that, The anti-false burning control method also includes: The host computer updates the adjustment value corresponding to the target programming code point to the test bit stream online; The FPGA downloads the updated test bit stream through its internal configuration download control logic and retests it, and outputs the corrected test values of each item to be adjusted to the test pin. The host computer reads the correction test values of each item to be adjusted through the test pins of the FPGA, corrects the target programming code point according to the deviation between the correction test value of the item to be adjusted and the target value, and re-executes the step of updating the correction value corresponding to the target programming code point online to the test bit stream until the deviation between the correction test value of the item to be adjusted and the target value is less than the deviation threshold. Then, the programming instruction containing the target programming code point is sent to the eFUSE control logic inside the FPGA.
3. The anti-false burning control method according to claim 1, characterized in that, The anti-false burning control method also includes: After the eFUSE cell inside the FPGA is programmed, the FPGA downloads the test bit stream through the internal configuration download control logic for testing, and outputs the actual value of each item to be adjusted after being adjusted by the corresponding adjustment value in the eFUSE cell to the test pin. The host computer reads the actual value of each item to be repaired through the test pins of the FPGA, and determines that the burning meets expectations when the deviation between the actual value of the item to be repaired and the target value is less than the deviation threshold; otherwise, it determines that the burning does not meet expectations.
4. The anti-false burning control method according to claim 1, characterized in that, The eFUSE control logic inside the FPGA responds to the programming command and programs the eFUSE cells inside the FPGA according to the target programming code, including: The eFUSE control logic inside the FPGA responds to the programming instruction and simultaneously programs multiple eFUSE units inside the FPGA according to the target programming code; wherein, the multiple eFUSE units integrated inside the FPGA are all connected to the eFUSE control logic.
5. The anti-false burning control method according to claim 4, characterized in that, The anti-false burning control method also includes: The eFUSE control logic simultaneously reads the write data of the programming bits corresponding to the same item to be adjusted from each eFUSE unit, and votes on multiple read data to determine the adjustment value of the item to be adjusted.
6. The anti-false burning control method according to claim 5, characterized in that, The initial state of each programming bit in the eFUSE unit is low, and it becomes high after programming. The eFUSE control logic inside the FPGA determines the adjustment value of the item to be adjusted by voting on multiple readback data, including: The eFUSE control logic inside the FPGA performs AND and logical operations on the readback data of the programming bits of multiple eFUSE cells corresponding to the same item to be adjusted to determine the adjustment value of the item to be adjusted.
7. The anti-false burning control method according to claim 1, characterized in that, The input control port PD of the eFUSE unit inside the FPGA is grounded so that the input control port PD is always at a low level.
8. The anti-false burning control method according to claim 1, characterized in that, The eFUSE control logic inside the FPGA responds to the programming command and programs the eFUSE cells inside the FPGA according to the target programming code, and also includes: The eFUSE control logic inside the FPGA performs format verification on the received programming command. If the format verification passes, it responds to the programming command and programs the eFUSE unit inside the FPGA according to the target programming code; otherwise, it does not respond to the programming command.
9. The anti-false burning control method according to claim 1, characterized in that, The host computer determines the target programming code point based on the deviation between the test value and the target value of each item to be repaired and adjusted, including: The host computer calculates the deviation between the test value and the target value of each item to be repaired and adjusts, and determines the repair code corresponding to the deviation value by combining the repair lookup table TRIM_TABLA. It then determines the target programming code point when the programming bit of the eFUSE unit corresponding to the current item to be repaired and adjusts is implemented.
10. The anti-false burning control method according to claim 1, characterized in that, The host computer is an automated testing equipment (ATE).