Microwave assembly micro-assembly process drawing automatic generation method and system

Abstract

The application discloses a microwave assembly micro-assembly process drawing automatic generation method and system, and the method comprises the following steps: obtaining two-dimensional CAD assembly drawing data containing multiple semantic layers, and extracting layer data; based on semantic information and geometric information of the layer data, corresponding process objects are identified and created, and matching process attribute information is automatically supplemented into the process objects; an association network for describing component assembly and connection relationship is generated; process sequence reasoning processing is performed, and complete micro-assembly process sequence data from part preparation to final packaging is automatically generated according to preset process rule logic; view synthesis processing is performed; corresponding process parameter annotation data and technical requirement text data are generated; document assembly processing is performed, and complete micro-assembly process drawing file data is output. According to the application, only two-dimensional CAD drawing data is needed, and full-process data processing from data analysis, semantic identification, relationship modeling to document generation can be automatically completed.

Description

Technical Field

[0001] This invention relates to the field of microwave components, and more particularly to a method and system for automatically generating micro-assembly process drawings for microwave components. Background Technology

[0002] In the research and development and manufacturing of microwave components (such as TR components, plastic-encapsulated SIP devices, ceramic-encapsulated SIP devices, and gold-encapsulated SIP devices), the design department ultimately outputs a two-dimensional CAD drawing containing all assembly-related information. This drawing manages different categories of design elements through layers. For example, the structural component layer describes the cavity and cover plate; the KeepOut-Layer, TopPaste-Layer, and Bottom Paste-Layer describe the PCB circuit board; the bare core layer describes the chip location and size; the carrier layer describes the metal carrier board; the connector layer describes the input / output interface; and the gold wire layer describes the bonding points and lead planning. This layered management contains complete design semantics and assembly logic. However, to guide production line manufacturing, it also needs to be converted into a process assembly drawing according to specific procedures.

[0003] However, the current conversion process from this "design drawing" to the "process assembly drawing" used in the workshop relies entirely on manual operation by the designer, which has fundamental defects: (1) Low efficiency: Designers manually extract, associate and translate information, add annotations, and check the bill of parts (BOM), which is a heavy and time-consuming task. (2) Prone to errors: Manual annotation is prone to missing dimensions, tolerances or part numbers, resulting in discrepancies between the drawings and the actual objects, affecting processing and assembly. (3) Broken data link, consistency cannot be guaranteed: Process drawings are the product of manual secondary creation and there is no digital link between them and the original design drawings. When the design changes, the process drawings must be updated manually in sync, which is very easy to cause omissions or contradictions, leading to production errors. (4) Poor consistency: Different designers have different drawing habits or different projects use different drawing standards, resulting in large differences in drawing styles and annotation methods, which is not conducive to standardized management. (5) Existing automated tools are powerless: General CAD software or simple batch drawing processing tools cannot understand the process semantics of layer names, let alone automatically derive the correct micro-assembly process flow based on the geometric relationship between layers.

[0004] Therefore, there is an urgent need for a technology that can deeply understand and utilize the semantic information of multiple layers in CAD drawings to achieve fully automated and intelligent generation of process drawings, so as to bridge the last mile from design to manufacturing. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and system for automatically generating process drawings for microwave component micro-assembly.

[0006] The objective of this invention is achieved through the following technical solution: A first aspect of the present invention provides a method for automatically generating process drawings for microwave component micro-assembly, comprising the following steps: S1: Obtain a 2D CAD assembly drawing data containing multiple semantic layers. The drawing data is organized into a data set of different design elements through multiple layers with standardized names. Perform layer parsing processing on the drawing data to extract layer data including at least structural component layer data, PCB related layer data, bare core component layer data, connector layer data, carrier layer data, and gold wire bonding layer data. S2: Based on the semantic and geometric information of the data of each layer extracted in step S1, identify and create corresponding process objects, including structural parts, connectors, PCB circuit boards, bare core devices, and carriers; and automatically supplement the process objects with matching process attribute information by calling the preset process knowledge base data and BOM list data, and generate a data interface for user confirmation. S3: Perform spatial relationship analysis on the process objects created in step S2. By calculating the geometric position and range of each process object in the drawing coordinate system, and by calculating the spatial inclusion relationship, adjacency relationship and coordinate matching relationship between process objects, an association network for describing the assembly and connection relationship of components is automatically generated. S4: Based on the association network and the preset process knowledge base data obtained in step S3, perform process sequence reasoning processing, automatically generate complete micro-assembly process sequence data from part preparation to final packaging according to preset process rule logic, and generate a process sequence interface that can be confirmed and modified by the user. S5: For each process step in the process sequence data described in step S4, perform view composition processing, including: automatically generating process state schematic diagram data for the corresponding step based on the association network described in step S3 and the original layer data in step S1, and performing local magnification processing on key process areas to generate local magnified detailed map data. S6: Based on the process attribute information of the process objects involved in the current process step, call the process knowledge base data to perform parameter matching processing, and automatically generate corresponding process parameter annotation data and technical requirement text data; S7: Perform document assembly processing on the process sequence data generated in step S4, the process status schematic diagram data and local enlarged detail data generated in step S5, the process parameter annotation data and technical requirement text data generated in step S6, and format the data according to the standardized template. After data verification, output a complete set of micro-assembly process drawing file data.

[0007] Furthermore, the semantic recognition processing in step S2 specifically includes: The bare die device layer data is parsed to extract the bare die size data, pad distribution data and chip name identification data; using the chip name identification data as an index, a search and matching is performed in the preset device library data to automatically obtain the corresponding chip thickness, chip type, functional indicators, assembly requirements and usage precautions, and the obtained data is added to the process object; The carrier layer data is parsed to extract the carrier's dimensional data. Using the dimensional data as a condition, a search and matching is performed in the BOM list to automatically obtain the carrier's model data, tag number data, material data, and thickness data. The obtained data is then added to the process object.

[0008] Furthermore, the spatial relationship analysis and processing in step S3 specifically includes: Perform spatial inclusion relationship judgment processing: calculate the geometric overlap relationship between the coordinate range of graphic elements in the bare die device layer data and the coordinate range of graphic elements in the carrier layer data. When it is determined that the bare die graphic element is included by the carrier graphic element, generate the association data of "chip mounted on carrier" in the association network. Execution of hierarchical inclusion relationship judgment and processing: Calculate the geometric overlap relationship between the coordinate range of graphic elements in the carrier layer data and the coordinate range of graphic elements in the structural component layer data or PCB related layer data. When it is determined that the carrier graphic element is included by the structural component or PCB graphic element, generate the association data of "carrier component is installed on PCB or structural component" in the association network. Perform coordinate matching processing: Match the coordinates of graphic elements in the connector layer data with the coordinates of graphic elements in the structural component layer data. When the coordinate adjacency condition is met, generate the associated data of the connector being installed on the structural component in the associated network. Perform bonding relationship matching processing: Match the coordinates of the gold wire endpoints in the gold wire bonding layer data with the coordinates of the pads in the bare core device layer data or PCB related layer data. When the coordinates coincide or the spacing is less than a preset threshold, generate bonding connection relationship data in the associated network.

[0009] Furthermore, the process sequence reasoning process in step S4 specifically includes: The process objects are traversed and searched. When object data of type "structural component" is identified, the process sequence data of structural component cleaning process node data, cover plate installation process node data, and sealing welding process node data are added to the process sequence data in sequence. When object data of type "PCB board" is identified, add PCB board installation process node data to the process sequence data; When object data of type "carrier" is identified and associated data of "chip mounted on carrier" exists in the associated network, add secondary assembly process node data containing two sub-steps: "chip and carrier pre-assembly" and "carrier component installation" to the process sequence data. When relevant data related to gold wire bonding is identified, add gold wire bonding process node data to the process sequence data; The above process node data are sorted according to preset priority rules to generate complete process sequence data.

[0010] Furthermore, in step S5, the view compositing process performs the following data processing on the magnified detailed view of the gold wire bonding process: The bonding point coordinates and lead path data in the gold wire bonding layer data are read, and the pad coordinates in the bare die layer data are read. The bonding point coordinates and pad coordinates are aligned and transformed. Based on the aligned data, a local magnified detailed image of the gold wire bonding area is automatically generated. The bonding point positions and lead paths are directly derived from the parsing and transformation results of the bare die layer data and the gold wire bonding layer data.

[0011] Further, in step S1, the PCB-related layer data includes: GKO layer data for defining the board boundary, GTP layer data and GTO layer data for describing the pads and markings of top-level components, and GBP layer data and GBO layer data for describing the pads and markings of bottom-level components. The semantic recognition process in step S2 includes: automatically recognizing the GKO, GTP, GTO, GBP, and GBO layer data according to the standardized naming rules of the layers, and associating the extracted layer data with the PCB circuit board process object.

[0012] Furthermore, the parameter matching process in step S6 specifically includes: Read the material attribute data of the process object involved in the current process step, and use the material attribute data as an index to search the process knowledge base data. Match at least one of the corresponding sintering temperature curve parameter data, bonding power parameter data, cleaning agent type data, and sealing torque parameter data, and automatically generate annotation box data and annotation text data containing the above parameter data. The annotation box data and annotation text data are attached to the process state diagram data generated in step S5.

[0013] A second aspect of the present invention provides an automatic generation system for microwave component micro-assembly process drawings, comprising: Data acquisition and parsing module: used to acquire 2D CAD assembly drawing data, perform parsing processing on the standardized named layers in the drawing data, and extract data from various layers; Semantic Recognition and Object Modeling Module: This module performs semantic recognition processing on the extracted layer data, creates a process object data structure, and supplements the data structure with attributes by calling process knowledge base data and BOM list data. Spatial Relationship Analysis Module: Used to perform spatial position relationship calculations on the data structure of each process object, and automatically generate an associated network data model describing the assembly and connection relationships of components; Process knowledge base storage module: used to store process rule data, process parameter data and standardized template data of microwave components; Process reasoning module: Based on the associated network data model and process knowledge base data, it performs reasoning processing according to preset process rules and logic to automatically generate process sequence data; View synthesis module: used to perform view generation processing based on the process sequence data and original layer data, automatically generating process schematic diagram data and local enlarged detail data; The parameter matching and annotation module is used to perform parameter matching processing based on process object attribute data and process knowledge base data, and automatically generate process parameter annotation data and technical requirement text data. Document assembly and output module: This module assembles the data generated by the above modules according to a standardized template, and outputs it as process drawing file data after verification.

[0014] Furthermore, the spatial relationship analysis module is specifically used for: Perform spatial inclusion relationship judgment processing, calculate the coordinate range overlap relationship of graphic elements in different layers of data, and generate corresponding related edge data in the related network data model based on the overlap judgment result; Perform coordinate matching processing to calculate the distance between the endpoint coordinates and pad coordinates in the gold wire bonding layer. When the distance is less than a preset threshold, generate bonding connection relationship data.

[0015] Furthermore, the process reasoning module is specifically used for: The process object data structure is traversed and retrieved by type. Based on the retrieval results and the associated edge data in the associated network data model, the process sequence data is automatically sorted and generated according to the priority rules of structural component cleaning and sealing welding first, carrier pre-assembly second, and gold wire bonding last. A data interface for user interaction, confirmation, and modification is generated.

[0016] The beneficial effects of this invention are: (1) Users only need to provide a two-dimensional CAD drawing data, and the entire process of data processing from data parsing, semantic recognition, relationship modeling to document generation can be completed automatically without manual intervention, reducing the original process preparation work of several hours to minutes.

[0017] (2) For missing process attribute data (such as thickness, material grade, etc.) in the drawings, the data is automatically filled in by matching the knowledge base, avoiding the tedious process of manually checking the BOM list and manual, and eliminating manual input errors.

[0018] (3) Reusability of structured data model: The generated associated network data model can not only be used for process sequence reasoning of the current drawing, but also stored in the knowledge base for reuse in the process design of similar products in the future, so as to realize the accumulation and inheritance of knowledge. Attached Figure Description

[0019] Figure 1 A flowchart of a method for automatically generating process drawings for microwave component micro-assembly provided as an exemplary embodiment of the present invention; Figure 2 An automatically generated "chip-carrier sintering" process diagram and its partial enlarged view are provided for an exemplary embodiment of the present invention; Figure 3 An automatically generated "gold wire bonding" process diagram is provided for an exemplary embodiment of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0021] See Figure 1 , Figure 1 The flowchart illustrates an exemplary embodiment of the present invention for automatically generating microwave component micro-assembly process drawings, including the following steps: S1: Obtain a 2D CAD assembly drawing data containing multiple semantic layers. The drawing data is organized into a data set of different design elements through multiple layers with standardized names. Perform layer parsing processing on the drawing data to extract layer data including at least structural component layer data, PCB related layer data, bare core component layer data, connector layer data, carrier layer data, and gold wire bonding layer data. S2: Based on the semantic and geometric information of the data of each layer extracted in step S1, identify and create corresponding process objects, including structural parts, connectors, PCB circuit boards, bare core devices, and carriers; and automatically supplement the process objects with matching process attribute information by calling the preset process knowledge base data and BOM list data, and generate a data interface for user confirmation. S3: Perform spatial relationship analysis on the process objects created in step S2. By calculating the geometric position and range of each process object in the drawing coordinate system, and by calculating the spatial inclusion relationship, adjacency relationship and coordinate matching relationship between process objects, an association network for describing the assembly and connection relationship of components is automatically generated. S4: Based on the association network and the preset process knowledge base data obtained in step S3, perform process sequence reasoning processing, automatically generate complete micro-assembly process sequence data from part preparation to final packaging according to preset process rule logic, and generate a process sequence interface that can be confirmed and modified by the user. S5: For each process step in the process sequence data described in step S4, perform view composition processing, including: automatically generating process state schematic diagram data for the corresponding step based on the association network described in step S3 and the original layer data in step S1, and performing local magnification processing on key process areas to generate local magnified detailed map data. S6: Based on the process attribute information of the process objects involved in the current process step, call the process knowledge base data to perform parameter matching processing, and automatically generate corresponding process parameter annotation data and technical requirement text data; S7: Perform document assembly processing on the process sequence data generated in step S4, the process status schematic diagram data and local enlarged detail data generated in step S5, the process parameter annotation data and technical requirement text data generated in step S6, and format the data according to the standardized template. After data verification, output a complete set of micro-assembly process drawing file data.

[0022] Specifically, in this exemplary embodiment, the two-dimensional CAD assembly drawing is considered as a structured data set, where each standardized layer (such as structural component layer, PCB-related layer, bare core layer, carrier layer, gold wire bonding layer, etc.) constitutes a data subset with a clear semantic label. Semantic recognition is performed through standardized naming rules for layer names, automatically understanding the design element type represented by each layer without relying on manual annotation. Specifically: At the data parsing level, the underlying data structure of the CAD file is first read to obtain the graphic data (including coordinate data and attribute data of geometric elements such as points, lines, polygons, and text) in each layer. Then, according to the preset mapping rules between layer names and process object types, the data of each layer is assigned to the corresponding process object data structure.

[0023] At the process object creation level, the dimensions, position coordinates, pad distribution, and other attributes of the process object are calculated based on the extracted geometric data and populated into the process object data structure. For attributes that cannot be directly obtained from the drawings (such as chip thickness, carrier material grade, etc.), the obtained data (such as chip model, carrier size, and the type of chip it carries) is used as a query index to search and match in the pre-set process knowledge base data and BOM list data. The matching results are automatically added to the data structure, thereby realizing intelligent completion of incomplete data.

[0024] At the level of network construction, spatial relationship calculations are performed on the position coordinate data in the data structure of each process object. Based on these calculation results, a directed graph data model is generated, where nodes represent process objects and edges represent assembly or connection relationships between objects.

[0025] At the process sequence reasoning level, the node types and edge types in the associated network data model are traversed, and an ordered sequence of process nodes is generated according to the preset process rules (such as structural component cleaning must be before all installation steps, and wire bonding must be after all curing processes).

[0026] At the view composition level, for each process node, the process object data involved in that step is extracted from the associated network data model, the geometric representation of the object in the drawing coordinate system is generated, and the visualization is rendered according to the process status (e.g., highlighting the objects involved in the current step and fading other objects). For key areas that need to be magnified locally, the original layer data is transformed and clipped according to the preset magnification and viewport range to generate magnified view data.

[0027] At the document assembly level, all generated data is formatted according to the standardized template requirements, including page layout, title levels, and annotation box positions, and finally output as process drawing files in PDF or DWG format.

[0028] In summary, in this exemplary embodiment, by transforming the entire process drawing generation process into a data processing flow, the following technical effects are achieved: (1) Users only need to provide one set of two-dimensional CAD drawing data to automatically complete the entire data processing process from data parsing, semantic recognition, relation modeling to document generation without manual intervention, reducing the original process preparation work of several hours to minutes. (2) For missing process attribute data in the drawings (such as thickness, material grade, etc.), the data is automatically filled in by matching with the knowledge base, avoiding the tedious process of manually consulting the BOM list and manual, and eliminating manual input errors. (3) Reusability of structured data model: The generated relational network data model can not only be used for process sequence reasoning of the current drawing, but also stored in the knowledge base for reuse in the process design of similar products in the future, realizing the accumulation and inheritance of knowledge.

[0029] More preferably, in an exemplary embodiment, in step S1, a two-dimensional assembly CAD drawing containing all design information is input. The drawing organizes different design elements through multiple layers with standardized naming. The layer data, including at least structural component layers, PCB-related layers, bare core device layers, connector layers, carrier layers, and gold wire bonding layers, is automatically parsed and extracted. The precise coordinates, attributes, and layer metadata of all geometric figures (points, lines, surfaces, and text) in each layer are extracted.

[0030] More preferably, in an exemplary embodiment, the semantic recognition processing in step S2 specifically includes: The bare die device layer data is parsed to extract the bare die size data, pad distribution data and chip name identification data; using the chip name identification data as an index, a search and matching is performed in the preset device library data to automatically obtain the corresponding chip thickness, chip type, functional indicators, assembly requirements and usage precautions, and the obtained data is added to the process object; The carrier layer data is parsed to extract the carrier's dimensional data. Based on the dimensional data, the carrier's material properties, thickness properties, and tag information are automatically matched according to the BOM list. The obtained data is then added to the process object.

[0031] Specifically, in this exemplary embodiment, the semantic recognition processing in step S2 is disclosed, the purpose of which is to solve the problem that the information contained in the bare die device layer and carrier layer in the two-dimensional CAD drawing data is incomplete. Specifically, the bare die device layer typically records the outline shape of the chip (generally rectangular or polygonal), the distribution of pad positions, and the chip name text label, but cannot record the chip thickness (thickness information cannot be expressed in two-dimensional drawings), the specific type classification of the chip (such as power amplifier chip, low noise amplifier chip, filter chip, etc.), and information such as the chip assembly method and usage precautions. The carrier layer records the outer contour of the carrier, but cannot record the carrier's model, reference number, material composition, and thickness.

[0032] In this exemplary embodiment, a multi-level data matching mechanism addresses the aforementioned information loss issue. For bare die device layer data, chip name identification data (e.g., "GMM0361") is first extracted from the layer, serving as the first-level index. Then, a pre-built device library is invoked. This library, with chip model as the primary key, stores a complete attribute dataset including chip thickness, chip type classification (e.g., "power amplifier chip," "driver chip," "capacitor chip," etc.), operating frequency range, power consumption parameters, assembly method, and usage conditions. A database retrieval operation is performed, matching the chip name identification data with the primary key field in the device library. Upon a match, the corresponding attribute data is read and written into the process object data structure.

[0033] For carrier layer data, the matching mechanism is more complex. Since the thickness and material information of the carrier are usually not marked in two-dimensional drawings, direct matching via name indexing is not possible. Therefore, this exemplary embodiment employs a combined condition matching strategy: retrieving the dimensional data (length, width) extracted from the carrier layer from the BOM list. The BOM list lists the carrier's material properties, length*width*thickness, tag number, and other information, and automatically supplements it into the process object data structure.

[0034] After data matching is complete, a data interaction interface is generated for user confirmation. This interface displays all automatically matched attribute data in table or form format and provides edit boxes for user modification. After user confirmation, the confirmed data is embedded into the process object data structure and enters the subsequent processing flow. This user confirmation mechanism ensures both the efficiency of automated processing and the flexibility of manual intervention.

[0035] This exemplary embodiment realizes cross-data source information fusion, that is, it realizes the automatic fusion of CAD drawing data, component library data, and process knowledge base data, integrating information scattered in different data sources into a unified process object data structure, thus solving the inherent problem of limited information carrying capacity of two-dimensional drawings.

[0036] It should be noted that in practical applications, the bare die layer of a CAD file can be parsed to obtain the size, pad distribution, and chip name of the bare die, but not the chip thickness, chip type, or chip assembly method. Based on a pre-built component library, the system can automatically match thickness information, intelligently classify chip types, determine the most suitable chip assembly method and parameter settings, invite the user for final confirmation, and grant the user modification permissions. After user confirmation, the system proceeds to the next step. Similarly, the carrier layer of a CAD file can obtain the carrier's size, but not its model, reference designator, material, or thickness. Based on the BOM (Bill of Materials), the system matches the carrier's material and thickness, invites the user for final confirmation, and grants the user modification permissions.

[0037] Therefore, in a specific exemplary embodiment, the identification in step S2 may include: identifying the contours in the structural component layer and creating "cavity" and "cover" objects; identifying the PCB_KEEPOUT layer contour as the outer boundary of the PCB, creating a "PCB" object by combining TOP / BOTTOM layer elements, and distinguishing between top and bottom surface components; identifying the polygons in the bare die device layer, creating a "bare die" object, and reading its reference designator and chip name attributes; and identifying the contours in the carrier layer, creating a "carrier" object, and reading its material and thickness attributes.

[0038] More preferably, in an exemplary embodiment, the spatial relationship analysis process in step S3 specifically includes: Perform spatial inclusion relationship judgment processing: calculate the geometric overlap relationship between the coordinate range of graphic elements in the bare die device layer data and the coordinate range of graphic elements in the carrier layer data. When it is determined that the bare die graphic element is included by the carrier graphic element, generate the association data of "chip mounted on carrier" in the association network. Execution of hierarchical inclusion relationship judgment and processing: Calculate the geometric overlap relationship between the coordinate range of graphic elements in the carrier layer data and the coordinate range of graphic elements in the structural component layer data or PCB related layer data. When it is determined that the carrier graphic element is included by the structural component or PCB graphic element, generate the association data of "carrier component is installed on PCB or structural component" in the association network. Perform coordinate matching processing: Match the coordinates of graphic elements in the connector layer data with the coordinates of graphic elements in the structural component layer data. When the coordinate adjacency condition is met, generate the associated data of the connector being installed on the structural component in the associated network. Perform bonding relationship matching processing: Match the coordinates of the gold wire endpoints in the gold wire bonding layer data with the coordinates of the pads in the bare core device layer data or PCB related layer data. When the coordinates coincide or the spacing is less than a preset threshold, generate bonding connection relationship data in the associated network.

[0039] Specifically, in this exemplary embodiment, the specific implementation of the spatial relationship analysis and processing in step S3 is disclosed: (1) Spatial inclusion relationship judgment and processing: Obtain the coordinate range of the graphic elements (usually rectangles or polygons) in the bare core device layer data and the coordinate range of the graphic elements in the carrier layer data. If it is determined that the bare core is included by the carrier, generate a directed edge of type "installed in" from the bare core node to the carrier node in the associated network data model. If the coordinate range of the bare core and the coordinate range of the carrier only partially overlap rather than completely include each other, it is determined to be "partially overlapping" and no installation relationship is generated.

[0040] (2) Hierarchical inclusion relationship judgment and processing: Calculate the inclusion relationship between the carrier graphic element and the structural component or PCB graphic element. Unlike the spatial inclusion relationship judgment and processing, this step also handles a special case: the carrier may be installed in a specific area of ​​the PCB (such as the heat dissipation copper area). For this reason, in addition to judging the geometric inclusion relationship, the specific area data in the relevant PCB layers will also be checked to determine whether the carrier coordinates overlap with the coordinates of that area.

[0041] (3) Coordinate matching processing: The installation relationship of the connector does not depend on the containment relationship, but on the adjacency relationship. Obtain the connector outline coordinates in the connector layer data and the cavity edge outline coordinates in the structural component layer data. When the minimum distance between the connector outline coordinates and the cavity edge outline coordinates is less than the preset adjacency threshold (e.g., 0.1mm), it is determined that the connector is installed on the side wall of the structural component cavity, and the associated data is generated.

[0042] (4) Bonding Relationship Matching Process: The accuracy requirement for gold wire bonding relationship matching is the highest. Obtain the endpoint coordinates (starting and ending coordinates) of each gold wire in the gold wire bonding layer data, as well as the coordinate set of all pads in the bare core device layer and PCB related layers. Execute the nearest neighbor matching algorithm: For each gold wire endpoint, find the pad with the smallest distance. If the minimum distance is less than the preset matching threshold (e.g., 0.05mm), it is determined that there is a bonding connection between the gold wire endpoint and the pad, and an undirected edge of type "bonding connection" (or two directed edges representing the signal flow direction) is generated in the associated network data model.

[0043] By executing the four spatial relationship determination algorithms described above, a relational network data model containing process object nodes and multiple types of associated edges is automatically constructed. This model is stored using a graph data structure, supporting subsequent traversal, search, and inference operations.

[0044] More preferably, in an exemplary embodiment, the process sequence reasoning process in step S4 specifically includes: The process objects are traversed and searched. When object data of type "structural component" is identified, the process sequence data of structural component cleaning process node data, cover plate installation process node data, and sealing welding process node data are added to the process sequence data in sequence. When object data of type "PCB board" is identified, add PCB board installation process node data to the process sequence data; When object data of type "carrier" is identified and associated data of "chip mounted on carrier" exists in the associated network, add secondary assembly process node data containing two sub-steps: "chip and carrier pre-assembly" and "carrier component installation" to the process sequence data. When relevant data related to gold wire bonding is identified, add gold wire bonding process node data to the process sequence data; The above process node data are sorted according to preset priority rules to generate complete process sequence data.

[0045] Specifically, in this exemplary embodiment, step S4, the process sequence reasoning process, is disclosed. First, the process object data structure is traversed and retrieved to identify the type labels of all process objects. Simultaneously, the associated network data model is traversed to extract the type information of all associated edges. Based on the retrieval results, sequence generation is performed according to preset process rule logic. Specifically: (1) Structural component processing rules: When object data of type "structural component" is detected, three process node data are automatically generated: structural component cleaning process node (process number: 0010), cover plate installation process node (process number: 0080), and sealing welding process node (process number: 0090). The relative order of these three nodes in the final sequence is fixed, with cleaning being the first and sealing welding the last.

[0046] (2) PCB processing rules: When object data of type "PCB board" is detected, the PCB board installation process node (process number: 0020) is automatically generated. This node should be located after the structural components are cleaned and before the carrier components are installed.

[0047] (3) Carrier processing rules: When object data of type "carrier" is identified, further check whether there is a "installed on" type directed edge from the bare chip node to the carrier node in the associated network data model. If it exists, generate secondary assembly process node data containing two sub-steps: sub-step A is "chip and carrier pre-assembly" (process number: 0040a), and sub-step B is "carrier component installation" (process number: 0040b). The design logic of the secondary assembly process is that the connection between the chip and the carrier (usually eutectic sintering or conductive adhesive bonding) needs to be completed before the carrier is installed on the PCB or cavity, because the connection surface between the chip and the carrier is the upper surface of the carrier, while the connection surface of the carrier installation is the lower surface of the carrier. The two operations do not affect each other and the step-by-step operation is more convenient for quality inspection.

[0048] (4) Gold wire bonding rules: When the associated edge data of the "bonding connection" type is identified, the gold wire bonding process node data (process number: 0050) is automatically generated. This node should be located after all installation processes (including carrier installation), because the gold wire bonding operation requires all connected devices to be fixed in place. Any movement of any device during the bonding process may cause the gold wire to break or the bonding point to fall off.

[0049] After generating all process nodes, the data is sorted according to the numerical order of the process numbers to generate complete process sequence data. The coding rule for process numbers is as follows: Structural component cleaning (0010) < PCB installation (0020) < Connector installation (0030) < Carrier pre-assembly (0040a) < Carrier assembly installation (0040b) < Gold wire bonding (0050) < Cover plate installation (0080) < Sealing soldering (0090). This sorting rule reflects the basic logic of micro-assembly process: from bottom to top, from inside to outside, and installation before connection.

[0050] Furthermore, a data interface is generated that allows users to interact, confirm, and modify data. It displays the process name, process number, and process description in a list format and supports drag-and-drop sorting and editing. After user confirmation, the process sequence data is solidified and enters the subsequent processing flow.

[0051] More preferably, in an exemplary embodiment, the view compositing process in step S5 performs the following data processing for a locally enlarged detail of the gold wire bonding process: The bonding point coordinates and lead path data in the gold wire bonding layer data are read, and the pad coordinates in the bare die layer data are read. The bonding point coordinates and pad coordinates are aligned and transformed. Based on the aligned data, a local magnified detailed image of the gold wire bonding area is automatically generated. The bonding point positions and lead paths are directly derived from the parsing and transformation results of the bare die layer data and the gold wire bonding layer data.

[0052] Specifically, in this exemplary embodiment, step S5 discloses the view compositing process for the gold wire bonding process. In the process drawings for the gold wire bonding process, the relative positions of the bonding points and the orientation of the gold wire leads are the most critical information. In this exemplary embodiment, a direct geometric mapping from the original layer data to the process view data is implemented. Specifically: First, read the gold wire bonding layer data. In the gold wire bonding layer, each gold wire is typically drawn as a polyline or curve connecting two pads, and the coordinates of the endpoints and inflection points of the polyline are precisely recorded in the layer data. Extract the endpoint coordinate data and the sequence of intermediate inflection point coordinates for each gold wire.

[0053] Secondly, the pad coordinate data is read from the bare die component layer data and the PCB-related layer data. Pads are usually drawn as solid circles or rectangles in the layers, and the center point coordinates of each pad are extracted using an image recognition algorithm.

[0054] Next, coordinate alignment transformation is performed. Since the gold wire bonding layer and the bare core layer may reside in different coordinate reference systems (in CAD files, different layers typically share the same global coordinate system, but view transformations may occur), a unified transformation of the coordinate data is required. Specifically, the global coordinate system definition of the CAD file is read, and the coordinate data of all layers is transformed to a unified drawing coordinate system, ensuring that the coordinates of the gold wire endpoints and the pad coordinates are comparable under the same reference system.

[0055] Finally, based on the aligned coordinate data, a magnified detailed view of the gold wire bonding region is automatically generated. The generation process includes: determining the magnified viewport range (expanding outwards by a preset distance from the bonding point), scaling the original coordinate data (magnification factor is a preset value, typically 2x-5x), drawing the gold wire connection lines (drawing polylines according to endpoint and inflection point coordinates), labeling the bonding point positions (identified by solid dots), and adding leader labels (labeling the bonding sequence number and gold wire parameters). The generated magnified detailed view data is stored as an independent view data block for later use in document assembly.

[0056] More preferably, in an exemplary embodiment, in step S1, the PCB-related layer data includes: GKO layer data for defining the board boundary, GTP layer data and GTO layer data for describing the pads and markings of top-level components, and GBP layer data and GBO layer data for describing the pads and markings of bottom-level components. The semantic recognition process in step S2 includes: automatically recognizing the GKO, GTP, GTO, GBP, and GBO layer data according to the standardized naming rules of the layers, and associating the extracted layer data with the PCB circuit board process object.

[0057] Specifically, in this exemplary embodiment, when parsing CAD drawing data, the name attribute string of each layer is read and matched against the pattern in the mapping rule table. Matching methods support exact matching (e.g., "GKO") and wildcard matching (e.g., "KeepOut"). When a match is successful, the layer data is automatically associated with the data structure of the PCB circuit board process object, and the specific purpose of the layer data is marked (e.g., "used for extracting contours," "used for extracting top-level pads," etc.).

[0058] More preferably, in an exemplary embodiment, the parameter matching process in step S6 specifically includes: Read the material attribute data of the process object involved in the current process step, and use the material attribute data as an index to search the process knowledge base data. Match at least one of the corresponding sintering temperature curve parameter data, bonding power parameter data, cleaning agent type data, and sealing torque parameter data, and automatically generate annotation box data and annotation text data containing the above parameter data. The annotation box data and annotation text data are attached to the process state diagram data generated in step S5.

[0059] Specifically, in this exemplary embodiment, the parameter matching process of step S6 is disclosed. First, material property data is read from the process object data structure involved in the current process step. For example, in the chip-carrier pre-assembly step, the material properties of the carrier process object (e.g., "MoCu"—molybdenum-copper alloy) and the type properties of the chip process object (e.g., "power amplifier chip") are read. In the "gold wire bonding" step, the wire diameter properties of the gold wire process object (e.g., "25μm" or "1.0mil") are read.

[0060] Then, a search is performed in the process knowledge base using a composite index of material property data and / or device type data. The process knowledge base pre-stores parameter configuration tables for different material combinations and process types.

[0061] After parameter matching is performed, annotation box data and annotation text data containing the aforementioned parameter data are automatically generated. The annotation box data defines the position (at the specified location on the schematic diagram), size, and border style of the annotation box; the annotation text data contains key-value pairs of parameter names and parameter values. For cases with multiple parameter values ​​(such as multiple temperature curve points), the data is organized in list form.

[0062] These annotation box data and annotation text data are appended to the schematic diagram data generated in step S5. Specifically, the annotation box data is added as an independent graphic element to the canvas data of the schematic diagram, and the annotation text data is inserted as supplementary content to the annotation box. In the final output process drawing, each process diagram includes a parameter annotation box next to it, clearly listing the process parameters required for that step.

[0063] The following explanation uses the automatic generation of process drawings for a specific "KU-band transmission module" as an example. The overall design drawing of this module includes the following key layers: structural layer, PCB-related layers (GKO, GTP, GTO, GBP and GBO), bare core layer, gold wire layer, connector layer, carrier layer, and reference designator layer.

[0064] Step S1: Drawing Analysis The design master drawing Ku_Tran.dwg is read, which contains a microwave component CAD assembly design drawing with multiple semantic layers. Through parsing, the layers with the above naming conventions are identified, and all graphic data is extracted. For example, a closed polygon is found in the GKO layer, which is the outer contour of the PCB circuit board; 37 rectangular blocks are found in the bare core layer, which are the outer contours of 37 chips; and 18 rectangular blocks are found in the carrier layer, which are the outer contours of 18 carriers.

[0065] Step S2: Feature Identification Due to the limitations of 2D CAD drawings, the information of process objects cannot be fully represented in the drawings. Therefore, based on step S1, and using the semantic and geometric information of each layer, corresponding process objects are identified and created, including but not limited to structural components, connectors, PCB circuit boards, bare core devices, carriers, etc. Furthermore, through a pre-built process knowledge base and BOM list, more attributes (including but not limited to model, reference number, material, thickness, component name, etc.) are automatically matched, and the user is invited to make final confirmation and given modification permissions. Specifically, this includes: By analyzing the bare die layer of the CAD file, the dimensions, pad distribution, and chip name of the bare die can be obtained, but the chip thickness and type cannot be determined. Based on a pre-built component library, the thickness information can be automatically matched, and the chip type can be intelligently categorized. The user is then invited to provide final confirmation and granted modification permissions. After user confirmation, the process proceeds to the next step. The reference designators for the three chips GMM0361, GCA0820, and JCT11A-15-X7R-100V-100M are U34, U35, and C55, respectively.

[0066] The dimensions of the carrier can be obtained from the carrier layer of the CAD file, but the carrier model, tag number, material, and thickness are not available. Based on the BOM list, the carrier material and thickness are automatically matched, and the user is invited to make final confirmation and given modification permissions. One particular carrier has tag number Z1 and dimensions of 3.14mm * 2.6mm * 0.15mm. Step S3: Association Construction Based on the analysis of the Ku_Tran.dwg drawing, a series of process objects were identified. By analyzing the spatial relationships between these objects, an association network describing the assembly and connection relationships of components was automatically constructed. For example, it was identified that the outlines of U34 and U35 are completely within the outline of the Z1 carrier. Based on this, the association is established: U34, U35 → Carrier Z1. At the same time, C55 is adjacent to a heat dissipation copper area on the PCB_TOP layer, and an association is established thereas as well.

[0067] Analyzing the BOND_WIRE layer revealed a series of points and curves. By matching coordinates, these points were associated with pads on U34, U35, C55, and PCB_TOP, forming a complete bonding network.

[0068] Step S4: Process Sequence Reasoning Based on the parsing of the Ku_Tran.dwg drawing, a series of process objects were identified, and rules were defined according to the process knowledge base: (1) Identify the process object with structural components, and set up the process of cleaning the structural components, installing the cover plate, and sealing the welding process; (2) Identify connector-type process objects and set up connector installation procedures; (not required) (3) Identify PCB circuit board type process objects and set PCB circuit board installation procedures; (not required) (4) Identify a carrier-type process object and set up a chip mounting process on the carrier. When the relationship of "chip mounting on carrier" exists in the associated network, a secondary assembly process is planned, including two sub-steps: "chip and carrier pre-assembly" and "carrier component installation". (Optional) (5) If the gold wire bonding process is detected, the gold wire bonding process is set.

[0069] (6) Therefore, the following executable sequence is finally generated: 1. Cavity cleaning → 2. Connector installation → 3. PCB installation and curing → 4a. Carrier preparation and chip eutectic sintering → 4b. Carrier assembly bonding → 5. Gold wire bonding (according to the planned path) → 6. Cover sealing and leak detection.

[0070] (7) After user confirmation, the drawing generation stage begins. User-defined process sequence adjustment is supported.

[0071] Steps S5 and S6: View generation and parameter matching For the step of "chip sintering on carrier Z1": generate an assembly diagram of carrier Z1 with U34 and U35, as shown below. Figure 2 As shown. A magnified view of the area where U34, U35 and the carrier surface are coated with solder (generated based on the outline offset of the bare core layer and the carrier layer). According to the BOM, the material property of the carrier is MoCu, and it is automatically matched and labeled as "Au80Sn20 solder sheet, sintering peak temperature 290°C".

[0072] For the "gold wire bonding" step: directly read the predefined bonding point coordinates and lead curvature in the BOND_WIRE layer, generate a magnified image of the bonding region, and automatically label it with "gold wire diameter: 25μm (1.0mil), bonding power: 70mA", such as... Figure 3 As shown.

[0073] The view generation and parameter matching steps in other processes are not listed here.

[0074] Step S6: Document Output The text and images of all steps are automatically filled into a standard A4 horizontal process card template, generating a PDF file Ku_Tran_V1.0.pdf that shows the completed process route and specific processing requirements, which can be printed directly in the workshop.

[0075] In summary, the above exemplary embodiments have the following advantages: (1) Single input, complete output: Only one design drawing is needed to automatically obtain practical process documents, which greatly simplifies data preparation and management.

[0076] (2) High efficiency and accuracy: Fully automatic drawing generation reduces the original manual drawing time of several hours or even days to minutes, realizing end-to-end digital transmission from original design data to manufacturing instructions, eliminating the manual transcription and interpretation process, and ensuring the absolute accuracy and consistency of the data.

[0077] (3) True intelligence: By understanding the semantics of layers and building a network of connections, the system imitates the reasoning process of senior process engineers and realizes the intelligent leap from what (design) to how (process).

[0078] (4) High standardization: Adopt unified drawing rules to ensure that the style of drawings and annotation methods meet the enterprise or industry standards.

[0079] (5) Deep knowledge solidification and reuse: process rules, parameters and experience are solidified into the system's knowledge base and reasoning logic, forming core manufacturing knowledge assets that can be inherited by the enterprise.

[0080] (6) Strong adaptability and scalability: By configuring layer naming rules and semantic mapping, the system can quickly adapt to the design specifications of different enterprises or different products.

[0081] Having the same inventive concept as the exemplary embodiments described above, another exemplary embodiment of the present invention provides an automatic generation system for microwave component micro-assembly process drawings, comprising: Data acquisition and parsing module: used to acquire 2D CAD assembly drawing data, perform parsing processing on the standardized named layers in the drawing data, and extract data from various layers; Semantic Recognition and Object Modeling Module: This module performs semantic recognition processing on the extracted layer data, creates a process object data structure, and supplements the data structure with attributes by calling process knowledge base data and BOM list data. Spatial Relationship Analysis Module: Used to perform spatial position relationship calculations on the data structure of each process object, and automatically generate an associated network data model describing the assembly and connection relationships of components; Process knowledge base storage module: used to store process rule data, process parameter data and standardized template data of microwave components; Process reasoning module: Based on the associated network data model and process knowledge base data, it performs reasoning processing according to preset process rules and logic to automatically generate process sequence data; View synthesis module: used to perform view generation processing based on the process sequence data and original layer data, automatically generating process schematic diagram data and local enlarged detail data; The parameter matching and annotation module is used to perform parameter matching processing based on process object attribute data and process knowledge base data, and automatically generate process parameter annotation data and technical requirement text data. Document assembly and output module: This module assembles the data generated by the above modules according to a standardized template, and outputs it as process drawing file data after verification.

[0082] Correspondingly, in an exemplary embodiment, the spatial relationship analysis module is specifically used for: Perform spatial inclusion relationship judgment processing, calculate the coordinate range overlap relationship of graphic elements in different layers of data, and generate corresponding related edge data in the related network data model based on the overlap judgment result; Perform coordinate matching processing to calculate the distance between the endpoint coordinates and pad coordinates in the gold wire bonding layer. When the distance is less than a preset threshold, generate bonding connection relationship data.

[0083] Correspondingly, in an exemplary embodiment, the process inference module is specifically used for: The process object data structure is traversed and retrieved by type. Based on the retrieval results and the associated edge data in the associated network data model, the process sequence data is automatically sorted and generated according to the priority rules of structural component cleaning and sealing welding first, carrier pre-assembly second, and gold wire bonding last. A data interface for user interaction, confirmation, and modification is generated.

[0084] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for automatically generating process drawings for microwave component micro-assembly, characterized in that, Includes the following steps: S1: Obtain a set of 2D CAD assembly drawing data containing multiple semantic layers. The drawing data is organized into a data set of different design elements through multiple layers with standardized names. Perform layer parsing processing on the drawing data to extract layer data including at least structural component layer data, PCB related layer data, bare core component layer data, connector layer data, carrier layer data, and gold wire bonding layer data; S2: Based on the semantic and geometric information of the data of each layer extracted in step S1, identify and create corresponding process objects, including structural components, connectors, PCB circuit boards, bare core devices, and carriers; By calling the preset process knowledge base data and BOM list data, the system automatically supplements the process object with matching process attribute information and generates a data interface for user confirmation. S3: Perform spatial relationship analysis on the process objects created in step S2. By calculating the geometric position and range of each process object in the drawing coordinate system, and by calculating the spatial inclusion relationship, adjacency relationship and coordinate matching relationship between process objects, an association network for describing the assembly and connection relationship of components is automatically generated. S4: Based on the association network and the preset process knowledge base data obtained in step S3, perform process sequence reasoning processing, automatically generate complete micro-assembly process sequence data from part preparation to final packaging according to preset process rule logic, and generate a process sequence interface that can be confirmed and modified by the user. S5: For each process step in the process sequence data described in step S4, perform view composition processing, including: automatically generating process state schematic diagram data for the corresponding step based on the association network described in step S3 and the original layer data in step S1, and performing local magnification processing on key process areas to generate local magnified detailed map data. S6: Based on the process attribute information of the process objects involved in the current process step, call the process knowledge base data to perform parameter matching processing, and automatically generate corresponding process parameter annotation data and technical requirement text data; S7: Perform document assembly processing on the process sequence data generated in step S4, the process status schematic diagram data and local enlarged detail data generated in step S5, the process parameter annotation data and technical requirement text data generated in step S6, and format the data according to the standardized template. After data verification, output a complete set of micro-assembly process drawing file data.

2. The method for automatically generating microwave component micro-assembly process drawings according to claim 1, characterized in that: The semantic recognition process in step S2 specifically includes: Parse the bare die device layer data to extract the bare die size data, pad distribution data and chip name identification data; use the chip name identification data as an index to search and match in the preset device library data, automatically obtain the corresponding chip thickness, chip type, functional indicators, assembly requirements and usage precautions, and supplement the obtained data into the process object; The carrier layer data is parsed to extract the carrier's dimensional data. Using the dimensional data as a condition, a search and matching is performed in the BOM list to automatically obtain the carrier's model data, tag number data, material data, and thickness data. The obtained data is then added to the process object.

3. The method for automatically generating microwave component micro-assembly process drawings according to claim 1, characterized in that: The spatial relationship analysis and processing in step S3 specifically includes: Perform spatial inclusion relationship judgment processing: calculate the geometric overlap relationship between the coordinate range of graphic elements in the bare die device layer data and the coordinate range of graphic elements in the carrier layer data. When it is determined that the bare die graphic element is included by the carrier graphic element, generate the association data of "chip mounted on carrier" in the association network. Execution of hierarchical inclusion relationship judgment and processing: Calculate the geometric overlap relationship between the coordinate range of graphic elements in the carrier layer data and the coordinate range of graphic elements in the structural component layer data or PCB related layer data. When it is determined that the carrier graphic element is included by the structural component or PCB graphic element, generate the association data "carrier component is installed on PCB or structural component" in the association network. Perform coordinate matching processing: Match the coordinates of graphic elements in the connector layer data with the coordinates of graphic elements in the structural component layer data. When the coordinate adjacency condition is met, generate the associated data of the connector being installed on the structural component in the associated network. Perform bonding relationship matching processing: Match the coordinates of the gold wire endpoints in the gold wire bonding layer data with the coordinates of the pads in the bare core device layer data or PCB related layer data. When the coordinates coincide or the spacing is less than a preset threshold, generate bonding connection relationship data in the associated network.

4. The method for automatically generating microwave component micro-assembly process drawings according to claim 3, characterized in that: The process sequence reasoning process in step S4 specifically includes: The process objects are traversed and retrieved. When object data of type "structural component" is identified, the process sequence data of structural component cleaning process node data, cover plate installation process node data, and sealing welding process node data are added to the process sequence data in sequence. When object data of type "PCB board" is identified, add PCB board installation process node data to the process sequence data; When object data of type "carrier" is identified and associated data of "chip mounted on carrier" exists in the associated network, add secondary assembly process node data containing two sub-steps, "chip and carrier pre-assembly" and "carrier component installation", to the process sequence data. When relevant data related to gold wire bonding is identified, add gold wire bonding process node data to the process sequence data; The above process node data are sorted according to preset priority rules to generate complete process sequence data.

5. The method for automatically generating microwave component micro-assembly process drawings according to claim 1, characterized in that: In step S5, the view compositing process performs the following data processing on the magnified details of the gold wire bonding process: The bonding point coordinates and lead path data in the gold wire bonding layer data are read, and the pad coordinates in the bare die layer data are read. The bonding point coordinates and pad coordinates are aligned and transformed. Based on the aligned data, a local magnified detailed image of the gold wire bonding area is automatically generated. The bonding point positions and lead paths are directly derived from the parsing and transformation results of the bare die layer data and the gold wire bonding layer data.

6. The method for automatically generating microwave component micro-assembly process drawings according to claim 1, characterized in that: In step S1, the PCB-related layer data includes: GKO layer data for defining the board boundary, GTP layer data and GTO layer data for describing the pads and markings of top-level components, and GBP layer data and GBO layer data for describing the pads and markings of bottom-level components. The semantic recognition process in step S2 includes: automatically recognizing the GKO, GTP, GTO, GBP, and GBO layer data according to the standardized naming rules of the layers, and associating the extracted layer data with the PCB circuit board process object.

7. The method for automatically generating microwave component micro-assembly process drawings according to claim 1, characterized in that: The parameter matching process in step S6 specifically includes: Read the material attribute data of the process object involved in the current process step, and use the material attribute data as an index to search the process knowledge base data. Match at least one of the corresponding sintering temperature curve parameter data, bonding power parameter data, cleaning agent type data, and sealing torque parameter data, and automatically generate annotation box data and annotation text data containing the above parameter data. The annotation box data and annotation text data are attached to the process state diagram data generated in step S5.

8. An automatic drawing generation system for microwave component micro-assembly processes, characterized in that, include: Data acquisition and parsing module: used to acquire 2D CAD assembly drawing data, perform parsing processing on the standardized named layers in the drawing data, and extract data from various layers; Semantic Recognition and Object Modeling Module: This module performs semantic recognition processing on the extracted layer data, creates a process object data structure, and supplements the data structure with attributes by calling process knowledge base data and BOM list data. Spatial Relationship Analysis Module: Used to perform spatial position relationship calculations on the data structure of each process object, and automatically generate an associated network data model describing the assembly and connection relationships of components; Process knowledge base storage module: used to store process rule data, process parameter data and standardized template data of microwave components; Process reasoning module: Based on the associated network data model and process knowledge base data, it performs reasoning processing according to preset process rules and logic to automatically generate process sequence data; View synthesis module: used to perform view generation processing based on the process sequence data and original layer data, automatically generating process schematic diagram data and local enlarged detail data; The parameter matching and annotation module is used to perform parameter matching processing based on process object attribute data and process knowledge base data, and automatically generate process parameter annotation data and technical requirement text data. Document assembly and output module: This module assembles the data generated by the above modules according to a standardized template, and outputs it as process drawing file data after verification.

9. The system according to claim 8, characterized in that, The spatial relationship analysis module is specifically used for: Perform spatial inclusion relationship judgment processing, calculate the coordinate range overlap relationship of graphic elements in different layers of data, and generate corresponding related edge data in the related network data model based on the overlap judgment result; Perform coordinate matching processing to calculate the distance between the endpoint coordinates and pad coordinates in the gold wire bonding layer. When the distance is less than a preset threshold, generate bonding connection relationship data.

10. The system according to claim 8, characterized in that, The process reasoning module is specifically used for: The process object data structure is traversed and retrieved by type. Based on the retrieval results and the associated edge data in the associated network data model, the process sequence data is automatically sorted and generated according to the priority rules of structural component cleaning and sealing welding first, carrier pre-assembly second, and gold wire bonding last. A data interface for user interaction, confirmation, and modification is generated.

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