Wiring complexity determination method, apparatus, and storage medium

Abstract

The embodiment of the application provides a wiring complexity determination method and device and a storage medium. The method comprises the following steps: obtaining a design netlist file; determining a first topology structure based on the design netlist file, wherein a node in the first topology structure represents a logic circuit unit in the design netlist file, and a weight corresponding to an edge in the first topology structure is determined based on the distance between two logic circuit units corresponding to the connected two nodes; determining a second topology structure based on the first topology structure, wherein the weight of the second topology structure and the minimum total resource consumption indicating the connectivity of all nodes; determining the wiring complexity of the design netlist file based on the weight sum of the second topology structure, and the wiring complexity of the design netlist file is in a positive correlation with the weight sum of the second topology structure. The technical scheme provided by the embodiment of the application is closer to the actual wiring situation, and the determination accuracy of the wiring complexity is improved.

Description

Technical Field

[0001] This application relates to the field of field-programmable logic array technology, and in particular to a method, apparatus and storage medium for determining wiring complexity. Background Technology

[0002] Currently, FPGA products need to use EDA software to determine the hardware design layout and connection relationships. The time and computing power costs consumed by more advanced and larger-scale placement and routing are constantly increasing. Therefore, it is necessary to estimate the layout complexity before placement and routing in order to improve the efficiency of routing work and reduce the cost of routing work.

[0003] The routing complexity estimation schemes provided by related technologies include: obtaining the number of logic circuit units and the number of logic connections in the design netlist file, performing simple algebraic operations on the number of logic circuit units and the number of logic connections, and using the operation results as the routing complexity estimation results.

[0004] The technical solutions provided by the related technologies have the following defects: the wiring complexity estimation model is too coarse, resulting in a large deviation between the wiring complexity estimation results and the actual results. Summary of the Invention

[0005] This application provides a method, apparatus, and storage medium for determining wiring complexity, aiming to improve the problem of large deviations between wiring complexity estimation results and actual results in related technologies.

[0006] In a first aspect, embodiments of this application provide a method for determining routing complexity, the method comprising: obtaining a design netlist file; determining a first topology based on the design netlist file, wherein nodes in the first topology represent logic circuit units in the design netlist file, and the weights corresponding to edges in the first topology are determined based on the distance between the logic circuit units corresponding to the two connected nodes; determining a second topology based on the first topology, wherein the second topology includes all nodes in the first topology, and the sum of weights in the second topology indicates the minimum total resource consumption for connecting all nodes; and determining the routing complexity of the design netlist file based on the sum of weights in the second topology, wherein the routing complexity of the design netlist file is positively correlated with the sum of weights in the second topology.

[0007] Secondly, embodiments of this application provide a routing complexity determination device, comprising: a file acquisition module for acquiring a design netlist file; a first topology generation module for determining a first topology based on the design netlist file, wherein nodes in the first topology represent logic circuit units in the design netlist file, and the weights corresponding to edges in the first topology are determined based on the distance between the logic circuit units corresponding to the two connected nodes; a second topology generation module for determining a second topology based on the first topology, wherein the second topology includes all nodes in the first topology, and the weights of the second topology indicate the minimum total resource consumption for connecting all nodes; and a complexity determination module for determining the routing complexity of the design netlist file based on the weights of the second topology, wherein the routing complexity of the design netlist file is positively correlated with the weights of the second topology.

[0008] Thirdly, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory is used to store a computer program; and the processor is used to execute the computer program stored in the memory to implement the wiring complexity determination method as described in the first aspect.

[0009] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the wiring complexity determination method as described in the first aspect.

[0010] Compared to related technologies, the technical solution provided in this application has at least the following technical effects: First, a first topology is constructed based on the design netlist file. The first topology is used to describe all the connection relationships in the design netlist file. Specifically, each logic circuit unit in the design netlist file is represented by a node of the first topology. The nodes corresponding to two logic circuit units with a connection relationship are connected by an edge. The weight of the edge is determined based on the distance between the two logic circuit units. Then, a second topology is determined based on the first topology. The second topology includes all the nodes in the first topology. The weight of the second topology indicates the minimum total resource consumption to connect all nodes. Since the distance between two logic circuit units is used as the basis for measuring routing complexity, compared to the related technologies that determine routing complexity based on the number of logic circuit units and the number of logic connections, the determined routing complexity is closer to the subsequent actual routing situation, thus improving the accuracy of routing complexity determination. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of a wiring complexity determination method provided in one embodiment of this application.

[0013] Figure 2 This is a flowchart of a wiring complexity determination method provided in another embodiment of this application.

[0014] Figure 3 This is a schematic diagram of a first topology provided in one embodiment of this application.

[0015] Figure 4 This is a schematic diagram of a second topology provided in one embodiment of this application.

[0016] Figure 5 This is a structural diagram of a wiring complexity determination device provided in one embodiment of this application.

[0017] Figure 6 This is a structural diagram of an electronic device provided in one embodiment of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] This application provides a method for determining routing complexity. The method includes: obtaining a design netlist file; determining a first topology based on the design netlist file, wherein nodes in the first topology represent logic circuit units in the design netlist file, and the weights of edges in the first topology are determined based on the distance between the logic circuit units corresponding to the two connected nodes; determining a second topology based on the first topology, wherein the second topology includes all nodes in the first topology, and the sum of weights in the second topology indicates the minimum total resource consumption for connecting all nodes; and determining the routing complexity of the design netlist file based on the sum of weights in the second topology, wherein the routing complexity of the design netlist file is positively correlated with the sum of weights in the second topology.

[0021] The technical solution provided in this application first constructs a first topology based on a design netlist file. The first topology describes all the connection relationships in the design netlist file. Specifically, each logic circuit unit in the design netlist file is represented by a node in the first topology. Nodes corresponding to two logic circuit units with a connection relationship are connected by an edge. The weight of the edge is determined based on the distance between the two logic circuit units. Then, a second topology is determined based on the first topology. The second topology includes all nodes in the first topology. The weights of the second topology indicate the minimum total resource consumption to connect all nodes. Since the distance between two logic circuit units is used as the basis for measuring routing complexity, compared with the related technology that determines routing complexity based on the number of logic circuit units and the number of logic connections, the determined routing complexity is closer to the subsequent actual routing situation, thus improving the accuracy of routing complexity determination.

[0022] Please refer to Figure 1 The diagram illustrates a flowchart of a wiring complexity determination method provided in one embodiment of this application. The method includes the following steps.

[0023] S10, Obtain the design netlist file.

[0024] The design netlist file is an intermediate file generated by synthesis tools after converting a hardware description language into low-level logic units and their connections. Essentially, it is a structured data representation of digital circuits, consisting of basic logic units and their connections. After receiving instructions to determine routing complexity, the electronic device reads the aforementioned design netlist file locally.

[0025] S20, determine the first topology based on the design netlist file.

[0026] The first topology describes the connections between the logic circuit units in the design netlist file. Optionally, the first topology can be an undirected connected graph.

[0027] The first topology comprises multiple nodes, each representing a logic circuit unit in the design netlist file. These nodes are connected by multiple edges, and an edge connects two nodes representing logic circuit units with a connection relationship. Each edge has a corresponding weight, which is determined based on the distance between the two connected logic circuit units. Specifically, the weight of an edge is positively correlated with the distance between the two connected logic circuit units; the greater the distance between the two connected logic circuit units, the greater the weight; conversely, the smaller the distance between the two connected logic circuit units, the smaller the weight. The process of determining the first topology will be described in the following embodiments.

[0028] S30, determine the second topology based on the first topology.

[0029] The second topology includes all nodes in the first topology. The weights and indices of the second topology represent the minimum total resource consumption required to connect all nodes. The electronic device can process the first topology using either the Kruskal's minimum spanning tree algorithm or the Prim's algorithm to obtain the second topology. The process of determining the second topology will be described in the following embodiments. S40 determines the routing complexity of the design netlist file based on the weights of the second topology.

[0030] The routing complexity of the netlist design file is positively correlated with the weight sum of the second topology. That is, the larger the weight sum of the second topology, the higher the routing complexity of the netlist design file and the worse the routing result; the smaller the weight sum of the second topology, the lower the routing complexity of the netlist design file and the better the routing result.

[0031] In summary, the technical solution provided in this application first constructs a first topology based on a design netlist file. The first topology describes all connections in the design netlist file. Specifically, each logic circuit unit in the design netlist file is represented by a node in the first topology. Nodes corresponding to two logic circuit units with a connection relationship are connected by an edge, and the weight of the edge is determined based on the distance between the two logic circuit units. Then, a second topology is determined based on the first topology. The second topology includes all nodes in the first topology. The weights of the second topology indicate the minimum total resource consumption to connect all nodes. Since the distance between two logic circuit units is used as the basis for measuring routing complexity, compared to related technologies that determine routing complexity based on the number of logic circuit units and the number of logic connections, the determined routing complexity is closer to the subsequent actual routing situation, thus improving the accuracy of routing complexity determination.

[0032] Please refer to Figure 2 This illustrates a flowchart of a wiring complexity determination method provided in one embodiment of this application. Figure 2 In the embodiment, S20 is replaced by S210-S220.

[0033] S10, Obtain the design netlist file.

[0034] S210, obtain the set of connection relationships in the design netlist file.

[0035] The connection set includes the connection relationships between various logic circuit units in the design netlist file.

[0036] S220, traverse each connection relationship in the set of connection relationships in turn, take the two logic circuit units connected by the connection relationship as two nodes in the second candidate topology, take the distance between the two logic circuit units connected by the connection relationship as the weight of the edge between the two nodes, and at the end of the traversal, determine the second candidate topology as the first topology.

[0037] The initial state of the second candidate topology is empty. The electronic device represents each connection as an edge in the second candidate topology according to the order of the connection relationships in the connection relationship set. The two logic circuit units connected by the connection relationship are represented as the nodes at both ends of the edge. The weight of the edge is the distance between the two logic circuit units connected by the connection relationship. After all the connection relationships have been processed, the second candidate topology obtained is also the first topology.

[0038] In a specific example, the set of connections includes 10 connections, each represented by (A, B, x). A and B are the two logic circuit units connected by this connection, and x is a weight determined based on the distance between the two logic circuit units connected by this connection. These 10 connections are represented as (Driver Source, Node 1, 6), (Driver Source, Node 2, 13), (Driver Source, Node 3, 10), (Driver Source, Node 4, 2), (Node 1, Node 2, 2), (Node 1, Node 3, 12), (Node 1, Node 4, 11), (Node 2, Node 3, 3), (Node 2, Node 4, 9), and (Node 3, Node 4, 4). The first topology constructed based on these 10 connections can be found in [reference needed]. Figure 3 , Figure 3 This diagram illustrates a first topology 300 according to an embodiment of this application. The first topology 300 includes 10 edges, which are used to describe the 10 connection relationships. Taking the connection relationship (driver source, node 1, 6) as an example, this connection relationship is represented by edge 310. The driver source and node 1 connected by this connection relationship are represented as nodes 320 at both ends of edge 310, and edge 310 is labeled with a weight of 6.

[0039] In some embodiments, the electronic device determines the distance between two logic circuit units connected by the connection relationship by: obtaining the coordinates corresponding to the two logic circuit units connected by the connection relationship respectively; and determining the distance between the two logic circuit units connected by the connection relationship by the sum of the absolute values ​​of the first difference and the second difference.

[0040] The first absolute difference is the absolute difference between the horizontal coordinates of the two logic circuit units, and the second absolute difference is the absolute difference between the vertical coordinates of the two logic circuit units.

[0041] Electronic devices establish a Cartesian coordinate system with any vertex on the motherboard as the origin and the two edges passing through that vertex as the coordinate axes. Since the overall on-chip resource distribution of an FPGA is in a "grid" shape, the length of one grid cell can be used as the unit length. Based on this coordinate system, the electronic device can determine the x and y coordinates of each logic circuit unit. In a specific example, the coordinates of logic circuit unit A are (x1, y1), and the coordinates of logic circuit unit B are (x2, y2). The distance between logic circuit units A and B is expressed by the following formula: .

[0042] S310, determine the set of all edges and their corresponding nodes based on the first topology.

[0043] S320 sorts all edges in ascending order of weight to obtain the sorting result.

[0044] Taking the above 10 connection relationships as an example again, the multiple edges are sorted in ascending order of weight, and the sorting result is as follows: (Driver source, node 4, 2), (Node 1, node 2, 2), (Node 2, node 3, 3), (Node 3, node 4, 4), (Driver source, node 1, 6), (Node 2, node 4, 9), (Driver source, node 3, 10), (Node 1, node 4, 11), (Driver source, node 2, 13).

[0045] S330: Starting from the edge with the smallest weight in the sorting result, iterate through each edge to check whether the two nodes connected by each edge belong to the first candidate topology. If there is a node in the two nodes connected by the edge that does not belong to the first candidate topology, add the node to the first candidate topology and build the connection relationship between the node and other nodes in the first candidate topology. Continue until all nodes in the first topology have been added to the first candidate topology, and then determine the first candidate topology as the second topology.

[0046] The initial state of the first candidate topology is empty. The second topology does not contain any ring structures, that is, it does not contain any connected components. There is one and only one path between any two nodes, which ensures that the resource consumption of connecting all nodes is minimized.

[0047] Taking the aforementioned 10 connection relationships as an example again, first, check whether the two nodes, driver source and node 4, in the edge (driver source, node 4, 2) belong to the first candidate topology. Since neither belongs, driver source and node 4 are added to the first candidate topology. Then, check whether nodes 1 and 2 in the edge (node ​​1, node 2, 2) belong to the first candidate topology. Since neither belongs, nodes 1 and 2 are added to the first candidate topology. Next, check whether nodes 2 and 3 in the edge (node ​​2, node 3, 3) belong to the first candidate topology. Since node 3 does not belong, node 3 is added to the first candidate topology and connected to nodes 2 and 4 respectively. At this point, all nodes in the first topology are in the first candidate topology, and the process ends to obtain the second topology. (Refer to the reference...) Figure 4 The diagram shows a second candidate topology 400 provided in an embodiment of this application, which includes five nodes: a driver source, node 1, node 2, node 3, and node 4, and the connection relationship between the above five nodes does not form a ring structure.

[0048] S340 determines the routing complexity of the design netlist file based on the weights of the second topology.

[0049] The routing complexity of the netlist design file is positively correlated with the weights of the second topology. Figure 4 Taking the second topology as an example, the weight sum of the second topology is 2+4+3+2=11.

[0050] In some embodiments, the electronic device determines the weights of the second topology directly as the routing complexity of the design netlist file.

[0051] In other embodiments, the electronic device determines the routing complexity of the design netlist file based on the weights of the second topology and a preset mapping relationship, the preset mapping relationship including the mapping relationship between different weights and different routing complexities.

[0052] In summary, the technical solution provided in this application first constructs a first topology based on a design netlist file. The first topology describes all connections in the design netlist file. Specifically, each logic circuit unit in the design netlist file is represented by a node in the first topology. Nodes corresponding to two logic circuit units with a connection relationship are connected by an edge, and the weight of the edge is determined based on the distance between the two logic circuit units. Then, a second topology is determined based on the first topology. The second topology includes all nodes in the first topology. The weights of the second topology indicate the minimum total resource consumption to connect all nodes. Since the distance between two logic circuit units is used as the basis for measuring routing complexity, compared to related technologies that determine routing complexity based on the number of logic circuit units and the number of logic connections, the determined routing complexity is closer to the subsequent actual routing situation, thus improving the accuracy of routing complexity determination.

[0053] Please refer to Figure 5 The diagram illustrates a block diagram of a wiring complexity determination apparatus 500 according to an embodiment of this application. The wiring complexity determination apparatus 500 includes: a file acquisition module 510, a first topology generation module 520, a second topology generation module 530, and a complexity determination module 540.

[0054] The file acquisition module 510 is used to acquire the design netlist file.

[0055] The first topology generation module 520 is used to determine the first topology based on the design netlist file. The nodes in the first topology represent logic circuit units in the design netlist file, and the weights of the edges in the first topology are determined based on the distance between the logic circuit units corresponding to the two connected nodes.

[0056] The second topology generation module 530 is used to determine a second topology based on the first topology. The second topology includes all nodes in the first topology, and the weights and indicators of the second topology indicate the minimum total resource consumption to connect all nodes.

[0057] The complexity determination module 540 is used to determine the routing complexity of the design netlist file based on the weights of the second topology. The routing complexity of the design netlist file is positively correlated with the weights of the second topology.

[0058] In some embodiments, the complexity determination module 540 is used to determine the weights of the second topology as the routing complexity of the design netlist file.

[0059] In some embodiments, the complexity determination module 540 is used to determine the routing complexity of the design netlist file based on the weights of the second topology and a preset mapping relationship, wherein the preset mapping relationship includes the mapping relationship between different weights and different routing complexities.

[0060] In some embodiments, the second topology generation module 530 is used to determine an edge set based on the first topology, the edge set including multiple edges, each edge including two connected nodes and a weight; sort the multiple edges in ascending order of weight to obtain a sorting result; starting from the edge with the smallest weight in the sorting result, iterate through whether the two nodes connected to each edge belong to the first candidate topology; if there is a node among the two nodes connected to the edge that does not belong to the first candidate topology, then add the node to the first candidate topology and construct the connection relationship between the node and other nodes in the first candidate topology, until all nodes in the first topology have been added to the first candidate topology, and determine the first candidate topology as the second topology. The initial state of the first candidate topology is empty, and there is no ring structure in the second topology.

[0061] In some embodiments, the first topology generation module 530 is used to obtain a set of connection relationships in the design netlist file, the set of connection relationships including the connection relationships between various logic circuit units in the design netlist file; sequentially traverse each connection relationship in the set of connection relationships, take the two logic circuit units connected by the connection relationship as two nodes in the second candidate topology, take the distance between the two logic circuit units connected by the connection relationship as the weight of the edge between the two nodes, and at the end of the traversal, determine the second candidate topology as the first topology.

[0062] In some embodiments, the apparatus further includes a distance determination module (not shown in the figure). The distance determination module is used to obtain the coordinates corresponding to the two logic circuit units connected by the connection relationship; and to determine the distance between the two logic circuit units connected by the connection relationship by the sum of the absolute value of the first difference and the absolute value of the second difference, wherein the first absolute value of the difference is the absolute value of the difference between the horizontal coordinates of the two logic circuit units, and the second absolute value of the difference is the absolute value of the difference between the vertical coordinates of the two logic circuit units.

[0063] like Figure 6 As shown, this application example also provides an electronic device 600, which includes a processor 610 and a memory 620. The memory 620 stores computer program instructions.

[0064] Processor 610 may include one or more processing cores. Processor 610 connects to various parts of the battery management system via various interfaces and lines, executing instructions, programs, code sets, or instruction sets stored in memory 620, and calling data stored in memory 620 to perform various functions and process data within the battery management system. Processor 810 may integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem handles wireless communication. It is understood that the modem may not be integrated into processor 610 and may be implemented separately through a communication chip. Optionally, the processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.

[0065] The memory 620 may include random access memory (RAM) or read-only memory (ROM). The memory 620 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 620 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing various method examples described below, etc. The data storage area may also store data created by the electronic device 600 during use (e.g., a set of connection relationships, a first topology, etc.).

[0066] This application also provides a computer-readable storage medium storing computer program instructions that can be invoked by a processor to execute the methods described in the above embodiments.

[0067] Computer-readable storage media can be electronic storage devices such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, computer-readable storage media include non-transitory computer-readable storage media. The computer-readable storage medium has storage space for computer program instructions that perform any of the method steps described above. These computer program instructions can be read from or written to one or more computer program products. The computer program instructions may be compressed in an appropriate form.

[0068] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0069] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip module, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a terminal, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component within the terminal (e.g., In chips, circuit modules, etc., or in different components, or at least some modules / units can be implemented by software programs that run on the processor integrated inside the terminal, while the remaining (if any) modules / units can be implemented by hardware methods such as circuits.

[0070] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for determining wiring complexity, characterized in that, The method includes: Obtain the design netlist file; A first topology is determined based on the design netlist file, where nodes in the first topology represent logic circuit units in the design netlist file, and the weights of edges in the first topology are determined based on the distances between the logic circuit units corresponding to the two connected nodes. A second topology is determined based on the first topology, the second topology including all nodes in the first topology, and the weights of the second topology and the minimum total resource consumption for connecting all the nodes. The routing complexity of the design netlist file is determined based on the weights of the second topology, and the routing complexity of the design netlist file is positively correlated with the weights of the second topology.

2. The method according to claim 1, characterized in that, The weights based on the second topology and the estimation of the routing complexity of the design netlist file include: The weights of the second topology are used to determine the routing complexity of the design netlist file.

3. The method according to claim 1, characterized in that, The weights based on the second topology and the estimation of the routing complexity of the design netlist file include: The routing complexity of the design netlist file is determined based on the weights of the second topology and a preset mapping relationship, wherein the preset mapping relationship includes the mapping relationship between different weights and different routing complexities.

4. The method according to claim 1, characterized in that, Determining the second topology based on the first topology includes: Based on the first topology, determine the set of all edges and their corresponding nodes; Sort all the edges in ascending order of their weights to obtain the sorting result; Starting with the edge with the smallest weight in the sorting result, iterate through each edge to check whether the two nodes connected to it belong to the first candidate topology. If there is a node in the two nodes connected to the edge that does not belong to the first candidate topology, add the node to the first candidate topology and establish the connection relationship between the node and other nodes in the first candidate topology. Continue until all nodes in the first topology have been added to the first candidate topology, and then determine the first candidate topology as the second topology. The initial state of the first candidate topology is empty, and there is no ring structure in the second topology.

5. The method according to claim 1, characterized in that, The process of determining the first topology based on the design netlist file includes: Obtain the set of connection relationships in the design netlist file, the set of connection relationships including the connection relationships between various logic circuit units in the design netlist file; Each connection in the set of connection relationships is traversed sequentially. The two logic circuit units connected by the connection relationship are taken as two nodes in the second candidate topology. The distance between the two logic circuit units connected by the connection relationship is taken as the weight of the edge between the two nodes. At the end of the traversal, the second candidate topology is determined as the first topology.

6. The method according to claim 5, characterized in that, Before using the distance between the two logic circuit units connected by the connection relationship as the weight of the edge between the two nodes, the method further includes: Obtain the coordinates of the two logic circuit units connected by the connection relationship; The sum of the first absolute difference and the second absolute difference is determined as the distance between the two logic circuit units connected by the connection relationship. The first absolute difference is the absolute difference between the horizontal coordinates of the two logic circuit units, and the second absolute difference is the absolute difference between the vertical coordinates of the two logic circuit units.

7. A wiring complexity determination device, characterized in that, The device includes: The file acquisition module is used to acquire the design netlist file; The first topology generation module is used to determine a first topology based on the design netlist file. The nodes in the first topology represent logic circuit units in the design netlist file. The weights of the edges in the first topology are determined based on the distance between the logic circuit units corresponding to the two connected nodes. The second topology generation module is used to determine a second topology based on the first topology. The second topology includes all nodes in the first topology. The weight of the second topology and the minimum total resource consumption for connecting all the nodes are also specified. The complexity determination module is used to determine the routing complexity of the design netlist file based on the weights of the second topology, wherein the routing complexity of the design netlist file is positively correlated with the weights of the second topology.

8. The apparatus according to claim 7, characterized in that, The complexity estimation module is used to determine the weights of the second topology as the routing complexity of the design netlist file.

9. An electronic device, characterized in that, Including processor and memory, among which, The memory is used to store computer programs; The processor is configured to execute the computer program stored in the memory to implement the wiring complexity determination method as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the wiring complexity determination method as described in any one of claims 1-6.

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