A method for finding cross-level logic equivalent points

Abstract

The present application belongs to the technical field of integrated circuit design optimization, and more particularly relates to a cross-level logic equivalence point searching method. A netlist to be processed is obtained and traversed, and each iteration driver device is dynamically recorded and stored in a container; iteration is performed, starting from the current driver device set, locating the load devices and input pins driven by the driver device, and screening out load devices whose all input pins have been traversed; for these load devices, on the one hand, a logic equivalence check is performed according to the function type and connection information to construct or update a logic equivalence search table; on the other hand, the output pins of the load devices are added to the container as new driver devices to enter the next iteration; the above iteration process is repeated until the driver container is empty, and a final logic equivalence search table is obtained. The present application solves the problem that current mainstream logic equivalence point searching methods are usually limited to logic operations within a single netlist.

Description

Technical Field

[0001] This invention belongs to the technical field of integrated circuit design optimization, and more specifically, relates to a method for finding cross-level logical equivalence points. Background Technology

[0002] In the entire design and verification process of digital integrated circuits, the circuit netlist structure is the core data foundation from register-transfer-level (RTL) description to physical implementation. It uses a formal connectivity description method to enumerate standard cell instances and their interconnections, transforming the circuit's logical function into an analyzable, convertible, and verifiable structured representation. All EDA tools in the entire process, including logic synthesis, placement and routing, test generation, and power analysis, use the netlist as the core data interaction carrier. Logical equivalence point identification is one of the key technologies in netlist analysis. Its goal is to locate sets of nodes with completely identical logical functions at different abstraction levels or in different design versions, forming the core foundation for subsequent structural reconstruction, redundancy elimination, and equivalence verification.

[0003] In practical engineering design, circuit netlists generally adopt a combination of hierarchical and flat organization: the top-level netlist describes the port connection relationship between modules, while the bottom-level netlist is expanded into specific standard units (such as AND gates, OR gates, flip-flops, etc.) and their interconnection networks; each net connects multiple unit pins and defines the signal propagation path; each instance corresponds to a functional unit, and its type and driving capability are specified by the technology library.

[0004] Chinese patent document CN115906731A discloses a circuit partitioning method, an equivalence verification method, and a storage medium. It performs combinational logic equivalence verification on a reference circuit and an implementation circuit, locates the registers that fail to match as partitioning nodes, and groups the circuits based on the logic cone affiliation of the partitioning nodes, splitting a large-scale netlist into multiple local sub-circuits for separate verification.

[0005] Current mainstream methods for finding logical equivalence points are mostly limited to logical operations within a single netlist, identifying and reconstructing logical structures only within the same level of modules. This makes it difficult to conduct collaborative optimization across module boundaries. For large-scale integrated circuit designs containing multiple nested sub-modules, single-layer optimization methods cannot uncover equivalent redundant structures across modules, limiting the global benefits of logic optimization and making it difficult to support larger-scale structural reconstruction and redundancy elimination. This becomes a bottleneck restricting further improvements in chip area, latency, and power consumption. Summary of the Invention

[0006] The present invention aims to overcome at least one of the defects of the prior art and provide a method for finding cross-level logical equivalence points. This solves the problem that current mainstream logical equivalence point finding methods are usually limited to logical operations within a single netlist, that is, they only identify and reconstruct logical structures within the same level module, making it difficult to perform collaborative optimization across module boundaries.

[0007] The detailed technical solution of this invention is as follows: A method for finding logical equivalence points across levels, the method comprising: S1. Obtain the netlist of the circuit to be processed. Store the input port of the top-level netlist of the circuit as the driving device of the first iteration in the traversal process into container U. Then, store other driving devices in container U for the next iteration. S2. Traverse all driving devices in container U, and only refer to the function of the device as a driving device. S3. Obtain the driven device that has been traversed, and search in the output direction to obtain all the load pins driven by it and traverse them. S4. Obtain and mark the traversed load pins to check whether a certain load device has been traversed; and store the load device where the load pin is located in container V. S5. Determine whether the load pins driven by the current driving device have been traversed: If not, continue traversing the remaining load pins and execute S4; if traversal is complete, execute S6. S6. Determine if the driving devices in container U have been traversed: If not, continue traversing the remaining driving devices and execute S3; if traversal is complete, execute S7. S7. Traverse all load devices stored in container V, then obtain the currently traversed load device, and determine whether the input pins of the current load device are all marked: If all are marked, save the load device to container W and save the input signal information of the load device, and execute step S8; If there are unmarked pins, execute S8 directly; S8. Determine whether the load devices stored in container V have been traversed completely: If not, continue traversing the remaining load devices and execute S9; if the traversal is complete, execute S9. S9. Combining the logical equivalence lookup table, update the input information of the device and match devices with the same function and the same input information to obtain logically equivalent devices; S10. Add the same functional output of the logic equivalent device as a new logic equivalence point to the logic equivalence lookup table; S11. Determine if container W is empty: If not empty, clear container U and store the devices in container W into container U, then execute S2 to enter the next iteration; if empty, it means that the netlist traversal is complete, the final logical equivalent lookup table is obtained, and the process ends.

[0008] Furthermore, the method is integrated into a logic synthesis tool and executed before the technology mapping stage for global redundant logic elimination and logic cone structure optimization. The output logical equivalence lookup table is used for integrated circuit equivalence verification, providing a fast query capability from node to equivalence node set.

[0009] Furthermore, the structure of the logical equivalence lookup table is as follows: First, group all logically equivalent nodes into the same group and assign a unique index identifier to each group; Then, the lookup table maintains two sets of mapping relationships: the forward mapping uses the index as the key and stores all equivalent nodes corresponding to that index; the reverse mapping uses the node as the key and stores the index of the combination to which that node belongs. In addition, after obtaining logically equivalent devices in the first iteration, the output pins of the same type of equivalent devices will be stored as logically equivalent nodes in the set of equivalent nodes; and a new index will be created for this logically equivalent node, constructing two sets of mapping relationships: forward mapping, i.e., index → ​​node set and reverse mapping, i.e., node → index.

[0010] Furthermore, after acquiring the fully driven load device and storing it in container V, it is analyzed and its logic information is extracted, specifically including: A1. Traverse the load devices to be processed in container V; A2. Obtain the load device that has been traversed, and traverse its input pins; A3. Obtain the input pins that have been traversed, and get their driving sources as input signals; A4. Determine whether the signal has been entered into the logical equivalence lookup table: If the signal is not found in the logical equivalence lookup table, use the signal name as the signal information for the current input pin. If the signal exists in the logical equivalence lookup table, its corresponding index number is obtained and used as the signal information of the current input pin. A5. Determine if the input pins of the device have been traversed: If the traversal is not completed, continue traversing the remaining input pins and execute step A3; If the traversal is complete, proceed to the next step; A6. Summarize the signal information of all input pins of the device, and combine it with the device type to obtain the logic information of the device. Then, obtain the mapping relationship between the device and its logic information through the container W. A7. Determine if all devices in container V have been traversed: If the traversal is not completed, continue traversing the remaining devices and execute step A2; If the traversal is complete, proceed to the next step; A8. Obtain the logic information of all devices in the container, then end.

[0011] Furthermore, obtain all physical load pins of the specified device and their corresponding load devices, specifically including: B1. Add all input pins of the device to container H as the initial values ​​for the container to be processed, so that they can be dynamically added and retrieved later. Iterate through the output pins in container H; B2. Obtain the output pins that have been traversed, and traverse their load pins; B3. Obtain the load pins that have been traversed, and find the device where the load pin is located, denoted as the load device; B4. Determine the type of the load device: If the load device is a module instance, then the input port of the corresponding load pin in the instance view needs to be obtained, and then all output pins of the input port are enqueued into container H for subsequent processing; proceed to step B6; If the load device is an output port of a non-top-level module, then locate the corresponding output pin in the upper-level instance through its reference, and enqueue the pin into container H for subsequent processing; proceed to step B6. If the load device is neither a module instance nor an output port of the top-level module, then the load pin that is traversed is the actual bottom-level driver pin, and the next step, B5, is executed. B5. Mark the load pin and store the load device in container V; B6. Determine whether the load pins of the currently processed output pins have been traversed: If the traversal is not completed, continue traversing the remaining load pins and continue executing step B3; If the traversal is complete, proceed to the next step; B7. Determine if the output pins in container H have been traversed: If the traversal is not completed, continue traversing the remaining output pins in container H and continue executing step B2; If the traversal is complete, proceed to the next step, B8; B8. The devices stored in container V are all the actual driving loads of that device. End.

[0012] Furthermore, containers H, U, V, and W are queues.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention provides a method for finding logical equivalence points across levels. It searches for logical equivalence points based on the circuit netlist structure, breaks through the optimization bottleneck of hierarchical design, and realizes global structure reconstruction. At the same time, by tracing the real underlying driving load across levels, a logical equivalence lookup table is constructed without hierarchical constraints, which can discover and merge logical equivalence points throughout the entire design scope.

[0014] (2) The present invention provides a method for finding logical equivalence points across levels, which establishes a bidirectional index mapping to achieve efficient management of equivalence nodes. By establishing a forward (index → ​​node set) and reverse (node ​​→ index) bidirectional index mapping mechanism, it realizes efficient searching, fast merging and dynamic expansion of logical equivalence nodes, and significantly improves the access efficiency and iterative optimization capability of equivalence point management in large-scale design.

[0015] (3) The present invention provides a method for finding cross-level logic equivalence points. In logic synthesis, by exploring cross-module equivalence structures and merging equivalence points before technology mapping, redundant logic can be eliminated and logic cone structure optimized in the early stage, thereby effectively improving the chip area, delay and power consumption. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the cross-level logical equivalence point search method described in this invention.

[0017] Figure 2 This is Example 1 of the logic equivalent device in Embodiment 1 of the present invention.

[0018] Figure 3 This is a flowchart of the device logic information extraction process in Embodiment 1 of the present invention.

[0019] Figure 4 This is example 2 of the logic equivalent device in embodiment 1 of the present invention.

[0020] Figure 5 This is an example of a circuit network representation in Embodiment 1 of the present invention.

[0021] Figure 6 This is a flowchart of the actual underlying driver pin marking and load acquisition in Embodiment 1 of the present invention.

[0022] Figure 7 This is a schematic diagram of the signal equivalence relationship of the flattened circuit netlist in Embodiment 1 of the present invention. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0027] Example 1 In the practical design of digital integrated circuits, the circuit netlist structure is usually organized using a combination of hierarchical and flattened methods: the top-level netlist describes the port connection relationships between modules, while the bottom-level netlist expands into specific standard cells (such as AND gates, OR gates, flip-flops, etc.) and their interconnection networks. Each net connects multiple unit pins, defining the signal propagation path; each instance corresponds to a functional unit, and its type and driving capability are specified by the technology library. The top-level module `top` contains sub-instance instances and basic logic gate (AND gate) instances, which are connected by nets to form a complete structural description.

[0028] However, current mainstream logical equivalence point lookup methods are typically limited to logical operations within a single netlist, i.e., identifying and reconstructing logical structures only within the same level of modules, making it difficult to perform collaborative optimization across module boundaries. To address this limitation, this design proposes a cross-level logical equivalence point lookup method. This method constructs a global logical equivalence lookup table without hierarchical constraints, thereby supporting subsequent, larger-scale structural reconstruction and redundancy elimination, effectively overcoming the performance bottleneck of traditional single-level netlist optimization. This embodiment proposes a hierarchical-independent method for finding logical equivalence points. Based on the circuit netlist within the logic synthesis tool, a breadth-first traversal strategy is employed to perform a structured scan of the entire circuit netlist to identify functionally equivalent logical nodes. The entire process can be summarized into the following key steps: obtaining the driving device for netlist traversal, obtaining the actual underlying driving load, matching logically equivalent devices, and constructing a logical equivalence lookup table.

[0029] Obtain the driving device for netlist traversal: Obtain the netlist of the circuit to be processed, traverse the netlist using a breadth-first search algorithm, dynamically record the driving device for each iteration and store it in a container (queue); the initial set of driving devices consists of the input ports of the top-level netlist of the circuit. Obtain the actual underlying driving load: perform iteration, starting from the current set of driving devices, locate the load devices and input pins driven by it, and filter out the load devices whose input pins have been traversed. Matching logically equivalent devices: For these load devices, on the one hand, logical equivalence is checked based on their functional type and connection information to build or update the logical equivalence lookup table; on the other hand, their output pins are added as new driving devices to the container (queue) for the next round of iteration. Construct the logical equivalence lookup table: Repeat the above iterative process until the container is empty, that is, no new driving device is generated; at this time, the entire netlist traversal is completed, and the final logical equivalence lookup table is obtained.

[0030] The method is integrated into the logic synthesis tool and executed before the technology mapping stage. It is used for global redundancy elimination and logic cone structure optimization. The output logical equivalence lookup table is used for integrated circuit equivalence verification, providing a fast query capability from node to equivalence node set.

[0031] Specifically, the functional types of devices include, for example, AND gates, OR gates, and NOT gates. A "load device" refers to the device being driven, and a "driving device" refers to the device that drives the "load device." AND gates, OR gates, and NOT gates can all serve as either "driving devices" or "load devices." The load pins mentioned below are the direct receiving terminals of the drive signals, and the load device is the functional unit to which the load pin belongs.

[0032] Figure 1 It demonstrates a more detailed execution process, for Figure 1 The specific steps for traversing the circuit netlist in the original text have been refined and supplemented. Specifically, a method for finding cross-level logical equivalence points is provided, the method comprising: S1. Obtain the netlist of the circuit to be processed. Store the input port of the top-level netlist of the circuit as the driving device of the first iteration in the traversal process into container U. Then, container U stores other driving devices for the next iteration. S2. Traverse all driving devices in container U, and only refer to the function of the device as a driving device. S3. Obtain the driven device that has been traversed, and search in the output direction to obtain all the load pins driven by it and traverse them. S4. Obtain and mark the traversed load pins to check whether a certain load device has been traversed; and store the load device where the load pin is located in container V. S5. Determine whether the load pins driven by the current driving device have been traversed: If not, continue traversing the remaining load pins and execute S4; if traversal is complete, execute S6. S6. Determine if the driving devices in container U have been traversed: If not, continue traversing the remaining driving devices and execute S3; if traversal is complete, execute S7. S7. Traverse all load devices stored in container V, then obtain the currently traversed load device, and determine whether the input pins of the current load device are all marked: If all are marked, save the load device to container W and save the input signal information of the load device, and execute step S8; If there are unmarked pins, execute S8 directly; S8. Determine whether the load devices stored in container V have been traversed completely: If not, continue traversing the remaining load devices and execute S9; if the traversal is complete, execute S9. S9. Combining the logical equivalence lookup table, update the input information of the device and match devices with the same function and the same input information to obtain logically equivalent devices; S10. Add the same functional output of the logic equivalent device as a new logic equivalence point to the logic equivalence lookup table; S11. Determine if container W is empty (i.e., the driving queue, whether no new driving devices are generated): If it is not empty, then clear container U, store the devices in container W into container U, and execute S2 to enter the next iteration; if it is empty, it means that the netlist traversal is complete, the final logical equivalent lookup table is obtained, and the process ends.

[0033] In this field, devices can also be classified into driving devices and load devices according to the direction of signal transmission. Driving device: A device that outputs a signal; it is the source or transmitter of the signal. Load device: A device that receives a signal; it is the endpoint or receiver of the signal. The same device can function as both a driving device and a load device, depending on whether it is acting as an output or input source of the signal.

[0034] Based on the signal directions discussed in the current execution flow, the devices stored in container U are driving devices, while the devices stored in containers V and W are load devices. However, when devices stored in container W are moved to container U for the next iteration, these devices will act as driving devices. This is because it's necessary to find the load devices driven by the output signals of these devices. The current flow involves continuously searching for load devices from the input ports of the netlist, layer by layer, based on the signal direction, until the output ports are found.

[0035] Having clarified the specific traversal process, it is necessary to further focus on the key supporting points in the algorithm implementation. Each step of the traversal process relies on the accurate location of the driving device and the processing of the load device. Among them, tracing the actual underlying driving device across module boundaries and constructing the structure and function of the logical equivalence lookup table are two crucial core aspects. These will be discussed in detail below.

[0036] The first is the structure and function of logical equivalence lookup tables. Preferably, the structure of a logical equivalence lookup table is as follows: First, group all logically equivalent nodes into the same group and assign a unique index identifier to each group; Then, the lookup table maintains two sets of mapping relationships simultaneously—the forward mapping uses the index as the key to store all equivalent nodes corresponding to that index; the reverse mapping uses the node as the key to store the index of the combination to which that node belongs. This enables fast traversal of the set of equivalent nodes through the index, and also allows looking up the index information of the equivalence group to which a node belongs. Therefore, the set of equivalent nodes can be accessed quickly through the index, and the index information of the equivalence group to which any node belongs can be queried. Furthermore, after obtaining logically equivalent devices in the first iteration, the output pins of the same type of equivalent devices will be stored as logically equivalent nodes in the set of equivalent nodes; and a new index will be created for this logically equivalent node, constructing two sets of mapping relationships: forward mapping (index → ​​node set) and reverse mapping (node ​​→ index).

[0037] In this embodiment, with Figure 2 Taking ALU0 and ALU1 as examples, they satisfy the logical equivalence condition: (1) Both devices are adder units, with the same device type and the same logic function; (2) The in0 port of ALU0 and the in0 port of ALU1 are both driven by signal a, the in1 port of ALU0 and the in1 port of ALU1 are both driven by signal b, and the cin port of ALU0 and the cin port of ALU1 are both driven by signal c. That is, the corresponding pins of ALU0 and ALU1 are connected to the same signals.

[0038] Based on the above conditions, ALU0 and ALU1 can be determined to be logically equivalent devices. Furthermore, their corresponding output pins also satisfy logical equivalence: ALU0.cout is equivalent to ALU1.cout, and ALU0.sum is equivalent to ALU1.sum. Accordingly, an index 0 is created for the combination of ALU0.cout and ALU1.cout, and an index 1 is created for the combination of ALU0.sum and ALU1.sum. These two sets of mappings are added to the logical equivalence lookup table. Thus, the node set {ALU0.cout, ALU1.cout} can be retrieved through index 0, and index 0 can be located in reverse through any node in this node set; the other set of mappings is handled similarly.

[0039] Furthermore, in subsequent iterations, since the logic equivalence lookup table is no longer empty, the logic equivalence determination of devices needs to be comprehensively judged in conjunction with this lookup table. The specific process for analyzing and extracting logic information from fully driven load devices stored in container V is as follows: Figure 3 As shown. Detailed steps are as follows: A1. Traverse the devices to be processed, i.e., the load devices, in container V; A2. Obtain the load device that has been traversed, and traverse its input pins; A3. Obtain the input pins that have been traversed, and further obtain their input signals, that is, the signals that drive the pins; A4. Determine whether the signal has been entered into the logical equivalence lookup table: If the signal is not found in the logical equivalence lookup table, use the signal name as the signal information for the current input pin. If the signal exists in the logical equivalence lookup table, its corresponding index number is obtained and used as the signal information of the current input pin. A5. Determine if the input pins of the device have been traversed: If the traversal is not completed, continue traversing the remaining input pins and execute step A3; If the traversal is complete, proceed to the next step; A6. Summarize the signal information of all input pins of the device, and combine it with the device type to obtain the logic information of the device. Then, obtain the mapping relationship between the device and its logic information through the container W. A7. Determine if all devices in container V have been traversed: If the traversal is not completed, continue traversing the remaining devices and execute step A2; If the traversal is complete, proceed to the next step; A8. Obtain the logic information of all devices in the container, then end.

[0040] Preferred, with Figure 4Taking ALU2 and ALU3 as examples, the process for determining the logic equivalence of devices is explained: Traverse the input pins of ALU2 {in0,in1,cin}: the driver source of in0, ALU0.cout, exists in the logical equivalence lookup table, so its index "0" is taken as the driver information; the driver source of in1, b, is not recorded in the table, so "b" is taken directly as the driver information; the driver source of cin, ALU0.sum, exists in the lookup table, so its index "1" is taken as the driver information. By combining the above driving information with the device type, the logic information of the device can be obtained; taking string construction as an example, the logic information of ALU2 is type_alu_in0_0_in1_b_cin_1; Perform the same processing on ALU3 to obtain the same result: type_alu_in0_0_in1_b_cin_1; After establishing the mapping between devices and logic information, the logical equivalence of devices can be determined by comparing whether the logic information is consistent.

[0041] In this example, ALU2 and ALU3 have exactly the same logical information, so they are determined to be logically equivalent.

[0042] Second, it allows for cross-module access to the actual underlying drivers; In a specific net, a despin refers to the load pin at the end of the signal flow of that net. However, for a hierarchical circuit netlist, the despin identified at the current level may not be the final physical load at the bottom level—it may only be the input port of a submodule, requiring further expansion across levels to find the device pin that the signal actually drives.

[0043] For a hierarchical circuit netlist, if a pin in the current level drives a submodule instance, to obtain the actual underlying pin that the driver ultimately drives in physical implementation, it is necessary to cross the hierarchical boundary and find the internal pin or load driven by the corresponding input port in the submodule instance's internal view. Similarly, for the output port of a submodule instance, to locate the actual underlying pin that it ultimately drives in a physical sense, it is also necessary to trace back across the hierarchical boundary: trace the output port back to the driver source pin inside the submodule, and then combine the load pin of the driver source inside the submodule with the external load connected to it in the previous level to form the complete set of load endpoints for the signal.

[0044] like Figure 5As shown, in the top-level netlist, the direct load pins of input port in0 include: the first input pin of submodule sub and the second input pin of device A. However, among the above loads, only the input pin of device A is the physical endpoint; the input pins of submodule sub are merely hierarchical boundaries, and their internal views need to be further expanded to locate the actual load. In the internal view of sub, its first input port i0 (corresponding to the first input pin of top-level sub) serves as the signal starting point of this level, and the load pins it drives are actually the first input pin of device C and the first input pin of device D. In summary, the direct load of input port in0 at the top level is the first input pin of sub and the second input pin of device A; while at the physical implementation level, its final load includes the second input pin of device A, as well as the first input pins of device C and device D after being passed through sub.

[0045] Based on the above hierarchical analysis, i.e., obtaining the actual underlying driver across modules, the process for obtaining all physical load pins and corresponding load devices of a specified device can be summarized as follows: Figure 6 As shown: B1. Add all input pins of the device to container H as the initial value of the container to be processed, so that subsequent dynamic additions and acquisitions can be made. Traverse the output pins in container H.

[0046] B2. Obtain the output pins that have been traversed, and traverse their load pins; B3. Obtain the load pins that have been traversed, and find the device where the load pin is located, denoted as the load device; B4. Determine the type of the load device: If the load device is a module instance, then the input port of the corresponding load pin in the instance view needs to be obtained, and then all output pins of the input port are enqueued into container H for subsequent processing; proceed to step B6; If the load device is an output port of a non-top-level module, the corresponding output pin in the upper-level instance is located through its reference, and the pin is enqueued into container H for subsequent processing; proceed to step B6. If the load device is neither a module instance nor an output port of the top-level module, then the load pin traversed is the actual underlying driver pin, and the next step, B5, is executed.

[0047] B5. Mark the load pin and store the load device in container V; B6. Determine whether the load pins of the currently processed output pins have been traversed: If the traversal is not completed, continue traversing the remaining load pins and continue executing step B3; If the traversal is complete, proceed to the next step; B7. Determine if the output pins in container H have been traversed: If the traversal is not completed, continue traversing the remaining output pins in container H and continue executing step B2; If the traversal is complete, proceed to the next step, namely B8; B8. The devices stored in container V are all the actual driving loads of that device. End.

[0048] The containers H, U, V, and W mentioned above can be implemented as collection-type containers that support element storage and traversal, preferably queues, but linked lists, hash sets, dynamic arrays, etc. are also acceptable.

[0049] In this embodiment, to intuitively illustrate the above process, the following is combined with... Figure 7 Please provide an explanation. Figure 7 Conceptually, a flattened circuit netlist obtained by expanding the submodule view is presented. This netlist contains only basic units and has no hierarchical structure. Signal equivalence relationships are indicated by different colors: when the driving load is a submodule instance or a non-top-level output port, the actual load pin is located by tracing across levels; simultaneously, if the unit types are the same and the output signals are logically equivalent, their corresponding outputs are set to the same color, with the same color representing logically equivalent signal nodes. It should be noted that in the actual workflow, this expansion step is not performed to maintain the hierarchical information of the design.

[0050] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific implementation of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the claims of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A method for finding logical equivalence points across levels, characterized in that, The method includes: S1. Obtain the netlist of the circuit to be processed. Store the input port of the top-level netlist of the circuit as the driving device of the first iteration in the traversal process into container U. Then, store other driving devices in container U for the next iteration. S2. Traverse all driving devices in container U, and only refer to the function of the device as a driving device. S3. Obtain the driven device that has been traversed, and search in the output direction to obtain all the load pins driven by it and traverse them. S4. Obtain and mark the traversed load pins to check whether a certain load device has been traversed; and store the load device where the load pin is located in container V. S5. Determine whether the load pins driven by the current driving device have been traversed: If not, continue traversing the remaining load pins and execute S4; if traversal is complete, execute S6. S6. Determine if the driving devices in container U have been traversed: If not, continue traversing the remaining driving devices and execute S3; if traversal is complete, execute S7. S7. Traverse all load devices stored in container V, then obtain the currently traversed load device, and determine whether the input pins of the current load device are all marked: If all are marked, save the load device to container W and save the input signal information of the load device, and execute step S8; If there are unmarked pins, execute S8 directly; S8. Determine whether the load devices stored in container V have been traversed completely: If not, continue traversing the remaining load devices and execute S9; if the traversal is complete, execute S9. S9. Combining the logical equivalence lookup table, update the input information of the device and match devices with the same function and the same input information to obtain logically equivalent devices; S10. Add the same functional output of the logic equivalent device as a new logic equivalence point to the logic equivalence lookup table; S11. Determine if container W is empty: If not empty, clear container U and store the devices in container W into container U, then execute S2 to enter the next iteration; if empty, it means that the netlist traversal is complete, the final logical equivalent lookup table is obtained, and the process ends.

2. The method for finding cross-level logical equivalence points according to claim 1, characterized in that, The structure of the logical equivalence lookup table is as follows: First, group all logically equivalent nodes into the same group and assign a unique index identifier to each group; Then, the lookup table maintains two sets of mapping relationships: the forward mapping uses the index as the key and stores all equivalent nodes corresponding to that index; the reverse mapping uses the node as the key and stores the index of the combination to which that node belongs. In addition, after obtaining logically equivalent devices in the first iteration, the output pins of the same type of equivalent devices will be stored as logically equivalent nodes in the set of equivalent nodes; and a new index will be created for this logically equivalent node, constructing two sets of mapping relationships: forward mapping, i.e., index → ​​node set and reverse mapping, i.e., node → index.

3. The method for finding cross-level logical equivalence points according to claim 1, characterized in that, After the fully driven load device is stored in container V, it is analyzed and its logic information is extracted, specifically including: A1. Traverse the load devices to be processed in container V; A2. Obtain the load device that has been traversed, and traverse its input pins; A3. Obtain the input pins that have been traversed, and get their driving sources as input signals; A4. Determine whether the signal has been entered into the logical equivalence lookup table: If the signal is not found in the logical equivalence lookup table, use the signal name as the signal information for the current input pin. If the signal exists in the logical equivalence lookup table, its corresponding index number is obtained and used as the signal information of the current input pin. A5. Determine if the input pins of the device have been traversed: If the traversal is not completed, continue traversing the remaining input pins and execute step A3; If the traversal is complete, proceed to the next step; A6. Summarize the signal information of all input pins of the device, and combine it with the device type to obtain the logic information of the device. Then, obtain the mapping relationship between the device and its logic information through the container W. A7. Determine if all devices in container V have been traversed: If the traversal is not completed, continue traversing the remaining devices and execute step A2; If the traversal is complete, proceed to the next step; A8. Obtain the logic information of all devices in the container, then end.

4. The method for finding cross-level logical equivalence points according to claim 1, characterized in that, Retrieve all physical load pins and corresponding load devices for a specified device, specifically including: B1. Add all input pins of the device to container H as the initial value of the container to be processed, so that they can be dynamically added and retrieved later. Traverse the output pins in container H. B2. Obtain the output pins that have been traversed, and traverse their load pins; B3. Obtain the load pins that have been traversed, and find the device where the load pin is located, denoted as the load device; B4. Determine the type of the load device: If the load device is a module instance, then the input port of the corresponding load pin in the instance view needs to be obtained, and then all output pins of the input port are enqueued into container H for subsequent processing; proceed to step B6; If the load device is an output port of a non-top-level module, then locate the corresponding output pin in the upper-level instance through its reference, and enqueue the pin into container H for subsequent processing; proceed to step B6. If the load device is neither a module instance nor an output port of the top-level module, then the load pin that is traversed is the actual bottom-level driver pin, and the next step, B5, is executed. B5. Mark the load pin and store the load device in container V; B6. Determine whether the load pins of the currently processed output pins have been traversed: If the traversal is not completed, continue traversing the remaining load pins and continue executing step B3; If the traversal is complete, proceed to the next step; B7. Determine if the output pins in container H have been traversed: If the traversal is not completed, continue traversing the remaining output pins in container H and continue executing step B2; If the traversal is complete, proceed to the next step, namely B8; B8. The devices stored in container V are all the actual driving loads of that device. End.

5. The method for finding cross-level logical equivalence points according to claim 1, characterized in that, The method is integrated into the logic synthesis tool and executed before the technology mapping stage. It is used for global redundancy elimination and logic cone structure optimization. The output logical equivalence lookup table is used for integrated circuit equivalence verification, providing a fast query capability from node to equivalence node set.

6. The method for finding cross-level logical equivalence points according to claim 4, characterized in that, The containers H, U, V and W are queues.

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