Three-dimensional integrated circuit electro-thermal co-analysis method based on hierarchical physical constraint neural network

Abstract

The application discloses a three-dimensional integrated circuit electric-thermal collaborative analysis method based on a layered physical constraint neural network, which comprises the following steps: obtaining chip geometry, layer stacking, material and boundary parameters, and discretizing into a three-dimensional grid; extracting input features such as load distribution, temperature and mask; constructing a coarse-grained electrical and thermal model coupled with residual interaction to predict global electric potential and temperature distribution; determining a region of interest according to electric-thermal residual, gradient threshold and key device area, and outputting high-resolution results in a local window with a buffer boundary through a fine-grained model; generating pseudo-true values and residual check quantities according to an electric-thermal coupling control equation, a conservation type boundary and a consistency condition; adopting an alternating update, residual reweighting and low confidence sampling strategy in the training stage; and outputting electric potential, temperature, hot spots, voltage drop, residual confidence and design optimization prompts in the reasoning stage. Through the layered closed-loop refinement mechanism, the electric-thermal collaborative analysis efficiency of the three-dimensional IC and the heterogeneous integrated system is significantly improved.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design automation, power integrity analysis, thermal analysis, three-dimensional integrated circuit reliability analysis, and artificial intelligence-assisted circuit simulation, and particularly to a three-dimensional integrated circuit electrothermal co-analysis method based on hierarchical physical constraint neural network, boundary scenario encoding, and residual-driven local refinement. Background Technology

[0002] With the development of integrated circuit manufacturing processes and advanced packaging technologies, 3D integrated circuits have significantly improved packaging density, space utilization, and signal transmission efficiency through vertical stacking, high-density interconnects, through-silicon vias (TSVs), and micro-bump connections, gradually becoming an important technological path for high-performance computing, artificial intelligence chips, and heterogeneous integrated systems. Compared to traditional 2D integrated circuits, 3D integrated circuits can integrate more functional modules and shorten interconnect lengths within a limited area, but they also bring higher power density, more complex heat dissipation paths, and stronger electrothermal coupling effects. As process nodes continue to shrink and supply voltages continue to decrease, IR drop, local hot spots, material interface thermal resistance, and temperature-dependent conductivity changes in the power network will interact with each other, making it difficult to accurately obtain potential and temperature distributions through a single field analysis.

[0003] The main shortcomings of existing technologies are as follows: 1. Traditional electrothermal co-analysis typically requires solving electrical and thermal partial differential equations, using numerical methods such as the finite element method, finite volume method, and finite difference method. Since directly solving the coupled equations involves significant computation, engineering processes usually employ multiple iterative steps involving electrical analysis, power density calculation, thermal analysis, and conductivity updates until convergence. For large-scale 3D integrated circuits, this type of numerical solution and iterative process is time-consuming and computationally resource-intensive, making it difficult to meet the needs of rapid design iteration. 2. Existing data-driven models often rely on a large number of commercial simulation results as labels, resulting in high training data generation costs and insufficient generalization ability for new boundary conditions, material interfaces, and packaging structures. 3. Existing physical information neural network methods often employ point-by-point coordinate input and automatic differential calculation of partial derivatives, making it difficult to adapt training and inference efficiency to large-scale 3D meshes; furthermore, the weights between control equation loss and boundary loss require manual adjustment. 4. Existing coarse and fine granularity analyses focus primarily on prediction accuracy, lacking unified processing of material interfaces, TSVs, micro-bumps, thermal resistance boundaries, residual confidence levels, and active sampling, making it difficult to directly serve the engineering design closed loop.

[0004] To address the aforementioned issues and achieve efficient collaborative analysis of potential and temperature distributions in 3D integrated circuits without requiring a large amount of commercial simulation label data, while simultaneously considering electrothermal coupling physical constraints, variable boundary conditions, multi-material interfaces, multi-scale local refinement, residual confidence, and fast inference capabilities, a 3D integrated circuit electrothermal collaborative analysis method based on hierarchical physical constraint neural networks is proposed. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a three-dimensional integrated circuit electrothermal co-analysis method based on a hierarchical physical constraint neural network. It utilizes coarse-grained electrical and thermal models to rapidly predict global potential and temperature distributions. Based on the global distribution, physical residuals, gradient changes, and key device information, it locates hotspot regions, regions with severe voltage drops, or material interface-sensitive regions. Then, it employs fine-grained electrical and thermal models to perform local high-resolution analysis on these regions of interest. Simultaneously, it constructs pseudo-true values ​​based on electrothermal coupling control equations, boundary conditions, material interface flux continuity conditions, and coarse-fine granular consistency constraints, unifying control equation constraints, boundary condition constraints, residual verification, and design risk output into a trainable, inference-enabled, and resampleable process.

[0006] The objective of this invention is achieved through the following technical solution: A three-dimensional integrated circuit electrothermal co-analysis method based on hierarchical physical constraint neural networks, the method comprising the following steps: Step 1: Obtain the geometric structure, layer stacking, material parameters, electrical boundary conditions, thermal boundary conditions, external load information, and process object information of the three-dimensional integrated circuit to be analyzed, and discretize the three-dimensional integrated circuit into a three-dimensional mesh according to the preset sampling step size; Step 2: Extract boundary scenario parameters and spatial features from the electrical boundary conditions, thermal boundary conditions, external load information and process object information to form input features including external load distribution map, power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, boundary type mask, material interface map and process object mask; Step 3: Construct a coarse-grained electrical model and a coarse-grained thermal model. Input the input features into the coarse-grained electrical model and the coarse-grained thermal model respectively to obtain the global potential distribution, the global temperature distribution, and the corresponding electrical residual map and thermal residual map. Step 4: Determine the region of interest based on the global potential distribution, global temperature distribution, electrical residual map, thermal residual map, external load density obtained by aggregating the external load distribution map within a preset neighborhood, and the region corresponding to preset key device information. The preset key device information includes the spatial location and region range of one or more of the following: power supply bumps, on-chip voltage regulator output terminals, through-silicon via arrays, micro-bump arrays, power devices, memory thermal regions, and user-specified devices. Construct a fine-grained electrical model and a fine-grained thermal model. Input the coarse-grained potential distribution and coarse-grained temperature distribution corresponding to the region of interest and its buffer boundary into the fine-grained electrical model and the fine-grained thermal model, respectively, to obtain the high-resolution potential distribution and high-resolution temperature distribution of the region of interest. Step 5: Generate pseudo-true values ​​and residual verification quantities based on the electrothermal coupling control equation, electrical boundary conditions, thermal boundary conditions, material interface continuity conditions, and coarse-fine grain size consistency conditions. The pseudo-true values ​​include internal node pseudo-true values, boundary node pseudo-true values, material interface node pseudo-true values, and local window boundary pseudo-true values. Step 6: Based on the pseudo-true value and residual verification quantity, construct a coarse-grained electrical loss function, a coarse-grained thermal loss function, a fine-grained electrical loss function, a fine-grained thermal loss function, and a coarse-fine granular consistency loss function. Adopt a phased approach of first coarse-grained and then fine-grained, so that the coarse-grained electrical model and the coarse-grained thermal model, and the fine-grained electrical model and the fine-grained thermal model are trained alternately. The model parameters are updated by reweighting the residuals and supplementing the low-confidence samples. Step 7: Using the trained coarse-grained electrical model, coarse-grained thermal model, fine-grained electrical model, and fine-grained thermal model, perform electrothermal synergistic analysis on the new combination of three-dimensional integrated circuit boundary conditions, and output potential distribution, temperature distribution, voltage drop information, hot spot region information, residual confidence level, and risk warnings for design optimization.

[0007] Furthermore, step 1 specifically includes: Step 1.1: Obtain the geometric structure, layer stack, material parameters, electrical boundary conditions, thermal boundary conditions, external load information, and process object information of the three-dimensional integrated circuit to be analyzed. The process object information includes the type, location, size, and connection relationship of metal interconnect layers, through-silicon vias, microbumps, interposers, heat dissipation layers, or thermal interface materials, and establish a material property mapping and process object mapping corresponding to spatial coordinates. Step 1.2: Based on the power supply method, external load connection method, package heat dissipation method, surface heat exchange method, and process object distribution of the 3D integrated circuit to be analyzed, set electrical boundary conditions, thermal boundary conditions, and switchable boundary scenario codes, specifically including: Step 1.2.1: Set the power supply surface, power supply bump, or on-chip regulator output terminal as the Dirichlet electrical boundary, and set the potential of each node on the boundary as the power supply voltage φ0 or the local power supply potential given by the power supply network model. Step 1.2.2: Set the side surface that is not connected to an external load and is not used as a power supply terminal as an insulating electrical boundary, or set it as a weak leakage boundary according to the packaging environment, so that the potential normal derivative or equivalent leakage current on the side surface meets the preset constraints. Step 1.2.3: The surface or internal load terminal connected to the external load is set as the impedance electrical boundary, which is jointly described by the external load resistance R, the external load cross-sectional area S, the local load duty cycle, and the external load distribution diagram; wherein, it is determined by... The basic load intensity is characterized as a channel feature of the external load distribution map; Step 1.2.4: Set the thermal boundary conditions to one or more of the following: Dirichlet thermal boundary, convective thermal boundary, Neumann thermal boundary, and thermal resistance boundary. The Dirichlet thermal boundary is represented by a given temperature, the convective thermal boundary is represented by the ambient temperature and the convective heat transfer coefficient, the Neumann thermal boundary is represented by the heat flow on the target boundary surface of the three-dimensional integrated circuit, packaging structure, or heat dissipation structure to be analyzed, and the thermal resistance boundary is represented by the equivalent thermal resistance of the heat dissipation structure. Step 1.3: Discretize the three-dimensional integrated circuit to be analyzed into a three-dimensional mesh of H×M×N according to the preset sampling step size s, and represent the discretized computational domain as a structured mesh domain Dc containing node coordinates, material number, process object number and layer number; Step 1.4: Sample and align the external load, power supply, heat dissipation and key device areas on the corresponding surface or internal area of ​​the 3D mesh, so that each object position corresponds to a node, cell or local window in the 3D mesh.

[0008] Further, step 1.1 specifically includes: Step 1.1.1: Determine the length, width, height and coordinate axis direction of the three-dimensional integrated circuit. Take the vertical stacking direction as the first spatial direction, and take the two directions in the horizontal plane that are orthogonal to each other and perpendicular to the first spatial direction as the second spatial direction and the third spatial direction. Record the height range of each chip layer, dielectric layer and heat dissipation layer. Step 1.1.2: Extract the reference electrical conductivity σ0, thermal conductivity k, temperature coefficient of resistance α, reference temperature T0, anisotropic thermal conductivity parameters and interface thermal resistance parameters for each material, and associate the material parameters with the corresponding mesh nodes or mesh cells; Step 1.1.3: Determine the material regions and their stacking relationships in the three-dimensional integrated circuit to be analyzed, and identify the regions occupied by process objects such as TSV, microbumps, and interposers; wherein, each material region is a region with uniform material parameters, and multiple material regions form a multi-material stacking structure, and the process object regions and material regions are allowed to overlap in space; Step 1.1.4: Create a material numbering diagram, process object mask, and material parameter table.

[0009] Furthermore, step 2 specifically includes: Step 2.1: Perform two-dimensional or three-dimensional sampling of the external load to obtain an external load distribution map L. The load characteristics at each sampling location include the external load resistance R, the load cross-sectional area S, and the load distribution map L. Characterized by one or more of the following: base load strength, switching activity ratio, and power density prior; Step 2.2: Extract the power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, equivalent thermal resistance of heat dissipation structure, and operating condition number as scalar boundary condition parameters; Step 2.3: Establish boundary type masks and boundary scenario codes for switchable boundary conditions. When using convective boundaries, retain the ambient temperature and convective heat transfer coefficient; when using Neumann thermal boundaries, retain the surface heat flux; and when using thermal resistance boundaries, retain the thermal resistance parameters and mask parameters that are irrelevant to the current scenario. Set corresponding masks for different boundary surfaces so that multiple boundary surfaces in the same structure can use different boundary types. Step 2.4: Combine the external load distribution map, scalar boundary condition parameters, boundary type mask, material interface map, and process object mask into model input features, and construct unlabeled training samples by randomly sampling load distribution, scanning scalar boundary condition parameters, and encoding perturbation boundary scenarios.

[0010] Furthermore, step 3 specifically includes: Step 3.1: Establish coarse-grained electrical model and coarse-grained thermal model respectively. The parameters of the two are independent of each other. The two are coupled during the training process through temperature-dependent conductivity, Joule heat power density and residual verification quantity. Step 3.2: Input the power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameter, boundary type mask and operating condition number into the multilayer perceptron subnetwork, output a conditional embedding vector of preset dimension, and reshape the conditional embedding vector into a spatial conditional feature map; Step 3.3: After fusing the spatial condition feature map with the external load distribution map, material interface map and process object mask by channel, input the fusion into a convolutional neural network, a U-shaped network or a residual convolutional sub-network, and output a three-dimensional distribution map and the corresponding physical residual map. Step 3.4: For the coarse-grained electrical model, the three-dimensional distribution map is used as the voltage drop distribution or potential correction distribution, and the global potential distribution is obtained by constraining the supply voltage; for the coarse-grained thermal model, the three-dimensional distribution map is used as the temperature rise distribution or temperature correction distribution, and the global temperature distribution is obtained by constraining the ambient temperature or reference temperature.

[0011] Furthermore, step 4 specifically includes: Step 4.1: Determine the candidate regions of interest based on the extreme voltage drop locations in the global potential distribution, the hot spot locations in the global temperature distribution, the electrical residual diagram, the thermal residual diagram, the region with dense external loads, the region near the material interface, or the region of the preset key device. Step 4.2: Sort the candidate regions of interest according to the risk score, and extract local windows containing buffer boundaries from the coarse-grained potential distribution, coarse-grained temperature distribution and related input features, and set the magnification of the first direction of the horizontal plane, the magnification of the second direction of the horizontal plane and the width of the buffer boundary. Step 4.3: Input the electrical local window and thermal local window containing the candidate region of interest and its buffer boundary into the fine-grained electrical model and fine-grained thermal model, respectively. Generate electrical feature maps and thermal feature maps with the same size as the local windows through convolutional layers, residual blocks or attention modules, respectively. Add the residuals of the electrical feature maps with the coarse-grained local potential distribution and the thermal feature maps with the coarse-grained local temperature distribution, respectively. Step 4.4: Perform one or more of the following on the residual summation result: interpolation amplification, deconvolution amplification, and implicit coordinate decoding. Then, refine the result locally through a convolutional layer. Finally, add local mean or coarse-grained reference value to each channel to obtain fine-grained output. Step 4.5: The size of the fine-grained output is determined by the coarse-grained window size, the magnification in the first direction of the horizontal plane, the magnification in the second direction of the horizontal plane, and the width of the buffer boundary, and is used to represent the high-resolution potential distribution or high-resolution temperature distribution of the region of interest.

[0012] Furthermore, step 5 specifically includes: Step 5.1: Establish electrothermal coupling constraints based on DC electrical control equations, steady-state thermal control equations, temperature-dependent conductivity, Joule thermal power density, and interface flux continuity conditions. Step 5.2: Generate electrical and thermal pseudo-true values ​​for the nodes inside the three-dimensional mesh based on the discrete control equations established by the finite difference method, finite volume method, or conservation difference method. The electrical pseudo-true values ​​are obtained by combining the neighborhood potential, local conductivity, and interface equivalent parameters, while the thermal pseudo-true values ​​are obtained by combining the neighborhood temperature, local thermal conductivity, Joule heat power density, and heat source priors. Step 5.3: For boundary nodes, based on one or more of the boundary conditions corresponding to Dirichlet boundary, impedance boundary, insulation boundary, convection boundary, Neumann boundary, or thermal resistance boundary, generate global computational domain physical boundary pseudo-values ​​and fine-grained local window computational boundary pseudo-values. This ensures that boundary condition constraints, governing equation constraints, and conserved residuals are unified into the same loss function. Specifically, this includes: Step 5.3.1: For Dirichlet boundaries, directly replace the potential or temperature output by the model with the corresponding given boundary value, and exclude the Dirichlet boundary nodes in the corresponding loss term or only retain the boundary consistency verification term. Step 5.3.2: For the impedance boundary, generate the potential boundary pseudo value based on the adjacent internal node values, local conductivity, external load distribution diagram, load duty cycle and sampling step size, and generate the temperature boundary pseudo value based on the boundary Joule heat and heat flux relationship. Step 5.3.3: For insulating boundaries, convection boundaries, Neumann boundaries and thermal resistance boundaries, introduce virtual nodes on the external adjacent surfaces, or construct equivalent mirror nodes, and substitute the virtual node values ​​into the conservation difference scheme to generate pseudo-true values ​​of the boundary nodes. Step 5.3.4: For the side boundary nodes of the fine-grained region of interest, use the linear interpolation, conserved interpolation, or weighted result of the coarse-grained result as the pseudo-true value of the side boundary. For nodes in the region of interest that also belong to the coarse-grained grid, constrain the fine-grained output to be consistent with the corresponding coarse-grained output. Step 5.4: Calculate the equivalent conduction parameters for the material interface node, TSV sidewall node, micro-bump connection node, and local window buffer boundary node based on the material parameters on both sides of the interface and the coarse-grained context results, and generate corresponding pseudo-true values ​​using the equivalent conduction parameters.

[0013] Furthermore, step 6 specifically includes: Step 6.1: Construct coarse-grained electrical loss function and coarse-grained thermal loss function, calculate the error between the coarse-grained model prediction value and the corresponding coarse-grained pseudo-true value, and set the region weights according to the electrical residual map, thermal residual map and boundary scenario code; Step 6.2: Construct fine-grained electrical loss function and fine-grained thermal loss function. The fine-grained loss function includes the error between fine-grained predicted value and fine-grained pseudo-true value, the consistency error between fine-grained predicted value and corresponding coarse-grained output, and the fusion consistency error between overlapping windows. Step 6.3: In the coarse-grained training phase, only one of the coarse-grained electrical model and the coarse-grained thermal model is updated, while the parameters of the other coarse-grained model remain unchanged; in the fine-grained training phase, only one of the fine-grained electrical model and the fine-grained thermal model is updated, while the parameters of the other fine-grained model remain unchanged; after several training phases, the number of consecutive updates of the current granularity electrical model and thermal model is adjusted according to the relative magnitude of the normalized electrical coupling residual and the normalized thermal coupling residual. Step 6.4: When training a coarse-grained electrical model or a fine-grained electrical model, update the temperature-related conductivity using the temperature and material interface diagram output by the corresponding thermal model. When training a coarse-grained thermal model or a fine-grained thermal model, calculate the Joule heat power density using the potential, load duty cycle, and process object mask output by the corresponding electrical model. Step 6.5: After a preset number of training iterations, switch to the updated model until the loss function converges, the residual verification value is lower than a preset threshold, and the number of low-confidence samples no longer increases within a preset number of consecutive rounds, or the maximum number of training iterations is reached.

[0014] Furthermore, step 7 specifically includes: Step 7.1: Obtain the electrical boundary conditions, thermal boundary conditions, external load information, material interface diagram, and process object mask of the three-dimensional integrated circuit to be analyzed during the inference stage. Generate the external load distribution diagram, supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameters, and boundary type mask according to the feature extraction method consistent with the training stage. Step 7.2: Input the external load distribution diagram, power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameter, boundary type mask, material interface diagram, and process object mask into the trained coarse-grained electrical model and coarse-grained thermal model to obtain the global potential distribution, global temperature distribution, and physical residual diagram. Step 7.3: Calculate the voltage drop distribution based on the global potential distribution, and determine the temperature hotspot region based on the global temperature distribution. First, determine the grid node or connected region that meets any of the following conditions as the risk candidate region: voltage drop exceeds a preset voltage threshold, temperature exceeds a preset temperature threshold, local distribution gradient exceeds a preset gradient threshold, or physical residual exceeds a preset residual threshold. Then, determine the pre-specified key device region as the forced inclusion region, and determine the union of the risk candidate region and the forced inclusion region as the region of interest. Step 7.4: Input the coarse-grained potential distribution and coarse-grained temperature distribution corresponding to the region of interest and its buffer boundary into the trained fine-grained electrical model and fine-grained thermal model, respectively, to obtain the high-resolution potential distribution and high-resolution temperature distribution of the region of interest, and perform weighted fusion on the overlapping regions; Step 7.5: Based on the global potential distribution, global temperature distribution, high-resolution potential distribution, high-resolution temperature distribution, and physical residual map, output voltage drop information, hot spot area information, highest temperature, hot spot location, local potential gradient, local temperature gradient, residual confidence level, and risk warnings for design optimization.

[0015] This invention also provides a three-dimensional integrated circuit electrothermal co-analysis system for implementing the three-dimensional integrated circuit electrothermal co-analysis method described above, comprising: The geometry meshing module is used to acquire and mesh the geometry, layer stack, material parameters, external load information, and process object information, and generate structured mesh domains, material number diagrams, material interface diagrams, and process object masks. The boundary scenario coding module is used to extract parameters of electrical and thermal boundary conditions and generate boundary type masks, boundary scenario codes, and scalar condition features. The hierarchical physical constraint neural network module is used to run coarse-grained electrical models, coarse-grained thermal models, fine-grained electrical models, and fine-grained thermal models, and output global and local high-resolution potential and temperature distributions. The pseudo-true value generation module is used to generate various pseudo-true values ​​based on the electrothermal coupling control equation, physical boundary conditions, material interface continuity conditions, and coarse-fine grain size consistency conditions. The residual verification module is used to calculate the electrical residual map, thermal residual map, interface flux residual, coarse and fine granularity consistency residual, and the residual confidence level obtained therefrom. The attention area scheduling module is used to determine the attention area, buffer boundary, and local window based on voltage drop, temperature, residual, external load density, material interface, and key device information; The results output module is used to merge coarse-grained and fine-grained results and output voltage drop, hot spots, residual confidence level, and risk warnings for design optimization.

[0016] The beneficial effects of this invention are as follows: This invention provides a three-dimensional integrated circuit electrothermal co-analysis method based on a hierarchical physical constraint neural network. It can rapidly predict the potential and temperature distributions of three-dimensional integrated circuits by simultaneously considering electrothermal coupling control equations, variable boundary conditions, multi-material interfaces, process object distribution, residual confidence, and multi-scale local refinement analysis without requiring a large amount of commercial simulation label data. Compared with traditional electrothermal co-numerical simulation methods, this invention constructs a hierarchical analysis framework combining coarse-grained and fine-grained models. It utilizes pseudo-true values ​​to unify control equation constraints, boundary condition constraints, material interface conservation constraints, and coarse-fine granular consistency constraints. Furthermore, it employs alternating training of electrical and thermal models, residual reweighting, and low-confidence sample supplementation strategies, effectively reducing the model training's dependence on label data and manual penalty coefficient adjustment, and improving model convergence speed, training stability, and electrothermal coupling analysis accuracy. Meanwhile, this invention achieves unified processing of various boundary conditions such as Dirichlet boundaries, impedance boundaries, insulation boundaries, convection boundaries, Neumann boundaries, and thermal resistance boundaries through boundary scenario coding. Furthermore, through material interface diagrams and process object masks, the model can identify regions such as TSVs, microbumps, interposers, and thermal interface materials, enabling high-precision and high-efficiency electrothermal co-analysis for advanced packaging and 3D integrated circuit engineering scenarios. Attached Figure Description

[0017] Figure 1 This is the overall flowchart of the electrothermal synergistic analysis method of the present invention; Figure 2 This is a schematic diagram of the input feature construction and hierarchical physical constraint training framework of the present invention; Figure 3 This is a schematic diagram of the coarse-grained and fine-grained two-layer model and boundary scenario coding structure of the present invention; Figure 4 This is a schematic diagram of the pseudo-true value generation, residual reweighting, and alternating electrothermal training process of the present invention; Figure 5 This is a schematic diagram of the process of selecting the region of interest, refining the local area, and fusing the results during the inference stage of this invention. Detailed Implementation

[0018] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0019] like Figures 1 to 5 As shown, the specific implementation steps of the three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network of the present invention are as follows: Step 1: Obtain the geometry, layer stacking, material parameters, electrical boundary conditions, thermal boundary conditions, external load information, and process object information of the 3D integrated circuit to be analyzed, and discretize the 3D integrated circuit into a 3D mesh according to a preset sampling step size. The geometry includes at least length, width, height, and the outline of each layer; the layer stacking includes the arrangement and thickness of chip layers, interconnect layers, dielectric layers, packaging layers, and heat dissipation layers; the material parameters include at least reference electrical conductivity, thermal conductivity, temperature coefficient of resistance, reference temperature, anisotropic thermal conductivity parameters, contact resistance, and interface thermal resistance.

[0020] Step 1.1: Obtain the geometry, layer stack, material parameters, electrical boundary conditions, thermal boundary conditions, external load information, and process object information of the 3D integrated circuit to be analyzed. The process object information includes the type, location, size, and connection relationship of metal interconnect layers, through-silicon vias, microbumps, interposers, heat dissipation layers, or thermal interface materials, and establish a material property mapping and process object mapping corresponding to spatial coordinates. The external load information referred to in this invention refers to the spatial location, connection surface, load resistance R, effective cross-sectional area S, switching activity ratio a, local load duty cycle d, prior equivalent current or power consumption density, and optional contact resistance of the load terminal or load area connected to the power supply network. The process object information may also include power supply bumps, on-chip regulator output terminals, heat dissipation vias, and other objects that may change local electrical or thermal conductivity.

[0021] Step 1.1.1: Determine the length, width, height, and coordinate axis orientation of the 3D integrated circuit. The vertical stacking direction is designated as the first spatial direction. Two directions orthogonal to each other and perpendicular to the first spatial direction within the horizontal plane are designated as the second and third spatial directions. Record the height range of each chip layer, dielectric layer, and heat dissipation layer. For example, the vertical stacking direction can be designated as the z-direction, and the two directions within the horizontal plane as the x and y directions. The spatial range of each material region or process object can be defined by the start and end coordinates in the x, y, and z directions.

[0022] Step 1.1.2: Extract the reference electrical conductivity σ0, thermal conductivity k, temperature coefficient of resistance α, reference temperature T0, anisotropic thermal conductivity parameters, and interfacial thermal resistance parameters for each material, and associate these material parameters with the corresponding mesh nodes or mesh cells. For materials with direction-dependent thermal conductivity characteristics, k can be recorded separately. x k y and k z For metal contact surfaces, thermal interface materials, or micro-bump contact surfaces, the electrical contact resistance per unit area can also be recorded. and interfacial thermal resistance per unit area The units for both are Ω·m. 2 and m 2 ·K / W.

[0023] Step 1.1.3 identifies whether the 3D integrated circuit to be analyzed contains one or more of the following: a uniform material region, a multi-material stacked region, and a process object region containing TSVs, microbumps, or interposers. It also records the different material regions and the interface positions between the materials and the process object. These attributes are not mutually exclusive: the same 3D integrated circuit can simultaneously have multi-material stacked regions and process object regions containing TSVs or microbumps; only when the material parameters of a certain local region are consistent can that local region be marked as a uniform material region.

[0024] Step 1.1.4 establishes a material numbering map, a process object mask, and a material parameter table. This enables the subsequent pseudo-true value generation process to call the electrical conductivity, thermal conductivity, interface equivalent parameters, and object type weights of the corresponding materials based on the node location. The material numbering map provides a material index for each node or cell; the material interface map marks the locations where the material indexes of adjacent nodes change and the interface normals; the process object mask can use a multi-channel binary map or a category map to mark TSVs, micro-bumps, interposers, power supply bumps, heat dissipation structures, and key device areas, respectively.

[0025] Step 1.2: Based on the power supply method, external load connection method, package heat dissipation method, surface heat exchange method, and process object distribution of the 3D integrated circuit to be analyzed, set the electrical boundary conditions, thermal boundary conditions, and switchable boundary scenario codes. Boundary scenario coding encodes the boundary type, surface number, and effective parameters of each boundary surface into a vector or spatial mask that can be input into the model; its function is to enable the same set of models to handle different combinations of power supply, convection, given heat flow, or thermal resistance without changing the network structure.

[0026] Step 1.2.1: Set the power supply surface, power supply bump, or on-chip regulator output as the Dirichlet electrical boundary, and set the potential of each node on this boundary to the supply voltage φ0 or the local supply potential given by the power supply network model. During training, the network output of this type of node can be directly replaced with the given potential, and this type of node can be excluded in the ordinary internal node loss, or only the given value consistency check item can be retained.

[0027] Step 1.2.2: Set the side surface that is not connected to an external load and is not used as a power supply terminal as an insulating electrical boundary, or set it as a weak leakage boundary according to the packaging environment, so that the potential normal derivative or equivalent leakage current on the side surface meets the preset constraints. Let n be the unit normal vector pointing outside the computational domain. The preset constraints of the insulating boundary are: The weak leakage boundary can be written as , where g leak For the equivalent leakage conductance per unit area, φ ext This is an external reference potential. Equivalently, if This represents the current density flowing out of the computational domain along the outer normal direction, and can also be set. .

[0028] Step 1.2.3: The surface or internal load terminal connected to the external load is set as the impedance electrical boundary, which is jointly described by the external load resistance R, the external load cross-sectional area S, the local load duty cycle d, and the external load distribution diagram. The basic load strength is defined as... In essence, it is the admittance density per unit area, which can be used as a channel feature of the external load distribution map and combined with the switching activity ratio, power density prior, or other load features. Here, d∈[0,1] represents the proportion of time the load is in an effective conducting or high-power state within a preset time window; the switching activity ratio a∈[0,1] represents the proportion of effective switching activity of the corresponding node within the preset time window; the power density prior represents the spatial power estimate obtained from layout power estimation, architecture-level model, test data, or design constraints before the formal electrothermal solution. Other load features may include switching frequency, root mean square current, peak current, contact resistance, load category, and phase number; features of different dimensions are first normalized and used as independent channel inputs.

[0029] Step 1.2.4: Set the thermal boundary conditions to one or more combinations of Dirichlet thermal boundary, convective thermal boundary, Neumann thermal boundary, and thermal resistance boundary. The Dirichlet thermal boundary is represented by a given temperature; the convective thermal boundary by the ambient temperature and convective heat transfer coefficient; the Neumann thermal boundary by the given heat flux density on the target boundary surface of the 3D integrated circuit, package structure, or heat dissipation structure to be analyzed; and the thermal resistance boundary by the equivalent thermal resistance of the heat dissipation structure. Let T be the temperature of the target boundary surface, and n be the unit normal vector pointing outside the computational domain. Then, the four types of boundary conditions can be written as: Dirichlet thermal boundary T = T d ; Convective thermal boundary Neumann thermal boundary Thermal resistance boundary Among them, T d Given the temperature of the Dirichlet thermal boundary, T a The ambient fluid temperature for heat exchange with the target surface, T sink The temperature of the heat sink, cold plate, or equivalent heat sink at the other end of the thermal resistance is given by q, where h is the convective heat transfer coefficient. n For a given heat flux density flowing out of the computational domain along the outer normal direction, Equivalent thermal resistance per unit area, in meters (m). 2 • K / W; k is the thermal conductivity of the material adjacent to the target boundary.

[0030] Step 1.3: Discretize the three-dimensional integrated circuit to be analyzed into a three-dimensional mesh of H×M×N according to the preset sampling step size s, and represent the discretized computational domain as a structured mesh domain D containing node coordinates, material number, process object number, and layer number. c When using a uniform grid, it can be recorded that... If different lengths are used in the three directions, they are denoted as s respectively. x s y and s z And the step size in the corresponding direction is used in the discrete control equation.

[0031] Step 1.4 involves sampling and aligning the external loads, power supply terminals, heat dissipation terminals, and critical device regions on the corresponding surfaces or internal regions of the 3D mesh, ensuring that each object location corresponds to a node, cell, or local window in the 3D mesh. Sampling and alignment refers to mapping continuous coordinates or layout coordinates to the mesh index: point objects can use nearest node mapping, and surface or volumetric objects can use overlapping area or overlapping volume weighting; when a cell contains multiple loads, equivalent characteristics can be obtained by summing admittance, area, activity ratio, or power consumption. The critical device region, as referred to in this invention, is the area covered by the device or structure in the mesh that requires priority inspection due to power input, localized heat generation, interconnect density, temperature sensitivity, or reliability constraints; this region can be determined by the device layout range, process object bounding box, or user-defined coordinates, and at least the object category, center coordinates, bounding box, and priority must be recorded.

[0032] Step 2: Extract boundary scenario parameters and spatial features from the electrical boundary conditions, thermal boundary conditions, external load information, and process object information to form input features including an external load distribution map, supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, boundary type mask, material interface map, and process object mask. These input features are divided into two categories: spatial tensors and scalar conditions. Spatial tensors maintain the positional relationship of objects within the grid, while scalar conditions describe the current operating conditions. The external load distribution map, as used in this invention, is a two-dimensional or three-dimensional multi-channel tensor formed by recording the spatial position and load attributes of the load end according to a structured grid. Grid positions without loads are set to zero or preset no-load values, while positions with loads are written with one or more of the following: equivalent admittance density, effective cross-sectional area, activity ratio, duty cycle, or power consumption estimate. The boundary type mask, as used in this invention, is a discrete marker corresponding to a boundary surface or boundary node, used to indicate the currently effective boundary type and mask parameters that do not match that type. A single surface can use one-thermal encoding or multi-channel binary encoding, while multiple surfaces are set according to their surface numbers.

[0033] Step 2.1: Perform two-dimensional or three-dimensional sampling of the external load to obtain an external load distribution map L. The load characteristics at each sampling location include one or more of the following: external load resistance R, load cross-sectional area S, base load strength represented by 1 / (RS), switching activity ratio, and prior power density. If the load is located only on a single boundary surface, If there is also a load on the internal side, C L This represents the number of channels with load characteristics.

[0034] The external load intensity is obtained as follows: First, determine the basic load intensity at each location. Combined with the activity ratio a(p) and duty cycle d(p), this yields the equivalent load value. For example, when using a product combination, L can be taken as... eq (p)=L0(p)a(p)d(p); Power density and other prior features of different dimensions are first independently normalized and used as additional channels, and then weighted and fused only after being transformed to the same dimensionless scale. The equivalent load value is then normalized to L. n (p)∈[0,1], and spatial aggregation is performed within a preset neighborhood. The preset neighborhood can be a surface window centered on a node, a volume window, or a set of nodes within a preset radius. Therefore, this quantity is directly derived from the external load distribution map in step 2.1 and does not require additional simulation data.

[0035] Step 2.2: Extract the supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, equivalent thermal resistance of the heat dissipation structure, and operating condition number as scalar boundary condition parameters. Each parameter can be sampled continuously within the design allowable range or scanned in discrete increments; the operating condition number can be used to distinguish the working mode, heat dissipation mode, power supply mode, or test scenario.

[0036] Step 2.3 establishes boundary type masks and boundary scenario codes for switchable boundary conditions. When using convective boundaries, ambient temperature and convective heat transfer coefficient are retained; when using Neumann thermal boundaries, surface heat flux is retained; and when using thermal resistance boundaries, thermal resistance parameters are retained, while parameters irrelevant to the current scenario are masked. Corresponding masks are set for different boundary surfaces, allowing multiple boundary surfaces in the same structure to use different boundary types. For example, for a switchable surface, [m...] can be used... C ,m N ,m R The value represents three states: convection, given heat flow, and thermal resistance. The effective parameters are multiplied by the corresponding mask. When there are multiple surfaces, the surface number is encoded together with the above states.

[0037] Step 2.4 combines the external load distribution map, scalar boundary condition parameters, boundary type mask, material interface map, and process object mask into model input features, and constructs unlabeled training samples by randomly sampling the load distribution, scanning the scalar boundary condition parameters, and encoding perturbation boundary scenarios. During the training process in Step 6, low-confidence samples are filtered based on the residual confidence level to form low-confidence supplementary sampling samples. Random sampling extracts the load map from a preset statistical model, an actual workload library, or a layout power consumption map; scanning covers the scalar range in a grid, Latin hypercube, or random uniform manner; perturbation involves small deviations in boundary type, surface number, or parameters. The material interface map is obtained by differentiating the material numbers in Steps 1.1.3 and 1.1.4, and is not additional data from unknown sources. The random sampling of the load distribution, as referred to in this invention, involves randomly determining the load location, coverage size, intensity, and activity parameters within a preset allowable range, or randomly selecting a load map from an actual workload library and mapping the resulting load map onto a structured grid; each time, a set of spatial load samples is extracted. The scanning scalar boundary condition parameters referred to in this invention are parameter combinations generated from scalars such as supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, and thermal resistance parameters within their respective allowable ranges, according to a grid sequence, hierarchical random sequence, or Latin hypercube sequence. The perturbation boundary scenario coding referred to in this invention is based on a set of physically valid boundary configurations, changing at least one of the allowed boundary type set, boundary surface number, or parameter neighborhood, and simultaneously updating the corresponding mask and valid parameters, so that the perturbed coding still corresponds to an implementable boundary condition combination, rather than performing an unconstrained flip of the coding bits.

[0038] Step 3: Construct coarse-grained electrical and thermal models. Input the input features into the coarse-grained electrical and thermal models respectively to obtain the global potential distribution, global temperature distribution, and corresponding electrical and thermal residual maps. The coarse-grained model outputs a three-dimensional field across the entire computational domain at once, avoiding point-by-point network calls using spatial coordinates.

[0039] Step 3.1: Establish coarse-grained electrical and thermal models respectively. The parameters of the two models are independent of each other. They are coupled during training through temperature-dependent conductivity, Joule thermal power density, and residual calibration. Both models can use the same convolutional skeleton, or different depths, kernels, or number of channels can be used to adjust the smoothness of the potential and temperature fields.

[0040] Step 3.2: Input the supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameter, boundary type mask, and operating condition number into the multilayer perceptron subnetwork, outputting a conditional embedding vector of a preset dimension, and reshaping the conditional embedding vector into a spatial conditional feature map. The conditional embedding vector is a low-dimensional numerical representation of the global boundary scenario and operating condition; it can be reshaped into... The two-dimensional feature map is copied along the stacking direction, or directly reshaped into... The three-dimensional feature map, where C B The spatial condition feature map, as referred to in this invention, is a condition tensor obtained by projecting the scalar conditions through a multilayer perceptron and arranging, copying, or broadcasting them according to a two-dimensional or three-dimensional spatial scale of a coarse-grained grid. Each spatial location carries a condition representation of the current operating condition, and parameters for specific boundary surfaces can be written only into the corresponding surface channels. The spatial condition feature map, along with the external load distribution map, material interface map, and process object mask, is combined in the channel dimension and input into the subsequent convolutional sub-network.

[0041] Step 3.3 involves fusing the spatial condition feature map with the external load distribution map, material interface map, and process object mask by channel, and then inputting the result into a convolutional neural network, a U-shaped network, or a residual convolutional sub-network. The output is a 3D distribution map and the corresponding physical residual map. The physical residual map is a 3D diagram formed by arranging the discrete control equation residuals, boundary condition residuals, or interface flux residuals at each grid node according to their original spatial positions. It can be directly calculated by the deterministic residual calculation layer after the model, or it can be predicted by an additional residual branch and then calibrated using deterministic residuals.

[0042] Step 3.4: For the coarse-grained electrical model, the three-dimensional distribution map is used as the voltage drop distribution or potential correction distribution, and the global potential distribution is obtained by constraining the supply voltage. For the coarse-grained thermal model, the three-dimensional distribution map is used as the temperature rise distribution or temperature correction distribution, and the global temperature distribution is obtained by constraining the ambient temperature or reference temperature. The voltage drop distribution is defined as Δφ = φ0 - φ; the potential correction distribution is relative to the preset reference potential field φ. base Increment δ φ That is, φ=φ base +δ φ The temperature rise distribution is defined as ΔT = TT. a The temperature correction distribution is relative to the reference temperature field T. base The increment δT, i.e., T=T base +δT. Where T base Ambient temperature T can be used a The Dirichlet provides a given temperature or other preset reference temperature; a model selects one of these output definitions before training and keeps it consistent.

[0043] Step 3.5: Calculate the voltage drop using the global potential distribution and locate hotspots using the global temperature distribution. Simultaneously, calculate the electrical and thermal residual maps. For internal nodes p, the calculations can be performed separately. and For boundary nodes, they can be respectively... and The residuals of the alternative internal governing equations are used. All reference scales and stability terms are taken to be positive, ensuring the resulting residuals are dimensionless and non-negative. The confidence level of the nodal residuals can be taken as... , where r int To normalize the interface flux residual, r ct This represents the normalized coarse-to-fine granularity consistency residual; when a node does not belong to the corresponding interface or coarse-to-fine overlapping region, the corresponding term is set to 0. The closer c(p) is to 1, the higher the physical consistency of the node.

[0044] Step 4: Determine the region of interest based on the global potential distribution, global temperature distribution, electrical residual map, thermal residual map, external load density obtained by aggregating the external load distribution map within a preset neighborhood, and preset key device information. The preset key device information includes the spatial location and region range of power supply bumps, on-chip voltage regulator output terminals, through-silicon via arrays, micro-bump arrays, power devices, memory thermal regions, or user-specified devices. Construct a fine-grained electrical model and a fine-grained thermal model, and input the coarse-grained distribution corresponding to the region of interest and its buffer boundary into the fine-grained electrical model and the fine-grained thermal model, respectively, to obtain the high-resolution potential distribution and high-resolution temperature distribution of the region of interest. The region of interest can be one or more connected regions; multiple regions that are close to each other can be merged into the same local window. The buffer boundary referred to in this invention is a transition zone formed by extending several layers of mesh outward around the candidate region of interest; this transition zone and the candidate region of interest together constitute a fine-grained local window, used to provide neighborhood field values ​​and boundary context to the fine-grained model to reduce edge errors caused by local truncation. The buffer boundary is not a real physical boundary of the chip, package, or heat dissipation structure, and can be removed according to preset clipping rules during the fusion process.

[0045] Step 4.1: Determine candidate regions of interest based on the extreme voltage drop locations in the global potential distribution, hot spot locations in the global temperature distribution, electrical residual diagrams, thermal residual diagrams, areas with dense external loads, areas near material interfaces, or pre-defined key device areas. External load density can be determined by... Calculation, where L is a predefined neighborhood centered at node p with radius r or side length k. n (q) represents the normalized load value, w pq ≥0 indicates a distance weight. For example, it can be taken as... ,in ρ is the spatial decay scale. L After normalization, it is located between 0 and 1. Preset key components include power supply bumps, on-chip regulator outputs, TSV arrays, micro-bump arrays, high-power computing units, power devices, memory thermal areas, and user-specified components.

[0046] Step 4.2: Sort candidate regions of interest according to risk scores, and extract local windows containing buffer boundaries from coarse-grained potential distribution, coarse-grained temperature distribution, and related input features. Set the magnification factor in the first horizontal direction, the magnification factor in the second horizontal direction, and the width of the buffer boundary. Related input features include external load distribution map, boundary type mask, material interface map, process object mask, electrical residual map, thermal residual map, and the broadcast-generated power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, and thermal resistance parameters. The risk score can be... The continuous indicators with wavy lines are all normalized to 0 to 1. These represent the key component mask and the material interface mask, respectively; the weights satisfy... .

[0047] Step 4.3: Input the electrical local window and thermal local window, containing the candidate region of interest and its buffer boundary, into the fine-grained electrical model and fine-grained thermal model, respectively. The model uses one or more of the following: convolutional layers, residual blocks, and attention modules to generate feature maps with the same size as the local windows. The electrical feature map is then residually added to the coarse-grained local potential distribution, and the thermal feature map is residually added to the coarse-grained local temperature distribution. This residual addition is a baseline plus correction relationship in the network structure, used to allow the fine-grained model to primarily learn local high-frequency details not expressed by the coarse-grained results, and is not the physical residual described in Step 3.

[0048] Step 4.4 involves amplifying the residual summation result using one or more of the following methods: interpolation amplification, deconvolution amplification, and implicit coordinate decoding. This amplification is then locally refined using a convolutional layer. Finally, local mean values ​​or coarse-grained reference values ​​are added to each channel to obtain a fine-grained output. The coarse-grained reference value can be the interpolated coarse-grained field, while the local mean is the average field value of each vertical channel or material layer within the input window.

[0049] Step 4.5: The size of the fine-grained output is determined by the coarse-grained window size, the magnification β1 in the first horizontal direction, the magnification β2 in the second horizontal direction, and the buffer boundary width b, and is used to represent the high-resolution potential distribution or high-resolution temperature distribution of the region of interest. If the input window size is H×M... ' ×N ' And it only magnifies in two horizontal directions, when (M ' -1)β1 and (N ' -1) When β2 are both integers, the enlarged size can be written as If the above product is not an integer, the corresponding size is rounded to the nearest positive integer. The buffer boundary is the context region obtained by expanding the bounding box of the candidate region of interest outward by b coarse-grained mesh layers. It does not belong to the actual physical boundary and can be truncated during output.

[0050] The buffer boundary width b can be fixed at 1 to 4 coarse-grained grid layers, or it can be adaptively increased according to the residual decay at the outer edge of the candidate region until the outer ring residual is lower than the preset ratio. When multiple fine-grained windows overlap, a window function with a high center and low edge is preferred, combined with residual confidence weighting, to reduce the splicing seam; if the difference in the overlapping results exceeds the consistency threshold, the overlapping area is added back to the region of interest or the low-confidence sample pool.

[0051] Step 5: Generate pseudo-true values ​​and residual verification quantities based on the electrothermal coupling control equations, electrical boundary conditions, thermal boundary conditions, material interface continuity conditions, and coarse-grained consistency conditions. The pseudo-true values ​​include internal node pseudo-true values, boundary node pseudo-true values, material interface node pseudo-true values, and local window boundary pseudo-true values. In this paper, the pseudo-true values ​​are training targets dynamically calculated from the current prediction field and discrete physical relationships, and are not equivalent to commercial simulation labels. The residual verification quantity is the normalized deviation between the predicted value and the corresponding control equation, boundary flux, interface flux, or coarse-grained consistency relationship. The coarse-grained consistency condition, as referred to in this invention, means that at nodes with the same physical coordinates in the coarse-grained and fine-grained grids, the difference between the fine-grained predicted value and the coarse-grained predicted value or its conserved interpolation does not exceed a preset tolerance. In local window boundaries or overlapping regions, the consistency of normal current, normal heat flow, or window fusion results can be further constrained. This condition ensures continuous connection between the global field and the local refined field, but does not require that each non-coincident fine-grained node equal the coarse-grained result.

[0052] Step 5.1: Establish electrothermal coupling constraints based on the DC electrical control equations, steady-state thermal control equations, temperature-dependent conductivity, Joule heat power density, and interface flux continuity condition. The DC electrical equations are as follows: Temperature-dependent conductivity can be taken as... The steady-state thermal equation is: Joule heat power density is The interface normal is uniformly defined as pointing from material side 1 to material side 2; when there is no contact resistance or interface thermal resistance, the two sides of the material interface satisfy the following: , , as well as When there is electrical contact resistance per unit area or interfacial thermal resistance per unit area, further methods can be adopted. and Describes the jump in the field quantity, where J int and q int These are the current density and heat flux density along the interface normal, respectively.

[0053] Step 5.2: For nodes within the 3D mesh, generate electrical and thermal pseudo-true values ​​based on the discrete governing equations established using the finite difference method, finite volume method, or conservative difference method. The electrical pseudo-true values ​​are obtained from the neighborhood potential, local conductivity, and interface equivalent parameters. The thermal pseudo-true values ​​are obtained from the neighborhood temperature, local thermal conductivity, Joule heat power density, and prior heat source parameters. For node p and its neighboring nodes... Electrical conductivity and thermal conductivity can be defined as... , Thus obtain and Among them, A pq d is the equivalent conduction area between nodes. pq V is the distance between the node centers. p Let the volume be the control volume of the nodes. For a homogeneous isotropic mesh, the above equation degenerates into: and The pseudo-true values ​​are training objectives dynamically updated based on the current prediction field, discrete control equations, and boundary conditions, and do not rely on commercial simulation labels as a necessary source. Here, the electrical pseudo-true value is the central node potential target that ensures current balance in the current node neighborhood for the selected discrete electrical equations; the thermal pseudo-true value is the central node temperature target that ensures energy balance for the selected discrete thermal equations after accounting for Joule heat and other volume heat sources. Both are dynamically updated based on the current model prediction field, rather than being pre-generated labels from commercial simulation tools. In a single pseudo-true value calculation, one of the following methods can be selected based on mesh regularity, material interface processing methods, and conservation requirements: finite difference method, finite volume method, or conservation difference method, or a compatible combination can be used in different mesh regions. The heat source prior referred to in this invention is a local heat generation estimate obtained beyond the Joule heat calculation from the current potential field, based on architecture-level power consumption estimation, layout power density, device switching activity, measured temperature rise information, or design constraints. This prior can be used as an additional volume heat source term or input feature, and is set to zero when no available prior is available; therefore, it does not constitute a mandatory supervision label.

[0054] Furthermore, the Joule heat power density at the internal nodes can be calculated using the central difference method: Near load boundaries, TSVs, micro-bumps, or contact interfaces, the duty cycle, activity ratio, contact resistance loss, or preset local heat sources can be added to the total power density. , The flux discontinuities, in turn, form internal node residuals, thermal residuals, and interface residuals, respectively.

[0055] Step 5.3 generates pseudo-real values ​​for the physical boundary of the global computational domain and pseudo-real values ​​for the computational boundary of the fine-grained local window for the physical boundary nodes of the global computational domain and the computational boundary nodes of the fine-grained local window, so that boundary condition constraints, governing equation constraints, and conservation residuals are uniformly incorporated into the same loss function. The pseudo-real values ​​for the physical boundary of the global computational domain are calculated on the actual outer surface of the chip, package, or heat dissipation structure, based on one or more of the following boundary types: Dirichlet boundary, impedance boundary, insulation boundary, convection boundary, Neumann boundary, or thermal resistance boundary. The pseudo-real values ​​for the computational boundary of the fine-grained local window are constructed on the artificially truncated surface formed after truncating a local window from the global computational domain, based on interpolation of the coarse-grained prediction field, conservation correction values, or fusion values ​​of adjacent windows. The former is used to constrain the actual physical outer surface, and the latter is used to transmit global field information to the local refinement model; both act on the corresponding boundary nodes.

[0056] Step 5.3.1: For Dirichlet boundaries, directly replace the potential or temperature output by the model with the corresponding given boundary value, and exclude the Dirichlet boundary nodes or retain only the boundary consistency check term in the corresponding loss term. This ensures that the given value conditions are met by hard constraints, avoiding the need to select a larger boundary penalty coefficient.

[0057] Step 5.3.2: For the impedance boundary, generate pseudo-values ​​for the potential boundary based on adjacent internal node values, local conductivity, external load distribution diagram, load duty cycle, and sampling step size; and generate pseudo-values ​​for the temperature boundary based on the relationship between boundary Joule heat and heat flux. Let the boundary basic admittance density be... The activity ratio is a b Duty cycle is d b When using product combination, Y can be taken. b =a b d b L0. Where Y b The boundary equivalent admittance density has a normal step size of s. n The potential of adjacent internal nodes is φ i Then the pseudo-true value of the potential boundary can be taken as If the heat dissipation of the load is calculated based on the positive heat flow into the computational domain, then we can take... and When the opposite heat flow direction convention is adopted, the sign of the corresponding heat flow term is adjusted synchronously.

[0058] Step 5.3.3: For insulating boundaries, convection boundaries, Neumann boundaries, and thermal resistance boundaries, introduce virtual nodes on the external adjacent surfaces, or construct equivalent mirror nodes, and substitute the virtual node values ​​into the conservation-type difference scheme to generate pseudo-true values ​​for the boundary nodes. Let the boundary node value be φ.b or T b The internal mirror node value is φ2 or T2, and the external virtual node value is φ. g or T g For example: the insulation boundary can be taken as φ g =φ2; the weak leakage boundary can be taken as... Convection boundary can be taken Given a heat flux boundary, one can take the following values: Thermal resistance boundary can be taken as All of the above equations adopt the convention of outside normal direction in computation.

[0059] Step 5.3.4: For the side boundary nodes of the fine-grained region of interest, linear interpolation, conservative interpolation, or overlapping window weighted results from the coarse-grained results are used as pseudo-values ​​for the side boundaries. For nodes within the region of interest that also belong to the coarse-grained grid, the fine-grained output is constrained to be consistent with the corresponding coarse-grained output. Linear interpolation assigns weights according to coordinate distance; conservative interpolation corrects the total boundary current or total heat flux after interpolation; overlapping window weighted results are obtained by weighting the predicted values ​​of multiple windows at the same location according to the weights from the window center and the residual confidence. This pseudo-value for the side boundary is a pseudo-value of the local computational boundary, not a pseudo-value of the physical boundary of the actual outer surface of the chip. Specifically, when the same node is covered by two or more local windows, the predicted value of each window at that node is obtained separately, and the product of the spatial window weight and the residual confidence is used as the unnormalized weight, which is then divided by the sum of all unnormalized weights to obtain the fused value; the spatial window weight gradually decreases when the window center is large and close to the buffer edge, and the weight of the window with a lower residual confidence decreases accordingly. When only one window is covered, the predicted value of that window is directly used as the weighted result of the overlapping windows.

[0060] Step 5.4: Calculate the equivalent conduction parameters for the material interface nodes, TSV sidewall nodes, micro-bump connection nodes, and local window buffer boundary nodes based on the material parameters on both sides of the interface and the coarse-grained context results, and generate corresponding pseudo-true values ​​using these equivalent conduction parameters. For nodes adjacent in the interface normal direction, electrical equivalent conduction can be used. Thermal equivalent conduction Where A is the interface conduction area, and d1 and d2 are the distances from the centers of adjacent nodes to the interface. and These are the unit area electrical contact resistance and unit area interface thermal resistance, respectively. When there is no interface impedance, both of these are set to 0, and the result is equivalent to a distance-weighted harmonic average. For local window buffer boundary nodes, the pseudo-true value is calculated using the surface conduction parameters of the material in which it resides and coarse-grained interpolation. The coarse-grained context result referred to in this invention refers to the neighborhood information extracted from the coarse-grained model output and its derivatives around the current material interface node, process object node, or local window buffer boundary. This information may include at least one or more of the following: coarse-grained potential, coarse-grained temperature, corresponding residual, material number, interface normal, and boundary scenario parameters, used to provide far-field references and local artificial boundary conditions. The equivalent conduction parameter referred to in this invention is the surface conduction coefficient obtained by combining the material conductivity or thermal conductivity, conduction area, distance from node to interface, and contact resistance or interface thermal resistance between adjacent control volumes. It includes electrical equivalent conduction parameters and thermal equivalent conduction parameters. It characterizes the current transmission capacity or heat flow transmission capacity corresponding to a unit potential difference or a unit temperature difference between adjacent nodes, and is not equivalent to the intrinsic conductivity or thermal conductivity of a single material.

[0061] The pseudo-true values ​​are further used to generate residual verification quantities: internal node residuals are the difference between the predicted value and the internal node pseudo-true value; true physical boundary residuals are the difference between the predicted flux and the given boundary flux; material interface residuals are the difference between the normal current or heat flux on both sides of the interface; local window boundary residuals are the difference between the fine-grained side boundary value and the coarse-grained context interpolation value; and coarse-fine granularity consistency residuals are the difference between the two granularities at the overlapping nodes. Each residual is dimensionally normalized and then written into the electrical residual map, thermal residual map, or consistency residual map, respectively.

[0062] Step 6: Based on the pseudo-true value and residual verification value, construct coarse-grained electrical loss function, coarse-grained thermal loss function, fine-grained electrical loss function, fine-grained thermal loss function, and coarse-fine granular consistency loss function. Adopt a phased approach, training the coarse-grained electrical model and then the coarse-grained thermal model alternately, and the fine-grained electrical model and the fine-grained thermal model alternately. Simultaneously, update the model parameters using residual reweighting and low-confidence sample supplementation. Training can be performed sequentially in the coarse-grained stage, the fine-grained stage, and the confidence calibration stage.

[0063] Step 6.1: Construct coarse-grained electrical loss functions and coarse-grained thermal loss functions, calculate the errors between the coarse-grained model predictions and the corresponding coarse-grained pseudo-true values, and set region weights based on the electrical residual map, thermal residual map, and boundary scenario encoding. For example, one could take... and Regional weights are acceptable. , where r p For the normalized nodal residuals of the corresponding field, r mean m is the average nodal residual of the current batch.b m i and m k These are respectively the boundary, material interface, and key component masks; This is used to limit the weight of individual nodes and prevent a few outliers from dominating training.

[0064] Step 6.2: Construct fine-grained electrical loss function and fine-grained thermal loss function. The fine-grained loss function includes the error between the fine-grained predicted value and the fine-grained pseudo-true value, the consistency error between the fine-grained predicted value and the corresponding coarse-grained output, and the fusion consistency error between overlapping windows. Let... Let the mean absolute error over the region Ω be expressed as: and D f ∩D c This indicates the position in the fine-grained mesh that coincides with the coarse-grained node; when the coordinates do not completely coincide, the coarse-grained output is first conserved and interpolated to the corresponding fine-grained coordinates. E overlap Constrain the prediction consistency of different local windows in the overlapping region, E flux Heat flux is conserved at local boundaries or material interfaces; all loss coefficients are non-negative.

[0065] Step 6.3: In the coarse-grained training phase, updates alternate only between the coarse-grained electrical model and the coarse-grained thermal model; in the fine-grained training phase, updates alternate only between the fine-grained electrical model and the fine-grained thermal model; each time, only one field model at the current granularity is updated while the other field model is frozen. After several training phases, the normalized electrical coupling residual R is calculated. e and normalized thermal coupling residual R t When R e >ηR t The number of consecutive updates to the electrical model is increased as R increases. t >ηR e Increase the number of consecutive updates to the thermal model if necessary; otherwise, maintain a one-to-one update ratio. A value of 1.1 ≤ η ≤ 1.5 can be used, and the number of consecutive updates should be limited to 1 ≤ K ≤ K. max In order to avoid a single session occupying a training session for too long.

[0066] Step 6.4: When training the coarse-grained or fine-grained electrical model, update the temperature-related conductivity using the temperature and material interface diagram output by the corresponding granular thermal model; when training the coarse-grained or fine-grained thermal model, calculate the Joule heat power density using the potential, load duty cycle, and process object mask output by the corresponding granular electrical model. After the coarse-grained model converges, provide local initial values ​​and local computational boundaries for the fine-grained model, thereby avoiding optimization direction conflicts caused by simultaneous updates of the four models.

[0067] Step 6.5: After a preset number of training iterations, switch to the updated model until the following conditions are met simultaneously: loss function convergence, residual validation rate below a preset threshold, and low-confidence samples no longer increasing within a preset number of consecutive rounds, or the maximum number of training iterations is reached. To maintain consistency with the reciprocal node confidence in Step 3.5, the sample residual confidence can be defined as... , where P 95 (·) represents the 95th percentile of the corresponding normalized residuals within the sample, and the weights satisfy the following: When c s <c low When this happens, the sample is classified as a low-confidence sample; c low The confidence level can be determined by the validation set, for example, by setting it to 0.6, or by using a preset proportion of samples with the highest current residuals as low-confidence samples. The normalized complement sampling probability for low-confidence samples can be set to... Where γ>0 controls the bias intensity towards low-confidence samples, This is the current set of candidate samples. If the three conditions of loss convergence, residual achievement, and stability of low-confidence samples are not met simultaneously, then training continues alternately; when the maximum number of iterations is reached, the training stops unconditionally and the confidence warning is retained.

[0068] When reweighting residuals, the loss weight of high residual regions can be increased according to the relative magnitude of the residuals of the current batch nodes, and upper and lower limits can be used to prevent single-point dominance in training. When resampling low-confidence samples, samples with similar load density, boundary type, material interface location, or key component distribution to the original low-confidence samples can be resampled first, or local perturbations can be performed near the original parameters. If the three conditions of loss convergence, residual achievement, and low-confidence sample stability are not met simultaneously, alternating training continues. When the maximum number of iterations is reached, the training stops unconditionally and confidence alarms are retained.

[0069] Step 7: Using the trained coarse-grained electrical model, coarse-grained thermal model, fine-grained electrical model, and fine-grained thermal model, perform electrothermal co-analysis on the new combination of 3D integrated circuit boundary conditions, outputting potential distribution, temperature distribution, voltage drop information, hot spot region information, residual confidence level, and risk warnings for design optimization. The network parameters are not updated during the inference phase, but residuals and confidence levels are still calculated using discrete physical relationships.

[0070] Step 7.1: Obtain the electrical boundary conditions, thermal boundary conditions, external load information, material interface diagram, and process object mask of the 3D integrated circuit to be analyzed during the inference stage. Generate the external load distribution diagram, supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameters, and boundary type mask using the same feature extraction method as in the training stage. If the mesh size, material type, or object channel of the inference structure differs from that in the training stage, it should be adapted first through resampling, channel mapping, or the corresponding structural model.

[0071] Step 7.2: Input the external load distribution diagram, supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameters, boundary type mask, material interface diagram, and process object mask into the trained coarse-grained electrical model and coarse-grained thermal model to obtain the global potential distribution, global temperature distribution, and physical residual diagram. The electrical residual diagram and thermal residual diagram are calculated according to the normalized residual in step 3.5, and the boundary residual diagram and interface residual diagram are output simultaneously if necessary.

[0072] Step 7.3: Calculate the voltage drop distribution based on the global potential distribution, and determine the temperature hotspot regions based on the global temperature distribution. First, identify grid nodes or connected regions that meet at least one of the following conditions: voltage drop exceeding a preset voltage threshold, temperature exceeding a preset temperature threshold, local distribution gradient exceeding a preset gradient threshold, or physical residual exceeding a preset residual threshold, as risk candidate regions. Then, identify pre-specified key device regions as mandatory inclusion regions, and determine the union of the two as the region of interest. Each threshold can be an absolute threshold given by the design specifications or a high quantile threshold of the current sample; regions meeting multiple conditions can have higher risk priority. The mandatory inclusion region is not contingent on exceeding the above thresholds; its function is to ensure that power supply bumps, on-chip regulator outputs, TSV arrays, micro-bump arrays, power devices, memory thermal regions, or user-specified devices can enter fine-grained analysis even if the current predicted value does not exceed the threshold.

[0073] Step 7.4: Input the coarse-grained potential distribution and coarse-grained temperature distribution corresponding to the region of interest and its buffer boundary into the trained fine-grained electrical model and fine-grained thermal model, respectively, to obtain the high-resolution potential distribution and high-resolution temperature distribution of the region of interest, and perform weighted fusion on the overlapping regions. For node p, let the set of windows covering the node be... The prediction for the m-th window is O. m (p) Spatial weight is w m (p) The confidence level of the window residual is c m Then you can press To merge, where w m (p) It is larger at the center of the window and gradually decreases at the edge of the buffer.

[0074] Step 7.5: Based on the global potential distribution, global temperature distribution, high-resolution potential distribution, high-resolution temperature distribution, and physical residual map, output voltage drop information, hotspot region information, maximum temperature, hotspot location, local potential gradient, local temperature gradient, residual confidence level, and risk warnings for design optimization. Risk warnings may include, for example: when voltage drop exceeds limits, suggesting widening the power supply path, adding or moving power supply bumps and power supply TSVs, and reducing local current concentration; when temperature exceeds limits, suggesting adjusting the layout of high-power modules, enhancing heat sinks or thermal interface materials, and adding thermal vias; when interface flux residuals are too large, prompting a check of material parameters, contact resistance, or mesh resolution; when residual confidence is too low, prompting the activation of a larger buffer window, resampling, or a small amount of high-precision numerical simulation calibration.

[0075] In a verification embodiment, two three-dimensional integrated circuit structures were selected: the first structure had dimensions of 0.5mm × 1mm × 1mm and used a homogeneous material, while the second structure had dimensions of 0.6mm × 2mm × 2mm and contained three types of materials. A coarse-grained sampling step size of 0.05mm was used, resulting in meshes of 11×21×21 and 13×41×41, respectively. For each structure, 5000 sets of unlabeled training samples were constructed, with the supply voltage sampling from 0.8V to 1.2V, the ambient temperature sampling from 293K to 313K, and the convective heat transfer coefficient set to 500 W / (m²). 2 ·K), with 100 and 400 external loads respectively in the two structures, and load distributions of different sizes and degrees of aggregation are formed by changing the correlation length of the random field.

[0076] When using commercial finite element analysis tools as reference solutions for verification only, the average relative errors of the coarse-grained electrical and thermal models under different convection or given heat flux boundaries range from 0.10% to 0.19%, with maximum relative errors ranging from 0.54% to 1.35%. The average relative error of the fine-grained model under different magnifications also ranges from 0.10% to 0.19%, with maximum relative errors ranging from 0.59% to 1.26%. The coarse-grained GPU inference times for the first and second structures are approximately 4.70 ms and 5.20 ms, respectively, while the corresponding commercial tool solution times are approximately 27.5 s and 189 s. When the fine-grained magnification is 10, the total GPU inference time is approximately 6.38 ms and 10.40 ms, respectively, while the commercial tool solution times are approximately 158 s and 395 s.

[0077] In summary, the proposed three-dimensional integrated circuit electrothermal co-analysis method based on hierarchical physical constraint neural networks can achieve efficient, accurate, and scalable electrothermal co-analysis without relying on a large amount of labeled simulation data. This method is particularly suitable for rapid voltage drop assessment, hotspot location, interface risk identification, and reliability design optimization in three-dimensional integrated circuits, power networks, advanced packaging, chip packaging, and heterogeneous integrated systems.

[0078] Although the present invention has been described in conjunction with specific embodiments, those skilled in the art will understand that various changes, modifications, substitutions, and variations can be made to the above embodiments without departing from the spirit and essence of the invention. The scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural networks, characterized in that, The method includes the following steps: Step 1: Obtain the geometric structure, layer stacking, material parameters, electrical boundary conditions, thermal boundary conditions, external load information, and process object information of the three-dimensional integrated circuit to be analyzed, and discretize the three-dimensional integrated circuit into a three-dimensional mesh according to the preset sampling step size; Step 2: Extract boundary scenario parameters and spatial features from the electrical boundary conditions, thermal boundary conditions, external load information and process object information to form input features including external load distribution map, power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, boundary type mask, material interface map and process object mask; Step 3: Construct a coarse-grained electrical model and a coarse-grained thermal model. Input the input features into the coarse-grained electrical model and the coarse-grained thermal model respectively to obtain the global potential distribution, the global temperature distribution, and the corresponding electrical residual map and thermal residual map. Step 4: Determine the region of interest based on the global potential distribution, global temperature distribution, electrical residual map, thermal residual map, external load density obtained by aggregating the external load distribution map within a preset neighborhood, and the region corresponding to preset key device information. The preset key device information includes the spatial location and region range of one or more of the following: power supply bumps, on-chip voltage regulator output terminals, through-silicon via arrays, micro-bump arrays, power devices, memory thermal regions, and user-specified devices. Construct a fine-grained electrical model and a fine-grained thermal model. Input the coarse-grained potential distribution and coarse-grained temperature distribution corresponding to the region of interest and its buffer boundary into the fine-grained electrical model and the fine-grained thermal model, respectively, to obtain the high-resolution potential distribution and high-resolution temperature distribution of the region of interest. Step 5: Generate pseudo-true values ​​and residual verification quantities based on the electrothermal coupling control equation, electrical boundary conditions, thermal boundary conditions, material interface continuity conditions, and coarse-fine grain size consistency conditions. The pseudo-true values ​​include internal node pseudo-true values, boundary node pseudo-true values, material interface node pseudo-true values, and local window boundary pseudo-true values. Step 6: Based on the pseudo-true value and residual verification quantity, construct a coarse-grained electrical loss function, a coarse-grained thermal loss function, a fine-grained electrical loss function, a fine-grained thermal loss function, and a coarse-fine granular consistency loss function. Adopt a phased approach of first coarse-grained and then fine-grained, so that the coarse-grained electrical model and the coarse-grained thermal model, and the fine-grained electrical model and the fine-grained thermal model are trained alternately. The model parameters are updated by reweighting the residuals and supplementing the low-confidence samples. Step 7: Using the trained coarse-grained electrical model, coarse-grained thermal model, fine-grained electrical model, and fine-grained thermal model, perform electrothermal synergistic analysis on the new combination of three-dimensional integrated circuit boundary conditions, and output potential distribution, temperature distribution, voltage drop information, hot spot region information, residual confidence level, and risk warnings for design optimization.

2. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 1 specifically includes: Step 1.1: Obtain the geometric structure, layer stack, material parameters, electrical boundary conditions, thermal boundary conditions, external load information, and process object information of the three-dimensional integrated circuit to be analyzed. The process object information includes the type, location, size, and connection relationship of metal interconnect layers, through-silicon vias, microbumps, interposers, heat dissipation layers, or thermal interface materials, and establish a material property mapping and process object mapping corresponding to spatial coordinates. Step 1.2: Based on the power supply method, external load connection method, package heat dissipation method, surface heat exchange method, and process object distribution of the 3D integrated circuit to be analyzed, set electrical boundary conditions, thermal boundary conditions, and switchable boundary scenario codes, specifically including: Step 1.2.1: Set the power supply surface, power supply bump, or on-chip regulator output terminal as the Dirichlet electrical boundary, and set the potential of each node on the boundary as the power supply voltage φ0 or the local power supply potential given by the power supply network model. Step 1.2.2: Set the side surface that is not connected to an external load and is not used as a power supply terminal as an insulating electrical boundary, or set it as a weak leakage boundary according to the packaging environment, so that the potential normal derivative or equivalent leakage current on the side surface meets the preset constraints. Step 1.2.3: The surface or internal load terminal connected to the external load is set as the impedance electrical boundary, which is jointly described by the external load resistance R, the external load cross-sectional area S, the local load duty cycle, and the external load distribution diagram; wherein, it is determined by... The basic load intensity is characterized as a channel feature of the external load distribution map; Step 1.2.4: Set the thermal boundary conditions to one or more of the following: Dirichlet thermal boundary, convective thermal boundary, Neumann thermal boundary, and thermal resistance boundary. The Dirichlet thermal boundary is represented by a given temperature, the convective thermal boundary is represented by the ambient temperature and the convective heat transfer coefficient, the Neumann thermal boundary is represented by the heat flow on the target boundary surface of the three-dimensional integrated circuit, packaging structure, or heat dissipation structure to be analyzed, and the thermal resistance boundary is represented by the equivalent thermal resistance of the heat dissipation structure. Step 1.3: Discretize the three-dimensional integrated circuit to be analyzed into a three-dimensional mesh of H×M×N according to the preset sampling step size s, and represent the discretized computational domain as a structured mesh domain Dc containing node coordinates, material number, process object number and layer number; Step 1.4: Sample and align the external load, power supply, heat dissipation and key device areas on the corresponding surface or internal area of ​​the 3D mesh, so that each object position corresponds to a node, cell or local window in the 3D mesh.

3. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 2, characterized in that, Step 1.1 specifically includes: Step 1.1.1: Determine the length, width, height and coordinate axis direction of the three-dimensional integrated circuit. Take the vertical stacking direction as the first spatial direction, and take the two directions in the horizontal plane that are orthogonal to each other and perpendicular to the first spatial direction as the second spatial direction and the third spatial direction. Record the height range of each chip layer, dielectric layer and heat dissipation layer. Step 1.1.2: Extract the reference electrical conductivity σ0, thermal conductivity k, temperature coefficient of resistance α, reference temperature T0, anisotropic thermal conductivity parameters and interface thermal resistance parameters for each material, and associate the material parameters with the corresponding mesh nodes or mesh cells; Step 1.1.3: Determine the material regions and their stacking relationships in the three-dimensional integrated circuit to be analyzed, and identify the regions occupied by process objects such as TSV, microbumps, and interposers; wherein, each material region is a region with uniform material parameters, and multiple material regions form a multi-material stacking structure, and the process object regions and material regions are allowed to overlap in space; Step 1.1.4: Create a material numbering diagram, process object mask, and material parameter table.

4. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 2 specifically includes: Step 2.1: Perform two-dimensional or three-dimensional sampling of the external load to obtain an external load distribution map L. The load characteristics at each sampling location include the external load resistance R, the load cross-sectional area S, and the load distribution map L. Characterized by one or more of the following: base load strength, switching activity ratio, and power density prior. Step 2.2: Extract the power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, equivalent thermal resistance of heat dissipation structure, and operating condition number as scalar boundary condition parameters; Step 2.3: Establish boundary type masks and boundary scenario codes for switchable boundary conditions. When using convective boundaries, retain the ambient temperature and convective heat transfer coefficient; when using Neumann thermal boundaries, retain the surface heat flux; and when using thermal resistance boundaries, retain the thermal resistance parameters and mask parameters that are irrelevant to the current scenario. Set corresponding masks for different boundary surfaces so that multiple boundary surfaces in the same structure can use different boundary types. Step 2.4: Combine the external load distribution map, scalar boundary condition parameters, boundary type mask, material interface map, and process object mask into model input features, and construct unlabeled training samples by randomly sampling load distribution, scanning scalar boundary condition parameters, and encoding perturbation boundary scenarios.

5. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 3 specifically includes: Step 3.1: Establish coarse-grained electrical model and coarse-grained thermal model respectively. The parameters of the two are independent of each other. The two are coupled during the training process through temperature-dependent conductivity, Joule heat power density and residual verification quantity. Step 3.2: Input the power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameter, boundary type mask and operating condition number into the multilayer perceptron subnetwork, output a conditional embedding vector of preset dimension, and reshape the conditional embedding vector into a spatial conditional feature map; Step 3.3: After fusing the spatial condition feature map with the external load distribution map, material interface map and process object mask by channel, input the fusion into a convolutional neural network, a U-shaped network or a residual convolutional sub-network, and output a three-dimensional distribution map and the corresponding physical residual map. Step 3.4: For the coarse-grained electrical model, the three-dimensional distribution map is used as the voltage drop distribution or potential correction distribution, and the global potential distribution is obtained by constraining the supply voltage; for the coarse-grained thermal model, the three-dimensional distribution map is used as the temperature rise distribution or temperature correction distribution, and the global temperature distribution is obtained by constraining the ambient temperature or reference temperature.

6. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 4 specifically includes: Step 4.1: Determine the candidate regions of interest based on the extreme voltage drop locations in the global potential distribution, the hot spot locations in the global temperature distribution, the electrical residual diagram, the thermal residual diagram, the region with dense external loads, the region near the material interface, or the region of the preset key device. Step 4.2: Sort the candidate regions of interest according to the risk score, and extract local windows containing buffer boundaries from the coarse-grained potential distribution, coarse-grained temperature distribution and related input features, and set the magnification of the first direction of the horizontal plane, the magnification of the second direction of the horizontal plane and the width of the buffer boundary. Step 4.3: Input the electrical local window and thermal local window containing the candidate region of interest and its buffer boundary into the fine-grained electrical model and fine-grained thermal model, respectively. Generate electrical feature maps and thermal feature maps with the same size as the local windows through convolutional layers, residual blocks or attention modules, respectively. Add the residuals of the electrical feature maps with the coarse-grained local potential distribution and the thermal feature maps with the coarse-grained local temperature distribution, respectively. Step 4.4: Perform one or more of the following on the residual summation result: interpolation amplification, deconvolution amplification, and implicit coordinate decoding. Then, refine the result locally through a convolutional layer. Finally, add local mean or coarse-grained reference value to each channel to obtain fine-grained output. Step 4.5: The size of the fine-grained output is determined by the coarse-grained window size, the magnification in the first direction of the horizontal plane, the magnification in the second direction of the horizontal plane, and the width of the buffer boundary, and is used to represent the high-resolution potential distribution or high-resolution temperature distribution of the region of interest.

7. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 5 specifically includes: Step 5.1: Establish electrothermal coupling constraints based on DC electrical control equations, steady-state thermal control equations, temperature-dependent conductivity, Joule thermal power density, and interface flux continuity conditions. Step 5.2: Generate electrical and thermal pseudo-true values ​​for the nodes inside the three-dimensional mesh based on the discrete control equations established by the finite difference method, finite volume method, or conservation difference method. The electrical pseudo-true values ​​are obtained by combining the neighborhood potential, local conductivity, and interface equivalent parameters, while the thermal pseudo-true values ​​are obtained by combining the neighborhood temperature, local thermal conductivity, Joule heat power density, and heat source priors. Step 5.3: For boundary nodes, based on one or more of the boundary conditions corresponding to Dirichlet boundary, impedance boundary, insulation boundary, convection boundary, Neumann boundary, or thermal resistance boundary, generate global computational domain physical boundary pseudo-values ​​and fine-grained local window computational boundary pseudo-values. This ensures that boundary condition constraints, governing equation constraints, and conserved residuals are unified into the same loss function. Specifically, this includes: Step 5.3.1: For Dirichlet boundaries, directly replace the potential or temperature output by the model with the corresponding given boundary value, and exclude the Dirichlet boundary nodes in the corresponding loss term or only retain the boundary consistency verification term. Step 5.3.2: For the impedance boundary, generate the potential boundary pseudo value based on the adjacent internal node values, local conductivity, external load distribution diagram, load duty cycle and sampling step size, and generate the temperature boundary pseudo value based on the boundary Joule heat and heat flux relationship. Step 5.3.3: For insulating boundaries, convection boundaries, Neumann boundaries and thermal resistance boundaries, introduce virtual nodes on the external adjacent surfaces, or construct equivalent mirror nodes, and substitute the virtual node values ​​into the conservation difference scheme to generate pseudo-true values ​​of the boundary nodes. Step 5.3.4: For the side boundary nodes of the fine-grained region of interest, use the linear interpolation, conserved interpolation, or weighted result of the coarse-grained result as the pseudo-true value of the side boundary. For nodes in the region of interest that also belong to the coarse-grained grid, constrain the fine-grained output to be consistent with the corresponding coarse-grained output. Step 5.4: Calculate the equivalent conduction parameters for the material interface node, TSV sidewall node, micro-bump connection node, and local window buffer boundary node based on the material parameters on both sides of the interface and the coarse-grained context results, and generate corresponding pseudo-true values ​​using the equivalent conduction parameters.

8. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 6 specifically includes: Step 6.1: Construct coarse-grained electrical loss function and coarse-grained thermal loss function, calculate the error between the coarse-grained model prediction value and the corresponding coarse-grained pseudo-true value, and set the region weights according to the electrical residual map, thermal residual map and boundary scenario code; Step 6.2: Construct fine-grained electrical loss function and fine-grained thermal loss function. The fine-grained loss function includes the error between fine-grained predicted value and fine-grained pseudo-true value, the consistency error between fine-grained predicted value and corresponding coarse-grained output, and the fusion consistency error between overlapping windows. Step 6.3: In the coarse-grained training phase, only one of the coarse-grained electrical model and the coarse-grained thermal model is updated, while the parameters of the other coarse-grained model remain unchanged; in the fine-grained training phase, only one of the fine-grained electrical model and the fine-grained thermal model is updated, while the parameters of the other fine-grained model remain unchanged; after several training phases, the number of consecutive updates of the current granularity electrical model and thermal model is adjusted according to the relative magnitude of the normalized electrical coupling residual and the normalized thermal coupling residual. Step 6.4: When training a coarse-grained electrical model or a fine-grained electrical model, update the temperature-related conductivity using the temperature and material interface diagram output by the corresponding thermal model. When training a coarse-grained thermal model or a fine-grained thermal model, calculate the Joule heat power density using the potential, load duty cycle, and process object mask output by the corresponding electrical model. Step 6.5: After a preset number of training iterations, switch to the updated model until the loss function converges, the residual verification value is lower than a preset threshold, and the number of low-confidence samples no longer increases within a preset number of consecutive rounds, or the maximum number of training iterations is reached.

9. The three-dimensional integrated circuit electrothermal synergistic analysis method based on hierarchical physical constraint neural network according to claim 1, characterized in that, Step 7 specifically includes: Step 7.1: Obtain the electrical boundary conditions, thermal boundary conditions, external load information, material interface diagram, and process object mask of the three-dimensional integrated circuit to be analyzed during the inference stage. Generate the external load distribution diagram, supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameters, and boundary type mask according to the feature extraction method consistent with the training stage. Step 7.2: Input the external load distribution diagram, power supply voltage, ambient temperature, convective heat transfer coefficient, surface heat flux, thermal resistance parameter, boundary type mask, material interface diagram, and process object mask into the trained coarse-grained electrical model and coarse-grained thermal model to obtain the global potential distribution, global temperature distribution, and physical residual diagram. Step 7.3: Calculate the voltage drop distribution based on the global potential distribution, and determine the temperature hotspot region based on the global temperature distribution. First, determine the grid node or connected region that meets any of the following conditions as the risk candidate region: voltage drop exceeds a preset voltage threshold, temperature exceeds a preset temperature threshold, local distribution gradient exceeds a preset gradient threshold, or physical residual exceeds a preset residual threshold. Then, determine the pre-specified key device region as the forced inclusion region, and determine the union of the risk candidate region and the forced inclusion region as the region of interest. Step 7.4: Input the coarse-grained potential distribution and coarse-grained temperature distribution corresponding to the region of interest and its buffer boundary into the trained fine-grained electrical model and fine-grained thermal model, respectively, to obtain the high-resolution potential distribution and high-resolution temperature distribution of the region of interest, and perform weighted fusion on the overlapping regions; Step 7.5: Based on the global potential distribution, global temperature distribution, high-resolution potential distribution, high-resolution temperature distribution, and physical residual map, output voltage drop information, hot spot area information, highest temperature, hot spot location, local potential gradient, local temperature gradient, residual confidence level, and risk warnings for design optimization.

10. A three-dimensional integrated circuit electrothermal co-analysis system, used to implement the three-dimensional integrated circuit electrothermal co-analysis method as described in any one of claims 1-9, characterized in that, include: The geometry meshing module is used to acquire and mesh the geometry, layer stack, material parameters, external load information, and process object information, and generate structured mesh domains, material number diagrams, material interface diagrams, and process object masks. The boundary scenario coding module is used to extract parameters of electrical and thermal boundary conditions and generate boundary type masks, boundary scenario codes, and scalar condition features. The hierarchical physical constraint neural network module is used to run coarse-grained electrical models, coarse-grained thermal models, fine-grained electrical models, and fine-grained thermal models, and output global and local high-resolution potential and temperature distributions. The pseudo-true value generation module is used to generate various pseudo-true values ​​based on the electrothermal coupling control equation, physical boundary conditions, material interface continuity conditions, and coarse-fine grain size consistency conditions. The residual verification module is used to calculate the electrical residual map, thermal residual map, interface flux residual, coarse and fine granularity consistency residual, and the residual confidence level obtained therefrom. The attention area scheduling module is used to determine the attention area, buffer boundary, and local window based on voltage drop, temperature, residual, external load density, material interface, and key device information; The results output module is used to merge coarse-grained and fine-grained results and output voltage drop, hot spots, residual confidence level, and risk warnings for design optimization.

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