A parameterized integrated circuit (IP) regression verification method

Abstract

The present application relates to a kind of parameterized integrated circuit IP regression verification method, comprising: building the device under test and verification test platform, wherein the configuration parameter of device under test is defined by parameter statement, and is associated to the compilation macro in verification test platform, device under test is parameterized integrated circuit IP;The following steps are repeatedly executed for a predetermined number of rounds: start regression automation control script, randomly generate configuration parameter value in legal value range;Configuration parameter value generated by regression automation control script is passed to verification test platform;Verification test platform receives configuration parameter value by compilation macro, and is compiled by simulation tool to device under test by regression automation control script, and then device under test is instantiated;And by regression automation script, simulation tool is called to the predetermined use case of device under test instance, and the use case running result is collected.The present application effectively improves the verification completeness and efficiency of parameterized integrated circuit IP.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit IP technology, and in particular to a parametric integrated circuit IP regression verification method. Background Technology

[0002] Integrated circuit IP (Intellectual Property) refers to standardized integrated circuit functional modules that have undergone pre-design, functional verification, and are reusable. These are the fundamental units of modern chip design, capable of rapid integration into various chip systems, effectively shortening chip development cycles and reducing design costs. Parametric integrated circuit IP is a type of dedicated IP core that adds configurable parameter interfaces to conventional IP. This type of IP sets key hardware attributes such as bit width, memory depth, operating mode, timing specifications, and interface type as configurable parameters, rather than a fixed circuit structure. In practical use, designers do not need to modify the internal circuit code of the IP; they can flexibly adjust the hardware specifications and operating characteristics of the IP by configuring the corresponding parameters, adapting it to different application scenarios, performance indicators, and system architectures. Compared to fixed-specification IP, parametric integrated circuit IP is characterized by strong versatility, wide adaptability, and high reusability, making it the most widely used IP form in current large-scale integrated circuit and SoC chip design.

[0003] In the field of regression verification of parameterized integrated circuit IPs (such as asynchronous FIFO (First-In-First-Out buffer)), existing verification technologies have many inherent defects, which severely restrict the completeness and efficiency of verification of parameterized IPs. The specific technical problems are as follows: First, the parameter configuration is fixed, resulting in incomplete coverage of verification scenarios. In the traditional regression verification process, the parameters of the device under test (DUT) are fixed constants at compile time. A single regression verification can only adapt to a single fixed parameter combination, which cannot cover all legal configuration requirements of parameterized IP. It is easy to miss various boundary parameter combinations, extreme parameter combinations and other special verification scenarios, which can easily lead to verification blind spots and potential functional defects being missed.

[0004] Secondly, multi-parameter configuration verification is inefficient. For the multi-scenario verification needs of parameterized IPs, existing technologies require staff to manually write multiple sets of corresponding parameter configuration scripts and repeatedly compile and verify them for the devices under test with different parameter configurations. The overall regression verification process is cumbersome and has a long iteration cycle, making it impossible to achieve automated batch verification of multi-parameter configurations. This greatly reduces the overall efficiency of IP verification and increases R&D verification costs.

[0005] Third, there is a lack of dynamic randomization verification capability for parameters. Existing regression verification schemes only support verification of preset fixed parameter combinations and cannot dynamically generate random parameter combinations during the verification stage. This makes it difficult to simulate various extreme, marginal, and unconventional parameter adaptation scenarios in actual chip applications, and cannot fully verify the robustness of parameterized IP under extreme or marginal configurations. Hidden functional defects are difficult to detect effectively.

[0006] In summary, existing parametric integrated circuit IP regression verification technologies suffer from problems such as incomplete verification coverage, low automation, and insufficient robustness verification, failing to meet the requirements for high-precision, high-completeness, and high-efficiency IP regression verification. Summary of the Invention

[0007] To address at least some of the aforementioned problems in the prior art, the present invention provides a parametric integrated circuit IP regression verification method, comprising: Set up the device under test and the verification test platform. The configuration parameters of the device under test are defined through parameter statements and associated with the compiler macros in the verification test platform. The device under test is a parameterized integrated circuit IP. Repeat the following steps for a preset number of rounds: Start the regression automation control script to randomly generate configuration parameter values ​​within the legal value range; The generated configuration parameter values ​​are passed to the verification test platform by the regression automation control script; The verification test platform receives configuration parameter values ​​through compiler macros, and the regression automation control script calls the simulation tool to compile the device under test (DUT), thereby instantiating the DUT; and The regression automation script calls the simulation tool to execute preset regression test cases on the device under test instance and collects the test case execution results.

[0008] Furthermore, it also includes summarizing all test case execution results to generate a verification report.

[0009] Furthermore, a weighted random strategy is used to generate configuration parameter values.

[0010] Furthermore, a boundary-first randomization strategy is used to generate configuration parameter values.

[0011] Furthermore, the parameter statements are compiled by assigning values ​​to the compiler macros, thereby adjusting the configuration parameter values ​​of the device under test.

[0012] Furthermore, the configuration parameter values ​​generated by the regression automation control script are passed to the verification test platform during the compilation phase through the compiler macro definition option of the simulation tool.

[0013] Furthermore, the results of the use case execution include pass or fail.

[0014] Furthermore, simulation logs are collected after executing the preset regression test cases.

[0015] The present invention has at least the following beneficial effects: This invention establishes a dynamic mapping relationship between compiler macros in the verification test platform and the configuration parameters of the device under test (DUT). By assigning values ​​to the compiler macros, the configuration parameter values ​​of the DUT can be flexibly adjusted, thereby breaking the limitation of fixed parameters and comprehensively covering various boundary and extreme parameter combinations. There is no need to manually write parameter configuration scripts. By using regression automation scripts to drive simulation tools to perform batch tests, it realizes automated configuration, randomized adaptation and batch verification of DUT parameters, effectively improving the verification completeness and regression verification efficiency of parameterized integrated circuit IP.

[0016] This invention uses a boundary-first random strategy to randomly generate configuration parameter values, increasing the probability of boundary values ​​being selected, focusing on boundary values, fully verifying the robustness of parameterized integrated circuit IP under extreme or edge configurations, and effectively detecting hidden functional defects. Attached Figure Description

[0017] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0018] Figure 1 A flowchart of a parameterized integrated circuit IP regression verification method according to an embodiment of the present invention is shown. Detailed Implementation

[0019] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0020] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0021] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0022] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0023] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0024] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0026] This invention proposes a parameterized IP regression verification method based on compiler macro dynamic transfer, which realizes automated configuration, randomized adaptation and batch verification of the parameters of the device under test during the regression verification process, effectively improving the verification completeness and regression verification efficiency of parameterized integrated circuit IP.

[0027] Figure 1 A flowchart of a parameterized integrated circuit IP regression verification method according to an embodiment of the present invention is shown.

[0028] like Figure 1 As shown, a parameterized integrated circuit IP regression verification method includes the following steps: Step S1 involves setting up a parameterized device under test (DUT) and a verification test platform. The configuration parameters of the DUT are defined using parameter statements and linked to compiler macros in the verification test platform. By assigning values ​​to the compiler macros and compiling the parameter statements, the configuration parameter values ​​of the DUT can be adjusted.

[0029] The device under test (DUT) is a parameterized integrated circuit IP, such as an asynchronous first-in-first-out (FIFO) buffer. The configuration parameters of the FIFO include address width ADDR_WIDTH, data width DATA_WIDTH, etc.

[0030] The verification test platform receives parameter values ​​through compiler macros to instantiate the device under test, for example: parameter fifo_addr_width = `ADDR_WIDTH; parameter fifo_data_width = `DATA_WIDTH; afifo_top#(.FIFO_AW(fifo_addr_width), .FIFO_DW(fifo_data_width)) afifo_inst(...).

[0031] Step S2: Start the regression automation control script to randomly generate configuration parameter values ​​within the legal value range.

[0032] A weighted random strategy is used when generating configuration parameter values ​​to flexibly control the focus of testing. For example, a boundary-first random strategy can be used to increase the probability of boundary values ​​being selected, focusing on boundary values ​​and discovering potential boundary defects more efficiently.

[0033] The following is an example of a regression automation control script randomly generating configuration parameter values: random_number = random.randint(3, 10) # Randomly generate address width, where 3 and 10 are the lower and upper limits of the address width.

[0034] random_number0 = random.randint(1, 16384) # Randomly generate data with a bit width of 1, 16384 being the lower and upper limits of the data bit width.

[0035] In step S3, the generated configuration parameter values ​​are passed to the verification test platform during the compilation phase by the regression automation control script through the compiler macro definition option of the simulation tool.

[0036] Regression automation control scripts use command-line arguments to dynamically configure parameters, with the general form being: +define+<PARAMETER_NAME> =<random_value> .

[0037] For example, the configuration of data bit width and address bit width can be represented as: +define+DATA_WIDTH={random_number0}+define+ADDR_WIDTH={random_number}.

[0038] Step S4: The verification test platform receives the configuration parameter values ​​through the compilation macro, and the regression automation control script calls the simulation tool to compile the device under test, thereby instantiating the device under test.

[0039] Step S5: The regression automation script calls the simulation tool to execute preset regression test cases on the device under test instance, and collects the test case execution results and simulation logs.

[0040] The test case execution result can be either pass or fail. The simulation log is a stream of all text information output by the simulation tool during its execution.

[0041] Repeat steps 2 through 5 until the preset number of rounds is completed.

[0042] Step 6: Summarize all test case execution results to generate a verification report.

[0043] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A parametric integrated circuit IP regression verification method, characterized in that, include: Set up the device under test and the verification test platform. The configuration parameters of the device under test are defined through parameter statements and associated with the compiler macros in the verification test platform. The device under test is a parameterized integrated circuit IP. Repeat the following steps for a preset number of rounds: Start the regression automation control script to randomly generate configuration parameter values ​​within the legal value range; The generated configuration parameter values ​​are passed to the verification test platform by the regression automation control script; The verification test platform receives configuration parameter values ​​through compiler macros, and the regression automation control script calls the simulation tool to compile the device under test, thereby instantiating the device under test; as well as The regression automation script calls the simulation tool to execute preset regression test cases on the device under test instance and collects the test case execution results.

2. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, It also includes summarizing all test case execution results to generate a verification report.

3. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, The configuration parameter values ​​are generated using a weighted random strategy.

4. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, The configuration parameter values ​​are generated using a boundary-first randomization strategy.

5. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, The configuration parameter values ​​of the device under test are adjusted by compiling the parameter statements through the assignment of compiler macros.

6. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, The configuration parameter values ​​generated by the regression automation control script are passed to the verification test platform during the compilation phase through the compiler macro definition options of the simulation tool.

7. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, The test case execution result includes pass or fail.

8. The parametric integrated circuit IP regression verification method according to claim 1, characterized in that, Simulation logs are also collected after executing the preset regression test cases.

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