A circuit optimization method and system based on incremental equivalent saturation and process-aware cost

Abstract

The application discloses a circuit optimization method and system based on incremental equivalent saturation and process-aware cost, and belongs to the technical field of electronic design automation (EDA). The method first converts a to-be-optimized circuit into an initial equivalent graph; then, a process-aware rewriting rule set is constructed based on a target process; an incremental equivalent saturation iteration operation is performed on the equivalent graph by using the rule set, and mode matching is only performed on nodes with changed states in each iteration until convergence; finally, a process-aware cost function which comprehensively evaluates logic depth, physical constraints and area flow is used to traverse the equivalent graph, and an optimal circuit structure with minimum physical cost is extracted and a net list is generated. The application significantly reduces the time and space complexity of the algorithm, effectively breaks the limitations of the optimization order, realizes high-quality physical mapping of large-scale circuits, and solves the problems that the existing circuit optimization methods are prone to local optimization.

Description

Technical Field

[0001] This invention belongs to the field of Electronic Design Automation (EDA) technology, specifically relating to a circuit optimization method and system based on incremental equivalence saturation and process-aware cost, which can be used in the logic synthesis process of Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC). Background Technology

[0002] As the design complexity of Very Large Scale Integration (VLSI) circuits continues to increase, logic synthesis, as a crucial link connecting high-level hardware description languages ​​(such as RTL) with the underlying physical implementation, directly determines the final performance (area, power consumption, and latency) of the chip. In traditional EDA tools (such as open-source synthesis tools ABC or Yosys), circuit optimization typically employs a heuristic rewriting rule flow. However, this traditional optimization method suffers from a severe "phase ordering problem," meaning that different orders of optimization rules can lead to drastically different synthesis results. Because the optimization steps are linear, once a locally suboptimal choice is made in an upstream step, it is often irreversible in downstream steps, making the optimization process prone to getting trapped in local optima and making it difficult to find the globally optimal circuit structure in the vast design space.

[0003] In recent years, Equality Saturation (EqSat) based on E-graphs has been introduced into circuit optimization. This technique maintains multiple equivalent forms of the circuit simultaneously in a compact data structure, allowing all rewrite rules to be explored concurrently, thus fundamentally avoiding the phase ordering problem.

[0004] However, existing optimization methods for equivalent saturated circuits face two major bottlenecks in practical industrial applications:

[0005] First, the time and space overhead explodes exponentially. As the scale of circuits increases and rewriting rules are repeatedly applied, the traditional EqSat algorithm requires a full graph traversal for pattern matching in each iteration, causing the node space of the E-graph to expand rapidly, resulting in extremely high memory consumption and redundant computation time, making it difficult to handle modern industrial circuits with millions of gates.

[0006] Second, the graph extraction strategy is disconnected from the underlying physical technology. Traditional E-graphs, after saturation, require a cost function to extract the "optimal solution." Existing cost functions typically employ simple heuristic metrics (such as the total number of nodes or the size of the abstract syntax tree). However, in actual hardware (such as FPGAs), multiple logical nodes can often be packaged into the same lookup table (K-LUT). Simply pursuing the minimum number of graph nodes not only fails to accurately reflect the consumption of underlying physical resources but may also lead to increased circuit area and timing degradation after mapping.

[0007] Therefore, finding an E-graph circuit optimization method that can balance the efficiency of large-scale circuit processing and accurately address the characteristics of underlying physical processes is of great practical significance. Summary of the Invention

[0008] The purpose of this invention is to address the shortcomings of existing technologies by providing a circuit optimization method and system based on incremental equivalent saturation and process-aware cost, in order to solve the problems of huge computational resource consumption and the disconnect between optimization results and physical processes in traditional equivalent saturation methods.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] In a first aspect, the present invention provides a circuit optimization method based on incremental equivalence saturation and process-aware cost, the method comprising:

[0011] Obtain the initial logic circuit to be optimized and transform it into an initial equivalence graph containing equivalence classes and equivalence nodes;

[0012] Obtain the target process library parameters, and construct a process-aware rewrite rule set suitable for the target hardware architecture based on the parameters;

[0013] The process-aware rewriting rule set is used to perform incremental equivalence saturation iteration on the initial equivalence graph. By maintaining a worklist, pattern matching and node rewriting are performed only on the equivalence classes whose states have changed and their associated nodes in each iteration until the convergence condition is met.

[0014] On the equivalent graph that has reached the convergence condition, dynamic programming evaluation is performed using a preset process-aware cost function to extract the optimal circuit structure with the minimum physical cost; wherein, the process-aware cost function includes area flow recursive calculation, and the area flow is used to distribute the area cost of child nodes according to their fan-out number.

[0015] The extracted optimal circuit structure is converted into a gate-level netlist for the target technology library and then output.

[0016] Furthermore, the initial equivalence graph consists of several equivalence classes and equivalence nodes; wherein, the equivalence nodes represent basic logical operations or computational units in the logical network, and the equivalence class contains at least one equivalence node that is logically equivalent; equivalence nodes with the same logical semantics are grouped into the same equivalence class.

[0017] Furthermore, the incremental equivalent saturation iteration operation includes the following steps:

[0018] Add all equivalence classes in the initial equivalence graph to the working list;

[0019] In the current iteration, the rewrite rule set is applied only to the equivalence classes and their associated nodes in the work list for pattern matching.

[0020] When a match is successful, a new equivalence node is generated in the equivalence graph according to the rewriting rules, and when the new node is logically equivalent to the existing node, the disjoint-set data structure algorithm is used to merge equivalence classes.

[0021] When an equivalence class merge occurs, the consistency maintenance algorithm is triggered to restructure the internal structure of the graph, and the equivalence classes that have undergone state changes in this round are added to the working list for the next round.

[0022] Furthermore, the convergence condition includes any one of the following: the current round's working list is empty, and the equivalence graph has not generated any new equivalence nodes or equivalence class merging operations (i.e., it has reached a fully saturated state); the number of iterations reaches a preset maximum limit; the algorithm's running time reaches a preset timeout limit.

[0023] Furthermore, when the target hardware architecture is a Field Programmable Gate Array (FPGA), the process-aware cost function specifically includes:

[0024] Physical constraint violation penalty: When the number of external independent inputs of the logic cone corresponding to the node to be evaluated exceeds the upper limit K of the lookup table inputs limited by the target technology library, a preset maximum penalty value is assigned to the node so that the node is excluded in the subsequent dynamic programming process.

[0025] The Area Flow recursive computation term is used to calculate the area flow cost of a node. The calculation method is as follows: the physical area cost of the node itself is added to the area flow cost of each fan-in child node of the node divided by the total number of fan-out children of the child node in the current equivalence network.

[0026] The logical depth evaluation item is used to determine the critical path delay depth to reach the node based on the node delay model.

[0027] Furthermore, when the number of independent inputs exceeds the upper limit K of the lookup table input, the physical constraint violation penalty term assigns a maximum value to the node to eliminate the structure during the dynamic programming process.

[0028] Furthermore, when the target hardware architecture is an application-specific integrated circuit (ASIC), the process-aware cost function specifically includes:

[0029] The standard cell matching and area evaluation item is used to evaluate whether the logical subgraph rooted at the current node can match the physical logic gates in the target standard cell library. If the match is successful, the physical area of ​​the standard cell in the library is used as the basic area cost of the node. If the match is unsuccessful, a preset maximum penalty cost is assigned to the node to eliminate unrealizable structures during the dynamic programming process.

[0030] The load-aware delay evaluation item is used to calculate the delay cost of the node on the actual physical path based on the timing model in the standard cell library and the output capacitive load of the current node.

[0031] The area flow recursive calculation term is used to calculate the area flow cost value of a node. The calculation method is as follows: the physical area cost value of the node itself is added together with the area flow cost value of each fan-in child node of the node divided by the total number of fan-out children of the child node in the current equivalence network.

[0032] Furthermore, the extraction of the optimal circuit structure with the minimum physical cost specifically involves:

[0033] Traverse all equivalence classes in the equivalence graph from bottom to top, following the network topology order.

[0034] For the equivalence class currently traversed, the cost value of all equivalence nodes contained within it is calculated based on the process-aware cost function.

[0035] The equivalence node with the minimum cost value is selected as the representative node of the equivalence class under the physical mapping.

[0036] After completing the traversal of all equivalence classes and selecting representative nodes, starting from the output node of the equivalence graph, the selected representative nodes are traced from top to bottom to construct the globally optimal circuit data path, and redundant nodes and branches that were not selected are eliminated.

[0037] Secondly, the present invention provides a circuit optimization system for implementing the above method, comprising:

[0038] The circuit analysis and graphing module is used to receive the initial logic circuit to be optimized and transform it into an initial equivalence graph containing equivalence classes and equivalence nodes.

[0039] The rule configuration module is used to obtain the target process library parameters and filter and build a process-aware rewrite rule set suitable for the target hardware architecture.

[0040] The incremental equivalence saturation module is used in each iteration to maintain a working list and apply the rewriting rule set to perform pattern matching, node rewriting, and consistency maintenance only for the changed equivalence classes and their associated nodes, so as to expand the equivalence graph.

[0041] The process-aware extraction module is used to extract the optimal circuit structure with the minimum physical cost from the converged equivalence graph by using dynamic programming to calculate the node cost value from the bottom up based on the process-aware cost function that integrates area flow and physical boundary constraints. The process-aware cost function includes area flow recursive calculation, and the area flow is calculated by dividing the total area flow cost value of each fan-in child node of the current equivalence node by the fan-out number of the corresponding child node, summing the sum, and then adding it to the physical area cost value of the current node itself.

[0042] The netlist generation module is used to convert the optimal circuit structure into a gate-level netlist for the target technology library and output it.

[0043] Thirdly, the present invention provides a machine-readable storage medium, characterized in that the machine-readable storage medium stores machine-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the method described in the first aspect.

[0044] Fourthly, the present invention provides an electronic device including a processor and a memory, wherein the memory stores machine-executable instructions executable by the processor, and the processor executes the instructions to implement the method described in the first aspect.

[0045] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0046] 1. Significantly Reduced Algorithm Time and Space Complexity: This invention introduces an incremental pattern matching mechanism (Worklist and Consistency Maintenance). During the equivalence saturation iteration process, the rewriting rules are explored and updated only for the local equivalence classes whose states have changed and their associated nodes. This completely avoids the repeated traversal of the entire massive graph structure in traditional algorithms, reducing the algorithm's runtime and peak memory consumption by several orders of magnitude. This overcomes the limitation of traditional EqSat, which cannot handle ultra-large-scale netlists due to the exponential expansion of node space.

[0047] 2. Achieving true physical optimization: This invention innovatively proposes a process-aware cost function, which brings low-level physical features such as LUT input size constraints, logic path depth, and area flow to the evaluation of the high-level E-graph. This ensures that the extracted circuit structure has the true minimum area and fastest timing after physical mapping, avoiding the defect of high-level optimization being disconnected from physical implementation. This is different from traditional methods that only use the number of nodes as the optimization objective.

[0048] 3. Breaking the limitations of local optima: Relying on the incremental equivalence saturation engine, this invention eliminates the dependence on the rule execution order in traditional logic synthesis tools, and can explore various equivalent logic transformations globally in parallel with limited resources, effectively improving the synthesis quality of the final circuit. Attached Figure Description

[0049] Figure 1 This is an overall flowchart of the circuit optimization method based on incremental equivalence saturation and process-aware cost provided by the present invention;

[0050] Figure 2 This is a schematic diagram of the execution logic of the incremental equivalent saturation iteration process in one embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the dynamic programming direction for graph extraction based on the process-aware cost function in one embodiment of the present invention. Detailed Implementation

[0052] The principles and features of the circuit optimization method based on incremental equivalent saturation and process-aware cost proposed in this invention will be further described in detail below with reference to the accompanying drawings. The embodiments given are only for explaining this invention and are not intended to limit its scope. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0053] Example 1: A circuit optimization method based on incremental equivalence saturation and process-aware cost

[0054] This embodiment provides a circuit optimization method based on incremental equivalence saturation and process-aware cost, primarily used in the logic synthesis and process mapping stages of Electronic Design Automation (EDA) toolchains. Its core idea is to explore the globally optimal structure with limited computational resources through an incremental equivalence graph (E-graph) rewriting mechanism, and to extract the precise optimal solution by combining the underlying physical process characteristics. Specifically, refer to... Figure 1 The method flowchart shown in this embodiment includes the following steps:

[0055] S1: Constructing the initial equivalence graph and initializing the environment

[0056] First, the initial logic circuit to be optimized is obtained. The input receives Register Transfer Level (RTL) code or a technically independent gate-level netlist (such as an AND-NOT graph AIG or a majority-decision graph MIG) after preliminary logic simplification. Then, the system parses the input logic circuit and isomorphically transforms it into an initial equivalence graph (E-graph) data structure. The equivalence graph consists of "equivalence nodes" (E-nodes) and "equivalence classes" (E-classes). Each basic logic operation (such as AND, OR, NOT) or arithmetic unit in the circuit is instantiated as an equivalence node; nodes that are logically equivalent or semantically equivalent are grouped into the same equivalence class. Initially, since no rewriting has been performed, each equivalence class contains only one initial equivalence node.

[0057] S2: Constructing a process-aware rewriting rule set

[0058] First, the target process library parameters are obtained. When the target hardware architecture is a Field-Programmable Gate Array (FPGA), the upper limit constraint K of the lookup table input is extracted; when the target hardware architecture is an Application-Specific Integrated Circuit (ASIC), the timing and area characteristics of the standard cell library are extracted. Based on the process library parameters, the system filters and loads a "process-aware rewrite rule set" from a preset rule base. This rule set not only includes general Boolean algebra laws (such as associative law, distributive law, De Morgan's laws, etc.), but also process-friendly structural transformation rules (such as MUX reconfiguration rules or additive tree balancing rules for FPGA architectures).

[0059] To further illustrate the specific implementation of the process-aware rewriting rules, a Field-Programmable Gate Array (FPGA) with a target process of 6-input lookup table (6-LUT) architecture is used as an example. Traditional Boolean algebra rewriting rules often only focus on logic simplification, while the process-aware rewriting rule set constructed in this invention includes folding rules specific to the hardware architecture. For example, if a 4-to-1 multiplexer (MUX) logic network consisting of multiple cascaded 2-input logic gates (such as AND gates, OR gates, and NOT gates) is matched in the current equivalence graph, the system will be aware of its input boundaries: this sub-network contains a total of 4 data input terminals and 2 selection control terminals, with a total of exactly 6 external independent input signals. At this time, the system will trigger a specific MUX folding rule, directly instantiating a new equivalence node representing a single 6-LUT in the equivalence graph, and classifying the original multi-level logic network and this new node into the same equivalence class. Through this process-aware rewriting rule, the algorithm can directly fold subgraphs with deep logical levels into optimal single-node structures with a physical depth of 1 in the early stages of equivalence saturation, thereby guiding the entire equivalence graph to evolve in the direction of maximizing physical resource utilization from the source.

[0060] S3: Perform incremental equivalent saturation iteration

[0061] like Figure 2 As shown, the process-aware rewriting rule set is used to perform iterative pattern matching and rewriting operations on the initial equivalence graph. To address the spacetime explosion problem caused by full graph traversal in traditional equivalence saturation methods, this embodiment employs an incremental equivalence saturation mechanism, with the specific execution steps as follows:

[0062] S301 (Initialization): The system maintains a worklist to record target equivalence classes that were newly generated or underwent internal state changes in the previous iteration. Before the first iteration, the worklist contains all equivalence classes in the initial equivalence graph.

[0063] S302 (Local Pattern Matching): In the current iteration, the matching engine applies the rewritten rule set to perform pattern matching only for the target equivalence class and its directly associated nodes in the working list.

[0064] S303 (Node Rewriting and Merging): If a match is successful, a new equivalent node is instantiated in the equivalence graph according to the right-hand side of the corresponding rewriting rule. If the newly inserted equivalent node is logically equivalent to an existing node in the graph, the Union-Find algorithm is used to merge the equivalence classes to which these two nodes belong, normalizing them to the same root node.

[0065] S304 (Consistency Maintenance and List Update): When an equivalence class merge occurs, the system triggers the Consistency Closure algorithm to reconstruct the internal structure of the graph. This algorithm enforces that if two nodes have the same operator and their child nodes belong to the same equivalence class, then these two nodes themselves must also be merged into the same equivalence class. Subsequently, the working list for the current round is cleared, and newly generated equivalence classes or those whose state has changed due to the merge operation are added to the working list for the next round. The system repeatedly executes the above incremental iterative process until the convergence condition is met.

[0066] The convergence conditions include: (a) the current working list is empty and no new equivalent nodes or equivalence classes have been merged (i.e., the graph is fully saturated); (b) the number of iterations reaches the preset maximum limit; and (c) the algorithm's running time reaches the timeout limit.

[0067] S4: Optimal solution extraction based on process-aware cost function

[0068] like Figure 3As shown, after the equivalence graph converges, it contains a vast number of equivalent implementations of the input circuit. At this point, the system employs a dynamic programming algorithm, combined with a pre-defined "technology-aware cost function," to extract the optimal circuit structure with the minimum physical cost from the equivalence graph. The system traverses all equivalence classes in the equivalence graph from bottom to top (from main input to main output) according to the network topology. For each equivalence class, the technology cost of all equivalent nodes within it is calculated. For an embodiment targeting FPGA technology, the technology cost of node n includes the following dimensions:

[0069] (1) Physical constraint violation penalty: Evaluate whether the logic cone rooted at node n can be completely absorbed by the target process. If the number of external independent inputs of the sub-cone is greater than the upper limit K of the lookup table, then apply a preset maximum penalty weight to it to eliminate illegal physical structures from the mechanism.

[0070] (2) Area Flow Calculation: To accurately evaluate the area amortization caused by multiple fan-out nodes, the area cost of node n not only includes its own process area consumption Area(n), but also recursively accumulates all its fan-in child nodes child. i The specific formula for calculating the area flow is:

[0071]

[0072] In the above formula, the specific meanings of each variable are as follows:

[0073] n: represents the equivalent node currently undergoing process cost evaluation;

[0074] Area(n): Represents the fixed physical area cost required for node n under the target process. For example, when the target process is a Field Programmable Gate Array (FPGA), the physical area cost of a single Lookup Table (LUT) is usually preset to a constant of 1;

[0075] child i : Represents the i-th fan-in child node of node n;

[0076] AreaFlow(child i ): This represents the area flow value of the i-th fan-in child node calculated recursively from bottom to top;

[0077] Fanout(child i ): This represents the total number of fan-out nodes driven by the i-th fan-in child node in the current equivalence network.

[0078] By dividing by Fanout(child) in the above formula i By using the parameter, this system can reasonably and evenly distribute the area cost of child nodes among all their fan-out nodes. This mechanism effectively encourages multi-fan-out multiplexing of logic structures at the algebraic level, thereby guiding the subsequent optimal solution extraction module to prefer circuit structures that consume fewer actual hardware resources.

[0079] (3) Delay evaluation: The critical path delay depth to the node is calculated by combining the node delay model. The system integrates the above penalty terms, area flow and logical depth, and selects the equivalent node with the minimum synthesis process cost value from each equivalence class as the "representative node" of that class.

[0080] In another preferred embodiment of the present invention, when the target hardware architecture is an Application-Specific Integrated Circuit (ASIC), the process-aware cost function will directly call the physical parameters of the target Standard Cell Library (such as a Liberty format feature file) for evaluation. Specifically, the process cost of node n includes the following dimensions:

[0081] (1) Standard cell matching and area evaluation: Evaluate whether the logic subgraph rooted at node n can be matched with any physical logic gate (such as NAND gate, NOR gate, AND-OR-NOT composite gate, etc.) in the standard cell library. If the match is successful, its basic area cost is directly taken as the actual physical area of ​​the standard cell in the library (such as calculated in square micrometers or gate equivalent); if the subgraph cannot be covered by any standard cell in the library, a very large violation penalty weight is applied to it, and the unrealizable structure is eliminated.

[0082] (2) Load-based latency assessment (Timing / Delay): Unlike simple models that only calculate logic depth, node latency in ASIC technology depends not only on the inherent latency of the cell itself, but also on the load it drives. The cost function combines timing lookup table data from the standard cell library (such as the nonlinear delay model NLDM) to calculate the actual physical path latency of node n based on the output capacitance load of node n (estimated from the pin capacitance and interconnect capacitance of the fan-out node).

[0083] (3) Power & Area Flow: The power cost is calculated by combining the leakage current and dynamic power consumption data of the standard cell. At the same time, in order to encourage the multiple fan-out reuse of the standard cell, the comprehensive area cost of node n also adopts the recursive amortization mechanism of area flow: the area flow cost of the fan-in child node is included.

[0084] S5: Netlist Generation and Output. After traversing all equivalence classes and selecting representative nodes, the system starts from the primary outputs node of the equivalence graph and traces the selected representative nodes and their interconnections from top to bottom to construct the globally optimal circuit data path. During this process, all redundant nodes and branches that were not selected as representative nodes are automatically removed. Finally, the constructed optimal circuit structure is converted into a gate-level netlist output for the target technology library, for use in subsequent physical design processes.

[0085] Example 2: A circuit optimization system

[0086] Based on the method described in Embodiment 1, this embodiment provides a circuit optimization system, characterized by comprising: a circuit parsing and graphing module, used to receive the initial logic circuit to be optimized and convert it into an initial equivalence graph containing equivalence classes and equivalence nodes; a rule configuration module, used to obtain target process library parameters and filter and construct a process-aware rewriting rule set suitable for the target hardware architecture; an incremental equivalence saturation module, used to, in each iteration, maintain a working list and apply the rewriting rule set only to the changed equivalence classes for pattern matching, node rewriting, and consistency maintenance, thereby expanding the equivalence graph with extremely low time and space overhead; a process-aware extraction module, used to, based on a process-aware cost function that integrates area flow and physical boundary constraints, use dynamic programming to calculate the node cost value from the bottom up and select representative nodes, extracting the optimal circuit structure with the minimum physical cost from the converged equivalence graph; and a netlist generation module, used to convert the optimal circuit structure into a gate-level netlist for the target process library and output it.

[0087] Example 3: An electronic device and a storage medium

[0088] This embodiment provides an electronic device including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor. When the processor receives an execution instruction, it runs the program to implement the circuit optimization method based on incremental equivalence saturation and process-aware cost as described in Embodiment 1. The processor may be a general-purpose central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The memory configuration may include fast random access memory (RAM) and non-volatile storage media, such as solid-state drives. This embodiment also provides a machine-readable storage medium containing a series of program codes. When these codes are executed by the processor of the electronic device, the aforementioned incremental equivalence saturation, process-aware cost extraction, and netlist generation processes can be implemented.

Claims

1. A circuit optimization method based on incremental equivalence saturation and process-aware cost, characterized in that, The method includes: Obtain the initial logic circuit to be optimized and transform it into an initial equivalent graph representation. Obtain the target process library parameters, and construct a process-aware rewrite rule set containing multiple rewrite rules based on the target process library parameters; The process-aware rewrite rule set is used to perform incremental equivalence saturation iteration on the initial equivalence graph, generating and merging new equivalence nodes in each iteration until the equivalence graph reaches the convergence condition. On the equivalent graph after the convergence condition is met, a preset process-aware cost function is used for traversal and evaluation. The process-aware cost function comprehensively evaluates the area consumption, logic depth and physical constraint characteristics of the nodes in the equivalent graph, and extracts the optimal circuit structure with the minimum process-aware cost from the equivalent graph. The optimal circuit structure is converted into a gate-level netlist for the target technology library and then output.

2. The circuit optimization method based on incremental equivalence saturation and process-aware cost as described in claim 1, characterized in that, The initial equivalence graph consists of several equivalence classes and equivalence nodes; wherein, the equivalence nodes represent basic logical operations or computational units in the logical network, and the equivalence class contains at least one equivalence node that is logically equivalent; equivalence nodes with the same logical semantics are grouped into the same equivalence class.

3. The circuit optimization method based on incremental equivalence saturation and process-aware cost as described in claim 1, characterized in that, The incremental equivalent saturation iteration operation includes the following steps: Add all equivalence classes in the initial equivalence graph to the working list; In the current iteration, the rewrite rule set is applied only to the equivalence classes and their associated nodes in the work list for pattern matching. When a match is successful, a new equivalence node is generated in the equivalence graph according to the rewriting rules, and when the new node is logically equivalent to the existing node, the disjoint-set data structure algorithm is used to merge equivalence classes. When an equivalence class merge occurs, the consistency maintenance algorithm is triggered to restructure the internal structure of the graph, and the equivalence classes that have undergone state changes in this round are added to the working list for the next round.

4. The circuit optimization method based on incremental equivalence saturation and process-aware cost as described in claim 1, characterized in that, The convergence conditions include any of the following: the current round's working list is empty, and the equivalence graph has not generated any new equivalence nodes or equivalence class merging operations; the number of iterations reaches the preset maximum limit; the algorithm's running time reaches the preset timeout limit.

5. The circuit optimization method based on incremental equivalence saturation and process-aware cost according to claim 1, characterized in that, When the target hardware architecture is a field-programmable gate array (FPGA), the process-aware cost function specifically includes: Physical constraint violation penalty: When the number of external independent inputs of the logic cone corresponding to the node to be evaluated exceeds the upper limit K of the lookup table inputs limited by the target technology library, a preset maximum penalty value is assigned to the node so that the node is excluded in the subsequent dynamic programming process. The area flow recursive calculation term is used to calculate the area flow cost value of a node. The calculation method is as follows: the physical area cost value of the node itself is added to the value obtained by dividing the area flow cost value of each fan-in child node of the node by the total number of fan-out children of the child node in the current equivalence network. The logical depth evaluation item is used to determine the critical path delay depth to reach the node based on the node delay model.

6. The circuit optimization method based on incremental equivalence saturation and process-aware cost as described in claim 5, characterized in that, The physical constraint violation penalty term assigns a maximum value to the node when the number of independent inputs exceeds the upper limit K of the lookup table input, so as to eliminate the structure during the dynamic programming process.

7. The circuit optimization method based on incremental equivalence saturation and process-aware cost as described in claim 5, characterized in that, When the target hardware architecture is an application-specific integrated circuit (ASIC), the process-aware cost function specifically includes: The standard cell matching and area evaluation item is used to evaluate whether the logical subgraph rooted at the current node can match the physical logic gates in the target standard cell library. If the match is successful, the physical area of ​​the standard cell in the library is used as the basic area cost of the node. If the match is unsuccessful, a preset maximum penalty cost is assigned to the node to eliminate unrealizable structures during the dynamic programming process. The load-aware delay evaluation item is used to calculate the delay cost of the node on the actual physical path based on the timing model in the standard cell library and the output capacitive load of the current node. The area flow recursive calculation term is used to calculate the area flow cost value of a node. The calculation method is as follows: the physical area cost value of the node itself is added together with the area flow cost value of each fan-in child node of the node divided by the total number of fan-out children of the child node in the current equivalence network.

8. The circuit optimization method based on incremental equivalence saturation and process-aware cost according to claim 1, characterized in that, The extraction of the optimal circuit structure with the minimum physical cost specifically involves: Traverse all equivalence classes in the equivalence graph from bottom to top, following the network topology order. For the equivalence class currently traversed, the cost value of all equivalence nodes contained within it is calculated based on the process-aware cost function. The equivalence node with the minimum cost value is selected as the representative node of the equivalence class under the physical mapping. After completing the traversal of all equivalence classes and selecting representative nodes, starting from the output node of the equivalence graph, the selected representative nodes are traced from top to bottom to construct the globally optimal circuit data path, and redundant nodes and branches that were not selected are eliminated.

9. A circuit optimization system for implementing the method as described in any one of claims 1-8, characterized in that, include: The circuit analysis and graphing module is used to receive the initial logic circuit to be optimized and transform it into an initial equivalence graph containing equivalence classes and equivalence nodes. The rule configuration module is used to obtain the target process library parameters and filter and build a process-aware rewrite rule set suitable for the target hardware architecture. The incremental equivalence saturation module is used in each iteration to maintain a working list and apply the rewriting rule set to perform pattern matching, node rewriting, and consistency maintenance only for the changed equivalence classes and their associated nodes, so as to expand the equivalence graph. The process-aware extraction module is used to extract the optimal circuit structure with the minimum physical cost from the converged equivalence graph by using dynamic programming to calculate the node cost value from the bottom up based on the process-aware cost function that integrates area flow and physical boundary constraints. The process-aware cost function includes area flow recursive calculation, and the area flow is calculated by dividing the total area flow cost value of each fan-in child node of the current equivalence node by the fan-out number of the corresponding child node, summing the sum, and then adding it to the physical area cost value of the current node itself. The netlist generation module is used to convert the optimal circuit structure into a gate-level netlist for the target technology library and output it.

10. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to perform the method as described in any one of claims 1-8.

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