Method for redirecting key units of a chip using time sequence driving, storage medium and electronic device

Abstract

The application relates to a method for redirecting key units of a chip by using time sequence driving, which comprises the following steps: identifying and redirecting the position of the key units at the beginning of incremental layout; calculating the time sequence information of the online net and the unit based on the time sequence information of the pins obtained by static time sequence analysis; identifying the key pins according to the time sequence and position information of the pins and calculating the boundary frame of the online net; identifying the key unit according to the time sequence information of the pins where the unit is located and calculating the new center point position according to the initial center point of the unit and the position of the boundary frame; and redirecting the position of the unit to the calculated new position to optimize the time sequence. According to the application, whether the unit is a key unit is determined by the time sequence of the unit, the new position of the key unit is determined by the boundary frame of the online net, and the new position is directly redirected, so that the direct optimization of the time sequence is realized with a small calculation cost, meanwhile, other time sequence optimization means can be compatible, and the speed and effect of time sequence convergence are improved.

Description

Technical Field

[0001] This invention relates to the field of very large-scale integrated circuit design technology, and in particular to a method, storage medium and electronic device for redirecting key units of a chip using timing-driven methods. Background Technology

[0002] Integrated circuit physical design is a critical step that determines chip performance, power consumption, and yield. As the size of chip transistors continues to increase, the complexity of physical design also increases exponentially, placing higher demands on achieving timing closure. In the physical design process, placement determines the physical location of cells within the layout and plays a crucial role in timing closure.

[0003] In the physical design and placement phase of very large-scale integrated circuits (VLSI), achieving timing convergence faces severe challenges as the size of chip transistors continues to increase. Existing technologies suffer from the following specific deficiencies: First, the timing optimization technique based on wire mesh uses timing analysis tools to obtain timing violation information, then converts it into wire mesh weights and indirectly optimizes timing by weighting the wire length. Instead of directly optimizing cell positions based on timing information, the optimization process is easily affected by wire length, resulting in poor timing optimization effect.

[0004] Second, path-based optimization methods identify critical paths that pose a bottleneck to overall time-series convergence and construct mathematical programming problems to optimize the location of path units. Although the solution quality is usually high, as the design scale increases, the number of critical paths increases exponentially, and the computational scale expands rapidly, resulting in poor scalability and making it unusable in large-scale designs.

[0005] Third, differentiable optimization methods directly incorporate the temporal objective into the objective function and realize the transformation from temporal sequence to cell location gradient through gradient backpropagation. Although this directly models the correspondence between temporal sequence and cell location, it is difficult to accurately handle each step of gradient propagation when the constraints are complex. Furthermore, gradient backpropagation is extremely time-consuming when the scale is large, making it difficult to implement in commercial electronic design automation tools.

[0006] Therefore, existing technologies cannot simultaneously meet the requirements of directly optimizing timing, low computational complexity, and easy engineering implementation. There is an urgent need for an optimization method that can efficiently solve timing convergence problems under complex constraints. Summary of the Invention

[0007] Therefore, this invention aims to be applied to advanced electronic design automation tools, by identifying and redirecting key placement cells that affect timing convergence, in order to solve the problem of timing convergence difficulties of traditional placement algorithms under advanced semiconductor process nodes, thereby improving the timing performance of chip design, shortening the design cycle and reducing design iteration costs.

[0008] To address the aforementioned technical problems, this invention provides a method for redirecting critical units of a chip using timing-driven methods, comprising the following steps: Pin timing information of the chip is obtained through static timing analysis; Based on the pin timing information and the pin physical location, each net is traversed to generate the source point bounding box, sink point bounding box, and net bounding box for each net. Key units were identified based on pin timing information; Using the key units obtained from the determination, and combining them with the source and sink bounding boxes of the corresponding wire mesh, we construct the unit input bounding box and the output bounding box. The target bounding box is selected according to the priority of output bounding box first and input bounding box second. The first candidate coordinates are obtained by clamping the initial center point of the key element into the target bounding box; Calculate the Manhattan distance between the initial center point of the key unit and the first candidate coordinate. If the distance is greater than or equal to the preset movement threshold, then constrain the first candidate coordinate to the bounding box of the wire mesh associated with the unit to obtain the final target coordinate. The Manhattan distance between the initial center point of the critical unit and the final target coordinates is rechecked. If the movement threshold requirement is met, the center point of the critical unit is redirected to the final target coordinates. After all key units have been redirected, the above steps are executed iteratively until the layout timing converges.

[0009] In one embodiment of the present invention, the timing margin of a single wire net is calculated as follows: ; in, Indicates wire mesh Timing margin, This represents the set of all pins on net e. Pin indication The timing margin.

[0010] In one embodiment of the present invention, the setting of the source point bounding box, sink point bounding box, and net bounding box of the net includes the following steps: Set timing thresholds for critical pins of the net: ,in, This is the timing margin for the network. It is a controllable boundary threshold hyperparameter; The source, sink, and net bounding boxes of the initial net are invalid values; Traverse all pins in the net. If the timing margin of a pin is less than the timing threshold of a critical pin, determine that the pin is a critical pin. Expand the source point bounding box or the sink point bounding box to the pin position according to whether the pin is the source point or the sink point. If the timing margin of the net is positive and the scaling factor is greater than 0.01, calculate the scaling factor. The mesh bounding box is generated by scaling the mesh according to the scaling factor, where r is the scaling factor. This is the timing margin for the network; Update the generated source point bounding box, sink point bounding box, and net bounding box to the corresponding net.

[0011] In one embodiment of the present invention, a method for redirecting critical units of a chip using timing-driven methods is employed, wherein the determination of critical units includes: The timing margin of a computing unit is calculated using the following formula: ; in, This represents the timing margin of unit v. This represents the set of all pins of unit v. Pin indication Timing margin; If unit v is a fixed unit or the timing margin of unit v is greater than or equal to 0, it is determined to be a non-critical unit and the redirection process is skipped; the remaining units are determined to be critical units.

[0012] In one embodiment of the present invention, the steps of constructing the unit input bounding box and output bounding box include: Set timing thresholds for key pins in unit v ,in, This represents the timing margin of unit v. This is the time-series boundary threshold; Iterate through all pins in the critical unit and obtain the timing margin of the net to which the pin belongs. Only if the timing margin of the net to which the pin belongs is less than or equal to the timing threshold of the critical pin is the timing margin determined. When this happens, the pin is determined to be a critical pin; If the critical pin is a cell input pin, the cell input bounding box is expanded using the corresponding net source point bounding box; if the valid critical pin is a cell output pin, the cell output bounding box is expanded using the corresponding net sink point bounding box.

[0013] In one embodiment of the present invention, the formula for calculating the first candidate coordinates is: ; ; in, , As the initial center point x and y coordinates , , , These represent the horizontal and vertical coordinate boundaries of the target bounding box, respectively.

[0014] In one embodiment of the present invention, the initial center point is calculated. With new coordinates The formula for calculating the Manhattan distance between them is: ; in: , For new coordinates The x and y coordinates.

[0015] The present invention also provides a storage medium having a computer program stored thereon, which, when executed, implements the aforementioned redirection method.

[0016] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the redirection method when executing the computer program.

[0017] The method described above for redirecting critical units of a chip using timing-driven approach of the present invention determines whether a unit is critical by timing, determines the new position of the critical unit by the bounding box of the network, and directly redirects it to the new position. This solves the problems of insufficient directness of optimization, computational complexity, and difficulty in implementation of existing technologies. It achieves direct timing optimization with a small computational cost, while being compatible with other timing optimization methods, thus improving the speed and effectiveness of timing convergence. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a timing-driven layout flowchart of the present invention; Figure 2 This is a flowchart of the timing optimization based on key unit redirection according to the present invention; Figure 3 This is a flowchart of the method for redirecting key units of a chip using timing-driven operation according to the present invention; Figure 4 This is a structural block diagram of the timing-driven key unit redirection device of the present invention; Figure 5 This is a schematic diagram of the structure of the electronic device of the present invention; Figure 6 This is a structural diagram of the computer-readable storage medium and program module of the present invention. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0025] In time-driven layout problems, the layout problem can be viewed as a multi-objective optimization problem considering line length, density, and timing. To make the layout process smoother and more controllable, we divide the entire layout process into two stages: the initial layout stage and the incremental layout stage (e.g., ...). Figure 1 (As shown). The initial placement phase accepts input files such as netlists and timing constraints. Considering density constraints, standard cells are placed in appropriate positions to minimize line length. After the initial placement phase, a placement result is obtained that basically satisfies the density constraints and has a relatively good line length. Then, the incremental placement phase adjusts the cell positions to optimize timing without excessively disrupting the initial placement result. This incremental placement is repeated multiple times until the placement converges to obtain the final placement result.

[0026] In a time-driven incremental layout process, the incremental layout is divided into three stages: global layout, validation, and detailed layout (e.g., ...). Figure 2 (The part inside the dashed box), and consider using timing optimization methods such as net-based, path-based, and differentiable methods when performing global and detailed layouts.

[0027] This invention proposes a method for redirecting critical units of a chip using timing-driven methods. This method redirects critical units before incremental placement begins to optimize timing (e.g., ...). Figure 2 As shown in the figure, the three stages of incremental layout are then carried out. The timing optimization method based on key unit redirection does not change the existing timing optimization method. It is an incremental timing optimization method that can be used in the incremental layout process in a plug-and-play manner and has good scalability.

[0028] Circuits are generally viewed as hypergraphs. ,in For the set of all units, For the set of all nets, The pins of all units in the middle form a set The objective of the redirection method based on this invention is to utilize... Information from Find the key unit set and will Each cell position in the sequence is redirected to a new position, resulting in an updated set of cells. (The positions of key units have been updated), and the wire mesh has also been updated. Obtain the hypergraph .

[0029] Specifically, such as Figure 3 As shown, the method for redirecting critical units of a chip using timing-driven methods includes the following steps: Pin timing information of the chip is obtained through static timing analysis; Based on the pin timing information and the pin physical location, each net is traversed to generate the source point bounding box, sink point bounding box, and net bounding box for each net. Key units were identified based on pin timing information; Using the key units obtained from the determination, and combining them with the source and sink bounding boxes of the corresponding wire mesh, we construct the unit input bounding box and the output bounding box. The target bounding box is selected according to the priority of output bounding box first and input bounding box second. The first candidate coordinates are obtained by clamping the initial center point of the key element into the target bounding box; Calculate the Manhattan distance between the initial center point of the key unit and the first candidate coordinate. If the distance is greater than or equal to the preset movement threshold, then constrain the first candidate coordinate to the bounding box of the wire mesh associated with the unit to obtain the final target coordinate. The Manhattan distance between the initial center point of the critical unit and the final target coordinates is rechecked. If the movement threshold requirement is met, the center point of the critical unit is redirected to the final target coordinates. After all key units have been redirected, the above steps are executed iteratively until the layout timing converges.

[0030] The timing margin of a single wire network is calculated as follows: ; in, Indicates wire mesh Timing margin, This represents the set of all pins on net e. Pin indication The timing margin.

[0031] In this invention, the method for setting the bounding box of the nets is as follows: the inputs are the net set E, the pin set P, and the pin timing information set. Temporal boundary threshold And the scaling factor r, the output is a set of nets with updated timing information and set net bounding boxes. .

[0032] Specifically, setting the source point bounding box, sink point bounding box, and net bounding box of a wire mesh includes the following steps: Set timing thresholds for critical pins of the net: ,in, This is the timing margin for the network. This is a controllable boundary threshold hyperparameter, which is set to 0.05 in this invention; The source, sink, and net bounding boxes of the initial net are invalid values; Traverse all pins in the net. If the timing margin of a pin is less than the timing threshold of a critical pin, determine that the pin is a critical pin. Expand the source point bounding box or the sink point bounding box to the pin position according to whether the pin is the source point or the sink point. If the timing margin of the net is positive and the scaling factor is greater than 0.01, calculate the scaling factor. The mesh bounding box is generated by scaling the mesh according to the scaling factor, where r is the scaling factor. This is the timing margin for the network; Update the generated source point bounding box, sink point bounding box, and scaled mesh bounding box onto the corresponding mesh.

[0033] The scaling ratio described above can be described as follows: the wireframe is scaled according to the scaling ratio with the geometric center of the wireframe as the reference; when the scaling ratio is greater than 1, it expands outward, and when the scaling ratio is greater than 0 and less than 1, it shrinks towards the center.

[0034] The key element location redirection method is as follows: the input is a standard element. Standard unit pin set Timing and bounding box information of the network to which each pin is located (including source point bounding box) Sinkpoint bounding box and wire mesh boundary frame ), Unit pin timing information set Temporal boundary threshold and movement threshold The output is the standard cell after position redirection. The core idea of ​​this method is to use the bounding box information of the wire mesh to guide the critical units to move towards the time-critical region, so as to shorten the physical distance on the critical path as much as possible, thereby optimizing the timing.

[0035] Specifically, the determination of key units includes: The timing margin of a computing unit is calculated using the following formula: ; in, This represents the timing margin of unit v. This represents the set of all pins of the unit v. Pin indication The timing margin; This calculation method takes the smallest timing margin among all pins of the unit as the timing margin of the unit, which means that as long as there is any critical pin (the timing margin is negative) on the unit, the unit is identified as a potential timing bottleneck.

[0036] The process for determining whether a cell needs relocation is as follows: if the cell is a fixed, immovable cell or the timing margin of a standard cell v is greater than or equal to 0, it is considered a non-critical cell and does not require location relocation, thus skipping the relocation process; the remaining cells are considered critical cells. This condition ensures that only standard cells that constitute an actual bottleneck to timing convergence and whose physical location is adjustable will enter the subsequent location relocation process, thereby avoiding unnecessary computational overhead and excessive disturbance to the layout results.

[0037] Specifically, the steps for constructing the cell input bounding box and output bounding box include: Setting a timing threshold for critical pins within a cell is used to filter out non-critical pins within the cell. ,in, This represents the timing margin of unit v. The timing boundary threshold is set to 0.2 in this invention; Iterate through all pins in the critical unit and obtain the timing margin of the net to which the pin belongs. Only if the timing margin of the net to which the pin belongs is less than or equal to the timing threshold of the critical pin is the timing margin determined. When this happens, the pin is determined to be a critical pin; If the critical pin is a cell input pin, the cell input bounding box is expanded using the corresponding net source point bounding box; if the valid critical pin is a cell output pin, the cell output bounding box is expanded using the corresponding net sink point bounding box.

[0038] In the above steps, when the timing margin of the network to which the pin is located... Greater than Pins that are considered non-critical do not require updating input and output bounding boxes with their relevant information (the net timing margin is used instead of individual pin timing margin because the net timing margin already reflects the worst timing condition of the net, and non-critical pins can be quickly eliminated). Determine the target bounding box for redirection: Prioritize determining the output bounding box. Is it valid (i.e., does a critical sink pin exist on the wireline)? If valid, then... The target bounding box is used as the input bounding box; if the output bounding box is invalid, then the input bounding box is considered. Is it valid (i.e., does a critical source pin exist on the wireline)? If valid, then... If both are invalid, then there is no valid target bounding box, and the original cell is returned directly. No processing is performed. If a valid target bounding box exists, the initial center point position of the obtained cell will be determined. Move to the target bounding box to obtain new coordinates Specifically, let the coordinate range of the target bounding box be... Then the new coordinates The calculation method is to use Limit to this range: Specifically, the formula for calculating the first candidate coordinates is: ; ; in, Indicates taking and The larger value in Indicates taking and The smaller value in; , As the initial center point x and y coordinates , , , These represent the horizontal and vertical coordinate boundaries of the target bounding box, respectively.

[0039] The meaning of this calculation method is: for the x-axis, if... Already Within the range, then Take again Still That is, the new x-coordinate is equal to the initial x-coordinate (no movement required); if ,but Take again This means dragging the x-coordinate back to the left edge of the bounding box; if ,but Take again This involves shifting the horizontal coordinate back to the right edge of the bounding box. The same applies to the vertical coordinate, thus minimizing movement and bringing the new center point as close as possible to the target bounding box. Furthermore, the rationale for prioritizing the output bounding box design is that in digital circuits, signal propagation occurs from input to output. Bringing critical units closer to their critical output regions directly shortens the interconnect length between that unit and downstream critical units, thereby more effectively reducing path delay; moving them closer to the input is a less optimal choice.

[0040] For new coordinates Perform the first verification of the movement's validity and calculate the initial center point. With new coordinates Manhattan distance between: In the above steps, calculate the initial center point. With new coordinates The formula for calculating the Manhattan distance between them is: ; in: , For new coordinates The x and y coordinates. If the movement distance is less than the preset movement threshold. If the movement is too small, its contribution to timing improvement is negligible. Furthermore, to avoid unnecessary disturbance to the layout results, the system directly returns to the original cell. No action taken. Movement threshold. In this invention, it is set to 4 times the default cell height to filter out minute positional changes that have little effect on timing optimization.

[0041] For new coordinates Further restrictions (adjustments) are applied to the cell-related mesh boundary boxes. Inside, obtained Among them, the wire mesh boundary box This can be obtained by taking the union (or bounding box) of the net boundaries of all key pins of the unit, used to perform secondary spatial constraints on the initially selected positions to prevent them from deviating too far from the original connection range of the unit. Perform a second verification of the move's validity. Return to the original unit. If the element passes all the above checks—that is, the element is a critical element and not a fixed element, a valid target bounding box exists, and both movement distances meet the minimum movement threshold requirement—then the element's center point is updated to the new coordinates. The standard unit after position redirection is obtained. And return. Updated unit This will replace the original cell positions in the hypergraph, thereby updating the hypergraph to obtain... This completes the relocation of the critical unit.

[0042] This invention also relates to a timing-driven key unit redirection device, such as... Figure 4 As shown, the device comprises three core functional modules: a recognition module, a computing module, and a mobility module. These three modules share a hypergraph. Pin timing information The network boundary information and unit target coordinates are interconnected and collaborate sequentially according to data dependencies to jointly complete the identification, relocation position calculation, and position update of key units. In the software implementation, the aforementioned identification module, calculation module, and movement module correspond to three functional sub-modules within the key unit relocation program module, which can be implemented by the processor of the computer device when executing the computer program.

[0043] In the collaborative relationship among the three modules, the identification module filters out key units requiring relocation from the hypergraph, the calculation module calculates the relocation target position for the key units output by the identification module, and the movement module writes the target position output by the calculation module into the corresponding unit and updates the hypergraph. The specific data flow is as follows: the identification module traverses the standard units in the hypergraph, passing units identified as key units and their related timing and bounding box information to the calculation module; the calculation module calculates the target coordinates based on this information and passes the unit and target coordinates that have passed the movement validity verification to the movement module; the movement module performs a position update operation, writing the updated unit back to the hypergraph, completing one relocation. The three modules can be executed sequentially or in batches until all key units are processed or a preset iteration termination condition is met.

[0044] The identification module identifies whether standard cells in the hypergraph are critical cells; non-critical cells do not require position redirection. The input to the identification module is the hypergraph. Standard unit in and its pin set The output determines whether a cell is a critical cell. Its internal processing flow is as follows: First, it receives pin timing information from the static timing analysis module. Computing unit Timing margin Then, determine whether the unit meets the redirection condition—if the unit is a fixed unit (such as a clock unit, power supply unit, or other physically immovable units) or If the timing of all pins in the unit meets the constraints, it is determined to be a non-critical unit and marked as not requiring redirection; otherwise, it is determined to be a critical unit and passed to the calculation module for further processing. The identification module ensures that if any pin on the unit has a timing violation, the unit is identified as a potential timing bottleneck by minimizing the timing margin.

[0045] The calculation module determines whether critical units need to be redirected and, if so, where they should be redirected. The input to the calculation module is the units identified as critical by the recognition module. The bounding box information of the nets connected to each pin of this unit (including the source point bounding box) Sinkpoint bounding box and wire mesh boundary frame and movement threshold The output is the target coordinates after redirection. Its internal processing flow is divided into three stages: The first phase involves bounding box initialization and critical pin filtering. The computation module first initializes the input bounding boxes of the cells. and output bounding box Initialize to an invalid value and set the timing threshold for critical pins. (in The timing boundary threshold is set to 0.2 in this invention. The cells are then traversed. All pins And obtain the network line connected to that pin. Source bounding box Sinkpoint bounding box and wire mesh boundary frame If the timing margin of the network to which the pin is located... Greater than If a pin is not critical, it is considered a non-critical pin and is skipped (the net timing margin is used here instead of a single pin margin because the net margin already reflects the worst-case timing of the net, allowing for quick elimination of non-critical pins); if it is a critical pin, the input bounding box of the cell is expanded according to the source or sink bounding box corresponding to the pin. Or output bounding box After the traversal is complete, The area enclosed by the boundary box corresponding to all the key sink pins of this unit represents the region where the downstream key units driven by the output signal of this unit are located. The region enclosed by the source point bounding box corresponding to all the key source point pins of this unit represents the area where the upstream key unit that drives the input signal of this unit is located.

[0046] The second stage involves target bounding box selection and initial position calculation. The calculation module uses a priority strategy to determine the target bounding box: it prioritizes determining the output bounding box. Whether it is effective, if effective, then The target bounding box is used; if invalid, the input bounding box is then evaluated. Whether it is effective, if effective, then If both are invalid, then there is no valid target bounding box; if neither is valid, then the element is marked as not requiring redirection and the original element is returned. After determining the target bounding box, obtain the initial center point of the element. And clamp it to the coordinate range of the target bounding box. Inside, new coordinates are obtained. The calculation formula is: , The design of this priority strategy is based on the fact that in digital circuits, signals propagate from input to output. By bringing key units closer to their outputs, the interconnect length to downstream key units can be shortened more directly, thereby reducing path delay more effectively.

[0047] The third stage involves verifying the effectiveness of the movement and fine-tuning the position. The calculation module first calculates the initial center point. With new coordinates Manhattan distance If the moving distance is less than the preset moving threshold (If the height is set to 4 times the default cell height in this invention), then the movement range is considered too small and its contribution to timing improvement is negligible, and the cell is marked as not requiring relocation; otherwise, the new coordinates are... Further restrictions (adjustments) are applied to the cell-related mesh boundary boxes. Obtain the target coordinates And verify again Does it meet the threshold requirements? This two-stage distance verification mechanism ensures that each redirection generates a meaningful displacement, avoiding unnecessary disturbances to the layout results.

[0048] The move module is used to move critical cells to a new location at the output of the compute module to optimize timing. The input to the move module is the original standard cell. and the target coordinates output by the calculation module The output is the standard cell with the updated position. The moving module will move the unit The center point coordinates are updated to the target coordinates. Synchronously update the position information of all pins of the unit, and update the unit. Write back to the supergraph Replace the original unit The location of the key unit is redirected, updating the hypergraph to its current position. .

[0049] The present invention also provides an electronic device, such as... Figure 5 As shown, it includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the redirection method.

[0050] First, the external netlist file and timing constraints are entered into the computer device through the input / output interface and written to memory via the communication bus as the initial input for the placement process. Subsequently, the processor reads the computer program and the initial input data from memory via the communication bus and sequentially calls each program module to execute the complete placement process. These program modules include, but are not limited to, an initial placement module, a static timing analysis module, a critical cell redirection module, and an incremental placement module (including global placement, legalization, and detailed placement sub-modules); the critical cell redirection module can be further functionally divided into, for example... Figure 4The diagram shows the identification module, calculation module, and movement module. During execution, each program module reads and writes data in the memory via the communication bus to complete data transfer and state updates between modules. After optimization, the processor writes the final converged layout result back to memory, and then outputs it to the external system via the input / output interface through the communication bus.

[0051] Then, the memory is used to store computer program instructions and various types of data required during execution. Specifically, the computer program stored in the memory includes, but is not limited to: program instructions for implementing initial placement, static timing analysis, critical cell redirection, and incremental placement, wherein the critical cell redirection program instructions further include program instructions corresponding to the identification module, calculation module, and movement module. The data stored in the memory includes, but is not limited to: netlist data representing the circuit (including hypergraph). All standard unit sets and wire mesh set The system includes information such as process library information, constraint files (timing constraint files, rule files, etc.), runtime logs, and intermediate results. Memory can be volatile memory (such as DRAM, SRAM) or non-volatile memory (such as Flash, SSD, hard disk), or any combination thereof. During operation, the processor reads from memory to obtain program instructions and input data, and writes to memory to save calculation results, thereby enabling the continuous execution of timing optimization methods.

[0052] Furthermore, the processor is used to read and execute the computer program from memory via a communication bus. When the processor executes the program, it implements all steps of the timing optimization method based on critical unit redirection, including: obtaining pin timing information using static timing analysis. And calculate the timing information of the wire network. Key pins are identified based on pin timing and location information, and the source point bounding box, sink point bounding box, and net bounding box of each net are calculated. The set of key elements is identified based on the timing information of the pins containing the elements. Based on the initial center point of the unit Calculate the new target coordinates from the bounding box position. This involves redirecting critical unit locations to new, calculated locations to optimize timing. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or other processing units with computational capabilities. During execution, the processor maintains a continuous read-write cycle with memory: read instructions → read data → execute operations → write back results, and connects to the external environment through input / output interfaces.

[0053] Furthermore, the input / output interface is used to enable data transmission and reception between the computer device and external systems. In timing optimization applications, the input / output interface receives initial input information such as netlist data and timing constraint files from external sources at the beginning of the process, and transmits it to memory via the communication bus for processor use. At the end of the process, it reads the final layout result generated by the processor (including the position information of all cells, updated net connections, etc.) via the communication bus and outputs it to memory or an external electronic design automation toolchain. The input / output interface can be a universal serial bus (USB) interface, an Ethernet interface, a PCIe interface, or a dedicated EDA tool interface, and its implementation can be flexibly selected according to the actual deployment environment.

[0054] Finally, the communication bus is a shared data transmission channel connecting the processor, memory, and input / output interfaces, used to transmit address signals, data signals, and control signals between these components. Processor read / write requests to memory, data transfer between the input / output interfaces and memory, and control coordination between the processor and the input / output interfaces are all accomplished through the communication bus. The communication bus can be a system bus, memory bus, I / O bus, or a combination thereof, and its bit width and transmission rate are determined according to the performance requirements of the computer equipment.

[0055] In practical applications, this computer device can be deployed within an Electronic Design Automation (EDA) software platform, running as a timing optimization module for the layout engine. In incremental layout workflows (such as...) Figure 1 , Figure 2 As shown, the processor executes this computer program before each incremental placement begins, identifying and redirecting critical cells in the current hypergraph, and then continues with the global placement, legalization, and detailed placement stages of the incremental placement. This computer device can exchange data with existing EDA toolchains (such as static timing analysis tools, place and route tools, etc.) through standard interfaces, exhibiting good integration and compatibility.

[0056] A storage medium storing a computer program thereon, which, when executed, implements the redirection method described above. A computer-readable storage medium refers to any tangible medium capable of persistently storing computer program instructions and data. The storage medium can be a non-volatile storage medium, including but not limited to: read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state drive (SSD), hard disk drive (HDD), optical disc (CD-ROM, DVD-ROM, Blu-ray), and magnetic tape, etc.; it can also be a volatile storage medium, such as static random access memory (SRAM), dynamic random access memory (DRAM), etc., which retains the stored program instructions during normal power supply to the computer device.

[0057] like Figure 6 As shown, the computer program stored on the medium includes program modules for implementing the complete layout process, wherein the key unit redirection part corresponds to Figure 4 The diagram shows the identification module, calculation module, and movement module. Specifically, the computer program includes the following functional modules: Pre-processing module: Used to prepare timing information and bounding box information for the redirection of critical units.

[0058] Static timing analysis module: Used to call static timing analysis tools to obtain pin timing information. And based on this, calculate the network timing information. Timing information of each pin of the unit .

[0059] Net bounding box calculation module: used to traverse the net set. Based on pin timing and location information, key pins are identified, and source point bounding boxes are calculated for each net. Sinkpoint bounding box and wire mesh boundary frame .

[0060] Key Unit Redirection Module: Used to implement Figure 4 The functions of the identification module, calculation module, and movement module are shown.

[0061] Key Unit Identification Module: Corresponding Figure 4 The identification module in the middle is used to determine the timing margin of the unit. Determine whether a unit is a critical unit, and filter out fixed units and non-critical units that meet timing constraints.

[0062] Target location calculation module: corresponding Figure 4The computation module is used to complete bounding box initialization and key pin filtering, target bounding box selection, initial position calculation, and movement validity verification, including expanding the input bounding box of the unit according to the source or sink bounding box corresponding to the key pin. and output bounding box After selecting the target bounding box according to the priority strategy, the initial center point of the cell is clamped into the target bounding box to obtain new coordinates, and the effectiveness of the movement is verified.

[0063] Unit position update module: corresponding Figure 4 The moving module is used to update the center point of the verified key cell to the target coordinates. and write back to the supergraph To complete the redirection.

[0064] When the computer program is executed by the processor, the aforementioned modules operate collaboratively according to the timing optimization process: first, the pre-processing module completes static timing analysis and net boundary box calculation; then, the critical element relocation module sequentially completes critical element identification, target position calculation, and element position update, fully realizing the entire timing optimization process based on critical element relocation. This computer program can run as a standalone timing optimization tool, or it can be integrated into existing electronic design automation software platforms as a plugin or library function, providing plug-and-play timing optimization capabilities for the placement engine.

[0065] The method for redirecting critical units of a chip using timing-driven mechanisms, as described in this invention, has the following technical advantages compared to existing technologies: 1. Directly optimize timings to improve optimization results. In existing technologies, wire mesh-based methods convert timing information into wire mesh weights and indirectly optimize timing through weighted wire lengths, which is easily affected by wire length, resulting in poor optimization performance. Path-based methods, while providing high-quality solutions, rely on mathematical programming. Differentiable methods, while directly modeling the relationship between timing and position, are complex to implement. The technical approach adopted in this invention is to obtain pin timing information through static timing analysis, identify key units based on the minimum value of the unit pin timing margin, and directly redirect the positions of the key units to new positions calculated based on wire mesh bounding boxes. Because this method directly adjusts the unit positions based on timing information, rather than indirectly optimizing through intermediate indicators such as wire length, it can more accurately optimize timing bottlenecks and significantly improve timing optimization performance.

[0066] 2. Low computational complexity and strong scalability In existing technologies, path-based methods experience an exponential increase in the number of critical paths as the design scale expands, leading to a rapid increase in computational scale and poor scalability. Differentiable-based methods incur significant time overhead due to gradient backpropagation at large scales. The technical approach employed in this invention is to identify and process only the critical units that constitute a bottleneck to temporal convergence, rather than traversing all paths or all units. During location calculation, a bounding box-based geometric clamping method is used, avoiding complex mathematical programming solutions and gradient backpropagation. Therefore, the core relocation computational scale of this invention is primarily related to the number of critical units (the preceding temporal analysis and bounding box calculation steps are linearly related to the number of wire meshes), rather than the number of critical paths or the total number of units, maintaining low computational complexity and good scalability even when handling ultra-large-scale designs.

[0067] 3. Simple to implement and easy to deploy in engineering projects. In existing technologies, differentiable-based methods require precise handling of each stage of gradient propagation in practical commercial applications. Achieving gradient backpropagation under complex constraints is not easy and is difficult to implement directly. The technical approach adopted in this invention is to decompose the time-series optimization process into three clearly defined steps: key unit identification, target position calculation, and unit position update. Each step is based on analytically computable geometric operations and simple threshold judgments. Furthermore, this method is executed before incremental placement begins, without altering the existing global layout, legalization, and detailed layout processes of the incremental placement. Therefore, this invention does not require a complex gradient calculation framework or mathematical programming solver, and can be integrated into existing electronic design automation tools in a plug-and-play manner, resulting in low engineering implementation difficulty and strong applicability.

[0068] 4. It has good compatibility and can be used in conjunction with other timing optimization techniques. Existing timing optimization methods are often independent of each other, and replacing or integrating them is costly. The technical approach adopted in this invention is to pre-redirect key units before incremental placement begins, providing better initial positions for subsequent incremental placement stages. After pre-redirection, the original global placement, legalization, and detailed placement stages continue to be executed, and existing timing optimization methods based on nets, paths, or differentiability can still be used normally. Therefore, this invention does not replace existing timing optimization methods, but rather works in conjunction with them as an incremental pre-optimization method, further improving the speed and effectiveness of overall timing convergence.

[0069] 5. Avoid unnecessary disturbances and ensure layout stability. Some existing optimization methods may make minor adjustments to a large number of cells, which contribute little to timing improvement but may disrupt the existing layout. The technical approach of this invention is to set a movement threshold during the redirection process, and only perform a position update when the distance between the calculated new position and the current position meets the threshold requirement; simultaneously, by using fixed cell filtering and timing-satisfying cell filtering, redirection of immovable and non-critical cells is avoided. Therefore, this invention can effectively filter invalid movements, reduce excessive disturbance to the layout result, and ensure the stability and reliability of the optimization process.

[0070] 6. The optimization direction is clear and conforms to the characteristics of signal propagation. Some existing methods lack consideration for the direction of signal propagation in digital circuits when determining the direction of cell movement. The technical approach adopted in this invention is to prioritize the use of the output bounding box when determining the target bounding box, followed by the input bounding box, and then combine this with the overall net bounding box to perform secondary constraints (fine-tuning) on ​​the target position. This strategy aligns with the directional characteristics of signal propagation from input to output, causing critical cells to preferentially move towards downstream critical cells, thereby more directly shortening the interconnect length on the critical path and further improving the targeting and effectiveness of timing optimization.

[0071] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for redirecting critical units of a chip using timing-driven methods, characterized in that, Includes the following steps: Pin timing information of the chip is obtained through static timing analysis; Based on the pin timing information and the pin physical location, each net is traversed to generate the source point bounding box, sink point bounding box, and net bounding box for each net. Key units were identified based on pin timing information; Using the key units obtained from the determination, and combining them with the source and sink bounding boxes of the corresponding wire mesh, the unit input bounding boxes and output bounding boxes are constructed. The target bounding boxes are selected according to the priority of output bounding boxes first and input bounding boxes second. The first candidate coordinates are obtained by clamping the initial center point of the key element into the target bounding box; Calculate the Manhattan distance between the initial center point of the key unit and the first candidate coordinate. If the distance is greater than or equal to the preset movement threshold, then constrain the first candidate coordinate to the bounding box of the wire mesh associated with the unit to obtain the final target coordinate. The Manhattan distance between the initial center point of the critical unit and the final target coordinates is rechecked. If the movement threshold requirement is met, the center point of the critical unit is redirected to the final target coordinates. After all key units have been redirected, the above steps are executed iteratively until the layout timing converges.

2. The method for redirecting key units of a chip using timing-driven methods according to claim 1, characterized in that, The timing margin of a single wire net is calculated as follows: ； in, Indicates wire mesh Timing margin, This represents the set of all pins on net e. Pin indication The timing margin.

3. The method for redirecting key units of a chip using timing-driven methods according to claim 1, characterized in that, Setting the source point bounding box, sink point bounding box, and net bounding box of a wire mesh includes the following steps: Set timing thresholds for critical pins of the net: ,in, This is for the timing margin of the network. It is a controllable boundary threshold hyperparameter; The source, sink, and net bounding boxes of the initial net are invalid values; Traverse all pins in the net. If the timing margin of a pin is less than the timing threshold of a critical pin, determine that the pin is a critical pin. Expand the source point bounding box or the sink point bounding box to the pin position according to whether the pin is the source point or the sink point. If the timing margin of the net is positive and the scaling factor is greater than 0.01, calculate the scaling factor. The mesh bounding box is generated by scaling the mesh according to the scaling factor, where r is the scaling factor. This is the timing margin for the network; Update the generated source point bounding box, sink point bounding box, and net bounding box to the corresponding net.

4. The method for redirecting key units of a chip using timing-driven methods according to claim 1, characterized in that, The determination of key units includes: The timing margin of a computing unit is calculated using the following formula: ； in, This represents the timing margin of unit v. This represents the set of all pins of unit v. Pin indication Timing margin; If unit v is a fixed unit or the timing margin of unit v is greater than or equal to 0, it is determined to be a non-critical unit and the redirection process is skipped; the remaining units are determined to be critical units.

5. The method for redirecting key units of a chip using timing-driven methods according to claim 1, characterized in that, The steps for constructing the cell input bounding box and output bounding box include: Set timing thresholds for key pins in unit v ,in, This represents the timing margin of unit v. This is the time-series boundary threshold; Iterate through all pins in the critical unit and obtain the timing margin of the net to which the pin belongs. Only if the timing margin of the net to which the pin belongs is less than or equal to the timing threshold of the critical pin is the timing margin determined. When this happens, the pin is determined to be a critical pin; If the critical pin is a cell input pin, the cell input bounding box is expanded using the corresponding net source point bounding box; if the valid critical pin is a cell output pin, the cell output bounding box is expanded using the corresponding net sink point bounding box.

6. The method for redirecting key units of a chip using timing-driven methods according to claim 1, characterized in that, The formula for calculating the first candidate coordinates is: ； ； in, , As the initial center point x and y coordinates , , , These represent the horizontal and vertical coordinate boundaries of the target bounding box, respectively.

7. The method for redirecting key units of a chip using timing-driven methods according to claim 6, characterized in that, Calculate the initial center point With new coordinates The formula for calculating the Manhattan distance between them is: ； in: , For new coordinates The x and y coordinates.

8. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the redirection method as described in any one of claims 1-6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor implements the redirection method according to any one of claims 1-6 when executing a computer program.

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