A power semiconductor device layout optimization design method

Abstract

The application discloses a power semiconductor device layout optimization design method, comprising: obtaining device power consumption density distribution and establishing power consumption density matrix; establishing a heat conduction model, using the Green function method to solve the semi-infinite medium and introducing the finite thickness mirror correction, calculating the inter-device thermal influence coefficient, and constructing the asymmetric thermal coupling matrix; based on the thermal coupling matrix, the spectral clustering algorithm is used to divide the thermal equilibrium region; a target function minimizing the sum of temperature gradient differences of each region is defined, a simulated annealing and genetic algorithm serial collaborative strategy is used to iteratively optimize the device position coordinates, and a penalty function is used to process the layout design rule constraint; a temperature gradient difference threshold is set as a thermal equilibrium criterion, and an optimized layout scheme is output when the iteration is terminated. The application realizes power device layout thermal perception adaptive layout, reduces the thermal coupling effect and local heat concentration, and improves the module thermal reliability and electrical performance.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductors, and specifically relates to a method for optimizing the layout design of power semiconductor devices. Background Technology

[0002] Power semiconductor devices are core components of power electronic systems and are widely used in new energy vehicles, rail transportation, smart grids, and industrial control. With the development of wide bandgap semiconductor material technology, the switching frequency and power density of devices continue to increase. Local heat concentration has become a major bottleneck restricting their stable operation, and thermal management efficiency directly determines the reliability and lifespan of the devices.

[0003] Layout optimization is a key technology for achieving thermally balanced distribution of power devices. Its core lies in integrating the power consumption characteristics, spatial distribution and heat conduction path of the devices, and optimizing the substrate arrangement to suppress thermal coupling effect, reduce local heat concentration, and thus improve the thermal reliability and electrical performance of the module.

[0004] For example, Chinese patent CN117709282A discloses a method for minimum junction temperature layout of power semiconductor modules. It calculates the self-thermal resistance and coupling thermal resistance of the device by constructing a Laplace three-dimensional thermal conductivity partial differential equation and expanding it into a Fourier series, thereby optimizing the relative position of the two power semiconductors to achieve a layout with minimum thermal resistance.

[0005] However, this method mainly focuses on the position optimization between two power semiconductors. It lacks a systematic region division mechanism based on the thermal coupling strength between devices for complex thermally coupled networks in scenarios where multiple chips and multiple types of power devices coexist. It cannot effectively merge strongly thermally coupled devices into the same region for targeted optimization, resulting in an excessively large optimization search space and easy to get trapped in local optima. It is difficult to adapt to complex layout scenarios where multiple devices and multiple types of power chips coexist.

[0006] For example, existing research on the layout optimization of multi-chip parallel power modules constructs a dynamic current distribution model and introduces the response surface methodology for electrothermal distribution balance optimization. However, the optimization method is still based on traditional numerical optimization techniques such as response surface methodology, which does not characterize the thermal coupling effect precisely enough and lacks a processing mechanism for grouping and clustering devices based on thermal coupling strength. It is impossible to effectively determine the thermal balance state of the layout scheme during the optimization process, resulting in a lack of convergence basis for the optimization process and making it difficult to ensure that the thermal balance performance of the final layout scheme meets the engineering reliability requirements.

[0007] Therefore, there is an urgent need to establish a thermally sensitive adaptive layout optimization method for power semiconductor devices to achieve thermally balanced distribution of devices and effectively suppress thermal coupling effects. Summary of the Invention

[0008] The purpose of this invention is to provide a layout optimization design method for power semiconductor devices, which can effectively solve the problems mentioned in the background art.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A layout optimization design method for power semiconductor devices includes acquiring power density distribution data of power semiconductor devices and establishing a power density matrix, establishing a heat conduction model and calculating the thermal coupling coefficient between devices to construct a thermal coupling matrix, and iteratively optimizing the device position coordinates using simulated annealing or a genetic algorithm, further comprising: Static power consumption parameters are extracted from device datasheets and dynamic power consumption data are obtained using SPICE-like circuit simulation tools. Static power consumption and dynamic power consumption are calculated and weighted by duty cycle to obtain a comprehensive power consumption value. The comprehensive power consumption value is normalized to obtain power density distribution data and a power density matrix is ​​constructed. A three-dimensional heat conduction model was established based on Fourier's law of heat conduction. The Green's function method was used to solve the three-dimensional steady-state heat conduction equation. The temperature response of a point heat source in a semi-infinite medium was obtained by solving the non-homogeneous Poisson equation. The thermal coupling coefficient between any two power semiconductor devices was calculated, and all thermal coupling coefficients were arranged according to the power semiconductor device numbers to form a... The thermal coupling matrix; Based on the thermal coupling matrix, a spectral clustering algorithm is used to divide the device set into several thermally balanced regions; With minimizing the temperature gradient difference within the thermal equilibrium region as the objective function, the device position coordinates are iteratively optimized using simulated annealing or a genetic algorithm. Set a temperature gradient difference threshold as a criterion for thermal equilibrium. When the temperature gradient difference of all K regions is lower than or equal to the temperature gradient difference threshold, the iteration terminates and the optimized layout scheme is output.

[0010] In summary, this application includes at least one of the following beneficial technical effects: 1. This invention improves the accuracy of power consumption assessment and the precision of thermal coupling characterization by integrating static parameter extraction and dynamic operating condition simulation, and establishing a three-dimensional heat conduction model combined with Green's function method and finite thickness correction. Furthermore, this invention can accurately quantify the thermal influence relationship between devices, providing a reliable data foundation for the construction of asymmetric thermal coupling matrices, thereby solving the problems of large power consumption assessment deviation and distorted thermal path characterization in traditional analysis methods.

[0011] 2. This invention improves the efficiency and solution quality of layout thermal equilibrium optimization by organically combining spectral clustering algorithm and collaborative optimization strategy. Adaptive region division of devices based on thermal coupling strength effectively reduces the optimization search space and avoids getting trapped in local optima. Simultaneously, the thermal equilibrium criterion enables quantitative evaluation and convergence control of the thermal state of the layout scheme, thereby quickly obtaining a globally optimal layout scheme in complex multi-device scenarios.

[0012] 3. This invention constructs a complete closed-loop design process from power consumption modeling, thermal coupling analysis, region partitioning to layout optimization and criterion output, realizing full-process thermally-aware adaptive layout of power device layout. This can effectively reduce the thermal coupling effect between devices and suppress local heat concentration, improve the overall temperature gradient distribution of the module, and enhance the thermal reliability and electrical performance of the power semiconductor module. Attached Figure Description

[0013] Figure 1 A schematic diagram of the overall technical solution for optimizing the layout design of power semiconductor devices.

[0014] Figure 2 A flowchart illustrating the process of obtaining power density distribution data and establishing a power density matrix.

[0015] Figure 3 A schematic diagram of the process for establishing a heat conduction model and constructing a thermal coupling matrix.

[0016] Figure 4 This is a schematic diagram of the process of dividing thermal equilibrium regions based on the spectral clustering algorithm.

[0017] Figure 5 A flowchart illustrating the process of iteratively optimizing the device position coordinates and thermal equilibrium criteria to output an optimized layout scheme. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the following description is provided in conjunction with the appendix. Figure 1 To be continued Figure 5 The present invention will be further described in detail below with reference to specific embodiments.

[0019] This invention provides a layout optimization design method for power semiconductor devices, establishing a dedicated thermally sensitive adaptive layout optimization model for power semiconductor devices to achieve thermal equilibrium design of the spatial distribution of heat-generating devices. The specific implementation includes the following core processing steps: Step S1: Obtain power density distribution data of power semiconductor devices and establish a device power density matrix; Step S2: Establish a heat conduction model and calculate the thermal coupling coefficient between devices to construct a thermal coupling matrix; Step S3: Divide the thermal equilibrium region based on the thermal coupling matrix using a graph clustering algorithm; Step S4: Iteratively optimize the device position coordinates using simulated annealing or a genetic algorithm; Step S5: Set a temperature gradient difference threshold as a thermal equilibrium criterion and output the optimized layout scheme upon termination of iteration. The specific implementation methods of each step are described in detail below.

[0020] First, step S1 in the embodiments of this application will be described. Step S1 is used to obtain the power density distribution data of the power semiconductor device and establish the device power density matrix. The output power density matrix and power density distribution map serve as the input basis for subsequent heat conduction model establishment and thermal coupling coefficient calculation, and are specifically performed as follows.

[0021] Step S101: Extract static power consumption parameters from the device datasheet and obtain dynamic power consumption data using SPICE-type circuit simulation tools. The static power consumption parameters to be extracted include leakage current, gate charge, and on-resistance. These parameters determine the power consumption level of the device under steady-state operating conditions.

[0022] Dynamic power consumption data is obtained using SPICE-type circuit simulation tools to simulate the switching behavior of the device under pulse width modulation or hard-switching operation. During the simulation, the energy loss in the voltage-current crossover region during each switching event is recorded, and the energy loss is multiplied by the switching frequency to obtain the dynamic switching power consumption.

[0023] Step S102: Calculate the static power consumption and dynamic power consumption, and then weight and sum them to obtain the comprehensive power consumption value. The static power consumption is calculated based on the parameters provided in the device datasheet to evaluate steady-state power consumption. Leakage current power consumption is calculated by multiplying the leakage current value by the operating voltage. Gate charging and discharging power consumption is determined by multiplying the gate charge by the gate drive voltage. Turn-on power consumption is calculated by multiplying the on-resistance by the square of the load current. Dynamic power consumption is the dynamic switching power consumption extracted in step S101.

[0024] The total power consumption is obtained by weighting the static power consumption and dynamic power consumption according to the duty cycle. The calculation formula is as follows: in This indicates the overall power consumption of the device, expressed in watts (W). It represents the duty cycle, is dimensionless, and ranges from 0 to 1, determined by the operating mode of the circuit in which the device is located; The dynamic switching power consumption is expressed in W, which is derived from the switching energy loss extracted by the simulation tool in step S101 and multiplied by the switching frequency. This represents static power consumption, measured in watts (W), and is obtained by summing the leakage current power consumption, gate charge / discharge power consumption, and turn-on power consumption.

[0025] The weighted summation formula originates from the classic decomposition method of total power consumption in the field of power semiconductor device power consumption analysis. The total power consumption of the device is decomposed into two parts: dynamic loss during the switching cycle and static loss during the conduction period. The average power consumption of the cycle is obtained by weighting and summing them according to the time proportion.

[0026] Static parameter extraction and dynamic simulation complement each other. Static power consumption reflects the energy loss of the device in the steady state of conduction and turn-off, while dynamic power consumption characterizes the additional energy consumption during the transient switching process. The weighted sum of the two according to the duty cycle can reflect the power consumption level of the power semiconductor device under actual operating conditions. For different types of power devices such as IGBT, MOSFET, and GaN, the power consumption composition can be decomposed into static and dynamic components.

[0027] Step S103: Normalize the overall power consumption value to obtain power density distribution data. Divide the overall power consumption value calculated in step S102 by the actual area occupied by the device to obtain the power density distribution data. The unit of the power density value is W / mm². The input to the normalization process is the overall power consumption value output in step S102 and the actual area occupied by the device obtained from the device package size data.

[0028] The processing involves dividing the total power consumption by the occupied area. The output is a scalar power density value, representing the heat intensity per unit area of ​​the device. A higher power density value indicates a more concentrated heat generation per unit area, and thus a greater impact on the thermal distribution of the layout.

[0029] Step S104: Construct and store the power density matrix. The power density matrix is ​​stored using a two-dimensional data structure. Both the row and column indices of the matrix correspond to device numbers, and the matrix elements represent the power density values ​​of the corresponding devices. The matrix dimension is... N represents the total number of power semiconductor devices included in the layout.

[0030] The elements of the power density matrix are denoted as The meaning is the power density value corresponding to the i-th row and j-th column, where the subscript i represents the row index, i.e. the device number, and the subscript j represents the column index, i.e. the device number. The values ​​of i and j are both from 1 to N.

[0031] Since the power density matrix only needs to represent the power density of each device itself, there is no need to establish cross-correlation between different devices, and the condition is met only if i equals j. The value is taken as the power density value of the device, when i is not equal to j. The value is zero. All non-zero elements are located on the main diagonal of the matrix. A sparse matrix storage format is used, storing only the position index of the non-zero elements and their corresponding power density values.

[0032] The power density matrix construction supports unified processing of various power device types, including IGBTs, MOSFETs, and GaN. This capability is achieved by establishing a device parameter library, which contains power consumption characteristic parameters and thermal parameter models for various devices. Power consumption characteristic parameters include on-resistance, gate charge, and leakage current, while thermal parameter models include thermal resistance coefficient, thermal capacitance coefficient, and temperature coefficient.

[0033] During the power density matrix establishment process, the device type identification field is first read. Based on this field, a matching device record is retrieved from the device parameter library. Then, the corresponding power calculation model and thermal parameter model from the record are called. For devices not included in the parameter library, a parameter configuration interface is provided, allowing the device's electrothermal parameters to be entered and automatically added to the parameter library.

[0034] Step S105: A power density distribution map is generated using a two-dimensional grid interpolation method. The layout design area is used as the canvas, and grid cells are divided according to a preset grid resolution. The preset grid resolution is... m m, that is, 100 m 100 The value of m is determined based on the typical power device package size and layout design accuracy requirements, and can be adjusted according to the actual layout size and device density. The power density value at the center point of each grid cell is calculated.

[0035] The interpolation algorithm employs an inverse distance weighting method. For the current grid cell center point, the Euclidean distance between the center point and the geometric center of each power device in the layout is calculated. The reciprocal of the square of the distance is used as the weight to sum the power density values ​​of all devices, yielding the estimated power density value of the grid cell. The devices involved in the interpolation calculation are all N power devices in the layout, and the power density value of each device is the scalar value calculated in step S103.

[0036] For grid cells in the boundary region, a mirror boundary condition is used. That is, with the layout boundary as the axis of symmetry, the devices inside the boundary are mirrored to virtual positions outside the boundary, and then the power density value of the boundary grid cells is calculated using the same interpolation method. If there are still boundary cells that cannot obtain effective interpolation results after mirroring, the boundary cells are truncated, the power density value is assigned to zero, and an anomaly is recorded.

[0037] The generated two-dimensional power density distribution map is stored in matrix form. The number of rows and columns of the matrix correspond to the number of rows and columns of the grid, respectively, and the matrix element values ​​are the estimated power density of the grid cells.

[0038] Therefore, the power density matrix output in step S1 can be obtained. Together with the power density distribution map, these constitute the input data required for subsequent step S2 to establish a three-dimensional heat conduction model and calculate the thermal coupling coefficient between devices. The power density matrix stores the power density values ​​of each device in a diagonal format, and the power density distribution map depicts the spatial distribution characteristics of power density across the entire layout in a gridded form.

[0039] Following this, for step S2 in the embodiments of this application, a heat conduction model is established and the thermal coupling coefficient between devices is calculated to construct a thermal coupling matrix. A three-dimensional heat conduction model is established based on Fourier's law of heat conduction, and the temperature response of a point heat source in the substrate is solved using the Green's function. The thermal influence coefficient between any two devices is calculated and formed. The thermal coupling matrix is ​​described in detail below.

[0040] Step S201: Idealize the dielectric substrate as a semi-infinite homogeneous medium, where the thermal conductivity, heat capacity, and specific heat capacity of the substrate material are spatially uniform and do not change with temperature. Establish a Cartesian coordinate system, with the substrate surface as the XY plane and the positive Z-axis pointing inwards. In the Cartesian coordinate system, the heat generated by the power semiconductor device diffuses outwards through the substrate material via three-dimensional thermal conduction. The three-dimensional steady-state thermal conduction equation is as follows: in, The thermal conductivity of the substrate material is expressed in W / (m·K), taken from the substrate material datasheet. Temperature is expressed in Kelvin (K). The heat source intensity per unit volume is expressed in W / m³. This represents the Laplace operator, which is the sum of the second-order partial derivatives of temperature with respect to the three spatial coordinate directions.

[0041] The three-dimensional steady-state heat conduction equation holds true throughout the entire interior of the substrate. The boundary conditions are set such that the substrate surface satisfies adiabatic boundary conditions, meaning the temperature gradient along the Z-direction at the substrate surface is zero. This equation is the governing equation for the steady-state heat conduction problem in classical heat transfer, derived by combining Fourier's law of heat conduction with the principle of energy conservation.

[0042] Step S202: The three-dimensional steady-state heat conduction equation is solved using the Green's function method. The temperature response of the point heat source in the semi-infinite medium is obtained by solving the non-homogeneous Poisson equation. The analytical expression of the Green's function is: in, Represents the field point coordinate vector, with components as follows: , , The unit is meters (m). Represents the source point coordinate vector, with components as follows: , , The unit is meters (m). This indicates the thermal conductivity of the substrate material, expressed in W / (m·K). Represents the source point A point heat source of unit intensity at the field point The temperature response generated at that point is expressed in Kelvin per watt.

[0043] In the Green's function expression, the first term represents the temperature response generated by the real heat source, and the second term represents the temperature response generated by the virtual heat source. The virtual heat source is located symmetrically to the real heat source on the outer side of the substrate surface, and its introduction satisfies the adiabatic boundary conditions of the substrate surface. This Green's function is a fundamental solution to the Poisson equation for the semi-infinite dielectric point heat source problem in classical heat conduction theory; this analytical result is directly cited.

[0044] Step S203: Calculate the thermal influence coefficient between any two power semiconductor devices based on the superposition principle. The superposition principle states that in a linear system, the temperature field generated by multiple heat sources is equal to the linear superposition of the temperature fields generated by each heat source acting alone. Each power semiconductor device is considered as an independent point heat source.

[0045] For the number is Power semiconductor devices and numbered Power semiconductor devices, thermal influence coefficient Defined as number The change in power density of a power semiconductor device by a unit size causes the numbered The magnitude of temperature change in power semiconductor devices. Numbered as... The total power consumption of a power semiconductor device is equal to the product of power density and footprint.

[0046] When the number is When the power density of a power semiconductor device changes by 1 W / mm², the total change in power consumption is numerically equal to the change in the occupied area. This change is numbered The temperature rise generated at the power semiconductor device is the footprint area Multiply by the Green's function value Therefore, the thermal influence coefficient The calculation expression is: in, Indicated by number Location of power semiconductor devices For the site, numbered Location of power semiconductor devices The Green's function value at the source point is expressed in K per watt, and is calculated by substituting the Green's function expression from step S202 into the coordinates of the power semiconductor device. Indicates the number is The footprint of the power semiconductor device, in square millimeters (mm), is obtained from the power semiconductor device package size data. The unit is K·mm² / W, and its physical meaning is the temperature rise caused by a change in unit power density.

[0047] when equal hour, Indicates the number is The self-heating coefficient of power semiconductor devices, i.e., numbered... The rate of temperature increase per unit area when the power consumption density of a power semiconductor device changes. Self-heating coefficient. The calculation method is as follows Since the Green's function diverges mathematically when the field point coincides with the source point, it is approximated in actual calculations using the equivalent size of the active region of the power semiconductor device.

[0048] The active region of the power semiconductor device is approximated as having a side length of... The square equivalent heat source region is defined, and the self-heating Green's function value is taken as the average Green's function value of the equivalent region, i.e. ,in , For the number The footprint of a power semiconductor device. This approximation method is derived from the analytical solution of the thermal temperature rise of a homogeneous surface heat source in a semi-infinite dielectric.

[0049] Step S204: Arrange all thermal influence coefficients according to the power semiconductor device number to form... thermal coupling matrix, thermal coupling matrix matrix elements Equal to thermal influence coefficient ,Right now: in, Indicates the number is The power density variation of the power semiconductor device for the numbered The degree to which temperature affects the power semiconductor device. Indicated by number Location of power semiconductor devices For the site, numbered Location of power semiconductor devices The value of the Green's function at the source point is expressed in K per watt. Indicates the number is The footprint of a power semiconductor device, expressed in square millimeters (mm²).

[0050] Thermal coupling matrix The construction process is as follows: for the thermal coupling matrix The Line number Column elements, take the number as The coordinates of the location of the power semiconductor device are field point, numbered as The coordinates of the location of the power semiconductor device are taken as the source point, and the device is numbered as follows: The footprint of power semiconductor devices Green's function value under coordinate combination Multiply, and fill the thermal coupling matrix with the product. The corresponding position. This operation applies to all From 1 to , From 1 to of Each combination is performed independently, with the calculations of each element decoupled, ultimately forming a complete combination. OK Column matrix.

[0051] Thermal coupling matrix diagonal elements The characterization number is Self-heating effect of power semiconductor devices, off-diagonal elements The characterization number is Power semiconductor devices and those numbered Thermal coupling effect between power semiconductor devices.

[0052] The heat conduction process satisfies the reciprocity principle, i.e., the Green's function. equal However, thermally coupled matrix elements and They are generally not equal. This is because semiconductor devices with different power ratings occupy different areas. and They may differ, thermal coupling matrix The asymmetric form is retained to accurately reflect the thermal asymmetry caused by the difference in the heating area of ​​semiconductor devices with different power.

[0053] In practical storage, thermally coupled matrices A sparse matrix storage format is used, which stores only the position index of non-zero elements and their corresponding thermal influence coefficient values.

[0054] Thermal coupling matrix After construction, eigenvalue analysis is performed using the power iteration method to obtain the thermal coupling matrix. Maximum eigenvalue and its corresponding eigenvectors The power iteration method is a standard numerical linear algebra algorithm, and its iteration format is: random initialization vector... Repeatedly The process continues until convergence, and the scaling factor after convergence is the largest eigenvalue. .in, Indicates the first Approximate eigenvector values ​​of the next iteration Representing vectors The Euclidean length.

[0055] The specific method for determining thermal stability is as follows: calculate the maximum eigenvalue. When the largest eigenvalue The closer the value is to 1, the stronger the thermal coupling matrix. The higher the overall thermal sensitivity of the thermal interaction network between power semiconductor devices, the weaker the ability of the power semiconductor device assembly to resist thermal disturbances.

[0056] When the largest eigenvalue A value less than 1 and a larger difference from 1 indicates a weaker thermal coupling effect and better thermal stability of the power semiconductor device assembly. Maximum eigenvalue The analysis results are used for the dynamic adjustment of the penalty function weight coefficients in subsequent step S4. During the iterative optimization process, if the largest eigenvalue... If the value exceeds the preset threshold range, the penalty factor weight value of the thermal balance constraint term will be increased or decreased accordingly to guide the optimization algorithm to prioritize improving the layout scheme with poor thermal stability.

[0057] Step S205: Perform finite thickness correction on the semi-infinite dielectric assumption, as the actual dielectric substrate has a finite thickness. After heat is conducted to the bottom surface of the substrate, it is constrained by boundary conditions, causing the temperature field distribution to deviate from the assumption of a semi-infinite dielectric. A finite thickness correction term is introduced using the mirror method, adding a sequence of mirrored heat sources from the bottom surface of the substrate to the Green's function expression: in, This indicates the substrate thickness, expressed in meters (m), and is derived from the substrate material specifications. The order of the mirror source is a positive integer. This represents the truncation order of the mirror source. For power semiconductor module ceramic substrates with thicknesses ranging from 0.25 mm to 1.0 mm, the mirror source truncation order is... A value of 3 to 5 is sufficient to meet the accuracy requirements.

[0058] Mirror source truncation order The convergence determination process is as follows: calculate sequentially Values ​​range from 1 to The contribution of each order of mirror source to the temperature response, when the first order is increased... When the relative rate of change of the thermal influence coefficient after mirroring the source is less than 1%, the current mirror source is considered to be of truncation order. The value has met the convergence requirement. The formula for calculating the relative rate of change is: in, Indicates the truncation before The thermal influence coefficient calculated for a mirror source is expressed as follows: , To take only the former The modified Green's function for the mirror image source. Indicates the truncation before The thermal influence coefficient is calculated when the image source is of the first order.

[0059] relative rate of change The calculation is performed for each pair of power semiconductor device combinations. , Performed independently, the maximum relative rate of change among all power semiconductor device combinations is selected as the current mirror source cutoff order. The overall convergence criterion under the given value. When the maximum value is less than 1%, the order of the mirror source is stopped from increasing, and the order of the mirror source is truncated at this point. The value represents the final truncation order used.

[0060] Thermal influence coefficient after finite thickness correction Replacement heat effect coefficient Used for constructing the subsequent thermal coupling matrix, the calculation formula is: in, For a modified Green's function that includes contributions from all truncated mirror sources, For the number The footprint of power semiconductor devices.

[0061] The correction for temperature predictions based on finite thickness is typically between 3% and 8%. This applies when the substrate thickness... Spacing between power semiconductor devices When the ratio is less than 0.5, the finite thickness correction cannot be ignored, especially for the feature spacing of power semiconductor devices. Defined as the median of the Euclidean distances between all power semiconductor devices. The introduction of a finite thickness correction term makes the thermal model more closely approximate the actual physical boundaries of the power semiconductor module.

[0062] Thus, step S2 completes the full modeling of the thermal coupling relationship between discrete power semiconductor devices, transforming the three-dimensional thermal coupling effect into an asymmetric matrix description with clear physical meaning. Thermal coupling matrix. The thermal interaction network inside the power semiconductor module is quantitatively characterized, and the engineering practicality of the model is improved by adjusting the finite thickness.

[0063] After completing the above steps, proceed to step S3 in this embodiment of the application: based on the thermal coupling matrix, a graph clustering algorithm is used to divide the thermal equilibrium region, and a weighted graph is constructed using the thermal coupling coefficient as the edge weight. The spectral clustering algorithm is used to divide the device set into several thermal equilibrium regions. The thermal coupling strength of the devices in the same region is higher than the coupling strength between regions. The specific operation process is detailed below.

[0064] Step S301: Construct an undirected weighted graph based on the thermal coupling matrix, mapping each power device in the layout to a node in graph theory, with the number of nodes equal to the total number of power devices N. Map the thermal influence coefficients in the thermal coupling matrix to the edge weights connecting the nodes, with the weight values ​​directly using the absolute values ​​of the thermal influence coefficients.

[0065] Since the thermal coupling matrix is ​​a symmetric matrix, the generated graph is an undirected weighted graph. In the graph's data structure representation, an adjacency list is used to store the edge list, and each edge entry contains the target node index and the corresponding edge weight value.

[0066] Step S302: Construct the Laplacian matrix based on the weighted graph. The Laplacian matrix is ​​equal to the degree matrix minus the adjacency matrix. The degree matrix is ​​a diagonal matrix, where the diagonal elements are the degree of the corresponding node, i.e., the sum of the weights of all connecting edges to that node. The adjacency matrix is ​​the same as the hot coupling matrix, which is... Symmetric matrix.

[0067] The Laplace matrix is ​​positive semidefinite; all eigenvalues ​​are greater than or equal to zero, and the smallest eigenvalue is always zero. The distribution of eigenvalues ​​in the Laplace matrix reflects the connectivity structure and clustering properties of the graph. When the number of connected components in the graph is K, the number of zero eigenvalues ​​in the Laplace matrix is ​​equal to K.

[0068] The two steps described above abstract the thermal coupling relationship between devices into a graph structure, and the device clustering problem is then transformed into a graph partitioning problem, which allows the graph partitioning to be solved through matrix eigenvalue analysis.

[0069] Step S303: Determine the optimal number of partitions K through eigenvalue spectrum analysis of the Laplace matrix, calculate all eigenvalues ​​of the Laplace matrix and arrange them in ascending order to obtain the eigenvalue sequence. Plot the eigenvalue distribution curve, calculate the difference between adjacent eigenvalues, and select the position with the largest difference as the transition point from near zero to a significant increase in eigenvalues.

[0070] The number of eigenvalues ​​close to zero corresponds to the number of connected components in the graph. The number of eigenvalues ​​before a transition point is an estimate of the number of connected components in the graph. The number of eigenvalues ​​corresponding to the transition point is selected as the initial estimated number of segments K.

[0071] The silhouette coefficient is used to verify the rationality of the number of segments. The silhouette coefficient is equal to the difference between the average distance within the same region and the average distance between the nearest neighbor regions, divided by the larger of the two values. The average distance within the same region is the average distance from one device to other devices within the same region, measured as the reciprocal of the difference in thermal coupling strength; devices with stronger thermal coupling strengths are closer together. The average distance between the nearest neighbor regions is the average distance from one device to another in its nearest neighbor region. The silhouette coefficient ranges from -1 to 1; a higher value indicates better clustering performance.

[0072] exist to Within the range, the mean contour coefficient corresponding to each candidate segment number is calculated sequentially, and the segment number with the largest mean contour coefficient is selected as the optimal K value.

[0073] The input to step S303 is the Laplace matrix output from step S302, and the output is the optimal number of partitions K.

[0074] Step S304: The device set is divided into K thermal equilibrium regions using a spectral clustering algorithm. The eigenvectors corresponding to the first K smallest eigenvalues ​​of the Laplacian matrix are extracted to form an N-by-K eigenvector matrix. Each row of the eigenvector matrix corresponds to a device, and each column corresponds to a eigenvector dimension.

[0075] Normalization is performed on each row of the eigenvector matrix by dividing the row vector by its own Euclidean modulus, resulting in the normalized eigenvector matrix. This normalization operation is an independent scalar operation for each row, with no cross-coupling between rows.

[0076] Each row of the normalized eigenvector matrix is ​​considered as a point in a K-dimensional space, resulting in N points. These points are then clustered into K clusters using the K-means clustering algorithm. The objective function of K-means clustering is to minimize the sum of squares within each cluster, i.e., to minimize: in Indicates the first Clusters, This represents a point in the cluster. This represents the centroid of the cluster.

[0077] The K-means clustering results are mapped back to the original device set, with each cluster corresponding to a thermally balanced region. After clustering, devices within the same region have similar feature vector components, reflecting their structural similarity in the thermally coupled network.

[0078] The input to step S304 is the Laplace matrix output from step S302 and the optimal number of partitions K output from step S303. The output is the device set partition of K thermal equilibrium regions.

[0079] Based on the above analysis, step S3 transforms the thermal coupling relationship between devices into a graph partitioning problem, and uses a spectral clustering algorithm to automatically group devices based on thermal coupling strength. The output of step S3 is K thermal equilibrium regions and their corresponding device sets, which serve as the basic units for temperature gradient difference optimization in step S4. Step S4, based on the thermal equilibrium regions partitioned in step S3, uses minimizing the temperature gradient difference within each region as the objective function, and employs simulated annealing or a genetic algorithm to iteratively optimize the device position coordinates.

[0080] Following this is step S4 in this embodiment, which uses simulated annealing or a genetic algorithm to iteratively optimize the device position coordinates. The objective function is to minimize the temperature gradient difference within the thermal equilibrium region, and the constraints include device spacing constraints and minimum trace width constraints. Step S4 follows the K thermal equilibrium regions and their corresponding device sets defined in step S3. It adjusts the position of each device in the layout through a numerical optimization algorithm to reduce the temperature gradient difference within each region and achieve thermal equilibrium in the spatial distribution of devices. Specifically, the following operations are performed.

[0081] Step S401: Define the global optimization objective function, using the sum of temperature gradient differences across all thermal equilibrium regions as the global optimization objective. For the region... Internal number is The device, operating temperature equal to ambient reference temperature Adding the sum of the temperature rise caused by the power consumption of all devices in the area, the calculation formula is: in, Indicates the region Internal components Operating temperature, in units of , Represents the ambient reference temperature, with a value of , This indicates the total number of power semiconductor devices included in the layout. Device The power density, expressed in W / mm², is derived from the diagonal elements of the power density matrix output in step S1. This indicates the device after finite thickness correction in step S205. For devices The thermal influence coefficient, in units of The thermal coupling matrix output from step S2 elements The summation operation is a scalar summation, where the contributions of each device are calculated independently and then summed.

[0082] The temperature gradient difference ΔTi in region i is defined as the maximum value minus the minimum value of the operating temperature of all devices in that region: Where Ri represents the set of devices in the i-th thermal equilibrium region divided in step S3.

[0083] The global objective function F is defined as the sum of the temperature gradient differences among K regions: Where K represents the total number of thermal equilibrium regions determined in step S3.

[0084] The essence of the optimization process is to search for a set of device position coordinates that minimizes the global objective function F.

[0085] Step S402: Transform the layout design rules into constraints for an optimization problem and process them using a penalty function method. The device spacing constraint requires that the Euclidean distance between the geometric centers of any two devices is not less than the minimum spacing dmin. The minimum spacing is determined based on the device package size and manufacturing process, and is taken as 1.2 to 1.5 times the maximum side length of the device.

[0086] The minimum trace width constraint requires that the device layout position meets the reserved space of the routing channel, ensuring that there is a trace channel with a width of not less than wmin between adjacent devices, where wmin is determined according to the metal layer routing rules.

[0087] Layout boundary constraints require that all devices be completely within the layout design area.

[0088] The penalty function method incorporates constraints as penalty terms into the objective function. The augmented objective function equals the global objective function plus the sum of the squares of the degree of non-compliance of each constraint and the corresponding penalty factor weights. The penalty factor weights range from 100 to 1000. When a constraint is satisfied, the degree of non-compliance is zero; when a constraint is violated, the degree of non-compliance is the violation amount, which is the difference between the actual value and the constraint boundary value.

[0089] Step S403: Iterative optimization is performed using a simulated annealing algorithm. When initializing the simulated annealing algorithm, the initial temperature T0 is set to 1000K, the termination temperature Tf is set to 1K, and the cooling rate α is set to 0.95.

[0090] During the algorithm iteration, a new solution x' is generated within the neighborhood of the current solution x through random perturbation. The perturbation method involves adding a uniformly distributed random offset to the coordinates of a single device, and the perturbation amplitude decreases linearly with decreasing temperature. The initial perturbation amplitude is set to 0.1 times the maximum side length of the device.

[0091] The acceptance of a new solution x' is determined using the Metropolis criterion. If the objective function value of the new solution is less than that of the current solution, the new solution is accepted. If the objective function value of the new solution is greater than or equal to that of the current solution, the new solution is accepted randomly with exponential probability. The acceptance probability decreases as the difference in objective function values ​​increases and as the temperature decreases.

[0092] The iteration terminates when the current temperature is lower than the termination temperature Tf. At this point, the current optimal solution is output as the final result of the simulated annealing algorithm.

[0093] Step S404 involves iterative optimization using a genetic algorithm, which encodes the device placement problem as a chromosome representation. Each chromosome contains N gene segments, each corresponding to a two-dimensional position coordinate (x, y) of a device in the layout. Chromosome initialization employs a random placement method, randomly generating device positions while satisfying layout boundary constraints.

[0094] The fitness function is defined as the reciprocal of the augmented objective function; a larger fitness value indicates a better quality solution.

[0095] Genetic operators include selection, crossover, and mutation operators. The selection operator uses a tournament selection method, in which s individuals are randomly selected from the population each time, and the individual with the highest fitness is selected to enter the next generation. This process is repeated until the size of the new population reaches a preset value.

[0096] The crossover operator uses a simulated binary crossover method, performing an arithmetic weighted combination of corresponding gene segments from the two parent chromosomes to generate two offspring chromosomes. The crossover probability pc is set to 0.9. The mutation operator uses a multinomial mutation method, adding a multinomial-distributed random perturbation to the genes of the parent chromosomes. The mutation probability pm is set to 0.1.

[0097] The control parameters for the genetic algorithm include: a population size of 200 individuals, a generation count of 300, and an elite retention rate of 5%. Elite retention means that the top 10 individuals from each generation are directly copied to the next generation without participating in crossover or mutation operations. The iteration terminates when the preset generation count is reached or the improvement in fitness over 50 consecutive generations is less than 0.1%.

[0098] Step S405 involves a collaborative optimization strategy combining simulated annealing and a genetic algorithm. First, the genetic algorithm performs a global search to quickly locate the advantageous region of the objective function. The final result of the genetic algorithm is used as the initial solution for the simulated annealing algorithm, continuing the local fine-tuning search and utilizing the Metropolis criterion to escape potential local optima. The final result of the simulated annealing algorithm is output as the final solution for the overall optimization. The number of iterations and parameter configurations of the collaborative optimization strategy are adaptively adjusted according to the specific layout size and number of devices.

[0099] Based on the above analysis, step S4 completes the entire process from optimization problem modeling to iterative optimization. Step S401 defines a global objective function F with the goal of minimizing the temperature gradient difference. Step S402 transforms the layout design rules into an augmented objective function in the form of a penalty function. Steps S403 and S404 respectively provide two implementation schemes: simulated annealing and genetic algorithm. Step S405 further presents a collaborative optimization strategy that combines the two algorithms in sequence.

[0100] Finally, in step S5 of this embodiment, a temperature gradient difference threshold is set as the thermal equilibrium criterion, and an optimized layout scheme is output when the iteration terminates. The difference between the highest and lowest temperatures within the thermal equilibrium region is defined as the temperature gradient difference. The threshold is set according to the thermal tolerance of the device. The iteration terminates when the temperature gradient difference in all regions is lower than the threshold. Specifically, the following operations are performed.

[0101] Step S501, set the temperature gradient difference threshold. As a quantitative criterion for determining thermal equilibrium, the threshold setting is based on the analysis of the device's thermal tolerance. The maximum junction temperature of silicon-based IGBT devices is limited to 150℃, and the temperature gradient difference threshold is set to 10 to 15℃.

[0102] The maximum junction temperature of silicon carbide MOSFET devices is limited to 200°C, with a temperature gradient difference threshold set to 15 to 20°C. Gallium nitride devices have a maximum junction temperature limited to 150°C and are highly sensitive to temperature gradients, with a temperature gradient difference threshold set to 5 to 10°C.

[0103] Threshold settings support automatic configuration based on device type. The configuration method is as follows: read the device type identifier in each thermal equilibrium area, match the corresponding threshold range according to the type identifier, and take the midpoint of the range as the initial threshold for the area. Threshold settings also support manual adjustment according to actual reliability requirements. When adjusting manually, directly input the specific temperature gradient difference value in the threshold setting interface.

[0104] Step S502: After each iteration, evaluate the thermal equilibrium state of the current layout scheme. For each thermal equilibrium region... Calculate the temperature gradient difference in the region. ,Will With threshold Comparison. When Less than or equal to At that time, the area is deemed to have reached a state of thermal equilibrium. The overall layout scheme satisfies the thermal equilibrium requirement if and only if all The temperature gradient difference in each region is lower than or equal to the threshold.

[0105] During the iterative process of simulated annealing or genetic algorithm, a thermal equilibrium state evaluation is performed every 50 iterations. The iteration process is terminated early when it is detected that all regions meet the thermal equilibrium condition.

[0106] The optimal layout is defined as one where the temperature gradient difference in all regions is less than or equal to a threshold. The global objective function in the layout scheme The solution with the minimum value. Since the iterative optimization in step S4... The objective is to minimize the threshold, and step S5 uses a threshold as a filtering condition, satisfying the thermal equilibrium criterion. The smallest possible solution is the optimal layout solution.

[0107] Step S503: Output the final layout scheme that satisfies the thermal equilibrium criterion in a structured data format. The output includes the final position coordinates of each device. and The system includes the thermal equilibrium region number to which the device belongs, the thermal equilibrium status indicators for each thermal equilibrium region, and the global optimization index. The thermal equilibrium status indicators include the highest temperature, lowest temperature, and temperature gradient difference; the global optimization index is the objective function value. .

[0108] The layout scheme is also exported in a layout data format, supporting data interface integration with mainstream layout editing tools. The output data is in JSON or XML format and includes four data segments: a list of device identifiers, a list of location coordinates, a list of region affiliations, and a list of performance indicators.

[0109] Step S504: The output layout scheme is verified a second time using a thermal simulation tool. The optimized device position coordinates are input into the thermal simulation environment to reconstruct a complete thermal model including the power consumption distribution and thermal coupling effects of all devices. The operating temperature of each device is calculated, and the thermal equilibrium state is verified. The optimization result is considered reliable if the error between the temperature gradient difference in the simulation results and the predicted value of the optimization algorithm is controlled within 5%. The error is calculated as the absolute value of the difference between the simulated value and the predicted value divided by the predicted value.

[0110] Finally, step S5 enables the optimized layout scheme output in step S4 to be screened and confirmed based on clear thermal equilibrium criteria, ultimately forming an engineering scheme that can be directly used for layout design. Thus, the complete technical chain of this application, from power consumption data acquisition, thermal coupling modeling, region partitioning, and location optimization to thermal equilibrium criteria and output verification, is closed, realizing the full-process thermally-aware adaptive optimization design of power semiconductor device layout.

[0111] This application also includes a heat dissipation channel configuration optimization step, in which heat conduction path constraints are embedded into the objective function during the iterative optimization process, and the overall thermal resistance distribution under different layout schemes is evaluated through thermal resistance network calculation.

[0112] Overall thermal resistance The calculation method is as follows: establish an equivalent thermal resistance network from the junction of each device to the environment, add the thermal resistance values ​​of the series paths in the thermal resistance network, and take the reciprocal of the sum of the thermal resistance values ​​of the parallel paths to obtain the final equivalent total thermal resistance from the device junction to the environment.

[0113] Maximum permissible overall thermal resistance The system's thermal design specifications are determined based on the cooling method, ambient temperature range, and the maximum allowable junction temperature of the devices. The value is determined by obtaining the device's maximum junction temperature from the device datasheet. Determine the ambient temperature based on the system design. The thermal resistance from the device casing to the environment is determined based on the cooling method. Then by The calculation yielded, where This represents the total power consumption of all devices.

[0114] When the overall thermal resistance of the layout scheme Exceed At this time, the objective function value is increased by increasing the penalty factor value, guiding the search process to converge towards lower thermal resistance, ensuring that the optimized layout satisfies the thermal equilibrium condition while the overall thermal resistance does not exceed the maximum allowable value. This step is performed synchronously during the iterative optimization process in step S4, specifically by adding an overall thermal resistance constraint term to the augmented objective function. When the overall thermal resistance of the layout scheme Exceed At that time, by increasing the penalty factor value, the objective function value is increased, thereby guiding the search process to converge towards the direction of low thermal resistance.

[0115] To better understand the technical solution of this application, a specific application example is provided below. Assume a power converter module contains six power semiconductor devices: two IGBT devices numbered D1 and D2, two MOSFET devices numbered D3 and D4, and two GaN devices numbered D5 and D6. The layout design area is a rectangular area of ​​20mm x 15mm, the substrate material is alumina ceramic, and the thermal conductivity is [missing information]. The thickness is 1mm.

[0116] In step S1, the static power consumption parameters of each device are extracted from the device datasheet. The on-resistance of D1 is... The on-resistance of D2 is The on-resistance of D3 is The on-resistance of D4 is The on-resistance of D5 is The on-resistance of D6 is The combined power consumption density of each device was obtained from the operating state simulation. , , , , , .

[0117] In step S2, the result is calculated based on the Green's function method. The symmetric thermal coupling matrix has diagonal elements, i.e., self-heating coefficients, as follows: , , , , , Off-diagonal elements reflect the thermal coupling strength between devices, with the coupling coefficient between D5 and D6 being the largest. The coupling coefficient between D1 and D2 is the second largest. .

[0118] In step S3, a spectral clustering algorithm is used to divide the six devices into three thermal equilibrium regions. Region A contains D1 and D2, i.e., the IGBT device group; Region B contains D3 and D4, i.e., the MOSFET device group; and Region C contains D5 and D6, i.e., the GaN device group.

[0119] In step S4, a collaborative optimization algorithm combining genetic algorithm and simulated annealing algorithm is used for iterative optimization of device position. The initial population size is 200, the genetic generation is 300, the crossover probability is 0.9, and the mutation probability is 0.1. The initial temperature of simulated annealing is 1000K, the cooling rate is 0.95, and the termination temperature is 1K.

[0120] In step S5, the temperature gradient difference threshold is set to 10℃. After 280 generations of genetic iteration and subsequent simulated annealing fine search, the temperature gradient difference in all thermal equilibrium regions has decreased to below the threshold. The temperature gradient difference in region A is 7.2℃, in region B it is 8.5℃, and in region C it is 6.8℃.

[0121] The optimized layout places the high-heat-density GaN device groups D5 and D6 at the edge of the layout near the heat dissipation pads, reducing thermal coupling between devices. The overall thermal resistance is... Satisfying the maximum allowed value The constraints.

[0122] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects.

[0123] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for optimizing the layout of power semiconductor devices, comprising acquiring power density distribution data of power semiconductor devices and establishing a power density matrix, establishing a heat conduction model and calculating the thermal coupling coefficient between devices to construct a thermal coupling matrix, and iteratively optimizing the device position coordinates using simulated annealing or a genetic algorithm, characterized in that: Also includes: Static power consumption parameters are extracted from the device datasheet and dynamic power consumption data are obtained using SPICE-type circuit simulation tools. Static power consumption and dynamic power consumption are calculated and weighted by duty cycle to obtain a comprehensive power consumption value. The comprehensive power consumption value is normalized to obtain power density distribution data and the power density matrix is ​​constructed. A three-dimensional heat conduction model was established based on Fourier's law of heat conduction. The Green's function method was used to solve the three-dimensional steady-state heat conduction equation. The temperature response of a point heat source in a semi-infinite medium was obtained by solving the non-homogeneous Poisson equation. The thermal coupling coefficient between any two power semiconductor devices was calculated, and all thermal coupling coefficients were arranged according to the power semiconductor device numbers to form a... The thermal coupling matrix; Based on the thermal coupling matrix, a spectral clustering algorithm is used to divide the device set into several thermally balanced regions; With minimizing the temperature gradient difference within the thermal equilibrium region as the objective function, the device position coordinates are iteratively optimized using simulated annealing or a genetic algorithm. Set a temperature gradient difference threshold as a criterion for thermal equilibrium. When the temperature gradient difference of all K regions is lower than or equal to the temperature gradient difference threshold, the iteration terminates and the optimized layout scheme is output.

2. The method according to claim 1, characterized in that: The static power consumption parameters include leakage current, gate charge, and on-resistance; The dynamic power consumption data is obtained by simulating the switching behavior of power semiconductor devices in pulse width modulation or hard switching operation using SPICE-type circuit simulation tools. During the simulation, the energy loss in the voltage-current crossover region during each switching event is recorded and the energy loss is multiplied by the switching frequency to obtain the dynamic switching power consumption. The formula for calculating the overall power consumption value is as follows: in This represents the overall power consumption of a power semiconductor device. Indicates the duty cycle. Indicates dynamic switching power consumption. Indicates static power consumption; The power density distribution data is obtained by dividing the overall power consumption value by the actual area occupied by the power semiconductor device.

3. The method according to claim 1, characterized in that: The three-dimensional heat conduction model idealizes the dielectric substrate as a semi-infinite homogeneous medium, establishes a Cartesian coordinate system with the substrate surface as the XY plane and the positive Z-axis pointing inwards from the substrate. The three-dimensional steady-state heat conduction equation is in the form of: Where k represents the thermal conductivity of the substrate material, T represents the temperature, and Q represents the heat source intensity per unit volume; The analytical expression for the Green's function is: Where r represents the field point coordinate vector, and r' represents the source point coordinate vector; The thermal coupling coefficient The calculation expression is: ;in, Indicates the number is The footprint of power semiconductor devices; thermal coupling matrix matrix elements Equal to thermal coupling coefficient .

4. The method according to claim 1, characterized in that: The device assembly is divided into several thermal equilibrium regions using a spectral clustering algorithm, specifically including: An undirected weighted graph is constructed based on the thermal coupling matrix, mapping each power semiconductor device in the layout to a node in graph theory, and mapping the thermal coupling coefficients in the thermal coupling matrix to the edge weights connecting the nodes. A Laplacian matrix is ​​constructed based on the weighted graph, and the Laplacian matrix is ​​equal to the degree matrix minus the adjacency matrix; The optimal number of partitions K is determined by eigenvalue spectrum analysis of the Laplace matrix. The eigenvectors corresponding to the first K smallest eigenvalues ​​of the Laplacian matrix are extracted to form an N-by-K eigenvector matrix. Each row of the eigenvector matrix is ​​normalized, and the K-means clustering algorithm is used to cluster the normalized rows into K clusters, with each cluster corresponding to a thermal equilibrium region.

5. The method according to claim 1, characterized in that: After constructing the power density matrix, a two-dimensional grid interpolation method is used to generate a power density distribution map. The layout design area is used as the canvas to divide the grid into grid cells according to the preset grid resolution, and the power density value at the center point of each grid cell is calculated. The interpolation algorithm uses an inverse distance weighting method to calculate the Euclidean distance between the center point of the grid cell and the geometric center of each power semiconductor device in the layout, and uses the reciprocal of the square of the distance as the weight to perform a weighted summation of the power density values ​​of all power semiconductor devices. For grid cells in the boundary region, a mirror boundary condition is used. The power semiconductor devices inside the boundary are mirrored to virtual positions outside the boundary with the layout boundary as the axis of symmetry. Then, the power density value of the boundary grid cells is calculated using the same interpolation method.

6. The method according to claim 1, characterized in that: After constructing the thermal coupling matrix, eigenvalue analysis is performed on the thermal coupling matrix using the power iteration method to obtain the largest eigenvalue of the thermal coupling matrix. and its corresponding eigenvectors ; The iterative format of the power iteration method is: random initialization vector Repeatedly until convergence; When the largest eigenvalue The closer the value is to 1, the higher the overall thermal sensitivity of the thermal interaction network between power semiconductor devices; During the iterative optimization process, if the largest eigenvalue... If the value exceeds the preset threshold range, the penalty factor weight value of the thermal equilibrium constraint term will be increased or decreased accordingly.

7. The method according to claim 1, characterized in that: The simulated annealing algorithm and the genetic algorithm are combined in a sequential optimization strategy for collaborative optimization. First, the genetic algorithm is run to perform a global search, and the final result of the genetic algorithm is used as the initial solution of the simulated annealing algorithm. Then, the simulated annealing algorithm is run to perform a local fine search, and the final result of the simulated annealing algorithm is used as the final solution for overall optimization. The iteration number and parameter configuration of the collaborative optimization strategy are adaptively adjusted according to the layout size and the number of power semiconductor devices.

8. The method according to claim 1, characterized in that: The temperature gradient difference threshold is set based on the thermal tolerance analysis of power semiconductor devices: The temperature gradient difference threshold for silicon-based IGBT devices is set to 10 to 15 degrees Celsius. The temperature gradient difference threshold for silicon carbide MOSFET devices is set to 15 to 20 degrees Celsius. The temperature gradient difference threshold for gallium nitride devices is set to 5 to 10 degrees Celsius. The temperature gradient difference threshold setting supports automatic configuration according to device type. The configuration method is as follows: read the type identifier of the power semiconductor device in each thermal equilibrium area, match the corresponding temperature gradient difference threshold interval according to the type identifier, and take the midpoint of the interval as the initial threshold of the area.

9. The method according to claim 1, characterized in that: To correct the semi-infinite dielectric assumption with finite thickness, a sequence of mirrored heat sources on the bottom surface of the substrate is added to the Green's function expression using the mirror method. in, Indicates the substrate thickness. The order of the mirror source. The truncation order of the mirror source; the thermal coupling coefficient after finite thickness correction. Replace the original thermal coupling coefficient The formula used to construct the thermal coupling matrix is: 。 10. The method according to claim 1, characterized in that: During the iterative optimization process, heat conduction path constraints are embedded into the objective function. The overall thermal resistance distribution under different layout schemes is evaluated by calculating the thermal resistance network. An equivalent thermal resistance network is established from the junction of each power semiconductor device to the environment. The thermal resistance values ​​of the series paths are added together, and the thermal resistance values ​​of the parallel paths are taken as the reciprocal of the sum of the reciprocals. Finally, the equivalent total thermal resistance from the junction of the power semiconductor device to the environment is obtained. When the overall thermal resistance of the layout scheme Exceeding the maximum allowed value In this case, an overall thermal resistance constraint term is added to the augmented objective function. By increasing the penalty factor value, the objective function value is increased, guiding the search process to converge toward a lower thermal resistance.

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