Probe card simulation evaluation method, device, system and storage medium

Abstract

The application relates to the technical field of probe card simulation test, and discloses a simulation evaluation method of a probe card, which greatly reduces simulation calculation amount through hybrid modeling, thereby improving evaluation efficiency, realizes multi-parameter coupling linkage evaluation through multi-parameter batch scanning, thereby accurately simulating actual complex working conditions, and establishes quantitative correlation rules between frequency boundaries, protection resistance fault tolerance intervals and signal integrity under different sharing architectures based on quantitative judgment of eye opening, thereby providing fast and accurate quantitative basis for probe card architecture selection and parameter optimization, and effectively solving the technical problem that there is no efficient and multi-parameter coupling fast simulation evaluation mechanism in related technologies. The application also discloses a simulation evaluation device and system of the probe card and a storage medium.

Description

Technical Field

[0001] This application relates to the field of probe card simulation testing technology, such as a probe card simulation evaluation method and apparatus, a probe card simulation evaluation system, and a computer-readable storage medium. Background Technology

[0002] Currently, with the continuous increase in the demand for high-speed and high-density parallel testing of semiconductor chips, automated test systems generally adopt channel-sharing probe card structures. This allows multiple devices under test to share test channels, increasing the number of simultaneous tests and reducing testing costs. The architecture of probe cards has gradually evolved from early single-channel independent structures to highly multiplexed shared topologies such as two-channel sharing, four-channel sharing, and eight-channel sharing. In traditional design methods, the industry mainly relies on 3D electromagnetic simulation, physical prototype testing, and item-by-item verification of individual indicators to complete the performance evaluation of probe cards. However, with the continuous increase in chip testing speed, signal degradation problems caused by channel crosstalk, impedance fluctuations, and protection resistor deviations are becoming increasingly prominent. This places higher demands on the frequency adaptation capability, resistance consistency, and the accuracy and speed of eye diagram signal quality evaluation for probe cards.

[0003] In related technologies, the simulation evaluation methods for probe cards mainly include performing three-dimensional electromagnetic simulation for specific shared topologies, measuring signal integrity using time-domain testing equipment after physical prototyping, and verifying individual indicators such as operating frequency, protection resistor value, and eye diagram margin item by item.

[0004] In the process of implementing the embodiments of this application, at least the following problems were found in the related technology: The evaluation methods for related technologies mostly rely on independent analysis of single indicators, lacking a mechanism for coupled and linked evaluation of multiple key parameters such as shared topology, operating frequency, and protection resistor values. This fails to simulate signal integrity under actual multi-parameter operating conditions, leading to significant deviations between simulation evaluation results and actual measurements. Furthermore, traditional full-size 3D simulation models are computationally intensive and have extremely long simulation cycles, making it difficult to meet the time requirements for rapid iterative selection. In addition, related technologies have not yet established quantitative correlation rules between frequency boundaries, protection resistor tolerance ranges, and eye diagram opening for different shared architectures. This makes probe card design selection and parameter matching heavily reliant on experience-based judgment, resulting in insufficient design margins, low yield rates in physical testing, and high rework rates.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a simulation evaluation method and apparatus for probe cards, a simulation evaluation system for probe cards, and a computer-readable storage medium to solve the technical problems of existing probe card simulation evaluation technologies lacking an efficient, multi-parameter coupled rapid simulation evaluation mechanism, resulting in low simulation efficiency, inaccurate quantification of the combined effects of multiple parameters, and a lack of quantitative basis for design selection.

[0008] In some embodiments, the probe card includes a shared node and multiple probe branches connected to the shared node; the method includes: establishing a three-dimensional electromagnetic simulation model for the shared bifurcation region where the shared node is located in the probe card, and establishing an equivalent transmission line model for the non-core region to construct a hybrid simulation model including the three-dimensional electromagnetic simulation model and the equivalent transmission line model; in the hybrid simulation model, setting multiple sets of values ​​for multiple parameter dimensions respectively, and performing batch scanning simulation to obtain frequency domain parameters; the multiple parameter dimensions include the shared topology, the operating frequency, and the resistance value of the protection resistor set on the probe branch; performing time-domain eye diagram simulation based on the frequency domain parameters to extract the eye diagram opening degree under each operating condition; the eye diagram opening degree is determined based on the ratio of the effective eye width time to the eye diagram opening width, wherein the eye diagram opening width is determined based on the statistical distribution of the waveform edge crossing time, and the effective eye width time is determined based on the time width corresponding to the preset percentage interval of the voltage swing; evaluating the performance of the probe card under each operating condition based on the comparison result of the eye diagram opening degree and the preset level threshold.

[0009] In some embodiments, the apparatus includes a processor and a memory storing program instructions, wherein the processor is configured to execute the aforementioned simulation evaluation method for the probe card when executing the program instructions.

[0010] In some embodiments, the probe card simulation evaluation system includes: a probe card simulation evaluation system body; and the aforementioned probe card simulation evaluation device is installed in the probe card simulation evaluation system body.

[0011] In some embodiments, the computer-readable storage medium stores program instructions that, when executed, perform the aforementioned simulation evaluation method for the probe card.

[0012] The simulation evaluation method, apparatus, system, and storage medium for probe cards provided in this disclosure can achieve the following technical effects: By constructing a hybrid simulation model that includes a 3D electromagnetic simulation model of the core region and an equivalent transmission line model of the non-core region, the simulation computation scale is significantly reduced, and simulation efficiency is significantly improved while ensuring the accuracy of the core region. By setting multiple sets of values ​​for multiple parameter dimensions such as shared topology, operating frequency, and protection resistor value, and performing batch scanning simulations, multi-parameter coupled linkage evaluation can be achieved, fully simulating complex operating conditions under the combined action of multiple parameters, making the simulation results closer to actual measurements. On this basis, the eye diagram opening is defined based on the ratio of eye diagram opening width to effective eye width time. The eye diagram opening width is determined by the statistical distribution of waveform edge crossing times, and the effective eye width time is determined by the preset percentage range of voltage swing. This allows for precise quantification of the degree of signal integrity degradation and automatic graded evaluation of performance under various operating conditions based on preset level thresholds. This method effectively solves the problems of low simulation efficiency, isolated parameter evaluation, and design matching dependence on experience in existing technologies. It can provide a fast and accurate quantitative basis for probe card architecture selection, frequency boundary determination, and protection resistor fault tolerance range determination, significantly improving the first-time pass rate of design and reducing rework costs.

[0013] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0014] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a simulation evaluation method for a probe card provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the eye diagram simulation effect under a simulation condition provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the eye diagram simulation effect under another simulation condition provided in this embodiment of the present disclosure; Figure 4 This is a schematic diagram of the eye diagram simulation effect under another simulation condition provided in this embodiment of the present disclosure; Figure 5 This is a schematic diagram of the eye diagram simulation effect under another simulation condition provided in this embodiment of the present disclosure; Figure 6 This is a schematic diagram of a simulation evaluation device for a probe card provided in an embodiment of this disclosure.

[0015] Figure label: 800: Simulation and evaluation device for probe card; 801: Processor; 802: Memory; 803: Communication interface; 804: Bus. Detailed Implementation

[0016] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0017] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. The terms "upper," "lower," "inner," "middle," "outer," "front," "rear," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. Unless otherwise stated, the term "multiple" means two or more. The character " / " indicates that the preceding and following objects are in an "or" relationship. The terms "and / or" indicate that three relationships can exist. The term "corresponding" refers to an association or binding relationship. It should be noted that, without conflict, the embodiments and features in the embodiments of this disclosure can be combined with each other.

[0018] This disclosure provides a simulation evaluation system for a probe card, including a probe card simulation evaluation system body and a probe card simulation evaluation device 800, which is installed in the probe card simulation evaluation system body. The installation relationship described herein is not limited to placement within the probe card simulation evaluation system, but also includes installation connections with other components of the probe card simulation evaluation system, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the probe card simulation evaluation device 800 can be adapted to feasible probe card simulation evaluation system bodies to achieve other feasible embodiments. The probe card simulation evaluation system body includes a shared branch area, a non-core area, protective resistors on each probe branch disposed after the shared node, and probe tips. The probe card simulation evaluation device 800 includes a processor 801, which is communicatively connected to the probe card simulation evaluation system body and is used to control at least a portion of the probe card simulation evaluation system body to operate.

[0019] Figure 1This is a schematic diagram of the simulation evaluation method for probe cards provided in this embodiment. Any of the following methods can be executed in the simulation evaluation system for probe cards, or in a server or terminal device that is communicatively connected to the simulation evaluation system for probe cards.

[0020] Based on the above system structure, such as Figure 1 As shown, this disclosure provides a simulation evaluation method for a probe card, the probe card including a shared node and multiple probe branches connected to the shared node; the method includes: S01. Establish a three-dimensional electromagnetic simulation model for the shared bifurcation region where the shared node is located in the probe card, and establish an equivalent transmission line model for the non-core region, so as to construct a hybrid simulation model that includes the three-dimensional electromagnetic simulation model and the equivalent transmission line model.

[0021] S02, in the hybrid simulation model, multiple sets of values ​​are set for multiple parameter dimensions, and batch scanning simulation is performed to obtain frequency domain parameters; the multiple parameter dimensions include shared topology, operating frequency, and the resistance value of the protection resistor set on the probe branch.

[0022] S03, perform time-domain eye diagram simulation based on frequency domain parameters to extract eye diagram opening under each operating condition; the eye diagram opening is determined based on the ratio of effective eye width time to eye diagram opening width, wherein the eye diagram opening width is determined based on the statistical distribution of waveform edge crossing time, and the effective eye width time is determined based on the time width corresponding to the preset percentage interval of voltage swing.

[0023] S04. Based on the comparison results between the eye diagram opening degree and the preset level threshold, evaluate the performance of the probe card under various working conditions.

[0024] In this embodiment, the three-dimensional electromagnetic simulation model performs three-dimensional solid geometric modeling of the conductor structure, dielectric layering, and metal boundaries within the shared bifurcation region, and refines the mesh at the conductor surface, dielectric interface, and regions with drastic field strength changes. The equivalent transmission line model simplifies the representation of regions where the cross-section remains unchanged along the transmission direction. By refining the solution of discontinuous regions using the three-dimensional electromagnetic simulation model and simplifying the representation of continuous regions using the equivalent transmission line model, the geometric range of the three-dimensional full-wave simulation is significantly reduced while ensuring the accuracy of electromagnetic field calculations at key discontinuities, thereby reducing computational resource consumption and simulation time.

[0025] The 3D electromagnetic simulation model employs an adaptive meshing strategy. First, an initial mesh is generated at the conductor edge and dielectric interface within the shared bifurcation region, with the initial mesh size not exceeding one-fifth of the minimum physical size of that region. Then, the mesh is iteratively refined based on the spatial distribution gradient of the electric field intensity. In regions where the electric field gradient magnitude exceeds a preset gradient threshold, the mesh size is reduced to half of the previous mesh size. This iteration is repeated until the rate of change of the scattering parameter matrix between adjacent iterations is less than a preset convergence threshold (one percent). After adaptive meshing, an additional boundary layer mesh is applied to the conductor surface within the shared bifurcation region. The thickness of the first layer mesh in the direction perpendicular to the conductor surface is no greater than one-third of the skin depth, and the ratio of the mesh size to the thickness of the first layer mesh in the direction parallel to the conductor surface is no less than three to one and no greater than ten to one.

[0026] The establishment of the equivalent transmission line model includes: extracting the cross-sectional geometric parameters (including the width and thickness of the signal conductor, the thickness of the dielectric layer between the signal conductor and the adjacent reference plane, and the type of dielectric material) for each transmission line segment in the non-core region; based on the above parameters and the preset electromagnetic parameters of the dielectric material, calculating the resistance, inductance, conductance, and capacitance per unit length using transmission line theory; and multiplying the above unit length parameters by the physical length of the transmission line segment to obtain the lumped equivalent circuit model (composed of series resistance, series inductance, parallel conductance, and parallel capacitance). When the physical length of the transmission line segment is greater than one-tenth of the wavelength corresponding to the highest frequency of the operating frequency band, the transmission line segment is divided into multiple sub-segments, each with a physical length not exceeding one-tenth of the wavelength. Lumped equivalent circuit models are then established for each sub-segment and cascaded sequentially according to the transmission direction.

[0027] In the hybrid simulation model, the frequency domain electromagnetic simulation is performed using the 3D electromagnetic field simulation software HFSS. Within the HFSS environment, the 3D electromagnetic simulation model for the core region employs a driven mode solution type, with the solution frequency set to twice the highest operating frequency of the target chip, and port field enhancement calibration enabled. The equivalent transmission line model for the non-core region is modeled using transmission line elements from the circuit element library. The connection between the 3D electromagnetic simulation model and the equivalent transmission line model is achieved through boundary coupling between port elements and circuit elements in HFSS. Specifically, the ports of the 3D electromagnetic simulation model and the equivalent transmission line model are set with the same characteristic impedance and reference impedance, enabling reflection-free transmission of frequency domain electromagnetic energy between the two models.

[0028] In this embodiment, the shared topology, operating frequency, and resistance value of the protection resistor each have multiple sets of discrete values. In the hybrid simulation model, after setting multiple sets of discrete values ​​for each of the three parameter dimensions, the batch scanning function of the simulation platform is triggered to traverse all combinations of values ​​for each parameter dimension, and frequency domain electromagnetic simulation is performed for each combination to obtain the frequency domain parameters corresponding to each combination.

[0029] In this embodiment, when performing time-domain eye diagram simulation based on frequency domain parameters, the frequency domain parameters are converted into time-domain impulse responses. Then, the test bitstream and the impulse response are convolved to obtain the time-domain output waveform after passing through the probe card link, thereby generating an eye diagram. The process of converting frequency domain parameters into time-domain impulse responses adopts the inverse Fourier transform method: a Hanning window function is applied to the complex scattering parameter values ​​at each frequency sampling point in the scattering parameter file, with a window length of 80% of the total number of frequency sampling points to suppress the Gibbs effect caused by frequency band truncation; an inverse Fourier transform is performed on the windowed scattering parameter sequence to obtain the time-domain impulse response sequence; time shift correction is performed to shift the main peak time to time zero; truncation is performed to retain the response values ​​within a preset time window before and after the main peak (three times the reciprocal of the frequency range covered by the scattering parameter file), and the response values ​​outside the range are set to zero.

[0030] In this embodiment, the eye opening is equal to the effective eye width time divided by the eye opening width. The eye opening width is determined based on the statistical distribution of waveform edge crossing times, and the effective eye width time is determined based on the time width corresponding to a preset percentage interval of the voltage swing. The performance level of each operating condition is determined based on the comparison between the eye opening and a preset grade threshold. The eye openings under multiple operating conditions are sorted, and a ranking list of the performance of each operating condition is generated based on the ranking results. The shared topology level, operating frequency value, protection resistor value, and corresponding eye opening value of each operating condition are listed in descending order of eye opening. When two or more operating conditions have the same eye opening, the operating condition with the lower operating frequency is prioritized, followed by the operating condition with the lower shared topology level. All operating conditions with an eye opening not lower than the excellent grade threshold are marked as the preferred operating condition set, and all operating conditions with an eye opening not lower than the good grade threshold are marked as the candidate operating condition set.

[0031] The simulation evaluation method for probe cards provided in this disclosure can significantly reduce the amount of simulation computation through hybrid modeling, thereby improving evaluation efficiency. It can achieve multi-parameter coupled linkage evaluation through multi-parameter batch scanning, thereby accurately simulating actual complex working conditions. Furthermore, based on the quantitative determination of eye diagram opening, it establishes quantitative correlation rules between frequency boundaries, protection resistor fault tolerance ranges, and signal integrity under different shared architectures, thus providing a fast and accurate quantitative basis for probe card architecture selection and parameter optimization.

[0032] Optionally, the shared bifurcation region and non-core region are divided based on structural continuity; regions with structural continuity are designated as non-core regions, and regions with structural discontinuity are designated as core regions.

[0033] In this embodiment, the specific criteria for determining structural continuity are whether the rate of change of the cross-sectional shape, conductor width, conductor spacing, and dielectric layer thickness of the region along the signal transmission direction is less than a preset rate of change threshold (a fixed value between 5% and 15%, preferably 10%). For N cross-sections (N greater than or equal to 10) selected at equal intervals along the transmission direction in the region, the conductor width W_i, conductor spacing S_i, and dielectric layer thickness H_i at each cross-section are measured respectively. The ratio of the absolute value of the change of each parameter between adjacent cross-sections to the corresponding parameter value of the previous cross-section is calculated, and the maximum value of the ratio between all adjacent cross-sections is taken as the rate of change of the geometric parameter. If any one of the conductor width change rate, conductor spacing change rate, and dielectric layer thickness change rate exceeds the preset rate of change threshold, the region is determined to be a structurally discontinuous region. When there is a sudden change in conductor width or conductor spacing in the region and the ratio of the change in conductor width before and after the sudden change point to the conductor width before the sudden change point exceeds 30%, or when the ratio of the change in conductor spacing before and after the sudden change point to the conductor spacing before the sudden change point exceeds 30%, the region where the sudden change point is located is designated as a non-core region. The structural discontinuity region includes the shared fork region where the shared fork node is located, the probe tip region, the pad region, and the transition region between different linewidths. The structural continuity region consists of parallel transmission line segments of equal width and spacing, whose cross-section remains unchanged in the transmission direction. Electromagnetic waves propagate in a quasi-transverse electromagnetic wave mode within the structural continuity region. The determination of structural continuity can also be adjusted in conjunction with the electromagnetic wave wavelength corresponding to the probe card's operating frequency band: when the operating frequency increases, the preset rate of change threshold is lowered, allowing more areas to be designated as non-core areas; when the operating frequency decreases, the preset rate of change threshold is increased.

[0034] In this way, a reasonable balance is achieved between simulation accuracy and simulation efficiency.

[0035] Optionally, the equivalent transmission line model adopts a stripline model; the dielectric layer thickness, dielectric constant, transmission line width, and transmission line thickness of the stripline model are preset fixed values.

[0036] In this embodiment, the stripline model consists of two reference planes, upper and lower, and a signal conductor located between the two reference planes, with the signal conductor completely embedded in the dielectric layer. The characteristic impedance of the stripline model is determined by the dielectric layer thickness, dielectric constant, transmission line width, and transmission line thickness; when these four parameters are fixed, the characteristic impedance of the stripline model is also fixed. An equivalent transmission line model can also be achieved using a microstrip line model; the microstrip line model consists of a top-layer signal conductor, a dielectric layer, and a bottom-layer reference plane. When the signal conductor in the non-core area is located on an intermediate layer of a multilayer printed circuit board and has continuous reference planes on both the upper and lower sides, the stripline model is used for equivalence; when the signal conductor in the non-core area is located on the top or bottom layer of a multilayer printed circuit board and has a continuous reference plane only below the signal conductor, the microstrip line model is used for equivalence. The choice of the equivalent transmission line model also depends on the actual wiring density of the signal conductors in the non-core area: when the number of signal conductors per unit area exceeds twenty per square centimeter, the stripline model is used for equivalence; when it does not exceed the density threshold, the microstrip line model or the coplanar waveguide model is used for equivalence.

[0037] In this embodiment, the stripline model has a dielectric layer thickness of 4.6 mil, a dielectric constant of 3.4, a transmission line width of 4 mil, a transmission line thickness of 0.65 mil, and a characteristic impedance of 50 Ω. These preset fixed values ​​are determined using the commercial transmission line impedance calculation software Polar Si9000 in conjunction with the following calculation process: The nominal values ​​of the dielectric layer thickness and dielectric constant are obtained from the probe card printed circuit board stack-up design data; the nominal values ​​of the transmission line width and thickness are obtained from the wiring design rules; these four nominal values ​​are input into the stripline calculation module of the Polar Si9000 software, and the characteristic impedance is calculated using the boundary element method; if the calculated characteristic impedance deviates from the 50 Ω target value by more than ±5%, the nominal value of the transmission line width is adjusted and recalculated until the characteristic impedance converges to within ±5% of the 50 Ω target value; the finally adjusted transmission line width value and the other three parameter values ​​are used together as the preset fixed values.

[0038] In this way, by setting the geometric and material parameters of the stripline model to fixed values, the uniqueness of parameter changes in multi-parameter scanning simulation is ensured by three variables: shared topology, operating frequency, and protection resistor value.

[0039] Optionally, the protection resistors are set on each probe branch after the shared node, and each protection resistor is a lumped parameter element.

[0040] In this embodiment, the shared node is a circuit connection node that branches from the main transmission line into multiple probe branches. Protective resistors are located on each probe branch after the shared node and before the probe tip. The protective resistor is defined as a lumped-parameter element, meaning it is considered an ideal resistor whose electrical characteristics are determined solely by its resistance value, excluding parasitic capacitance and inductance. The lower limit of the protective resistor's resistance value scan range is no less than one-third of the signal driver output impedance on the probe branch, and the upper limit is no more than three times the signal driver output impedance. When the operating frequency exceeds 1 GHz, a higher-order equivalent model is constructed by adding parallel parasitic capacitance and series parasitic inductance to the lumped-parameter model; the parallel parasitic capacitance is 0.1 picofarads to 0.5 picofarads, and the series parasitic inductance is 0.5 nanohenries to 2 nanohenries. The values ​​of parallel parasitic capacitance and series parasitic inductance are determined based on the physical package size of the protective resistor: 0.3 picofarads and 1.2 nanohenries for 0603 imperial size; 0.15 picofarads and 0.6 nanohenries for 0402 imperial size; 0.08 picofarads and 0.3 nanohenries for 0201 imperial size; and obtained through linear interpolation for other package sizes.

[0041] This simplifies the complexity of the simulation model and provides a reliable component model basis for scanning the resistance value of the protection resistor.

[0042] Optionally, the shared topology includes at least one of the following topologies: non-shared mode, 2-level shared mode, 4-level shared mode, and 8-level shared mode.

[0043] In this embodiment, the non-shared mode has the main transmission line directly connected to a probe branch, with no branching at the shared node, and one test channel serves only one device under test (DUT). In the 2-level shared mode, the main transmission line branches into two probe branches at the shared node, and one test channel serves two DUTs simultaneously. In the 4-level shared mode, the main transmission line branches into four probe branches at the shared node, and one test channel serves four DUTs simultaneously. In the 8-level shared mode, the main transmission line branches into eight probe branches at the shared node, and one test channel serves eight DUTs simultaneously. The shared topology can also include 16 levels of shared modes, with different numbers of branches but the same hybrid modeling and multi-parameter batch scanning methods. The branching angles of the probe branches corresponding to each of the above shared topology levels within the shared branching region are set to the same preset angle value (a fixed angle between 45 and 90 degrees). In the alternative scheme, the bifurcation angle is adaptively adjusted according to the shared topology level: 180 degrees for level 2 sharing mode, 90 degrees for level 4 sharing mode, and 45 degrees for level 8 sharing mode. A separate hybrid simulation model is established for each shared topology level. The topology of the shared bifurcation region is geometrically modeled according to the number of bifurcations in that level, while the equivalent transmission line model and protection resistor settings for non-core areas remain consistent.

[0044] In this way, by establishing models and conducting simulations across multiple shared topology levels, the signal integrity performance of each shared topology can be compared horizontally under completely identical conditions, thereby accurately assessing the impact of the shared fork itself on signal quality.

[0045] Optionally, the multiple sets of operating frequency values ​​are multiple discrete frequency values, and the multiple sets of protection resistor values ​​are multiple discrete resistance values; each discrete frequency value and each discrete resistance value is set according to the specifications of the chip under test.

[0046] In this embodiment, the discrete frequency values ​​include at least two selected from 50MHz, 100MHz, 133MHz, 150MHz, and 200MHz; the discrete resistance values ​​include at least two selected from 180Ω, 240Ω, 300Ω, and 360Ω. The selection of the discrete frequency values ​​covers the entire frequency band from the lowest to the highest operating frequency required by the chip under test specifications, with a denser frequency step size in the latter third of the highest operating frequency band compared to the first two-thirds. The selection of the discrete resistance values ​​covers the nominal resistance value of the probe card's protection resistor and its extended resistance range above and below it, with a lower limit of 60% of the nominal resistance value and an upper limit of 140% of the nominal resistance value. The step size between adjacent discrete resistance values ​​is no greater than 20% of the nominal resistance value. The number of discrete frequency value ranges is determined based on simulation requirements and computational resources; fewer ranges are selected for initial rapid screening, while all ranges are selected for refined evaluation. The discrete frequency values ​​can be selected as 25MHz, 66MHz, 125MHz, or 250MHz depending on the target chip protocol; the discrete resistance values ​​can be selected as 150Ω, 220Ω, 270Ω, or 330Ω depending on the component supplier's nominal value series. Boundary values ​​are added beyond the range specified in the specifications to evaluate the performance margin of the probe card when it exceeds the specification range.

[0047] In this way, by using the specifications of the chip under test as the benchmark for setting discrete frequency and discrete resistance values, the simulation evaluation results are closely aligned with actual engineering needs, while also providing a basis for judging the design redundancy of the probe card.

[0048] Optionally, the fixed parameters in the hybrid simulation model include at least one of the following: printed circuit board material, dielectric constant of printed circuit board material, loss factor of printed circuit board material, stripline width, stripline spacing, stripline thickness, dielectric layer thickness, probe material, probe length, and probe diameter.

[0049] In this embodiment, the dielectric constant of the printed circuit board substrate determines the speed at which electromagnetic waves propagate in the medium, and the loss factor determines the energy attenuation of electromagnetic waves during propagation. The curves showing the dielectric constant and loss factor changing with temperature within a preset temperature range of 25°C to 125°C are pre-stored. During simulation evaluation, the corresponding parameter values ​​are selected from the curves based on the actual operating temperature of the probe card; when the actual operating temperature is unknown, the parameter values ​​at 85°C are used by default. The stripline width affects characteristic impedance and conductor loss; the stripline spacing affects crosstalk strength; the stripline thickness affects DC resistance and skin effect loss; and the dielectric layer thickness affects characteristic impedance and dielectric loss. Different conductivity of the probe material affects the probe's resistance and frequency response; the probe length affects parasitic inductance and transmission delay; and the probe diameter affects contact resistance and parasitic capacitance. The conductivity of the probe material is corrected for temperature coefficient variations: ±1.2 per thousandth of a degree Celsius for beryllium copper, ±0.8 per thousandth of a degree Celsius for palladium copper alloy, and ±0.5 per thousandth of a degree Celsius for tungsten rhenium alloy. The probe length and diameter are corrected based on the wear condition of the probe tip: when the probe length shortens by more than 5% of the initial length, the corrected length value is used; when the probe diameter increases by more than 10% of the initial diameter, the corrected diameter value is used. Fixed parameters remain constant throughout the multi-parameter scanning simulation. When different probe card designs are used, the specific values ​​of the fixed parameters are adjusted accordingly, but remain constant throughout the entire simulation evaluation task after being set. The printed circuit board material is EM888, with a dielectric constant of 3.4 and a loss factor of 0.003; the stripline width is 4mil, the line spacing is 12mil, and the thickness is 0.65mil; the dielectric layer thickness is 4.6mil; the probe material is beryllium copper, the probe length is 5.35mm, and the probe diameter is 0.38mm.

[0050] In this way, by explicitly listing the fixed parameters in the hybrid simulation model, the uniqueness of variables in multi-parameter sweep simulation is further guaranteed.

[0051] Optionally, the frequency sweep range of the frequency domain parameters is from DC to five times the highest operating frequency of the target chip.

[0052] In this embodiment, the frequency sampling points within the frequency scanning range are non-uniformly distributed: the step size is one-fiftieth of the target chip's highest operating frequency in the frequency band from DC to the target chip's highest operating frequency; the step size is one-twentieth of the target chip's highest operating frequency to its third harmonic; and the step size is one-tenth of the target chip's third harmonic to its fifth harmonic. The upper limit of the frequency scanning range can also be determined based on the signal rise time specified by the target chip's interface protocol. The effective bandwidth of the signal is equal to 0.35 divided by the rise time; the upper limit of the frequency scanning range is the greater of five times the target chip's highest operating frequency and the effective bandwidth. The frequency scanning range is 0 to 1 GHz.

[0053] In this way, by adaptively adjusting the frequency scanning range according to the signal rise time, the bandwidth shortage problem of the fixed multiple strategy in the case of extremely fast edge signal scenarios is avoided.

[0054] Optionally, the frequency domain parameters are output as a scattering parameter file.

[0055] In this embodiment, the scattering parameter file contains scattering parameter matrices for each port in the hybrid simulation model. Each element in the scattering parameter matrix is ​​a complex number, whose amplitude represents the ratio of the reflected or transmitted amplitude of the signal at that frequency point, and whose phase represents the phase shift of the signal at that frequency point. Before output, the scattering parameter matrix undergoes port normalization processing, uniformly converting the reference impedance of each port to a 50Ω standard impedance value. The specific steps of port normalization are as follows: a first normalization factor is applied to each diagonal element in the scattering parameter matrix, and a second normalization factor is applied to each off-diagonal element. Both the first and second normalization factors are determined by the ratio between the default impedance value of the port and the 50Ω standard impedance value. The scattering parameter file corresponding to the hybrid simulation model contains one input port and multiple output ports. The input port corresponds to the input endpoint of the main transmission line, and each output port corresponds to the end endpoint of each probe branch. The scattering parameter file is output as an SNP file in Touchstone format, where N represents the total number of ports in the hybrid simulation model.

[0056] In this way, by outputting frequency domain parameters in the form of scattering parameter files, standardized data exchange between frequency domain electromagnetic simulation and time domain circuit simulation is achieved.

[0057] Optionally, the time-domain eye diagram simulation is performed using parametric scan settings. The parametric scan settings configure the operating frequency and protection resistor as parametric variables, and configure multiple sets of values ​​for each parametric variable. By triggering the batch execution function of the simulation platform, all combinations of values ​​for each set of parametric variables are traversed, and the time-domain eye diagram simulation under each combination is executed.

[0058] In this embodiment, the parametric scan setting further includes setting the scan order among the parametric variables: first traversing the shared topology range, then traversing the operating frequency range, and finally traversing the protection resistor value range. In an alternative embodiment, the scan order is to first traverse the protection resistor value range, then traverse the operating frequency range, and finally traverse the shared topology range. The parametric scan setting defines the operating frequency as the parameter variable Frequency and the protection resistor as the parameter variable PR in the time-domain simulation platform, and then assigns a set of discrete values ​​to each. When the time-domain simulation platform receives the simulation command, it automatically traverses all value combinations and performs a time-domain eye diagram simulation for each combination. During each simulation execution, the parameter variable values ​​under the current combination are substituted into the corresponding component parameters in the time-domain simulation circuit, a time-domain transient simulation is performed, and an eye diagram is generated. Finally, the built-in eye diagram measurement function is used to extract the eye diagram opening width and effective eye width time under this combination and calculate the eye diagram opening degree. The shared topology levels configured in the parametric scan settings are traversed using a batch execution method: the first batch executes all combinations of non-shared mode and level 2 shared mode; the second batch executes all combinations of level 4 shared mode; and the third batch executes all combinations of level 8 shared mode. After each batch is completed, the corresponding intermediate evaluation results are output. If the eye diagram opening of all conditions in the intermediate evaluation results of the first batch is higher than the excellent level threshold, the execution of subsequent batches is skipped. The batch execution function of the parametric scan settings supports parallel execution, allowing the time-domain simulation platform to simultaneously execute simulation tasks with different parameter combinations on multiple computing cores.

[0059] In this way, by adopting parametric scan settings and batch execution functions, time-domain eye diagram simulation under multiple parameter combinations can be completed automatically and efficiently.

[0060] Optionally, the test bitstream for time-domain eye diagram simulation is a pseudo-random binary sequence; the voltage swing of the test bitstream is a preset voltage range; and the rise and fall times of the test bitstream are preset time values.

[0061] In this embodiment, the initial phase of the pseudo-random binary sequence of the test code stream is set to a non-zero preset initial phase value. During repeated time-domain eye diagram simulations, a different preset initial phase value is used each time, and the average eye opening obtained from multiple simulations is taken as the final eye opening under that operating condition. The pseudo-random binary sequence is PRBS15; the voltage swing is 0V to 1V; and the rise and fall times are both 416ps. The length of the PRBS15 sequence is 32767 bits. The voltage swing, rise time, and fall time parameters of the test code stream are kept fixed in the time-domain eye diagram simulation to ensure the comparability of eye diagram results under different shared topologies, different operating frequencies, and different protection resistor values. The test code stream can also use a clock pattern or a repeated specific data sequence.

[0062] In this way, by using a pseudo-random binary sequence as the test bitstream and fixing its parameters, the consistency of simulation results under various operating conditions is ensured.

[0063] Optionally, the statistical distribution of waveform edge crossing times is obtained as follows: using the average value of the waveform's high and low levels as the horizontal measurement reference voltage; extracting the left and right crossing edge times of all waveforms along the horizontal measurement reference voltage; generating a left crossing edge time histogram based on the left crossing edge times of all waveforms, and generating a right crossing edge time histogram based on the right crossing edge times of all waveforms; determining the mean and standard deviation of the left crossing edge based on the left crossing edge time histogram, and determining the mean and standard deviation of the right crossing edge based on the right crossing edge time histogram.

[0064] In this embodiment, the binning width of the left cross-edge time histogram and the right cross-edge time histogram is one-hundredth of the eye diagram bit interval; edge events in each histogram whose time deviation values ​​exceed plus or minus three times the standard deviation are marked as outliers and removed. The mean is calculated using a weighted average method, where the weight is the number of events corresponding to each time deviation value; the standard deviation is calculated using an unbiased estimation method. The eye diagram opening width is determined according to the following formula: Where μTL is the mean of the left cross edge, σTL is the standard deviation of the left cross edge, μTR is the mean of the right cross edge, σTR is the standard deviation of the right cross edge, and EyeWidth is the eye diagram opening width. The selection of three standard deviations corresponds to a confidence level of 10 to the power of -12 for the bit error rate. The coefficients in the formula can be adjusted to other values ​​according to the bit error rate requirements: from 3 to 4 or 5 when the bit error rate requirement is higher; and from 2.5 when the bit error rate requirement is more lenient. The above coefficients are also adaptively adjusted according to the application scenario of the probe card: a value of 3.5 is used for mass production testing, and a value of 2.5 is used for engineering verification or design debugging. When the difference between the mean of the left cross edge and the mean of the right cross edge is less than the sum of three times the standard deviation of the left cross edge and three times the standard deviation of the right cross edge, the eye diagram opening width is forcibly set to zero.

[0065] Thus, the eye diagram opening width becomes a quantitative indicator with a clear meaning of bit error rate.

[0066] Optionally, the effective eye width time is the time domain width corresponding to the range of 20% to 80% of the voltage swing.

[0067] In this embodiment, the voltage values ​​corresponding to the 20% and 80% positions of the voltage swing are determined; horizontal lines are drawn vertically at the 20% and 80% positions in the eye diagram; the smaller of the right intersection time value of the horizontal line at the 20% position and the right intersection time value of the horizontal line at the 80% position is taken as the effective right boundary time, and the larger of the left intersection time value of the horizontal line at the 20% position and the left intersection time value of the horizontal line at the 80% position is taken as the effective left boundary time; the effective eye width time is obtained by subtracting the effective left boundary time from the effective right boundary time. When the left and right boundaries of the eye diagram are asymmetrical, the effective left boundary time (the larger of the left intersection time values ​​corresponding to the 20% and 80% positions of the left boundary) and the effective right boundary time (the smaller of the right intersection time values ​​corresponding to the 20% and 80% positions of the right boundary) are calculated respectively, and then the difference is calculated. The voltage percentage range can also be adjusted according to the sensitivity and noise margin of the decision circuit: reduced to 30% to 70% for differential receivers with high sensitivity; and expanded to 10% to 90% for single-ended receivers that are susceptible to power supply noise.

[0068] In this way, the effective eye width time can comprehensively reflect the constraint of the voltage margin in the vertical direction on the effective sampling interval.

[0069] Optionally, the eye opening is determined according to the following formula: EyeOpening = EyeTime / EyeWidth; where EyeTime is the effective eye width time, EyeWidth is the eye opening width, and EyeOpening is the eye opening degree.

[0070] In this embodiment, the eye opening can also be expressed as a percentage. The eye opening is further corrected in conjunction with the eye opening height as follows: the eye opening height (the maximum opening voltage value of the eye in the vertical direction) is extracted; a correction factor is calculated equal to the ratio of the eye opening height to the voltage swing; the eye opening is multiplied by this correction factor to obtain the corrected eye opening. The eye opening can also be converted into an absolute time margin based on the probe card's operating frequency, which is equal to the eye opening multiplied by the unit bit interval (the reciprocal of the operating frequency).

[0071] In this way, signal integrity can be compared on a unified scale under different operating frequencies, different shared topologies, and different protection resistor values.

[0072] Optionally, the preset grade thresholds include an excellent grade threshold, a good grade threshold, and a poor grade threshold; when the eye opening is greater than the excellent grade threshold, it is determined to be excellent; when the eye opening is greater than the good grade threshold and less than or equal to the excellent grade threshold, it is determined to be good; when the eye opening is less than or equal to the good grade threshold, it is determined to be poor.

[0073] In this embodiment, the excellent grade threshold is 80%, and the good grade threshold is 60%. When the eye opening is within the transition range of 60% to 80%, a transition grade indicator is generated based on the relative position of the eye opening within this transition range: a slightly better grade indicator is generated when it is greater than 70%, and a slightly worse good grade indicator is generated when it is less than or equal to 70%. The preset grade thresholds can be further subdivided into five or seven grades. The excellent and good grade thresholds can be dynamically adjusted according to the application scenario: set to 70% and 50% in the rapid screening stage, and 85% and 65% in the final verification stage.

[0074] This enables automated grading and evaluation of probe card performance.

[0075] Optionally, after evaluating the performance of the probe card under various operating conditions, the evaluation also includes: outputting an evaluation report, which includes at least one of the following: the eye opening degree and its corresponding performance level under each operating condition; the limiting operating frequency and the range of compliant protection resistor values ​​under each shared topology; and the operating condition configuration with the optimal eye opening degree.

[0076] In this embodiment, the evaluation report displays the eye opening and corresponding performance level under each operating condition in tabular form. Different operating frequency ranges are listed in the row direction, and different protection resistor value ranges are listed in the column direction. Each table cell is filled with the percentage value of the eye opening under that combination and the corresponding level identifier. The limiting operating frequency under each shared topology is determined as follows: For each shared topology range, all operating frequency ranges are checked one by one in descending order. When at least one set of protection resistor values ​​exists under a certain operating frequency range such that the eye opening is not lower than the good grade threshold, that operating frequency range is marked as the working frequency under that shared topology; the highest frequency value among all working frequencies is taken as the limiting operating frequency. The compliant protection resistor value ranges under each shared topology are determined as follows: For each shared topology range and each operating frequency range, all protection resistor value ranges are arranged in ascending order, and all protection resistor value ranges with an eye diagram opening not lower than the good grade threshold are marked; the lowest and highest marked resistance values ​​constitute the compliant protection resistor value range. When there is no continuous coverage of all intermediate resistance values ​​among the marked protection resistor value ranges, the range is divided into multiple sub-ranges for output. The optimal operating condition configuration for eye diagram opening is the parameter combination with the highest eye diagram opening after traversing all combinations. The evaluation report can also include the overall evaluation conclusions of the probe card, providing an overall evaluation and improvement suggestions based on the evaluation results of each operating condition.

[0077] In this way, the final results of multi-parameter coupled simulation evaluation can be presented to designers in a complete, structured, and easy-to-read format.

[0078] Optionally, the simulation evaluation method for the probe card also includes: generating feedback information when the eye diagram opening does not meet the preset level threshold under all operating conditions; the feedback information includes a prompt that the current configuration has no solution, and also includes at least one of the following suggestions: reduce the level of the shared topology; reduce the operating frequency; reduce the value of the protection resistor.

[0079] In this embodiment, the feedback information also provides detailed suggestions based on the specific situation of the maximum eye opening value under all current operating conditions: if the maximum value appears at the highest frequency level and is still below the good grade threshold, it is recommended to reduce the operating frequency; if the maximum value appears at the highest protection resistor value and is still below the good grade threshold, it is recommended to reduce the protection resistor value; if the maximum value appears in the 8-level shared mode and is still below the good grade threshold, it is recommended to use the 4-level shared mode or the 2-level shared mode. The feedback information can also include quantitative suggestions (reducing the operating frequency to 80% of the current highest acceptable frequency, or reducing the protection resistor value to 70% of the current resistance value) and hyperlinks or file paths pointing to the location of the current simulation project file.

[0080] In this way, the method not only has an evaluation function but also a design guidance function.

[0081] In practical applications, based on the above simulation evaluation method, a set of typical working conditions were simulated and verified, and the following eye diagram simulation results were obtained. For example... Figure 2 As shown, under the conditions of operating frequency of 50MHz, shared topology in non-shared mode, and protection resistor value of 180Ω, the eye diagram exhibits a clear open state, with an eye diagram opening degree reaching 95.12%, which is judged as excellent. Under this condition, due to the low operating frequency and the absence of reflections and crosstalk introduced by the shared bifurcation, the protection resistor value is moderate, the signal edge after passing through the probe card link is steep and the jitter is minimal, and the central region of the eye diagram has ample timing and voltage windows for the receiver to sample. Figure 3 As shown, under the operating conditions of 100MHz, a shared topology in 2-stage sharing mode, and a protection resistor of 240Ω, the eye diagram still exhibits an acceptable opening, with an eye opening of 75.09%, which is rated as good. Under this condition, the 2-stage sharing bifurcation introduces a slight impedance discontinuity, causing a slight thickening of the eye diagram's crossover edge. Simultaneously, the protection resistor value is slightly higher than 180Ω, resulting in some attenuation of the signal amplitude. However, the opening width and height of the eye diagram in the central region still meet the sampling requirements of the receiver. Figure 4As shown, under the operating conditions of 133MHz, a shared topology in 4-level shared mode, and a protection resistor value of 300Ω, the eye diagram opening decreased to 34.00%, which is classified as poor. Under these conditions, there is significant impedance discontinuity and inter-branch crosstalk at the 4-level shared bifurcation. Simultaneously, the high protection resistor value further attenuates the signal amplitude, the eye diagram opening height narrows significantly in the vertical direction, and the jitter at the horizontal crossover edge increases significantly, leaving only a very narrow central region available for sampling, resulting in severely insufficient margin. Figure 5 As shown, under the operating conditions of 150MHz, 8-level shared topology, and 360Ω protection resistor, the eye diagram is nearly completely closed, with an eye opening of 0.00%, which is classified as poor. Under these conditions, multiple reflections at the 8-level shared bifurcation and severe inter-branch crosstalk cause severe signal waveform distortion. This, combined with the significant attenuation caused by the high-value protection resistor, results in no effective opening in the eye diagram in either the vertical or horizontal directions, making it impossible for the receiver to recover the correct logic level. The eye opening values ​​for the above four operating conditions monotonically decrease with increasing shared topology level, operating frequency, and protection resistor value, verifying the rationality of the multi-parameter coupling quantization judgment rule established in this method: prioritizing low-level shared architecture and low protection resistor values ​​for high-frequency operating conditions.

[0082] Combination Figure 6 As shown, this disclosure provides a probe card simulation evaluation device 800, including a processor 801 and a memory 802. Optionally, the device may further include a communication interface 803 and a bus 804. The processor 801, communication interface 803, and memory 802 can communicate with each other via the bus 804. The communication interface 803 can be used for information transmission. The processor 801 can call logical instructions in the memory 802 to execute the probe card simulation evaluation method of the above embodiment.

[0083] Furthermore, the logic instructions in the aforementioned memory 802 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0084] The memory 802, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 801 executes functional applications and data processing by running the program instructions / modules stored in the memory 802, thereby realizing the simulation evaluation method of the probe card in the above embodiments.

[0085] The memory 802 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 802 may include high-speed random access memory and may also include non-volatile memory.

[0086] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the simulation evaluation method of the probe card described above.

[0087] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.

[0088] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0089] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0090] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0091] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A simulation evaluation method for a probe card, characterized in that, The probe card includes a shared node and multiple probe branches connected to the shared node; the method includes: A three-dimensional electromagnetic simulation model is established for the shared bifurcation region where the shared nodes in the probe card are located, and an equivalent transmission line model is established for the non-core region, so as to construct a hybrid simulation model that includes the three-dimensional electromagnetic simulation model and the equivalent transmission line model. In the hybrid simulation model, multiple sets of values ​​are set for multiple parameter dimensions, and batch scanning simulation is performed to obtain frequency domain parameters; the multiple parameter dimensions include shared topology, operating frequency, and the resistance value of the protective resistor set on the probe branch; Time-domain eye diagram simulation is performed based on frequency domain parameters to extract the eye diagram opening under various operating conditions. The eye diagram opening is determined based on the ratio of effective eye width time to eye diagram opening width. The eye diagram opening width is determined based on the statistical distribution of waveform edge crossing times, and the effective eye width time is determined based on the time width corresponding to the preset percentage interval of voltage swing. The performance of the probe card under various working conditions is evaluated based on the comparison between the eye diagram opening degree and the preset level threshold.

2. The method according to claim 1, characterized in that, Shared bifurcation regions and non-core regions are divided based on structural continuity; regions with continuous structure are designated as non-core regions, while regions with discontinuous structure are designated as core regions.

3. The method according to claim 1, characterized in that, The protection resistors are set on each probe branch after the shared node, and each protection resistor is a lumped parameter element.

4. The method according to claim 1, characterized in that, Temporal eye diagram simulation is performed using parametric scan settings; The parameterized scan settings configure the operating frequency and protection resistor as parameterized variables, and assign multiple sets of values ​​to each parameterized variable. By triggering the batch execution function of the simulation platform, all combinations of values ​​for each group of parameterized variables are traversed, and time-domain eye diagram simulations are performed for each combination.

5. The method according to claim 1, characterized in that, The statistical distribution of waveform edge crossing times is obtained as follows: The average value of the high and low levels of the waveform is used as the reference voltage for horizontal measurement. Along the horizontal reference voltage, extract the left and right cross-edge times of all waveforms; Generate a left cross-edge time histogram based on the left cross-edge times of all waveforms, and generate a right cross-edge time histogram based on the right cross-edge times of all waveforms. The mean and standard deviation of the left cross edge are determined based on the time histogram of the left cross edge, and the mean and standard deviation of the right cross edge are determined based on the time histogram of the right cross edge.

6. The method according to any one of claims 1 to 5, characterized in that, After evaluating the probe card's performance under various operating conditions, the following steps are also included: Output an evaluation report, which shall include at least one of the following: Eye opening under various operating conditions and their corresponding performance levels; Limiting operating frequencies and compliant protection resistor value ranges for each shared topology; The optimal operating condition configuration for eye diagram opening.

7. The method according to any one of claims 1 to 5, characterized in that, Also includes: When the eye opening does not meet the preset level threshold under all operating conditions, feedback information is generated. The feedback message includes a message indicating that the current configuration has no solution, and also includes at least one of the following suggestions: Lower the level of the shared topology; Reduce working frequency; Reduce the value of the protection resistor.

8. A simulation evaluation device for a probe card, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute the simulation evaluation method for the probe card as described in any one of claims 1 to 7 when running the program instructions.

9. A simulation evaluation system for a probe card, characterized in that, include: The simulation evaluation system body for the probe card; and, The simulation evaluation device for the probe card as described in claim 8 is installed in the simulation evaluation system body of the probe card.

10. A computer-readable storage medium storing program instructions, characterized in that, When the program instructions are executed, they cause the computer to perform the simulation evaluation method for the probe card as described in any one of claims 1 to 7.

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