A graphics processor, task execution method, device and medium

Abstract

The application discloses a graphics processor, a task execution method, equipment and a medium, and relates to the technical field of data processing. The graphics processor comprises an instruction pipeline, an instruction cache unit, and an execution unit group comprising a plurality of execution units, a plurality of first registers, and a plurality of second registers. The instruction cache unit stores a task instruction sequence of a first type and a second type of to-be-executed task. The first registers correspond to the first type of task, and the second registers correspond to the second type of task. The instruction pipeline transmits a control flow of the task instruction sequence of the to-be-executed task to the registers corresponding to the task type. When the corresponding registers receive and configure the control flow of the to-be-executed task, the data flow is transmitted to the execution unit to execute the to-be-executed task. By adding the registers corresponding to the task type, the tasks of different task types use the corresponding type of registers, and context switching is not required, thereby saving the overhead.

Description

Technical Field

[0001] This application belongs to the field of data processing technology, and in particular relates to a graphics processor, a task execution method, an apparatus, and a medium. Background Technology

[0002] The types of tasks that a graphics processing unit (GPU) can perform include a variety of types, such as 2D tasks and 3D tasks.

[0003] Generally, 2D tasks and 3D tasks can be executed by different engines within the GPU. However, since the engine for 2D tasks is difficult to perform complex operations such as pixel-level multiplication, interpolation, or format conversion, these complex operations can be delegated to the engine for 3D tasks.

[0004] At this point, 3D tasks are executed interspersed among a large number of 2D tasks, involving frequent context switching between 2D and 3D tasks. This context switching consumes a lot of computing resources and time, which affects GPU performance. Summary of the Invention

[0005] This application provides a graphics processor, task execution method, device, and medium to solve the problem that frequent context switching between 2D and 3D tasks consumes a lot of computing resources and time, leading to a decrease in GPU performance.

[0006] A first aspect of this application provides a graphics processor, the graphics processor including an instruction pipeline, an instruction cache unit, and an execution unit group, the instruction cache unit storing task instruction sequences of at least two tasks to be executed, the task types of the tasks to be executed including a first type and a second type, the execution unit group including at least one execution unit, at least one first register, and at least one second register, the first register corresponding to the task of the first type to be executed, and the second register corresponding to the task of the second type to be executed; wherein: The instruction pipeline is used to transfer the control flow of the task instruction sequence of the first type of task to be executed in the instruction cache unit to the first register, and to transfer the control flow of the task instruction sequence of the second type of task to be executed in the instruction cache unit to the second register; The first register is used to receive and configure the control flow of the task to be executed of the first type; The second register is used to receive and configure the control flow of the second type of task to be executed; The instruction pipeline is also used to transmit the data stream of the task instruction sequence of the task to be executed to the execution unit when the control flow configuration of any of the tasks to be executed is completed; The execution unit is configured to execute the task to be executed based on the received data stream, provided that the control flow configuration for any of the tasks to be executed is completed.

[0007] A second aspect of this application provides a task execution method applied to a graphics processor (GPU). The GPU includes an instruction pipeline, an instruction cache unit, and an execution unit group. The instruction cache unit stores task instruction sequences for at least two tasks to be executed. The task types of the tasks to be executed include a first type and a second type. The execution unit group includes at least one execution unit, at least one first register, and at least one second register. The first register corresponds to a task of the first type, and the second register corresponds to a task of the second type. The method includes: Through the instruction pipeline, the control flow of the task instruction sequence of the first type of task to be executed in the instruction cache unit is transferred to the first register, and the control flow of the task instruction sequence of the second type of task to be executed in the instruction cache unit is transferred to the second register; The control flow of the first type of task to be executed is received and configured through the first register; The control flow of the second type of task to be executed is received and configured through the second register; Through the instruction pipeline, when the control flow configuration of any of the tasks to be executed is completed, the data stream of the task instruction sequence of the task to be executed is transmitted to the execution unit; The execution unit executes the task to be executed based on the received data stream, provided that the control flow configuration for any of the tasks to be executed is completed.

[0008] A third aspect of this application provides an electronic device, the electronic device comprising: a memory and a program or instructions stored in the memory and executable on a processor, wherein when the program or instructions are executed by the processor, they implement the task execution method provided in any of the above-described aspects of the embodiments of this application.

[0009] A fourth aspect of the embodiments of this application provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, having a computer program thereon, wherein the computer program, when run by a processor, performs the steps of the task execution method provided in any aspect of the embodiments of this application.

[0010] In the graphics processor, task execution method, device, and medium provided in this application embodiment, by adding one or more registers corresponding to the task type, the registers of 3D tasks are isolated from the registers of 2D tasks. When executing tasks of different task types, since different registers are used, there is no need to perform context switching, which saves overhead and improves GPU performance. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of context switching provided for an embodiment of this application; Figure 2 This is a schematic diagram of a graphics processor structure provided in an embodiment of this application; Figure 3 This is a schematic diagram of a task execution process provided in Embodiment 1 of this application; Figure 4 This is a schematic diagram of a task execution process provided in Embodiment 2 of this application; Figure 5 This is a schematic diagram of task execution timing provided in Embodiment 2 of this application; Figure 6 This is a schematic diagram of a free register selection process provided in an embodiment of this application; Figure 7 This application provides a schematic diagram of a task switching process as an embodiment of the present application. Figure 8 A flowchart illustrating a task execution method for a graphics processor provided in another embodiment of this application; Figure 9 This is a schematic diagram of a computer device provided in one embodiment of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0016] Currently, to perform complex calculations in 2D tasks, these calculations can be moved to the execution unit of the 3D task. However, if the task types of the preceding and following tasks are inconsistent, context switching requires a certain amount of computing resources and time. Especially when 2D and 3D tasks are executed intermittently, the frequency of context switching is high, consuming more computing resources and time, which leads to a decrease in GPU performance.

[0017] It should be noted that context switching can be understood as follows: when the current task is in a blocked state, all context information of the current task stored in the register is first written to the corresponding task's dedicated context storage area in memory, thus saving the information. Then, all pre-saved context content is read from the dedicated storage area of ​​the target task to be switched to and filled back into the register, completing the information restoration. After the register configuration takes effect, the execution unit continues to execute the target task based on the restored task context. After the blocked task is restored to an unblocked state, the above context saving and loading process is repeated, reloading the context of the task restored to an unblocked state from memory into the register, thus resuming the execution flow.

[0018] For example, context information may include control flow and data context such as instruction pointers, program status words, intermediate results of operations, and task status flags.

[0019] Figure 1 A context switching diagram provided for an embodiment of this application, such as Figure 1As shown.

[0020] In this embodiment, a 2D task (2D Block Transfer, 2D BLT) is used for 2D block transfer, and a 3D task is used for 3D rendering (3D Drawing) and 3D block transfer (3D BLT) as examples. It should be noted that... Figure 1 The task execution order is from bottom to top, that is, first execute the 2D block transfer, then execute the 3D block transfer task, then execute the 2D block transfer again, and finally execute the 3D rendering task.

[0021] Currently in 2D mode, executing a 2D block transfer task. The next task is a 3D block transfer task. Save the current 2D context information from register 101 and restore the previously saved 3D block transfer task context information. Switch to 3D mode and execute the 3D block transfer task. Then, execute another 2D block transfer task. Again, save the current 3D block transfer task context information from register 101 and restore the previously saved 2D context information. Switch to 2D mode and execute another 2D block transfer task. Finally, execute the 3D rendering task. Save the current 2D context information from register 101, restore the 3D rendering task context information, switch to 3D mode, and execute the final image rendering.

[0022] During the interleaved execution of different task types, frequent context switching operations were performed. Each switch required a register-level overhead of saving the context information of the current task and restoring the context information of the next task, which consumed a lot of computing resources and time, resulting in low GPU performance.

[0023] The technical solution of this application addresses the issue of frequent context switching between 2D and 3D tasks, which consumes a lot of computing resources and time. It proposes a graphics processor, task execution method, device, and medium.

[0024] First, the graphics processor provided in the embodiments of this application will be introduced. Figure 2 This is a schematic diagram of a graphics processor structure provided in an embodiment of this application, such as... Figure 2 As shown, the graphics processor 100 includes an instruction pipeline 102, an instruction cache unit 106, and an execution unit group 104. The instruction cache unit 106 stores task instruction sequences for at least two tasks to be executed. The task types for the tasks to be executed include a first type and a second type. The execution unit group 104 includes at least one execution unit 10402, at least one first register 10404, and at least one second register 10406. The first register 10404 corresponds to the task of the first type, and the second register 10406 ​​corresponds to the task of the second type.

[0025] For example, the graphics processor 100 may further include multiple execution unit groups 104. The number of execution units, the number of first registers, and the number of second registers in each execution unit group 104 may be different or the same, and this application embodiment does not impose any limitations on this. For example, an execution unit group 104 may include one execution unit 10402, one first register 10404, and one second register 10406. When there are multiple execution unit groups 104, the executable logic is the same for each execution unit group 104, and the specific execution logic corresponding to the steps will be described later. For ease of explanation, this application embodiment uses a graphics processor 100 including one execution unit group 104 as an example for description.

[0026] Figure 2 The instruction cache unit 106 shows two task instruction sequences 1 and 2 for tasks to be executed, and may also include other numbers of task instruction sequences, which are not limited in this embodiment.

[0027] In this embodiment, the first type can be the aforementioned 2D task, and the second type can be the aforementioned 3D task. For example, the first type is a two-dimensional block transfer task, i.e., a 2D block transfer task, and the second type is a three-dimensional block transfer task or a three-dimensional rendering task, i.e., a 3D block transfer task or a 3D rendering task. The first register 10404 can be a register dedicated to executing 2D tasks, and the second register 10406 ​​is a register dedicated to executing 3D tasks.

[0028] Of course, the first type can be the aforementioned 3D task, and the second type can be the aforementioned 2D task. For example, the first type is a 3D block transfer task or a 3D rendering task, and the second type is a 2D block transfer task. The first register 10404 can be a register dedicated to executing 3D tasks, and the second register 10406 ​​is a register dedicated to executing 2D tasks. This application does not limit the specific task types corresponding to the first and second types; a correspondence between the registers and the task types is sufficient.

[0029] In some embodiments, when the execution unit group 104 includes multiple execution units 10402, two different types of registers can be configured for each execution unit 10402. For example, the execution unit group 104 includes two execution units 10402, namely execution unit 1 and execution unit 2, and a first register 10404 and a second register 10406 ​​can be configured for execution unit 1 and execution unit 2 respectively.

[0030] In some embodiments, multiple execution units 10402 may share multiple registers of different types. For example, execution unit 1 and execution unit 2 may share one or more first registers 10404 and one or more second registers 10406. This application embodiment does not limit this.

[0031] The instruction cache unit 106 is used to store the sequence of task instructions corresponding to at least two tasks to be executed by the graphics processor 100. For example, the instruction cache unit 106 may be an instruction cache area (Command Buffer, CMDBuffer).

[0032] In some embodiments, the task instruction sequence may include a control flow and a data flow for the task to be executed. The control flow is used for register data configuration to guide the execution unit 10402 in executing the task. The data flow is used to be transferred to the execution unit 10402 through the instruction pipeline 102 to execute the task.

[0033] In some embodiments, the instruction pipeline 102 is used to transfer the control flow of the task instruction sequence of a first type of task to be executed in the instruction cache unit 106 to the first register 10404, and to transfer the control flow of the task instruction sequence of a second type of task to be executed in the instruction cache unit to the second register 10406. The first register 10404 is used to receive and configure the control flow of the first type of task to be executed; The second register 10406 ​​is used to receive and configure the control flow of the second type of task to be executed; The instruction pipeline 102 is also used to transmit the data stream of the task instruction sequence of the task to be executed to the execution unit 10402 when the control flow configuration of any task to be executed is completed. The execution unit 10402 is used to execute the task to be executed based on the received data stream, provided that the control flow configuration of any task to be executed is completed.

[0034] It is understandable that when transmitting control flow, instruction cache unit 106 can simultaneously transmit the control flow of the task instruction sequence of the first type of task to be executed to the first register 10404, and transmit the control flow of the task instruction sequence of the second type of task to be executed in instruction cache unit 106 to the second register 10406.

[0035] Alternatively, the control flow of the task instruction sequence of the first type of task to be executed can be transferred to the first register 10404 first, and then the control flow of the task instruction sequence of the second type of task to be executed in the instruction cache unit 106 can be transferred to the second register 10406. The embodiments of this application do not limit the order of control flow transmission.

[0036] For example, tasks can also be transferred based on their storage order in the instruction cache unit 106.

[0037] Both registers can be configured in either way to control the flow of the task to be executed, and this application embodiment does not limit this.

[0038] In this embodiment, the instruction pipeline 102's data stream transmission operation must be performed only after the control flow configuration is complete. This is because if the data stream transmission and control flow transmission occur simultaneously, or if the control flow is transmitted first and the data stream is transmitted immediately, the execution unit 10402 will encounter problems when executing the task based on the data stream because the control flow configuration is incomplete. To ensure normal task execution, the instruction pipeline 102 can transmit the corresponding data stream to the execution unit 10402 after the control flow configuration of the task to be executed is completed.

[0039] In some embodiments, since multiple registers and multiple execution units 10402 may exist, each execution unit 10402 can execute a task, and there may be one execution unit 10402 that can switch tasks and execute the switched task. Therefore, it is possible that multiple registers or multiple registers are configuring the control flow simultaneously, which may result in the completion of control flow configuration for multiple tasks to be executed. To further improve data flow transmission efficiency, the instruction pipeline 102 can transmit the corresponding data stream immediately upon completion of control flow configuration for any task to be executed, rather than waiting for the control flow configuration of all tasks to be executed to be completed before transmitting the corresponding data stream.

[0040] For example, there is an execution unit 10402 and two tasks to be executed, namely task 1 and task 2. The first register 10404 configures the control flow of task 1, and the second register 10406 ​​configures the control flow of task 2. Then, after the control flow of either task 1 or task 2 is configured, the instruction pipeline 102 can transmit the data flow of the task whose control flow has been configured.

[0041] In some embodiments, if the control flows of at least two tasks to be executed are configured at the same time, the instruction pipeline 102 may transmit the data flows of the two tasks to be executed in any transmission order.

[0042] In some embodiments, the instruction pipeline 102 may transmit the data streams of two tasks to be executed to the same execution unit at different times, or it may transmit the data streams of two tasks to be executed to different execution units at the same time. This application embodiment does not limit this.

[0043] For example, the instruction pipeline 102 can transmit the data stream of a task to be executed to the execution unit at a first moment, and transmit the data stream of another task to be executed to the execution unit at a second moment after the execution unit has completed the task to be executed.

[0044] Figure 3 This is a schematic diagram of a task execution process provided in Embodiment 1 of this application, as follows: Figure 3 As shown.

[0045] Example 1 uses a graphics processor 100 that includes an execution unit group 104, which includes a first register 10404 and a second register 10406. The first register 10404 corresponds to 2D tasks, and the second register 10406 ​​corresponds to 3D tasks. For example, the first register 10404 can be referred to as the 2D register 302, and the second register 10406 ​​can be referred to as the 3D register 304.

[0046] Instruction pipeline 102 can transmit the control flow of the first 2D block transport task to 2D register 302 and the control flow of the 3D block transport task to 3D register 304. 2D register 302 receives and configures the control flow of the first 2D block transport task, and 3D register 304 receives and configures the control flow of the 3D block transport task. Once the control flow configuration for either the first 2D block transport task or the 3D block transport task is complete, instruction pipeline 102 transmits the data flow of the corresponding task to execution unit 10402. Execution unit 10402 executes the task based on the data flow of the task configured with the control flow.

[0047] In some embodiments, if there is an execution unit 10402 and the control flow of the first 2D block transport task and the 3D block transport task are configured simultaneously, the data stream of any one of the tasks can be transmitted to the execution unit 10402 first, and after the execution unit 10402 finishes executing the task, the data stream of the other task can be transmitted to the execution unit 10402.

[0048] In some embodiments, the execution unit 10402 receives the data stream of the first 2D block transport task at a third time and the data stream of the 3D block transport task at a fourth time. The third time and the fourth time are different times, and at the fourth time, the execution unit 10402 has not completed the execution of the first 2D block transport task.

[0049] Of course, other methods for transmitting data streams may exist, and this application does not limit them.

[0050] Subsequently, instruction pipeline 102 can also transfer the control flow of the second 2D block transport task to 2D register 302 and the control flow of the 3D rendering task to 3D register 304, repeating the aforementioned process without the need for register switching.

[0051] In this embodiment, by adding registers and using different registers for different task types, the registers for 3D tasks are isolated from the registers for 2D tasks. When executing tasks of different task types, since different registers are used, there is no need to perform context switching, which saves overhead and improves GPU performance.

[0052] In some embodiments, the execution unit 10402 is configured to obtain task data of a task to be executed from the memory included in the graphics processor 100 based on the received data stream, and execute the task to be executed based on the task data.

[0053] It is understandable that the data stream can be task data required to execute the task, or it can be the address index of the task data. After receiving the data stream, the execution unit 10402 can retrieve the task data from the memory including the address corresponding to the address index based on the data stream, and then execute the task.

[0054] In this embodiment, since retrieving task data from memory requires a period of time for the memory to respond before returning the task data to the task data retrieval module, the instruction pipeline 102 transmits a data stream instead of task data to the execution unit 10402. Therefore, the instruction pipeline 102 does not need to retrieve task data from memory or wait for a memory response, thus improving task transmission efficiency.

[0055] In some embodiments, since the execution unit group 104 may include at least two registers, in order to overlap the control flow transmission time with the computation pipeline, the instruction pipeline 102 is used to transfer the control flow of the next task to be executed in the instruction cache unit 106 to an idle register corresponding to the task type of the next task to be executed during the process of the execution unit 10402 obtaining task data of the task to be executed from the memory included in the graphics processor 100 based on the received data flow.

[0056] For example, the data stream obtained by the execution unit 10402 is the data stream of the task to be executed 1, and the next task to be executed is the task to be executed 3. The task type of the task to be executed 3 is the first type. When the execution unit 10402 obtains the task data of the task to be executed from the memory included in the graphics processor 100 based on the received data stream, if there is still an idle register at this time, and the register corresponds to the task of the first type, the instruction pipeline 102 can transfer the control flow of the task to be executed 3 to the idle register.

[0057] In this embodiment, when the execution unit 10402 acquires task data, the control flow of another task is transferred to an idle register, enabling the parallel execution of task control flow transfer and the acquisition of task data by the execution unit 10402. By executing multiple operations simultaneously, pipeline pauses are reduced or eliminated, thereby improving the sustained throughput of the GPU.

[0058] In some embodiments, the instruction pipeline 102 is used to transfer the control flow of the next task to be executed in the instruction cache unit 106 to an idle register corresponding to the task type of the next task to be executed during the execution unit 10402 executing the task to be executed based on the task data.

[0059] Furthermore, during the execution of a task by the execution unit 10402, the instruction pipeline 102 does not need to perform any other related operations on the task being executed by the execution unit 10402. At this time, the transmission process of control flow and data flow is decoupled from the execution process of the execution unit 10402. Therefore, the instruction pipeline 102 can transmit the control flow of the next task to be executed to the free register corresponding to the task type of the next task to be executed.

[0060] Of course, if the control flow configuration for the next task to be executed is completed, the instruction pipeline 102 can also transmit the data flow of the next task to be executed to other execution units 10402 that are in an idle state during the execution of the task by the execution unit 10402.

[0061] In this embodiment of the application, by transmitting the control flow of another task to an idle register while the execution unit 10402 is executing a task, the control flow transmission and task execution of the task can be performed simultaneously. That is, while a certain register is being occupied by the execution unit 10402, the idle register can receive the control flow of other tasks while the task is being executed, thereby realizing the parallel execution of control flow transmission while the task is being executed, without consuming additional time to perform control flow transmission operations separately.

[0062] In some embodiments, since the execution unit group 104 may include multiple registers corresponding to tasks of the same task type, when transmitting control flow, there may be at least two free registers corresponding to tasks of the same task type. Then, the instruction pipeline 102 may select any free register as the target register of the task and transmit the control flow of the task to the target register.

[0063] For example, instruction pipeline 102 is used to determine the target register from at least two free registers by means of a polling algorithm when at least two free registers exist, and to transfer the control flow of the next task to be executed in instruction cache unit 106 to the target register.

[0064] The polling algorithm can be understood as using registers in a certain order.

[0065] For example, the task type of the next task to be executed is the first type, which corresponds to the first register 10404. There are currently three free first registers 10404, namely registers 1 to 3. Register 1 can be used first, register 2 can be used next time, and register 3 can be used the time after that.

[0066] In some embodiments, if two free registers exist, a ping-pong algorithm can be used. For example, following the previous example, register 1 can be used first, followed by register 2. After register 1 becomes free again, it can be used a third time.

[0067] Of course, if the task corresponding to register 2 is executed faster, causing register 2 to be in an idle state before register 1, then register 2 can be used a third time in order to improve the transmission efficiency of the task's control flow.

[0068] In other words, in some embodiments, if there is an idle register corresponding to the task type of the next task to be executed, the instruction pipeline 102 is used to transfer the control flow of the next task to be executed to the idle register.

[0069] In this embodiment, a polling algorithm is used to utilize idle registers, resulting in a more balanced use of each register. This effectively avoids the problem of tasks occupying a particular register for an extended period, leading to excessively frequent reads and writes to that register while other registers remain relatively idle. It also reduces the probability of register read / write conflicts and improves the efficiency of task control flow transmission.

[0070] In some embodiments, the instruction pipeline 102 is configured to stop the step of transferring the control flow of the task to be executed in the instruction cache unit 106 to a register of the corresponding type if no free register is available.

[0071] It is understandable that the absence of a free register can include two cases: the first is that there is no free register corresponding to any task type, and the second is that there is no free register corresponding to the task that currently needs to transmit control flow.

[0072] For example, if no free register is currently available, instruction pipeline 102 stops executing control flow transfer operations.

[0073] For example, if there are three free registers corresponding to the first type of task, and the task that needs to transfer control flow first is of the second type, the instruction pipeline 102 stops performing the control flow transfer operation.

[0074] This is because there may be dependencies between tasks, and there is no corresponding relationship between the task to be executed first and the free register. It is difficult to transfer the control flow of the task to be executed first to the free register, otherwise there will be frequent context switching.

[0075] Furthermore, in some embodiments, when a free register exists and there is no dependency between the tasks to be executed, the control flow of any task to be executed corresponding to the free register can be transferred to the free register.

[0076] In this embodiment of the application, if there is no free register, the control flow transmission step can be stopped to avoid problems with control flow transmission.

[0077] In some embodiments, when the task to be executed by the execution unit 10402 is in a blocked state and task data of other tasks to be executed is obtained, the execution unit 10402 is used to execute other tasks to be executed based on the task data of other tasks to be executed.

[0078] The fact that the task to be executed by execution unit 10402 is in a blocked state indicates that execution unit 10402 cannot currently execute the task to be executed. For example, the blocked state of the task to be executed by execution unit 10402 may include execution unit 10402 waiting for memory to return the task data of the task to be executed, execution unit 10402 waiting for the calculation results of other execution units 10402, or waiting for external interrupts, hardware handshake signals, etc. The embodiments of this application do not limit this.

[0079] In some embodiments, the graphics processing unit may further include an arbitrator, which can use a polling algorithm to determine whether each task to be executed in each execution unit 10402 is in a blocked state. Alternatively, the arbitrator can use a polling algorithm to determine whether each task to be executed in each execution unit 10402 is in a non-blocking runnable state, and obtain an arbitration result. This arbitration result can be sent to the execution unit 10402 that executes the arbitration object in the arbitration result, so that the execution unit 10402 executes the corresponding task to be executed. For example, the arbitration object in the arbitration result can be each task to be executed.

[0080] For example, the arbitrator can also cyclically check whether each task to be executed is in a non-blocking runnable state according to the order of instruction issuance. This application embodiment does not limit how specifically it determines whether each task to be executed is in a non-blocking runnable state. The order of instruction issuance can be understood as the order in which each task to be executed forms a task scheduling instruction queue in the instruction cache unit 106.

[0081] It is understandable that, as mentioned above, during data transmission, different data streams of tasks to be executed can be transmitted to the same execution unit 10402 at different times. Therefore, the execution unit 10402 can retrieve task data for different tasks from memory at different times based on the different data streams of the tasks to be executed. Consequently, it can receive task data for each task to be executed at different times. This can lead to a situation where the execution unit 10402 receives task data for one task at a certain time, while task data for another task is still being requested. To improve the throughput of the execution unit 10402, it can first execute the corresponding task based on the already acquired task data.

[0082] Understandably, since the execution unit 10402 has already transferred the memory access instructions for retrieving task data from memory to memory before the switch, even if other tasks are executed, the memory access instructions for the blocked tasks are still being executed, thereby reducing the latency caused by task memory access, achieving high throughput execution of the execution unit 10402, and improving overall efficiency.

[0083] Figure 4 This is a schematic diagram of a task execution process provided in Embodiment 2 of this application, as follows: Figure 4 As shown.

[0084] In embodiment 2, the execution unit group 104 includes three registers and one execution unit 3. Figure 4 Execution unit 3 is not shown. Execution unit 3 can interact with memory 408. Registers include registers 402, 404, and 406. Registers 402 and 404 correspond to 2D tasks, and register 406 corresponds to 3D tasks. The tasks to be executed include one 3D block transport task, three 2D block transport tasks, and one 3D rendering task. The three 2D block transport tasks are designated as 2D block transport task A, 2D block transport task B, and 2D block transport task C. All tasks to be executed can form a task scheduling instruction queue.

[0085] The task at the head of the task scheduling instruction queue is a 3D block transport task. Instruction pipeline 102 can transmit the control flow of the 3D block transport task to register 406, and register 406 configures the control flow of the 3D block transport task. After configuration, instruction pipeline 102 can transmit the data flow of the 3D block transport task to execution unit 3. Execution unit 3 retrieves the task data of the 3D block transport task from memory 408 based on the data flow of the 3D block transport task.

[0086] Since memory 408 needs time to respond to data, it also needs time to obtain the task data of the 3D block transport task, and it also needs time to transfer the task data of the 3D block transport task to execution unit 3, the 3D block transport task of execution unit 3 is blocked.

[0087] The task scheduling instruction queue read pointer moves forward, and instruction pipeline 102 can transfer the control flow of 2D block transport task A to register 402. Register 402 configures the control flow of 2D block transport task A. After configuration, instruction pipeline 102 can transfer the data flow of 2D block transport task A to execution unit 3. Execution unit 3, based on the data flow of 2D block transport task A, retrieves the task data of 2D block transport task A from memory 408.

[0088] Similarly, since memory 408 needs time to respond to data, it also needs time to obtain the task data of 2D block transport task A, and it also needs time to transfer the task data of 2D block transport task to execution unit 3. Therefore, 2D block transport task A of execution unit 3 is blocked.

[0089] At this time, memory 408 returns the task data of the 3D block transport task to execution unit 3. Execution unit 3 receives the data and executes the 3D block transport task based on the task data and the control flow of the 3D block transport task configured in register 406, without context switching.

[0090] After the 3D block transport task is completed, if the execution unit 3 receives the task data of the 2D block transport task A returned by the memory 408, it can execute the 2D block transport task A based on the task data of the 2D block transport task A and the control flow of the 2D block transport task A configured in the register 402, without the need for context switching.

[0091] The task scheduling instruction queue read pointer moves forward, and instruction pipeline 102 can transfer the control flow of 2D block transport task B to the idle register 404. Register 404 configures the control flow of 2D block transport task B. After configuration, instruction pipeline 102 can transfer the data flow of 2D block transport task B to execution unit 3. Execution unit 3, based on the data flow of 2D block transport task B, retrieves the task data of 2D block transport task B from memory 408.

[0092] Repeat the above process until all pending tasks are completed.

[0093] It is understandable that when the 3D block transport task of execution unit 3 is blocked, instruction pipeline 102 can simultaneously execute the step of transferring the control flow of 2D block transport task A to register 402. It can also be understood that while register 406 is executing a task as a runtime register, instruction pipeline 102 can transfer the control flow of subsequent 2D block transport task A to register 402. Similarly, when execution unit 3 executes 2D block transport task A based on the task data of 2D block transport task A and the control flow of 2D block transport task A configured in register 402, instruction pipeline 102 can simultaneously execute the step of transferring the control flow of 2D block transport task B to register 404, which is in an idle state.

[0094] In this embodiment, adding two registers corresponding to 2D tasks can save context switching overhead and reduce the time consumed by executing control flow transfer operations separately. When a data transfer task is blocked due to memory access, the executable task can be flexibly switched, greatly improving the pipeline throughput of the execution unit 10402 and enhancing overall performance.

[0095] Figure 5 This is a schematic diagram of task execution timing provided in Embodiment 2 of this application, as follows: Figure 5 As shown. The execution timing diagram of this task is as follows. Figure 4 The timing diagram corresponding to Embodiment 2 shown is as follows: Figure 5 The registers, memory, and execution units in the middle are Figure 4 The registers, memory, and execution units in the system.

[0096] exist Figure 5 In the first instance, register 406 receives the control flow of the 3D block transport task sent by instruction pipeline 102 and configures it. After configuration, instruction pipeline 102 sends the data flow of the 3D block transport task to execution unit 3. Execution unit 3 retrieves the task data of the 3D block transport task from memory 408 based on the data flow of the 3D block transport task, and the 3D block transport task is in a blocked state. Register 402 receives the control flow of the 2D block transport task A sent by instruction pipeline 102 and configures it. After configuration, instruction pipeline 102 sends the data flow of the 2D block transport task A to execution unit 3. Execution unit 3 retrieves the task data of the 2D block transport task A from memory 408 based on the data flow of the 2D block transport task A, and the 2D block transport task A is in a blocked state.

[0097] Execution unit 3 receives the task data for the 3D block transport task returned by memory 408 and executes it. After execution, if it receives the task data for the 2D block transport task A returned by memory 408, it executes the 2D block transport task A based on the task data of the 2D block transport task A.

[0098] Subsequently, register 404 can receive the control flow of 2D block transport task B sent by instruction pipeline 102 and configure it. The aforementioned process is repeated, and will not be described in detail in this embodiment of the application.

[0099] Figure 6 This application provides a schematic diagram of a free register selection process, as shown in the embodiments of the present application. Figure 6 As shown. Includes S602~S612. This embodiment takes as an example that includes one register corresponding to the 3D task and two registers corresponding to the 2D task.

[0100] S602, Task issued.

[0101] The arbitrator can perform task distribution operations.

[0102] S604, Task Type.

[0103] Instruction pipeline 102 can be used to determine the task type. If the task type is a 2D task, then execute S608. If the task type is a 3D task, then execute S606.

[0104] S606 checks if the register is free.

[0105] For example, determine whether the register corresponding to the 3D task is free. If yes, execute S612. If no, execute S602.

[0106] S608, Ping-Pong Select Register.

[0107] For example, if the two registers corresponding to 2D are register 0 and register 1, the ping-pong algorithm for register selection means that if register 0 was used last time, then register 1 will be used next time. Or, if register 1 was used last time, then register 0 will be used next time.

[0108] S610 checks if the register is free.

[0109] For example, it is determined whether the register corresponding to the 2D task is free. If so, S612 is executed. If not, S602 is executed. It can be understood that if there is no free register corresponding to the 2D task, the step of transferring the control flow of the 2D task to the corresponding register is stopped, thus blocking the pipeline upward.

[0110] S612, control flow transmission.

[0111] For example, the control flow of a 2D task can be transferred to the corresponding free register, and the control flow of a 3D task can also be transferred to the corresponding free register.

[0112] Figure 7 This application provides a schematic diagram of a task switching process, as shown in the embodiment of the present application. Figure 7 As shown. Includes S702~S712. This embodiment takes as an example that includes one register corresponding to the 3D task and two registers corresponding to the 2D task.

[0113] S702, task issued.

[0114] The arbitrator can perform task distribution operations.

[0115] S704 determines whether the task is blocked.

[0116] The arbitrator can determine whether a task is blocked. For example, the arbitrator determines whether the current task is blocked due to waiting for a memory response or other transactions. If so, S706 is executed. If not, the execution unit 10402 can execute the task normally (not shown in the figure).

[0117] S706 determines whether other register contexts are executable.

[0118] For example, if yes, it indicates that the execution unit 10402 can perform other tasks, and executes S710. If no, it indicates that there is no complete control flow transmission or that it is in a blocked state and has not yet recovered, and the execution unit 10402 has no other executable tasks, and executes S708.

[0119] S708, waiting.

[0120] This can also be understood as blocking the upstream flow.

[0121] S710, Polling Select Register.

[0122] S712, task switching.

[0123] For example, if the currently executing task is task 1 and is in a blocked state, the control flow configuration of task 1 is completed, and the task data of task 2 is obtained, then the execution unit 10402 can switch to task 2 and execute it.

[0124] Based on the same technical concept as the graphics processor described above, this application also provides a task execution method for a graphics processor, which can be applied to the graphics processor described above.

[0125] Figure 8 A flowchart illustrating a task execution method for a graphics processor provided in another embodiment of this application is shown below. Figure 8As shown, the method is applied to a graphics processor, which includes an instruction pipeline, an instruction cache unit, and an execution unit group. The instruction cache unit stores task instruction sequences for at least two tasks to be executed. The task types of the tasks to be executed include a first type and a second type. The execution unit group includes at least one execution unit, at least one first register, and at least one second register. The first register corresponds to the task to be executed of the first type, and the second register corresponds to the task to be executed of the second type. The method includes steps S801 to S805.

[0126] S801, through the instruction pipeline, the control flow of the task instruction sequence of the first type of task to be executed in the instruction cache unit is transferred to the first register, and the control flow of the task instruction sequence of the second type of task to be executed in the instruction cache unit is transferred to the second register.

[0127] S802, through the first register, receives and configures the control flow of the task to be executed of the first type.

[0128] S803 receives and configures the control flow of the second type of task to be executed through the second register.

[0129] S804, through the instruction pipeline, when the control flow configuration of any of the tasks to be executed is completed, the data stream of the task instruction sequence of the task to be executed is transmitted to the execution unit.

[0130] S805, the execution unit executes the task to be executed based on the received data stream when the control flow configuration of any of the tasks to be executed is completed.

[0131] As an optional embodiment, the execution unit, upon completion of the control flow configuration for any of the tasks to be executed, executes the task based on the received data stream, including: The execution unit retrieves task data for the task to be executed from the memory included in the graphics processor based on the received data stream, and executes the task to be executed based on the task data.

[0132] As an optional embodiment, during the process of the execution unit obtaining task data of the task to be executed from the memory included in the graphics processor based on the received data stream, the method further includes: Through the instruction pipeline, the control flow of the next task to be executed in the instruction cache unit is transferred to the free register corresponding to the task type of the next task to be executed.

[0133] As an optional embodiment, during the process of the execution unit executing the task to be executed based on the task data, the method further includes: Through the instruction pipeline, the control flow of the next task to be executed in the instruction cache unit is transferred to the free register corresponding to the task type of the next task to be executed.

[0134] As an optional embodiment, the control flow of the next task to be executed in the instruction cache unit is transferred to the free register corresponding to the task type of the next task to be executed through the instruction pipeline, including: If at least two of the free registers exist through the instruction pipeline, a target register is determined from the at least two free registers using a polling algorithm, and the control flow of the next task to be executed in the instruction cache unit is transferred to the target register.

[0135] As an optional embodiment, in the absence of a free register, the method further includes: The instruction pipeline stops the step of transferring the control flow of the task to be executed in the instruction cache unit to the corresponding type of register.

[0136] As an optional embodiment, when the task to be executed by the execution unit is in a blocked state and task data of other tasks to be executed is obtained, the following is included: The execution unit executes the other tasks based on their task data.

[0137] As an optional embodiment, the first type is a two-dimensional block transfer task, and the second type is a three-dimensional block transfer task or a three-dimensional rendering task.

[0138] Figure 9 This is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of this application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0139] like Figure 9As shown, the electronic device 1000 includes at least one graphics processor 100 and a memory, such as a read-only memory (ROM) 1002 or a random access memory (RAM) 1003, communicatively connected to the at least one graphics processor 100. The memory stores computer programs executable by the at least one graphics processor. The graphics processor 100 can perform various appropriate actions and processes based on the computer program stored in the ROM 1002 or loaded from the storage unit 1008 into the RAM 1003. The RAM 1003 may also store various programs and data required for the operation of the electronic device 1000. The graphics processor 100, the ROM 1002, and the RAM 1003 are interconnected via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0140] Multiple components in electronic device 1000 are connected to input / output interface 1005, including: input unit 1006, such as keyboard, mouse, etc.; output unit 1007, such as various types of monitors, speakers, etc.; storage unit 1008, such as disk, optical disk, etc.; and communication unit 1009, such as network card, modem, wireless transceiver, etc. Communication unit 1009 allows electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0141] The graphics processor 100 can be any dedicated graphics processing component with processing and computing capabilities. The graphics processor 100 executes the various methods and processes described above, such as task execution methods.

[0142] In some embodiments, the task execution method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 1000 via read-only memory 1002 and / or communication unit 1009. When the computer program is loaded into random access memory 1003 and executed by graphics processor 100, one or more steps of the task execution method described above may be performed. Alternatively, in other embodiments, graphics processor 100 may be configured to execute the task execution method by any other suitable means (e.g., by means of firmware).

[0143] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable graphics processor, which may be an application-specific programmable processor, capable of receiving data and instructions from a memory system, at least one input device, and at least one output device, and transmitting data and instructions to the memory system, the at least one input device, and the at least one output device.

[0144] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to the graphics processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the graphics processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0145] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory, erasable programmable read-only memory (flash memory or erasable programmable read-only memory, EPROM), optical fibers, compact disc read-only memory (CD ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0146] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0147] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include: Local Area Networks (LANs), Wide Area Networks (WANs), blockchain networks, and the Internet.

[0148] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product within the cloud computing service system to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0149] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0150] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A graphics processor, characterized in that, The graphics processor includes an instruction pipeline, an instruction cache unit, and an execution unit group. The instruction cache unit stores task instruction sequences for at least two tasks to be executed. The task types for the tasks to be executed include a first type and a second type. The execution unit group includes at least one execution unit, at least one first register, and at least one second register. The first register corresponds to the task of the first type, and the second register corresponds to the task of the second type. The instruction pipeline is used to transfer the control flow of the task instruction sequence of the first type of task to be executed in the instruction cache unit to the first register, and to transfer the control flow of the task instruction sequence of the second type of task to be executed in the instruction cache unit to the second register; The first register is used to receive and configure the control flow of the task to be executed of the first type; The second register is used to receive and configure the control flow of the second type of task to be executed; The instruction pipeline is also used to transmit the data stream of the task instruction sequence of the task to be executed to the execution unit when the control flow configuration of any of the tasks to be executed is completed; The execution unit is configured to execute the task to be executed based on the received data stream, provided that the control flow configuration for any of the tasks to be executed is completed.

2. The graphics processor as described in claim 1, characterized in that, The execution unit is configured to obtain task data of the task to be executed from the memory included in the graphics processor based on the received data stream, and execute the task to be executed based on the task data.

3. The graphics processor as described in claim 2, characterized in that, The instruction pipeline is used to transfer the control flow of the next task to be executed in the instruction cache unit to an idle register corresponding to the task type of the next task to be executed during the process of the execution unit obtaining the task data of the task to be executed from the memory included in the graphics processor based on the received data stream.

4. The graphics processor as described in claim 2, characterized in that, The instruction pipeline is used to transfer the control flow of the next task to be executed in the instruction cache unit to an idle register corresponding to the task type of the next task to be executed during the execution unit's execution of the task to be executed based on the task data.

5. The graphics processor as described in claim 4, characterized in that, The instruction pipeline is used to determine the target register from at least two of the free registers by means of a polling algorithm when at least two of the free registers exist, and to transfer the control flow of the next task to be executed in the instruction cache unit to the target register.

6. The graphics processor as described in claim 4, characterized in that, The instruction pipeline is configured to stop the step of transferring the control flow of the task to be executed in the instruction cache unit to a register of the corresponding type if no free register is available.

7. The graphics processor as claimed in claim 1, characterized in that, When the task to be executed by the execution unit is in a blocked state and task data of other tasks to be executed is obtained, the execution unit is used to execute the other tasks to be executed based on the task data of the other tasks to be executed.

8. The graphics processor as claimed in claim 1, characterized in that, The first type is a two-dimensional block transfer task, and the second type is a three-dimensional block transfer task or a three-dimensional rendering task.

9. A task execution method, characterized in that, The method is applied to a graphics processing unit (GPU), which includes an instruction pipeline, an instruction cache unit, and an execution unit group. The instruction cache unit stores task instruction sequences for at least two tasks to be executed. The task types of the tasks to be executed include a first type and a second type. The execution unit group includes at least one execution unit, at least one first register, and at least one second register. The first register corresponds to the task of the first type, and the second register corresponds to the task of the second type. The method includes: Through the instruction pipeline, the control flow of the task instruction sequence of the first type of task to be executed in the instruction cache unit is transferred to the first register, and the control flow of the task instruction sequence of the second type of task to be executed in the instruction cache unit is transferred to the second register; The control flow of the first type of task to be executed is received and configured through the first register; The control flow of the second type of task to be executed is received and configured through the second register; Through the instruction pipeline, when the control flow configuration of any of the tasks to be executed is completed, the data stream of the task instruction sequence of the task to be executed is transmitted to the execution unit; The execution unit executes the task to be executed based on the received data stream, provided that the control flow configuration for any of the tasks to be executed is completed.

10. An electronic device, characterized in that, The electronic device includes: a memory and a program or instructions stored in the memory and executable on a processor, wherein the program or instructions, when executed by the processor, implement the task execution method as described in claim 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause the graphics processor to execute the task execution method of claim 9.

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