A method and system for detecting semiconductor wire and solder joints

Abstract

The application belongs to the technical field of semiconductor packaging process and automatic optical detection, and particularly relates to a semiconductor wire bonding and solder joint detection method and system. The method obtains a three-dimensional height map of a chip packaging area, divides the height map according to a standard gold wire template, uses the height increment of the corresponding carrier surface of each area as a threshold value for segmentation, and obtains a gold wire region of interest. The gold wire region of interest is used to detect few wires, many wires, wire collapse and wire distortion. The threshold value is set as the height increment of the background height in the local window for binaryzation and segmentation, and the solder joint entity contour is extracted. The ratio of the contour outer diameter to the wire diameter is calculated and compared with the qualified interval configured by the client to determine the point shape. According to the solder joint attachment carrier type recorded by the template, the reference area is positioned to the corresponding chip surface or substrate surface, the height characteristic values are extracted respectively, and the difference is calculated and compared with the process thickness to determine the root lifting and virtual welding.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor packaging technology and automated optical inspection technology, and in particular to a method and system for detecting semiconductor bonding wires and solder joints. Background Technology

[0002] In microelectronics and semiconductor back-end packaging processes, wire bonding is the core process for achieving electrical connections between internal chip circuitry and external pins. With the development of advanced packaging technologies, system-in-package (SiP), multi-chip modules, and 3D chip stacking have become key methods for increasing the integration density of microelectronic devices. The vertical stacking of heterogeneous chips transforms the internal spatial topology into a multi-tiered, three-dimensional structure, introducing numerous chip-to-chip direct gold wire connections, which places extremely high demands on automated optical inspection equipment.

[0003] Currently, the two-dimensional automated optical inspection equipment widely used in the industry faces many insurmountable technical bottlenecks:

[0004] First, optical depth-of-field limitations cause large areas of defocusing in gold wire images. Gold wire diameters are typically extremely fine (e.g., 0.8 mil, approximately 20 μm), requiring high-magnification lenses for two-dimensional inspection to meet planar resolution requirements. However, high-magnification lenses typically have very shallow depths of field (e.g., a 2x lens has a depth of field of approximately 160 μm). In advanced packaging, the spatial arc height of gold wires often reaches 250 μm or even higher, far exceeding the lens's depth of field range. This results in large areas of defocusing and blurring of the gold wires in two-dimensional imaging, making it impossible to effectively identify three-dimensional morphological defects such as wire collapse and misalignment.

[0005] Secondly, the similarity in color and contrast makes it impossible to segment the outline of the solder joints. The shape of the solder joint is a core indicator for process control. However, solder joints made of gold or copper have extremely high similarity with the metal pads or substrates underneath in terms of material, color, and grayscale. Under two-dimensional top-down imaging, the contrast is extremely low, and the edges visually merge, making it impossible to accurately quantify and segment the shape of the solder joints.

[0006] Third, the lack of three-dimensional spatial height information leads to the missed detection of hidden vertical defects. Tiny lifts or peeling solder joints at the root of solder joints are deformations in the vertical direction, which have no observable geometric features in two-dimensional plane projection. Two-dimensional inspection cannot detect such defects when shooting from directly above, thus creating a serious hidden danger for the later failure of semiconductor devices. Summary of the Invention

[0007] This invention proposes a method and system for detecting semiconductor bonding wires and solder joints, aiming to solve the technical problems of existing two-dimensional automatic optical inspection methods, which are limited by optical depth of field, resulting in gold wire defocusing; limited by material contrast, resulting in the inability to segment solder joint edges; and lack of three-dimensional height data, resulting in missed detection of vertical defects such as root lifting and cold solder joints. These problems make it impossible to meet the high-precision, full-three-dimensional inspection requirements in multi-chip stacking scenarios in advanced packaging processes.

[0008] In a first aspect, the present invention provides a method for detecting semiconductor bonding wires and solder joints, comprising:

[0009] Obtain a 3D height map of the chip package area, including the gold wire and solder joint to be tested;

[0010] The three-dimensional height map is divided into multiple regions based on the standard gold wire template. The height of the carrier surface corresponding to each region is used as a reference, and a preset threshold increment is superimposed as the segmentation threshold for binarization segmentation. The segmented contours are connected to form a full-span continuous gold wire region of interest. Gold wire defect detection is performed based on the gold wire region of interest to obtain the gold wire defect detection result.

[0011] A local window containing the solder joint to be tested is defined, and the solid contour of the solder joint to be tested is extracted by segmentation using a height threshold; point defect detection is performed based on the solid contour to obtain the point defect detection result;

[0012] Based on the attachment carrier type of the solder joint to be tested recorded in the standard gold wire template, the positioning reference area is located, the first height feature value in the solid contour and the second height feature value in the reference area are extracted respectively, the difference between the two is calculated and compared with the process standard thickness to obtain the detection results of root lifting and cold solder joint.

[0013] Based on the gold wire defect detection results, the dot-shaped defect detection results, and the root lifting and cold solder joint detection results, the overall pass / fail judgment result of the chip packaging area is output.

[0014] Furthermore, based on the standard gold line template, the three-dimensional height map is divided into multiple regions. Using the height of the carrier surface corresponding to each region as a benchmark, a preset threshold increment is superimposed as the segmentation threshold for binarization segmentation. Specifically, this includes:

[0015] The standard gold wire template records the spatial distribution area of ​​each chip on the projection plane, the height value of each chip surface relative to the substrate surface, the expected trajectory coordinates of each gold wire, and the design coordinates and attachment carrier type of each solder joint.

[0016] After dividing the three-dimensional height map into multiple chip regions and one substrate region on the projection plane according to the standard gold wire template, for any pixel, the corresponding carrier surface height reference value is determined according to the region to which the pixel belongs. and threshold increment Calculate the segmentation threshold If the height value of the pixel If it is, it is determined to be a gold line entity; otherwise, it is determined to be background.

[0017] Furthermore, gold wire defect detection is performed on the gold wire under test using the region of interest of the gold wire, specifically including:

[0018] Align the region of interest of the gold wire with the standard gold wire template in terms of spatial coordinates. Establish a search window within the expected trajectory range of each gold wire recorded in the standard gold wire template. If there is no pixel connected region that meets the segmentation threshold within the search window, it is determined that there are few wires. If there is a pixel connected region that meets the segmentation threshold outside the expected trajectory range, it is determined that there are many wires.

[0019] Extract the center trajectory lines of each gold wire in the region of interest of the gold wire, and compare the lateral position deviation and angle deviation of the center trajectory lines with the expected trajectory recorded in the standard gold wire template to determine the wire misalignment;

[0020] Multiple discrete positions are set on the central trajectory line and the highest point of the entire line is determined. The height values ​​of each discrete position and the highest point are extracted respectively. If the height value of any discrete position or the highest point is lower than the corresponding safe height threshold, the collapse is determined.

[0021] Further, the solid contour of the solder joint to be tested is extracted by segmentation using a height threshold, including:

[0022] The height values ​​of all pixels within the local window are statistically analyzed. The set of pixels corresponding to the peaks with lower height values ​​is determined as the background layer. The arithmetic mean of the pixel height values ​​within this set is calculated as the background height reference value. Set the segmentation threshold , For a preset threshold increment, the height value within the local window is greater than or equal to... The pixels that are identified as solder joint entities are determined, and the remaining pixels are determined as background, thus obtaining the physical outline of the solder joint to be tested.

[0023] Furthermore, a local window containing the solder joint to be tested is defined, and the solid contour of the solder joint to be tested is extracted by multimodal fusion segmentation, including:

[0024] Obtain a two-dimensional intensity image with the same field of view as the three-dimensional height map. ;

[0025] The segmentation result obtained by the three-dimensional height map under a loose segmentation threshold is used as a spatial constraint mask. The loose segmentation threshold is lower than the standard segmentation threshold of the corresponding region, so that the area of ​​the spatial constraint mask is larger than the actual area of ​​the solder joint to be tested but smaller than the area of ​​the local window.

[0026] Within the area defined by the spatial constraint mask, the total energy functional is constructed using the segmentation boundary as a variable:

[0027] ;

[0028] in For along the dividing boundary The inverse of the gradient magnitude of the two-dimensional image is integraled along the boundary line. The magnitude of the local gradient in the two-dimensional image; For along the dividing boundary The inverse of the gradient magnitude of the 3D heightmap is integraled along the boundary line. This represents the local elevation gradient magnitude of the 3D height map; and For preset weighting coefficients, The derivative of the arc length along the dividing boundary;

[0029] Through iterative evolution of the level set method, When the minimum value is reached, the segmentation boundary at this point is taken as the solid contour of the weld point to be tested.

[0030] Furthermore, the specific method for detecting point defects based on the entity contour is as follows:

[0031] The actual outer diameter is obtained by performing circle fitting on the solid contour of the weld point to be tested. The circle fitting employs either the minimum circumcircle method or the equivalent area circle fitting method; the actual outer diameter and the gold wire design diameter are calculated. ratio Read the client-preset pass / fail ratio range [ ],like If the point shape is deemed unqualified, then it is determined that the shape is not up to standard.

[0032] Furthermore, the specific method for defining the positioning reference area is as follows:

[0033] The standard gold wire template records the type of attachment carrier for each solder joint, and the type of attachment carrier is the chip surface or the substrate surface.

[0034] When the attachment carrier of the solder joint to be tested is the chip surface, the corresponding flat area of ​​the chip around the solder joint is used as the reference area; when the attachment carrier is the substrate surface, the flat area of ​​the substrate around the solder joint is used as the reference area.

[0035] Furthermore, the extraction methods for the first height feature value and the second height feature value are as follows:

[0036] Extract the set of height values ​​of all pixels within the solid outline of the weld point to be tested and the set of height values ​​of all pixels within the reference area.

[0037] For each of the two sets, calculate the height feature value using any of the following statistical methods: arithmetic mean, median, mode, value at a specified quantile, or weighted average of the remaining pixels after removing outliers that deviate from the mean by more than three standard deviations.

[0038] Secondly, the present invention provides a semiconductor bonding wire and solder joint detection system, comprising:

[0039] The 3D data acquisition module is used to acquire a 3D height map of the chip package area, which includes the gold wire and solder joint to be tested.

[0040] The storage module is used to store the standard gold wire template and the qualified ratio range preset by the client;

[0041] The gold wire segmentation and detection module is used to divide the three-dimensional height map into multiple regions based on the standard gold wire template, and perform binary segmentation by superimposing a preset threshold increment as the segmentation threshold based on the height of the carrier surface corresponding to each region. The segmented contours are connected into a full-span continuous gold wire region of interest, and the gold wire region of interest is used to perform gold wire defect detection and output the gold wire defect detection result.

[0042] The solder joint segmentation module is used to delineate a local window containing the solder joint to be tested, and extract the solid contour of the solder joint to be tested by height threshold segmentation or multimodal fusion segmentation.

[0043] The dot shape detection module is used to perform circle fitting on the contour of the entity to obtain the actual outer diameter, calculate the ratio of the actual outer diameter to the design diameter of the gold wire, read the qualified ratio range, and if the ratio does not fall within the qualified ratio range, the dot shape is determined to be unqualified, and the dot shape defect detection result is output.

[0044] The root detection module is used to locate the reference reference area according to the attachment carrier type of the solder joint to be tested recorded in the standard gold wire template, extract the first height feature value in the solid contour and the second height feature value in the reference reference area respectively, calculate the difference between the two and compare it with the process standard thickness. If the difference is less than the lower limit of the process standard thickness, it is determined that the root is raised or the solder joint is cold, and the detection results of root raised and cold solder joint are output.

[0045] The judgment output module is used to output the overall pass / fail judgment of the chip packaging area based on the gold wire defect detection results, the dot-shaped defect detection results, and the root lifting and cold solder joint detection results.

[0046] Furthermore, the specific method for detecting gold wire defects using the region of interest in the gold wire in the gold wire segmentation and detection module is as follows:

[0047] The region of interest (ROI) of the gold wire is aligned with the standard gold wire template in terms of spatial coordinates. Search windows are established within the expected trajectory range of each gold wire recorded in the standard gold wire template to determine missing wires. Connected components are detected outside the expected trajectory range to determine extra wires. The center trajectory line of each gold wire in the ROI is extracted, and the lateral position deviation and angle deviation are compared to determine wire misalignment. Multiple discrete positions are set on the center trajectory line, and the highest point of the entire line is determined. The height value is extracted and compared with the corresponding safe height threshold to determine wire collapse.

[0048] The technical effects of this invention are:

[0049] (1) For the extraction of regions of interest (ROI) of gold wires, this invention divides the three-dimensional height map into multiple chip regions and one substrate region on the projection plane based on a standard gold wire template. Pixels in each region are binarized using the height value of the corresponding carrier surface as a reference and a preset threshold increment as the segmentation threshold. This scheme overcomes the shortcomings of a single fixed threshold in multi-chip stacking scenarios, achieving accurate extraction of gold wire ROI that is continuous across the entire span from the first bonding point to the second bonding point without background adhesion.

[0050] (2) For gold wire defect detection, the present invention establishes an independent search window within the expected trajectory range of each gold wire to determine the missing wire, and detects the connected domain outside the expected trajectory range to determine the multiple wire; extracts the center trajectory line of the gold wire and compares the lateral position deviation and angle deviation to determine the wire crookedness; sets multiple discrete positions on the center trajectory line and combines the highest point to perform height detection to determine the wire collapse, which can accurately capture local wire collapse that occurs at any position.

[0051] (3) For weld point contour extraction, this invention proposes two methods: pure height binarization segmentation and height-two-dimensional image multimodal fusion segmentation. The multimodal fusion method uses the coarse segmentation result of the three-dimensional height map as a spatial constraint mask. Within the range defined by the mask, a weighted energy functional is constructed using the edge gradient field of the two-dimensional image and the elevation gradient field of the three-dimensional height map. The segmentation boundary is obtained by iteratively minimizing the energy functional. This method can achieve accurate positioning by relying on height tomographic information when the weld point and the background color are similar.

[0052] (4) For the detection of weld point shape, the present invention uses a circle fitting algorithm to calculate the actual outer diameter of the weld point and calculates the ratio with the design diameter of the gold wire, reads the qualified ratio range preset by the client for judgment, and adapts to the differentiated requirements of different processes.

[0053] (5) For the detection of root lifting and cold solder joints, this invention locates the reference area to the corresponding chip surface or substrate surface based on the type of solder joint attachment carrier recorded in the standard gold wire template. Root lifting is detected by subtracting the statistical height features of the solder joint area and the reference area, thus eliminating common-mode noise. Various types of noise interference are selectively filtered out by using different statistical calculation methods such as arithmetic mean, median, specified quantile points, or weighted average after removing outliers on the pixel height set. Attached Figure Description

[0054] Figure 1 This is a schematic flowchart of a method for detecting semiconductor bonding wires and solder joints according to an embodiment of the present invention. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] To address the limitations of existing two-dimensional automatic optical inspection methods mentioned in the background art—namely, optical depth of field leading to gold wire defocusing, material contrast limitations resulting in inability to segment solder joint edges, and the lack of three-dimensional height data causing missed detection of vertical defects such as root lifting and cold solder joints—these methods fail to meet the high-precision, full-dimensional inspection requirements of multi-chip stacking scenarios in advanced packaging processes. This invention provides a method for detecting semiconductor bonding wires and solder joints. The technical solution of this invention will be described in detail below with reference to specific industrial application scenarios. In this embodiment, the three-dimensional height map of the chip packaging area obtained by any three-dimensional measurement means is represented as an elevation matrix. ,in Represents the coordinates of a pixel on a two-dimensional projection plane. This represents the height value at that coordinate, in μm. The 3D height map can be obtained using methods such as line spectral confocal sensors, structured light 3D scanning equipment, or laser triangulation equipment; this invention does not limit the method used. (Reference) Figure 1 As shown, the specific steps include:

[0057] Step 1: Obtaining the 3D height map. This step involves obtaining a 3D height map of the chip package area, including the gold wires and solder joints to be tested. The chip package area can be a single-chip package structure or a multi-chip assembly structure containing multiple layers of vertically stacked and horizontally parallel heterogeneous chips. The 3D height map covers the entire chip package area to be tested, including suspended gold wires (including high-altitude gold wire segments crossing different chip levels and low-altitude gold wire segments close to the substrate surface), solder joints located on the chip surface or substrate surface (including first bonding points, second bonding points, and cross-level direct connection bonding points between heterogeneous chips), and background areas such as the chip surface and substrate surface.

[0058] Step 2: Extraction of the Region of Interest (ROI) for Gold Lines. In multi-chip vertical stacking packages (e.g., a 100μm thick first-layer chip Die1 is mounted on the bottom substrate, and an 80μm thick second-layer chip Die2 is stacked on top of Die1), gold lines spanning different layers experience severe three-dimensional elevation discontinuities below them. If a fixed single height threshold is used for global segmentation, when the threshold is set low (e.g., 50μm), due to the large heights of Die1 and Die2, the entire upper surface features of the chip will meet the threshold condition, resulting in large-area adhesion between the gold lines at higher elevations and the chip body. When the threshold is set high (e.g., 150μm), the lower-lying gold lines near the substrate's drop section will be directly cut off because they are below the threshold. To overcome this problem, this step employs a partitioned dynamic threshold segmentation method.

[0059] A standard gold wire template is a pre-built data file that records the expected spatial arrangement trajectory of each gold wire in a defect-free, qualified product, the design coordinates of each solder joint, the spatial distribution area of ​​each chip on the projection plane, the height of each chip surface relative to the substrate surface, and the attachment carrier type of each solder joint (i.e., the specific layer of chip surface or substrate surface to which the solder joint is attached). This template can be obtained by 3D scanning and annotation of qualified samples, or it can be derived from chip packaging design documents (such as CAD files).

[0060] After the system loads the standard gold wire template, it divides the three-dimensional height map into the top-level chip Die2 region on the projection plane based on the spatial distribution area of ​​each chip recorded in the template. Middle layer chip Die1 area and the peripheral substrate area For package structures containing more chip layers, they can be similarly divided into N chip regions. } and at least one substrate region .

[0061] Then, different segmentation thresholds are applied to different regions. The heightmap matrix is ​​traversed. For each pixel in the image, the corresponding segmentation threshold is... Dynamically changes with the region where the pixel is located:

[0062] For the top-level chip area The pixels, in terms of the height value of the Die2 chip surface. As a benchmark (e.g., obtained by taking the arithmetic mean of pixel heights in the flat area of ​​the Die2 surface, where the flat area refers to the area on the chip surface not covered by gold wires or solder joints), a threshold increment is superimposed. Segmentation threshold In a specific example, the height of the Die2 chip surface is approximately 180 μm (i.e., the height from the substrate surface to the top surface of the Die2). If we set it to 20μm, then Approximately 200 μm. When If the pixel is found to be a gold line entity, it is determined to be part of the background. Since the chip surface height is approximately 180μm and the gold line is suspended at least 20μm above the chip (i.e., height ≥ 200μm), the gold line is completely stripped away, and the chip surface texture is effectively filtered out.

[0063] For the middle layer chip area The pixels, in terms of the height value of the Die1 chip surface. As a baseline (approximately 100 μm), the threshold increment is superimposed. (Set to 20μm), segmentation threshold ≈120μm.

[0064] For areas belonging to the substrate The pixels, in terms of the height value of the substrate surface As a reference (with the substrate surface as the reference zero plane) =0μm), with the threshold increment superimposed. (Set to 20μm), segmentation threshold ≈20μm.

[0065] The threshold increments for the above regions ( , , The typical arc height of the gold wire and the noise level of the measurement system in the actual process can be preset and stored in the system configuration.

[0066] Through the aforementioned pixel-by-pixel dynamic thresholding, the gold wires within each region are extracted, while the large-area surface background of each chip layer is effectively filtered out. Subsequently, the extracted gold wire contours are joined at region boundaries. Specifically, at region boundaries (e.g., the step boundary between Die1 and Die2), the endpoints of adjacent gold wire contours are extracted, the spatial distance between each endpoint is calculated, and the closest endpoints are paired and connected to form a continuous gold wire contour from the first bonding point to the second bonding point—that is, a full-span continuous region of interest (ROI). This ROI is a binarized image. Pixels with a value of 1 represent gold line entities, while pixels with a value of 0 represent the background.

[0067] Step 3: Gold wire defect detection, extracting the region of interest of the gold wire. Spatial coordinate alignment with a standard gold wire template is performed, meaning that the spatial coordinate systems of the two are optimally matched through translation, rotation, and scaling, ensuring that the positions of each gold wire in the region of interest (ROI) correspond one-to-one with the desired positions recorded in the template. The specific method for spatial coordinate alignment is as follows: using a reference point recorded in the standard gold wire template (such as a chip corner point or a specific solder joint position), calculate the position offset and rotation angle of the corresponding reference point in the ROI of the gold wire, and apply a rigid body transformation to the ROI to make it coincide with the template coordinate system.

[0068] (I) Detection of defects with few or many wires: Within the expected trajectory range of each gold wire recorded by the standard gold wire template, establish independent search windows. Specifically, establish a search window for each expected gold wire, with the window size slightly larger than the design line width and positional tolerance range of that gold wire (e.g., the window width is 3 times the design line width, and the length is the length of that gold wire trajectory). Traverse each search window: If no defective wire is found within a certain search window... If a pixel connected region is marked as a gold wire entity, it is determined that the channel has a "missing wire" defect (i.e., the gold wire is missing or not soldered), and the specific channel number is recorded.

[0069] At the same time, it traverses non-preset areas outside the expected trajectory range of each gold wire. If a connected region with an area greater than a preset threshold (e.g., more than twice the cross-sectional area of ​​a normal gold wire) is detected in these background areas where gold wires should not appear, it is determined that there is external broken wire residue or accidental overlap, triggering a multi-wire alarm and recording the coordinates of the defect location.

[0070] (ii) Detection of wire misalignment defects: Morphological skeletonization is performed on the extracted connected components of the gold wire to obtain the center trajectory line of the gold wire with a single pixel width. Morphological skeletonization can be performed using a skeleton extraction algorithm based on distance transform: calculate the binarized image... The distance from each gold line pixel to the nearest background pixel is used to extract the local maxima of the distance transformation to form the skeleton; or a thinning-based morphological algorithm is used: while keeping the gold line connectivity and endpoint positions unchanged, pixels are peeled off layer by layer from the gold line boundary until a center line with a single pixel width is obtained.

[0071] The extracted center trajectory line is compared with the expected trajectory recorded in the standard gold wire template. The lateral position deviation (i.e., the planar offset of the actual gold wire position relative to the design position, in μm) and angular deviation (i.e., the angle between the actual gold wire direction and the design direction, in degrees) of the center trajectory line relative to the expected trajectory are calculated. If the lateral position deviation exceeds the preset lateral tolerance threshold (e.g., ±5μm) or the angular deviation exceeds the preset angular tolerance threshold (e.g., ±3°), a wire misalignment defect is determined, and the deviation amount is recorded.

[0072] (III) Detection of wire collapse defects: On the center trajectory line of each gold wire extracted through the skeleton, multiple discrete positions are set as height control points along its direction. In a specific example, for a gold wire with a span of 2mm, three height control points are set at the neck area at 10% of the distance from the starting point, the middle arc apex area at 50% of the distance, and the tail area at 90% of the distance. In practical applications, the number, location, and spacing of control points can be flexibly configured according to the specific length of the gold wire, the characteristics of the arc height curve, and the process requirements. For example, control points can be densely set in areas with large curvature changes.

[0073] The system in the 3D height map Extract the height values ​​at these three locations respectively. Simultaneously extract the maximum height along the entire center trajectory line. (That is, the height value of the highest point). In the system's configuration register, independent safety height thresholds are set for each control point and the highest point. For example, the safety height of the control point at the apex of the arc is set at 220μm, the neck control point at 90μm, the tail control point at 80μm, and the highest point safety height at 230μm. These safety height thresholds are preset according to the specific product's process specifications.

[0074] During testing, the real-time height of each control point is compared sequentially with its corresponding safe height threshold. Simultaneously, the real-time height of the highest point is compared with its highest point safe height threshold. If the real-time height of any control point is lower than its corresponding safe height threshold (i.e.,...), the system will detect if the real-time height of any control point is lower than its corresponding safe height threshold. ), or the real-time height of the highest point is lower than the safe height threshold of the highest point (i.e. If the gold thread has a collapse defect, the location of the defect (specifically, which control point or highest point the collapse occurred at) is recorded.

[0075] The above-mentioned detection results for missing / excessive wires, misaligned wires, and collapsed wires are summarized as the gold wire defect detection results, which include whether defects exist, the type of defect (missing / excessive wires / misaligned wires / collapsed wires), and the location of the defect.

[0076] Step four, extracting the external contour of the solder joint. A local window containing the complete solder joint to be tested is defined around the solder joint design coordinates recorded in the standard gold wire template. The window size should be slightly larger than the maximum design size of the solder joint (e.g., 5-10 pixels larger than the design radius of the solder joint) to ensure that the solder joint is completely contained within the window. At the same time, the window should not be too large to avoid introducing excessive background noise. This invention provides two methods for solder joint contour extraction.

[0077] (a) Pure height binarization segmentation method: First, for local windows... Statistical analysis was performed on the height values ​​of all pixels within the histogram. Since the height of the solder joint entity area is significantly higher than the surrounding background (pad surface), a bimodal distribution appears in the height histogram, with the lower peak corresponding to the background layer (pad surface) and the higher peak corresponding to the solder joint entity layer. The set of pixels corresponding to the lower peak (i.e., pixels within the interval of the first peak in the histogram) was extracted, and the arithmetic mean of their height values ​​was calculated as the background height baseline. .

[0078] Then set the segmentation threshold:

[0079] ;

[0080] in This represents the preset threshold increment, in μm. In a specific example, Choose 3μm. This value should be greater than the surface roughness amplitude of the pad (usually 1-2μm) and less than the typical height of the solder joint (usually 10-50μm) to ensure that the solder joint can be effectively separated from the background and is not affected by surface roughness noise.

[0081] Set the height value within the local window The pixels are identified as solder joint entities. The pixels identified as background are considered as the outer contour of the solder joint being tested. All pixels identified as solder joint entities together constitute the outer contour of the solder joint being tested. .

[0082] (ii) Height and 2D image multimodal fusion segmentation method: When there are burrs or height gradients at the edge of the solder joint, pure height segmentation may introduce discrete noise at the edge; when the grayscale of the solder joint and the background are similar in the 2D image, pure 2D image segmentation will result in boundary fusion. This method solves the above problems by combining information from both modalities.

[0083] First, obtain the 3D height map. High-resolution two-dimensional intensity images in the same spatial coordinate system and under the same field of view The two-dimensional intensity image can be acquired by the same device at the same detection station (e.g., a grayscale image captured using a coaxial light source), or it can be acquired by multiple sensors and then spatially registered.

[0084] Then, coarse segmentation is performed using a 3D height map with a relatively lenient segmentation threshold. The term "lenient segmentation threshold" refers to the segmentation threshold used in method (one) of this implementation. By appropriately reducing the size (e.g., by 2-3 μm), the coarse segmentation result can completely include the solid region of the solder joint, but also include part of the background region, i.e., the spatial constraint mask obtained from the coarse segmentation. The area is larger than the actual area of ​​the solder joint but smaller than the local window. The area of ​​the spatial constraint mask. The function of this spatial constraint mask is to limit the search range of subsequent fine segmentation to the area covered by the mask, thereby shielding the pseudo-edge interference outside the local window that is unrelated to the solder joint.

[0085] Spatial Constraint Mask Within the defined scope, using the dividing boundary C as a variable, the following weighted energy functional is constructed:

[0086] ;

[0087] The specific definitions of each data item are as follows:

[0088] ;

[0089] Let be the line integral along the boundary C, representing the reciprocal of the two-dimensional image gradient magnitude. Two-dimensional intensity image In coordinates The local gradient magnitude at a given point, expressed in grayscale value per pixel; This is the differential of the arc length along the segmentation boundary, with pixels as the unit. The physical meaning of this data item is: at each point on the segmentation boundary, the larger the local gradient magnitude of the 2D image (i.e., the more obvious the image edge), the smaller the integrand value at that point. Thus, during the energy functional minimization process, the segmentation boundary is driven to move closer to the high-frequency texture edge in the 2D image.

[0090] ;

[0091] Let be the line integral along the boundary, which is the reciprocal of the gradient magnitude of the 3D heightmap along the dividing boundary C. 3D height map In coordinates The local elevation gradient magnitude at a given location, in units of μm / pixel; The value is the differential of the arc length along the segmentation boundary, with pixels as the unit. The physical meaning of this data item is: at each point on the segmentation boundary, the larger the local gradient magnitude of the 3D height map (i.e., the more drastic the height change, corresponding to the physical edge of the weld point), the smaller the integrand value at that point. Thus, during the energy functional minimization process, the segmentation boundary is driven to move closer to the elevation fault edge in the 3D height map.

[0092] and Preset weighting coefficients (dimensionless) are used to adjust the relative importance of the two modalities in segmentation. In a specific example, when the height map has higher contour sharpness than the 2D image, =0.3, =0.7. and The specific values ​​can be calibrated and optimized offline based on the relative quality of the two-dimensional image and the three-dimensional height map in the actual detection scenario.

[0093] The energy functional above is solved iteratively using the level set method: the dividing boundary C is represented as a level set function. The zero level set (i.e., satisfying) (the set of points where = 0), constructing a function about the level set. Partial differential evolution equations The level set function is iteratively updated using gradient descent, so that... The value is continuously reduced until it converges to a minimum. At this point, the segmentation boundary is located at the intersection of the high-frequency texture edge of the two-dimensional image and the elevation fault edge of the three-dimensional height map, which is the precise external outline of the weld point to be tested.

[0094] Step 5: Weld Joint Shape Defect Detection. Based on the solid contour of the weld joint to be tested extracted in Step 4 (i.e., the binarized image)... The actual geometric outer diameter of the solder joint is calculated using a circle fitting algorithm (a set of pixels with a median value of 1).

[0095] In a specific example, a minimum circumcircle fitting is used: the diameter of the smallest circle that completely contains all pixels of the solder joint's solid outline is found, and this diameter is taken as the actual geometric outer diameter of the solder joint. The method for finding the minimum circumcircle is as follows: traverse all pairs of pixels on the contour, construct a candidate circle with the line connecting each pair of points as the diameter, check whether the circle contains all contour points, and record the circle with the smallest diameter among all circles that meet the conditions; or use the rotating caliper algorithm to search on the convex hull, which has lower time complexity and is suitable for high-speed detection.

[0096] In another specific example, an equivalent area circle fitting is used: the total number of pixels enclosed by the solid outline of the solder joint is counted and converted into the actual area. (Number of pixels multiplied by the actual area corresponding to a single pixel, in units of...) ), calculate the diameter of the circle with the same area:

[0097] ;

[0098] This refers to the actual geometric outer diameter of the weld joint.

[0099] The minimum circumscribed circle method is suitable for scenarios with strict requirements on the maximum radial dimension of the solder joint (such as checking whether the solder joint exceeds the pad boundary), while the equivalent area circle fitting method is suitable for scenarios with strict requirements on the overall area of ​​the solder joint (such as checking whether the solder joint pressing area meets the standard).

[0100] Get the design diameter of the gold wire currently in use. (This value is a known process parameter, in μm, for example, 20μm corresponds to 0.8mil gold wire), calculate the ratio:

[0101] ;

[0102] This ratio is dimensionless and reflects the degree of widening of the weld joint after it is pressed together.

[0103] The client can pre-configure and input the pass / fail ratio range corresponding to the current product through a human-computer interaction interface or production control system. ], and All values ​​are dimensionless positive numbers. This range can be flexibly set according to the requirements of different end customers or the process specifications of different power devices. For example, high-reliability automotive electronic devices can be set to [2.5, 4.0] (requiring sufficient solder joint bonding but not excessive diffusion), while power semiconductor devices can be set to [1.8, 5.5] (allowing a larger range of bonding diffusion to withstand large currents).

[0104] The system reads the acceptable ratio range, if If the weld shape is deemed acceptable, then the weld shape is deemed unacceptable and the defect type is recorded as unacceptable.

[0105] Step 6: Detection of weld root lifting and cold weld defects.

[0106] (i) Location of the reference area: The solder joints under test are classified into several types according to their position in the package structure: the first bonding point located at the chip surface level (the connection point between the gold wire start end and the chip pad), the second bonding point located at the substrate surface level (the connection point between the gold wire end and the substrate pin), and the cross-level direct connection bonding point located between heterogeneous chips (e.g., the gold wire of the top layer Die2 is bonded to the pad of the middle layer Die1). Different types of solder joints have different physical attachment carriers.

[0107] The standard gold wire template records an attachment carrier type field for each solder joint, with the value being either chip surface or substrate surface. When the attachment carrier is the chip surface, the template also records the specific chip layer number to which the solder joint is attached (such as Die1, Die2, etc.).

[0108] When a solder joint to be tested is detected, the positioning method of the reference area is determined according to the type of attachment carrier recorded in the template for that solder joint:

[0109] If the attachment carrier is a chip surface, the corresponding flat area of ​​the chip surrounding the solder joint is used as the reference area. The specific positioning method is as follows: with the solder joint design coordinates as the center, select several sampling points in an annular area 5-10μm away from the edge of the solder joint (for example, uniformly select points on an annular circle with a radius of 1.5 to 2 times the diameter of the solder joint). The location of all these sampling points is the reference area.

[0110] If the attachment carrier is the substrate surface, the flat area of ​​the substrate surrounding the solder joint is used as the reference area. The positioning method is the same as above, but the sampling area is located on the substrate surface.

[0111] In this way, the reference area is adaptively positioned to the carrier surface to which the solder joint is actually attached. Taking a multi-chip stacking scenario as an example, assuming there is a cumulative height tolerance of 50μm between the top layer Die2 and the bottom layer Die1, when detecting solder joints attached to the surface of Die2, the reference area is positioned on the surface of Die2. This 50μm tolerance exists simultaneously in the solder joint height and the reference area height, and is canceled out in the subsequent difference calculation, thereby eliminating the influence of the cumulative tolerance on the root lifting detection.

[0112] (ii) Statistical calculation of height feature values: extracting the set of height values ​​of all pixels within the solid contour of the weld point to be tested. Calculate the first height feature value Extract the set of height values ​​for all pixels within the reference area. Calculate the second height characteristic value .

[0113] This invention provides a variety of statistical calculation methods, which can be selected according to the actual noise type:

[0114] Arithmetic mean: Simply sum all height values ​​in the set and divide by the number of pixels. Suitable for scenarios with low noise levels, offering the fastest computation speed.

[0115] Median: The median value after sorting all height values ​​in the set from smallest to largest. Suitable for scenarios with a small number of extremely high or low noise values, effectively shielding against occasional metal splashes or scratches.

[0116] Mode: The height value that appears most frequently in the set. It is suitable for scenarios where the height distribution has a clear unimodal characteristic (such as the height distribution of a flat surface being concentrated around a certain value), and can quickly determine the most typical height.

[0117] Specify the value of the quantile point: For example, take the upper quartile (75th quantile), which is the value at the 75th position after sorting all height values ​​in the set from smallest to largest. This value can represent the height of the upper surface of the body and exclude low-level noise such as pits, which is suitable for scenarios where there are cleaving marks or central fisheye pits on the surface of the solder joint.

[0118] Weighted average after removing outliers: First, calculate the mean μ and standard deviation σ of the set. Remove extreme highs and lows that deviate from the mean by more than σ. Then, assign weights to the remaining pixels based on their distance from the center of the solder joint (higher weight for the center, lower weight for the edges), and finally calculate the weighted average. ,in Let be the weight of the i-th pixel. This method can simultaneously shield high-order noise (metal spatter particles) and low-order noise (deep scratches), making it suitable for extremely high-precision detection scenarios and providing stereo repeatability accuracy up to 0.5 μm.

[0119] Of the five methods mentioned above, for and The calculation can be performed in the same way, or different methods can be selected according to the noise characteristics of the two sets respectively. For example, when there is a central pit (low noise) in the solder joint area, the upper quartile point is used, and when there is metal spatter (high noise) in the reference area, the median is used.

[0120] (iii) Determining the height difference by judging the root curvature:

[0121] ;

[0122] in This is the first height feature value. The second height characteristic value, both are in the dimension of μm, and ΔH is in the dimension of μm. This difference reflects the actual vertical height of the solder joint entity relative to the reference plane of its attachment carrier.

[0123] Compare ΔH with the standard process thickness (i.e., the standard height range of a qualified solder joint relative to the carrier reference surface, pre-set by the process specification, in μm). If ΔH is less than the lower limit of the standard process thickness (e.g., the standard thickness is 15-25 μm, the lower limit is 15 μm, but the measured ΔH is only 8 μm), it indicates that the root of the solder joint is lifted from the carrier surface, and the actual adhesion height is lower than the normal value, indicating a root lifting defect. If ΔH is close to 0 or is negative, it indicates that the solder joint has failed to form an effective metallurgical connection with the carrier surface, is only suspended above the carrier by surface tension, or has completely detached, indicating a poor solder joint.

[0124] By combining the above-mentioned adaptive positioning of the reference area with specific statistical filtering, the present invention deconstructs the complex global cumulative deformation into the calculation of the relative height difference of each local area, so that the micron-level warping defects at the root of the solder joint at any multi-level step height can be accurately captured.

[0125] Step 7: Comprehensive judgment of test results. The test results of gold wire defects obtained in Step 3 (including whether there are missing wires, extra wires, crooked wires, collapsed wires and their respective defect locations), the test results of point defects obtained in Step 5 (point shape qualified / unqualified), and the test results of root lifting and cold solder joints obtained in Step 6 (whether the root is lifted and whether there is cold solder joints) are summarized.

[0126] If all the above test items are qualified (i.e., no missing, extra, crooked, or collapsed gold wires; qualified solder joint shape; no lifting or cold solder joint at the root of the solder joint), then the overall qualified judgment of the chip packaging area will be output; if any of the above test items are unqualified, then the overall unqualified judgment will be output, along with specific defect type and defect location information, for subsequent process adjustment and defect traceability.

[0127] Based on the same inventive concept, the present invention also provides a semiconductor bonding wire and solder joint detection system, comprising the following modules:

[0128] The 3D data acquisition module is used to acquire a 3D height map of the chip package area, including the gold wires and solder joints to be tested. This module may include a line spectral confocal sensor, a structured light 3D scanning device, or a laser triangulation device.

[0129] The storage module stores the standard gold wire template and the client-preset pass ratio range. The standard gold wire template records the spatial distribution area of ​​each chip on the projection plane, the height value of each chip surface relative to the substrate surface, the expected trajectory coordinates of each gold wire, the design coordinates of each solder joint, and the attachment carrier type.

[0130] The gold wire segmentation and detection module is used to divide the 3D height map into multiple chip regions and one substrate region on the projection plane based on a standard gold wire template. Pixels within each region are binarized using the height value of the corresponding carrier surface as a reference, and a preset threshold increment is added as the segmentation threshold. The obtained gold wire contours are then connected at the region boundaries to generate a continuous region of interest (ROI) spanning the entire length of the gold wire. This ROI is then used to detect gold wire defects and output the detection results. The specific methods for gold wire defect detection include: aligning the ROI with the standard gold wire template in spatial coordinates; establishing search windows within the expected trajectory range of each gold wire recorded in the standard template to determine missing wires; detecting connected components outside the expected trajectory range to determine multiple wires; extracting the center trajectory lines of each gold wire within the ROI and comparing lateral positional and angular deviations to determine wire misalignment; setting multiple discrete positions on the center trajectory lines and determining the highest point of the entire line, extracting the height value and comparing it with the corresponding safe height threshold to determine wire collapse.

[0131] The solder joint segmentation module is used to delineate a local window containing the solder joint to be tested. The height reference value of the background area within the local window is superimposed with a preset threshold increment as the segmentation threshold to perform binarization segmentation and extract the entity contour of the solder joint to be tested. Alternatively, a two-dimensional intensity image with the same field of view as the three-dimensional height map is acquired. The segmentation result obtained by the three-dimensional height map under a loose segmentation threshold is used as a spatial constraint mask. Within the range defined by the spatial constraint mask, a weighted energy functional is constructed by the edge gradient field of the two-dimensional image and the elevation gradient field of the three-dimensional height map. The entity contour of the solder joint to be tested is obtained by iteratively solving and minimizing the weighted energy functional.

[0132] The dot shape detection module is used to perform circle fitting on the solid contour of the weld point to be tested to obtain the actual outer diameter, calculate the ratio of the actual outer diameter to the design diameter of the gold wire, read the qualified ratio range, and if the ratio does not fall into the qualified ratio range, the dot shape is determined to be unqualified, and the dot shape defect detection result is output.

[0133] The root detection module is used to locate the reference area in the 3D height map based on the attachment carrier type of the solder joint to be tested recorded in the standard gold wire template, and to extract the height value set of each pixel in the solid outline of the solder joint to be tested and the height value set of each pixel in the reference area. Statistical calculations are performed on the two sets to obtain the first height feature value and the second height feature value. The difference between the two is calculated and compared with the process standard thickness. If the difference is less than the lower limit of the process standard thickness, the root is determined to be raised or a cold solder joint, and the detection results of root raised or cold solder joint are output.

[0134] The judgment output module is used to output the overall pass / fail judgment of the chip packaging area based on the gold wire defect detection results, the dot-shaped defect detection results, and the root lifting and cold solder joint detection results.

[0135] The above modules can be integrated into a single automated optical inspection device, or they can be distributed across multiple devices and work together through data communication.

[0136] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for detecting semiconductor bonding wires and solder joints, characterized in that, include: Obtain a 3D height map of the chip package area, including the gold wire and solder joint to be tested; The three-dimensional height map is divided into multiple regions based on the standard gold wire template. The height of the carrier surface corresponding to each region is used as a reference, and a preset threshold increment is superimposed as the segmentation threshold for binarization segmentation. The segmented contours are connected to form a full-span continuous gold wire region of interest. Gold wire defect detection is performed based on the gold wire region of interest to obtain the gold wire defect detection result. A local window containing the solder joint to be tested is defined, and the solid contour of the solder joint to be tested is extracted by segmentation; point defect detection is performed based on the solid contour to obtain the point defect detection result; Based on the attachment carrier type of the solder joint to be tested recorded in the standard gold wire template, the positioning reference area is located, the first height feature value in the solid contour and the second height feature value in the reference area are extracted respectively, the difference between the two is calculated and compared with the process standard thickness to obtain the detection results of root lifting and cold solder joint. Based on the gold wire defect detection results, the dot-shaped defect detection results, and the root lifting and cold solder joint detection results, the overall pass / fail judgment result of the chip packaging area is output.

2. The method according to claim 1, characterized in that, The three-dimensional height map is divided into multiple regions based on a standard gold line template. Binary segmentation is performed by overlaying a preset threshold increment as the segmentation threshold, using the height of the carrier surface corresponding to each region as a reference. Specifically, this includes: The standard gold wire template records the spatial distribution area of ​​each chip on the projection plane, the height value of each chip surface relative to the substrate surface, the expected trajectory coordinates of each gold wire, and the design coordinates and attachment carrier type of each solder joint. After dividing the three-dimensional height map into multiple chip regions and one substrate region on the projection plane according to the standard gold wire template, for any pixel, the corresponding carrier surface height reference value is determined according to the region to which the pixel belongs. and threshold increment Calculate the segmentation threshold If the height value of the pixel If it is, it is determined to be a gold line entity; otherwise, it is determined to be background.

3. The method according to claim 1, characterized in that, Gold wire defect detection is performed on the gold wire under test using the region of interest of the gold wire, specifically including: Align the region of interest of the gold wire with the standard gold wire template in terms of spatial coordinates. Establish a search window within the expected trajectory range of each gold wire recorded in the standard gold wire template. If there is no pixel connected region that meets the segmentation threshold within the search window, it is determined that there are few wires. If there is a pixel connected region that meets the segmentation threshold outside the expected trajectory range, it is determined that there are many wires. Extract the center trajectory lines of each gold wire in the region of interest of the gold wire, and compare the lateral position deviation and angle deviation of the center trajectory lines with the expected trajectory recorded in the standard gold wire template to determine the wire misalignment; Multiple discrete positions are set on the central trajectory line and the highest point of the entire line is determined. The height values ​​of each discrete position and the highest point are extracted respectively. If the height value of any discrete position or the highest point is lower than the corresponding safe height threshold, the collapse is determined.

4. The method according to claim 1, characterized in that, The solid contour of the solder joint to be tested is extracted by segmentation based on a height threshold, including: The height values ​​of all pixels within the local window are statistically analyzed. The set of pixels corresponding to the peaks with lower height values ​​is determined as the background layer. The arithmetic mean of the pixel height values ​​within this set is calculated as the background height reference value. Set the segmentation threshold , For a preset threshold increment, the height value within the local window is greater than or equal to... The pixels that are identified as solder joint entities are determined, and the remaining pixels are determined as background, thus obtaining the physical outline of the solder joint to be tested.

5. The method according to claim 1, characterized in that, A local window containing the solder joint to be tested is defined, and the solid contour of the solder joint to be tested is extracted by multimodal fusion segmentation, including: Obtain a two-dimensional intensity image with the same field of view as the three-dimensional height map. ; The segmentation result obtained by the three-dimensional height map under a loose segmentation threshold is used as a spatial constraint mask. The loose segmentation threshold is lower than the standard segmentation threshold of the corresponding region, so that the area of ​​the spatial constraint mask is larger than the actual area of ​​the solder joint to be tested but smaller than the area of ​​the local window. Within the area defined by the spatial constraint mask, the total energy functional is constructed using the segmentation boundary as a variable: ； in For along the dividing boundary The inverse of the gradient magnitude of the two-dimensional image is integraled along the boundary line. The magnitude of the local gradient in the two-dimensional image; For along the dividing boundary The inverse of the gradient magnitude of the 3D heightmap is integraled along the boundary line. This represents the local elevation gradient magnitude of the 3D height map; and For preset weighting coefficients, The derivative of the arc length along the dividing boundary; Through iterative evolution of the level set method, When the minimum value is reached, the segmentation boundary at this point is taken as the solid contour of the weld point to be tested.

6. The method according to claim 1, characterized in that, The specific method for detecting point defects based on the solid contour is as follows: The actual outer diameter is obtained by performing circle fitting on the solid contour of the weld point to be tested. The circle fitting employs either the minimum circumcircle method or the equivalent area circle fitting method; the actual outer diameter and the gold wire design diameter are calculated. ratio ; Read the client-preset pass / fail ratio range [ ],like If the point shape is deemed unqualified, then it is determined that the shape is not up to standard.

7. The method according to claim 1, characterized in that, The specific method for positioning the reference area is as follows: The standard gold wire template records the type of attachment carrier for each solder joint, and the type of attachment carrier is the chip surface or the substrate surface. When the attachment carrier of the solder joint to be tested is the chip surface, the corresponding flat area of ​​the chip around the solder joint is used as the reference area; when the attachment carrier is the substrate surface, the flat area of ​​the substrate around the solder joint is used as the reference area.

8. The method according to claim 1, characterized in that, The extraction methods for the first height feature value and the second height feature value are as follows: Extract the set of height values ​​of all pixels within the solid outline of the weld point to be tested and the set of height values ​​of all pixels within the reference area. For each of the two sets, calculate the height feature value using any of the following statistical methods: arithmetic mean, median, mode, value at a specified quantile, or weighted average of the remaining pixels after removing outliers that deviate from the mean by more than three standard deviations.

9. A semiconductor bonding wire and solder joint detection system, characterized in that, include: The 3D data acquisition module is used to acquire a 3D height map of the chip package area, which includes the gold wire and solder joint to be tested. The storage module is used to store the standard gold wire template and the qualified ratio range preset by the client; The gold wire segmentation and detection module is used to divide the three-dimensional height map into multiple regions based on the standard gold wire template, and perform binary segmentation by superimposing a preset threshold increment as the segmentation threshold based on the height of the carrier surface corresponding to each region. The segmented contours are connected into a full-span continuous gold wire region of interest, and the gold wire region of interest is used to perform gold wire defect detection and output the gold wire defect detection result. The solder joint segmentation module is used to delineate a local window containing the solder joint to be tested, and extract the solid contour of the solder joint to be tested by height threshold segmentation or multimodal fusion segmentation. The dot shape detection module is used to perform circle fitting on the contour of the entity to obtain the actual outer diameter, calculate the ratio of the actual outer diameter to the design diameter of the gold wire, read the qualified ratio range, and if the ratio does not fall within the qualified ratio range, the dot shape is determined to be unqualified, and the dot shape defect detection result is output. The root detection module is used to locate the reference reference area according to the attachment carrier type of the solder joint to be tested recorded in the standard gold wire template, extract the first height feature value in the solid contour and the second height feature value in the reference reference area respectively, calculate the difference between the two and compare it with the process standard thickness. If the difference is less than the lower limit of the process standard thickness, it is determined that the root is raised or the solder joint is cold, and the detection results of root raised and cold solder joint are output. The judgment output module is used to output the overall pass / fail judgment of the chip packaging area based on the gold wire defect detection results, the dot-shaped defect detection results, and the root lifting and cold solder joint detection results.

10. The detection system according to claim 9, characterized in that, The specific method for detecting gold wire defects using the region of interest in the gold wire segmentation and detection module is as follows: Align the region of interest of the gold wire with the standard gold wire template in terms of spatial coordinates. Establish search windows within the expected trajectory range of each gold wire recorded in the standard gold wire template to determine missing wires. Detect connected components outside the expected trajectory range to determine multiple wires. Extract the center trajectory lines of each gold wire in the region of interest of the gold wire, and compare the lateral position deviation and angular deviation to determine the wire misalignment; set multiple discrete positions on the center trajectory lines and determine the highest point of the entire line, extract the height value and compare it with the corresponding safe height threshold to determine the wire collapse.

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