Wafer defect detection method, device, storage medium and program product

Abstract

The application discloses a wafer defect detection method, device, storage medium and program product, and relates to the technical field of semiconductors. The method comprises the following steps: forming a standard defect pattern in a non-functional area of a target wafer; in response to a defect detection instruction, acquiring a first quantity, a second quantity and a third quantity; for any wafer to be detected, acquiring a fourth quantity, a fifth quantity and a sixth quantity; and based on the quantity of the standard defect pattern, the first quantity, the second quantity, the third quantity, the fourth quantity, the fifth quantity, the sixth quantity and a preset correction model, correcting an estimated quantity of process defect points to obtain a defect detection result of the wafer to be detected. The application improves the accuracy of defect rate estimation and the reliability of yield risk judgment under the condition of sample quantity compression.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to wafer defect detection methods, equipment, storage media, and program products. Background Technology

[0002] In semiconductor manufacturing, wafer defect detection is a crucial step in estimating device yield. Currently, the mainstream defect detection method employs a combination of coarse scanning across the entire wafer surface and precise review through sampling. Specifically, optical inspection equipment first scans the entire wafer surface to identify all potential defects, and then performs preliminary classification based on optical signal intensity and pattern recognition algorithms. Based on this preliminary classification, samples are taken from the potential defect points for review and precise classification. Finally, statistical methods are used to estimate the quantity and distribution of various process defects across the entire wafer, thereby calculating the wafer yield. However, with the continuous increase in semiconductor manufacturing capacity and the ever-increasing production speed requirements, the number of samples in wafer defect detection has been gradually reduced, making it impossible to accurately determine wafer yield and affecting the quality of the finished wafer. Summary of the Invention

[0003] The main objective of this application is to provide a wafer defect detection method, device, storage medium, and program product, which aims to solve the technical problems of inaccurate defect rate estimation and decreased reliability of yield risk assessment in wafer defect detection due to the compression of the number of sampling samples.

[0004] To achieve the above objectives, this application proposes a wafer defect detection method, which includes: Standard defect patterns are formed in the non-functional regions of the target wafer; In response to a defect detection command, a first quantity, a second quantity, and a third quantity are obtained, wherein the first quantity is the number of suspected defect points measured by full-area scanning of the target wafer, the second quantity is the number of sampled defect points obtained by sampling the suspected defect points of the target wafer, and the third quantity is the number of standard defect points among the sampled defect points of the target wafer. For any wafer to be inspected, a fourth quantity, a fifth quantity, and a sixth quantity are obtained, wherein the fourth quantity is the number of suspected defect points measured by full-area scanning of the wafer to be inspected, the fifth quantity is the number of sampled defect points obtained by sampling the suspected defect points of the wafer to be inspected, and the sixth quantity is the number of process defect points among the sampled defect points of the wafer to be inspected. Based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model, the defect detection result of the wafer to be inspected is determined; The step of determining the defect detection result of the wafer to be inspected based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model includes: Calculate the ratio of the sixth quantity to the fifth quantity to obtain the sample proportion of the process defect points; Calculate the product of the fourth quantity and the sample proportion of the process defect points to obtain the estimated number of the process defect points; The estimated number of process defect points is corrected based on the number of standard defect patterns, the first number, the second number, the third number, and the preset correction model to obtain the corrected number of process defect points. The defect detection result is determined based on the corrected number of the process defect points.

[0005] In addition, to achieve the above objectives, this application also proposes a wafer defect detection device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the wafer defect detection method as described above.

[0006] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the wafer defect detection method described above.

[0007] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the wafer defect detection method described above.

[0008] This application forms a standard defect pattern in a non-functional area of ​​a target wafer; in response to a defect detection command, it acquires a first quantity, a second quantity, and a third quantity, wherein the first quantity is the number of suspected defect points measured by a full-area scan of the target wafer, the second quantity is the number of sampled defect points obtained by sampling the suspected defect points of the target wafer, and the third quantity is the number of standard defect points among the sampled defect points of the target wafer; for any wafer to be inspected, it acquires a fourth quantity, a fifth quantity, and a sixth quantity, wherein the fourth quantity is the number of suspected defect points measured by a full-area scan of the wafer to be inspected, the fifth quantity is the number of standard defect points among the sampled defect points of the target wafer, and the sixth quantity is the number of standard defect points among the sampled defect points of the target wafer. The number of sampled defect points obtained by sampling suspected defect points, wherein the sixth quantity is the number of process defect points in the sampled defect points of the wafer to be inspected; the ratio of the sixth quantity to the fifth quantity is calculated to obtain the sample proportion of the process defect points; the product of the fourth quantity and the sample proportion of the process defect points is calculated to obtain the estimated number of process defect points; the estimated number of process defect points is corrected based on the number of standard defect patterns, the first quantity, the second quantity, the third quantity and a preset correction model to obtain the corrected number of process defect points; the defect detection result is determined based on the corrected number of process defect points.

[0009] By pre-setting standard defect patterns in the non-functional areas of the wafer to match the optical detection resolution limit, these standard defect patterns are identified as suspected defect points under the same conditions as actual process defects during the full-area scanning stage. Based on the known number of standard defect patterns, a quantitative relationship between sampling bias and the detection miss rate is established by comparing the total number of suspected defect points output during the full-area scanning stage of the target wafer, the number of defect points extracted during the sampling review stage, and the number of detected standard defect points. The number of process defects detected on the wafer under inspection is then corrected based on this quantitative relationship to obtain the defect detection results. By using standard defect patterns as a known reference in the inspection, and with a compressed sample size, the overall detection bias is estimated by the detection ratio of standard defect patterns, thereby correcting the sampling statistics and improving the accuracy of defect rate estimation and the reliability of yield risk assessment. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating an embodiment of the wafer defect detection method of this application. Figure 2 This is a schematic flowchart illustrating the process of determining the defect detection result provided in Embodiment 1 of the wafer defect detection method of this application. Figure 3 This is a flowchart illustrating Embodiment 3 of the wafer defect detection method of this application; Figure 4 A simplified flowchart illustrating a wafer defect detection method provided in an embodiment of this application; Figure 5 This is a schematic diagram of the equipment structure of the hardware operating environment involved in the wafer defect detection method in this application embodiment.

[0013] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0015] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0016] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or wafer defect detection device capable of performing the above functions. The following description uses a wafer defect detection device as an example to illustrate this embodiment and the subsequent embodiments.

[0017] This application provides a wafer defect detection method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the wafer defect detection method of this application.

[0018] In this embodiment, the wafer defect detection method includes steps S10 to S40: Step S10: Form a standard defect pattern in the non-functional area of ​​the target wafer.

[0019] The surface of a wafer is divided into functional areas and non-functional areas. Functional areas are the regions on the wafer used to cut and form individual chips (dies), and these areas contain circuit structures such as transistors and interconnects. Non-functional areas are the regions on the wafer not used to form circuit chips, including scribe lines, edge exclusion areas, and dummy areas.

[0020] Standard defect patterns are pre-formed defect structures of a predetermined number in the non-functional areas of a wafer. Since the number of standard defect patterns is predetermined, comparing the number of detected standard defect patterns during inspection with this predetermined value quantifies the systematic bias in the inspection process, thus serving as a known benchmark for correcting defect inspection data. The standard defect patterns employ a periodic grating structure, specifically a two-dimensional periodic grating array, with predetermined geometric dimensions, shape, and distribution. The number, type, and spatial distribution of the standard defect patterns are known values, determined before manufacturing through design data, and are not limited here.

[0021] A target wafer is a wafer selected from a wafer batch to set a standard defect pattern, providing baseline data for subsequent inspection and correction. The target wafer can be one or more wafers randomly selected from the same production batch. There are no restrictions on the selection method of the target wafer; for example, it can be randomly selected or wafers at specific locations selected at fixed intervals.

[0022] The dimensions of a standard defect pattern are its line width and spacing in the planar direction, and its height or depth in the vertical direction. The dimensions of the standard defect pattern are matched to the resolution limit of the device performing a full-area scan (hereinafter referred to as the first scanning device for convenience). The resolution limit is the minimum distance between two adjacent features that the first scanning device can distinguish, and it is determined by the light source wavelength, the numerical aperture of the objective lens, and the aberrations of the optical system. The resolution limit can be estimated using the Rayleigh criterion, which will not be elaborated here.

[0023] In this embodiment, the size of the standard defect pattern is on the same order of magnitude as or slightly larger than the resolution limit of the first scanning device. The size of the standard defect pattern cannot be much smaller than the resolution limit; otherwise, the device performing full-area scanning cannot stably identify the standard defect pattern, leading to missed detections. Conversely, the size of the standard defect pattern cannot be much larger than the resolution limit; otherwise, one standard defect pattern may be identified by the first scanning device as multiple scattered defect points, disrupting the one-to-one correspondence between the preset quantity and the detected quantity. In a feasible implementation, the process of determining whether the size of the standard defect pattern matches the resolution limit of the first scanning device can be as follows: obtain the resolution limit value, compare the design size of the standard defect pattern with the resolution limit value, and ensure that the size of the standard defect pattern is within the range that the first scanning device can stably identify. For example, the stably recognizable range is set to be greater than or equal to 1.0 to 1.5 times the resolution limit. If it is within the range, it indicates that the size of the standard defect pattern matches the resolution limit of the first scanning device; otherwise, it indicates a mismatch.

[0024] Standard defect patterns are formed in the non-functional areas of the target wafer. These standard defect patterns employ a periodic grating structure with geometric parameters, material composition, and manufacturing process consistent with the currently manufactured device layers. This ensures that the standard defect patterns generate predictable, high signal-to-noise ratio scattering signals during optical inspection. Specifically, standard defect patterns are set on a mask at positions corresponding to the non-functional areas of the target wafer. These standard defect patterns are two-dimensional periodic grating array structures. The two-dimensional periodic grating array structure adopts an asymmetric misalignment distribution corresponding to the non-functional areas of the target wafer. This asymmetric misalignment distribution refers to the introduction of positional offsets when arranging the standard defect patterns in the non-functional areas of the wafer. This causes the spatial arrangement of the standard defect patterns to deviate from the periodicity of the chip array on the wafer. Consequently, the standard defect patterns do not exhibit periodic matching in die-to-die differential scanning and die-to-database comparisons, ensuring that the standard defect patterns are identified as defects. Standard defect patterns are generated concurrently with the current device layer process, which includes photolithography, etching, electroplating, or chemical mechanical polishing. These processes are performed simultaneously with the device layer process, using the same equipment parameters and materials, eliminating the need for additional masks or separate process steps for the standard defect patterns. Since non-functional regions are not part of the chip circuitry, standard defect patterns do not affect the device's electrical performance. Furthermore, since non-functional regions and functional regions are processed simultaneously in the same step, standard defect patterns accurately reflect the optical response characteristics of the device layer process.

[0025] Step S20: In response to a defect detection command, a first quantity, a second quantity, and a third quantity are obtained, wherein the first quantity is the number of suspected defect points measured by full-area scanning of the target wafer, the second quantity is the number of sampled defect points obtained by sampling the suspected defect points of the target wafer, and the third quantity is the number of standard defect points among the sampled defect points of the target wafer.

[0026] Defect points are the coordinate locations marked by the first scanning device during wafer surface scanning based on abnormal scattered light signals. Suspected defect points are locations initially identified as abnormal by the first scanning device during full-area scanning based on signal strength thresholds and pattern recognition algorithms. Suspected defect points may include actual physical defects, signals generated by standard defect patterns, and some false alarms caused by noise or normal pattern edges. The first quantity is the total number of all suspected defect points identified and recorded by the first scanning device after full-area scanning of the target wafer, representing the total number of abnormal points reported by the first scanning device across the entire target wafer.

[0027] The sampling defect points are specific locations selected from suspected defect points through a sampling process and that need to be sent to the second scanning device for verification. The second quantity is the total number of sampling defect points, representing the sample size sent to the second scanning device for verification. The determination of the second quantity is usually based on statistical sampling theory, considering the population size and confidence level. In this embodiment, the sampling method is not limited; for example, it can be simple random sampling, stratified random sampling, or systematic sampling.

[0028] A standard defect point is a single defect point identified and confirmed as belonging to a standard defect pattern during the verification and inspection process of the second scanning device. A standard defect pattern is a physical structure artificially set in a non-functional area, and a standard defect point is the abnormal coordinate of the physical structure corresponding to the standard defect pattern identified in the inspection data by optical inspection or the second scanning device. Under ideal design conditions, one standard defect pattern corresponds to one standard defect point. The relationship between the number of standard defect points and the number of standard defect patterns depends on the degree of matching between the size design of the standard defect pattern and the resolution of the optical inspection: when the size of the standard defect pattern matches the resolution limit of the first scanning device, the first scanning device identifies each standard defect pattern as an independent standard defect point, and the number of standard defect points equals the number of standard defect patterns; when the size of the standard defect pattern is much smaller than the resolution limit, the number of standard defect points may be less than the number of standard defect patterns; when the size of the standard defect pattern is much larger than the resolution limit, one standard defect pattern may be identified as multiple standard defect points. Therefore, by matching the size of the standard defect pattern to the resolution limit of the first scanning device, a known correspondence between the number of standard defect points and the number of standard defect patterns can be ensured, thus providing an accurate physical basis for the calculation of the correction coefficient. The third quantity is the number of standard defect points that belong to the standard defect pattern after the sampled defect points are checked and verified by the second scanning device. It represents the actual number of standard defect points detected in the sample. The ratio of the third quantity to the second quantity reflects the detection ratio of the standard defect pattern in the sample.

[0029] Obtaining the first, second, and third quantities can be achieved in various ways, and no specific method is limited here. For example, after the first and second scanning devices automatically perform the inspection, the first, second, and third quantities can be directly transmitted to the wafer defect inspection device via a data interface; alternatively, the inspection engineer can read the above quantities from the inspection reports of the first and second scanning devices and input them into the data processing system; still another option is to calculate the above quantities online based on the raw inspection data (such as a defect coordinate list and classification results) output by the first and second scanning devices.

[0030] Step S30: For any wafer to be inspected, obtain a fourth quantity, a fifth quantity, and a sixth quantity, wherein the fourth quantity is the number of suspected defect points measured by full-area scanning of the wafer to be inspected, the fifth quantity is the number of sampled defect points obtained by sampling the suspected defect points of the wafer to be inspected, and the sixth quantity is the number of process defect points among the sampled defect points of the wafer to be inspected.

[0031] The wafer to be inspected is the specific wafer whose defect detection result needs to be determined. The wafer to be inspected and the target wafer belong to the same production batch, undergo the same manufacturing process, and use the same inspection equipment and procedures. The number of wafers to be inspected can be one or more, covering all wafers in the entire batch except the target wafer, or it can include the target wafer itself. A known number of standard defect patterns are formed on the target wafer, used to determine correction coefficients based on the detection results of the standard defect patterns. The fourth, fifth, and sixth defect counts are obtained through the same inspection procedure, and combined with the correction coefficients established for the target wafer, the defect detection result of the wafer to be inspected is determined. Since the target wafer and the wafer to be inspected are in the same inspection batch and are inspected by the same first and second scanning equipment, their inspection conditions, process levels, and system deviations are comparable.

[0032] The fourth quantity is the total number of all suspected defect points identified and recorded by the first scanning device after a full-area scan of the wafer to be inspected. The fourth quantity has the same definition as the first quantity, the difference being that the fourth quantity corresponds to the wafer to be inspected, while the first quantity corresponds to the target wafer; the fourth quantity represents the total number of abnormal points across the entire wafer to be inspected. The fifth quantity is the total number of sampled defect points extracted from the suspected defect points of the wafer to be inspected. The fifth quantity has the same definition as the second quantity, the difference being that the fifth quantity corresponds to the wafer to be inspected, while the second quantity corresponds to the target wafer, representing the sample size sent to the second scanning device for verification inspection.

[0033] Process defects are real physical defects formed on or inside the wafer surface during wafer manufacturing due to factors such as process parameter deviations, equipment status changes, or material inhomogeneities. Process defects include, but are not limited to, bridging defects, particle defects, void defects, and scratch defects. Process defects are unintended and their quantity, location, and type are unknown during manufacturing; standard defect patterns are pre-defined, and their quantity, location, and type are known. The sixth quantity refers to the number of process defect points identified from the sampled defect points of the wafer under inspection after being detected by the second scanning equipment.

[0034] The implementation of obtaining the fourth, fifth, and sixth quantities can refer to the method for obtaining the first, second, and third quantities in step S20, and is not limited thereto.

[0035] Step S40: Based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and the preset correction model, determine the defect detection result of the wafer to be inspected.

[0036] The preset calibration model is a mathematical processing framework that is pre-selected or configured before determining the defect detection results. The specific form of the calibration model is not limited; it can be a linear normalization model, a Bayesian model, a generalized linear regression model, or other statistical models, and can be set according to actual needs.

[0037] The specific method for determining the defect detection results of the wafer under inspection based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model depends on the specific model and is not limited here. It can be that the first, second, and third numbers of the target wafer and the number of standard defect patterns are used to calculate a priori values ​​characterizing the degree of defect detection; the fourth, fifth, and sixth numbers of the wafer under inspection are used to calculate the sample proportion of process defects among the sampled defect points of the wafer under inspection and the estimated number of process defects in the wafer under inspection; the priori values ​​are then adjusted to adjust the sample proportion and estimated number of process defects to obtain the corrected number of process defects in the wafer under inspection. In other words, the standard defect data of the target wafer is used as a benchmark, and systematic bias compensation is applied to the inspection data of the wafer under inspection to obtain a defect quantity estimate that is closer to the true value.

[0038] The defect detection results include at least the corrected number of process defects in the wafer under inspection, the distribution of process defects on the wafer, the defect density calculated based on the corrected number, and the wafer yield grade predicted based on the defect density. These can be set according to actual needs and are not limited here. In one feasible embodiment, process defects include multiple types of defects, and the corrected number of each type of process defect includes the corrected number of bridging defects, the corrected number of particle defects, the corrected number of void defects, etc.

[0039] In one feasible embodiment, the sixth quantity is the quantity of each type of process defect point. The sixth quantity is a set of data containing multiple values, each value corresponding to the detection quantity of a type of process defect. For example, the sixth quantity may include the quantity of bridging defect points, the quantity of particle defect points, and the quantity of void defect points.

[0040] In this embodiment, please refer to Figure 2 Step S40, which involves determining the defect detection result of the wafer to be inspected based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model, includes: Step S401: Calculate the ratio of the sixth quantity to the fifth quantity to obtain the sample proportion of process defect points.

[0041] The fifth quantity is the total number of sampled defects on the wafer to be inspected, i.e., the total number detected by the second scanning device; the sixth quantity is the number of process defects among the sampled defects on the wafer to be inspected, i.e., the total number of process defects confirmed by the second scanning device. Dividing the sixth quantity by the fifth quantity yields the sample proportion of process defects, that is, the proportion of process defects among the sampled defects on the wafer to be inspected to the total number of sampled defects on the wafer to be inspected.

[0042] In one feasible implementation, the sixth quantity includes multiple values, each corresponding to a type of process defect. For each type of process defect, the quantity of that type of process defect is divided by the fifth quantity to obtain the sample proportion of that type of process defect in the sampled defect points. That is, the proportion of a certain type of process defect to the total number of sampled defect points is calculated. For example, the sixth quantity may include the number of bridging defects, the number of particle defects, and the number of void defects. The number of process defects is a specific value for a certain type of process defect in the sixth quantity. For example, if 10 bridging defects are identified in the sampled defect points, then the number of bridging defects is 10.

[0043] Step S402: Calculate the product of the fourth quantity and the sample proportion of process defect points to obtain the estimated number of process defect points.

[0044] The fourth quantity is the total number of suspected defect points obtained after a full-area scan of the wafer to be inspected, that is, the total number of locations marked as abnormal by the first scanning device within the entire area of ​​the wafer to be inspected.

[0045] Multiplying the fourth quantity by the sample proportion of process defects yields an estimated number of process defects in the wafer under inspection. In other words, the estimated number of process defects is the total estimated number of process defects on the entire wafer under inspection, obtained through extrapolation from the sample proportion. Assuming the sample is representative, the total number of defects in the population is approximately equal to the population size multiplied by the defect proportion in the sample. The fourth quantity represents the population size (total number of suspected defects on the entire wafer), and the sample proportion of process defects represents the defect proportion. Multiplying the two yields a preliminary estimate of the number of this type of process defect across the entire wafer under inspection.

[0046] In one feasible implementation, the sixth quantity includes the quantity of each type of process defect. For each type of process defect, the estimated quantity of that type of process defect in the wafer to be inspected is determined by the quantity of that type of process defect, the fifth quantity, and the fourth quantity. Specifically, for the i-th type of process defect in the sixth quantity, the ratio of the quantity of the i-th type of process defect to the fifth quantity is first calculated to obtain the sample proportion of the i-th type of process defect; then, the product of the fourth quantity and the sample proportion of the i-th type of process defect is calculated to obtain the estimated quantity of the i-th type of process defect in the wafer to be inspected. Taking the sixth quantity, which includes the number of bridging defects, particle defects, and void defects, as an example, if the fifth quantity is 100, the fourth quantity is 1000, and the number of bridging defects, particle defects, and void defects are 20, 30, and 10 respectively, then the sample proportion of bridging defects is 0.2, and the estimated number of bridging defects is 200; the sample proportion of particle defects is 0.3, and the estimated number of particle defects is 300; and the sample proportion of void defects is 0.1, and the estimated number of void defects is 100. The estimated number of each type of process defect represents the estimated total number of each type of process defect on the entire wafer under inspection, collectively constituting a classification estimate of the overall process defect status of the wafer under inspection, providing input for subsequent correction of each type of process defect.

[0047] Step S403: Based on the number of standard defect patterns, the first number, the second number, the third number, and the preset correction model, the estimated number of process defect points is corrected to obtain the corrected number of process defect points.

[0048] The number of standard defect patterns is the total number of standard defect patterns preset on the non-functional area of ​​the target wafer. The above number is a known preset value.

[0049] By utilizing the deviation between the known values ​​of standard defect patterns and the estimated detection values, the degree of systematic bias in the first scanning device is quantified. This systematic bias is then applied to compensate for the estimated number of process defects in the wafer under inspection. Specifically, a first quantity, a second quantity, and a third quantity are used to calculate the detection bias of the first scanning device for standard defects: the ratio of the third quantity to the second quantity reflects the detection proportion of standard defects in the sample; the product of the first quantity and the aforementioned detection proportion reflects the estimated number of standard defects across the entire target wafer; and the ratio of the number of standard defect patterns to the aforementioned estimated number reflects the degree of systematic bias. A pre-defined correction model uses this degree of bias to correct the estimated number of process defects in the wafer under inspection, resulting in a corrected number of process defects in the wafer under inspection that is closer to the true value.

[0050] In one feasible embodiment, the sixth quantity includes the quantity of each type of process defect among the sampled defect points of the wafer to be inspected. The estimated quantity of each type of process defect is corrected based on a preset correction model to obtain the corrected quantity of each type of process defect in the wafer to be inspected. For example, the estimated quantity of bridging defects, particle defects, and void defects are corrected separately to obtain the corrected quantity of bridging defects, particle defects, and void defects. For a specific classification and correction process, please refer to the feasible embodiment of step S4031.

[0051] Step S404: Determine the defect detection result based on the corrected number of process defect points.

[0052] The corrected number of process defects is the number of process defects in the wafer under inspection after correction. In one feasible embodiment, process defects can include multiple types, and the corrected number of process defects can include the number of each type of process defect. The numbers of each type of defect after system bias compensation are summarized to form a complete assessment of the wafer defect status, i.e., the defect detection result. The defect detection result includes, but is not limited to: the corrected number of each type of process defect, the distribution of each type of process defect on the wafer under inspection, the defect density calculated based on the corrected number, and the wafer yield grade predicted based on the defect density. The defect detection result can be output in the form of a data report or electronic data to guide wafer grading, process adjustment, or equipment maintenance.

[0053] In this embodiment, by extending the sampling statistical results from the sample space to the global space, and by constraining and correcting the extended results using the known number of standard defect patterns, the defect detection results maintain statistical reliability even when the number of sampling samples is compressed.

[0054] In one feasible embodiment, step S10, the step of forming a standard defect pattern in the non-functional area of ​​the target wafer, includes: Step S101: Set a standard defect pattern on the mask at the position corresponding to the non-functional area of ​​the target wafer. The standard defect pattern is a two-dimensional periodic grating array structure with an asymmetric misalignment distribution.

[0055] Standard defect patterns are set on the mask in the area corresponding to the non-functional area of ​​the wafer, eliminating the need for a separate mask for standard defect patterns.

[0056] By using asymmetric misalignment distribution, the arrangement of standard defect patterns formed in the non-functional area of ​​the wafer does not follow the periodicity of the chip array on the wafer. This arrangement artificially introduces positional offset, so that the standard defect patterns are not recognized as the periodic repeating structure of normal chip patterns in die-to-die differential scanning and die-to-database comparison.

[0057] In step S102, the standard defect pattern of the mask is transferred to the non-functional area of ​​the target wafer through the device layer process performed by the semiconductor process equipment to form a standard defect pattern.

[0058] Device layer processes are specific process steps currently being performed during wafer manufacturing, such as photolithography, etching, thin film deposition, or chemical mechanical polishing of metal layers.

[0059] The standard defect pattern and the device layer structure are formed simultaneously in the same process step, without adding any additional dedicated process steps. In the photolithography step, the lithography machine exposes the wafer through a mask, simultaneously transferring the device layer pattern and the standard defect pattern to the photoresist layer on the wafer surface. In the etching step, the etching equipment simultaneously etches the device layer area and the standard defect area, transferring the photoresist pattern to the underlying material layer. In the thin film deposition step, the deposition equipment deposits the same material across the entire wafer, resulting in the same film quality for both the device layer area and the standard defect area. In the chemical mechanical polishing (CMP) step, the polishing equipment planarizes the entire wafer, with the device layer and the standard defect pattern undergoing the same polishing conditions simultaneously. Through synchronous transfer, the standard defect pattern is composed of the same material as the current device layer, possessing the same optical response characteristics and surface morphology as the device layer structure. No additional process steps are required; once formed, the standard defect pattern becomes the physical structure on the non-functional area of ​​the wafer, serving as a known benchmark in subsequent inspections.

[0060] In one feasible embodiment, step S20, the step of obtaining the first quantity, the second quantity, and the third quantity, includes: Step S201: Perform a full-area scan on the target wafer using the first scanning device to identify and record the number of suspected defect points on the target wafer as the first quantity.

[0061] The first scanning device is an automated inspection device used to scan the entire surface of a wafer for defects. The specific type of the first scanning device is not limited; it can be an optical inspection device based on the principle of laser scattering, a bright-field or dark-field inspection device based on the principle of image comparison, or other types of surface inspection instruments. The core function of the first scanning device is to rapidly scan the entire wafer and identify suspected defect locations with abnormal signals.

[0062] Specifically, performing a full-area scan on a target wafer can involve placing the target wafer in a first scanning device, which scans the entire surface of the target wafer line by line according to a preset scanning path, collecting surface scattered light signals or image data. A signal processing algorithm identifies all abnormal locations where the signal intensity exceeds a threshold, marking these abnormal locations as suspected defects. The total number of these suspected defects is then counted and recorded as a first quantity. The implementation process does not limit the specific scanning speed, light source wavelength, or signal processing algorithm; these can be set according to actual needs.

[0063] Step S202: According to the random sampling principle, defect points are selected from the suspected defect points of the target wafer as sampled defect points, and the number of sampled defect points on the target wafer is recorded as the second quantity.

[0064] After the full-area scan is completed, from the list of all suspected defect points corresponding to the first quantity, a portion of suspected defect points are selected according to the random sampling principle. These selected suspected defect points are marked as sampled defect points, and the number of these sampled defect points is counted and recorded as the second quantity. The random sampling principle requires that the sample be determined from all suspected defect points obtained from the full-area scan using a simple random sampling method. That is, each suspected defect point has an equal probability of being selected, the sampling process is not affected by human factors, and it avoids preferential selection of defect points with strong signals or defect points in specific areas.

[0065] In one feasible embodiment, the random sampling principle conforms to a hypergeometric distribution, that is, the total number of chips formed from the wafer is N, and n chips are randomly selected from the above N chips as sampling chips. The sampled n chips include K suspected defect points, that is, the number of sampled defect points is K, and the defect rate k follows a hypergeometric distribution:

[0066] The hypergeometric distribution describes the probability distribution of the number of successful items in a sample when sampling without replacement in a finite population. Based on this law, the defect rate in the sample can be used as a statistical estimate of the overall defect rate. The extrapolation of the sample proportion to the overall proportion has a mathematical basis. Therefore, it is statistically reasonable and predictable to sample defect points from suspected defect points according to the principle of random sampling and estimate the total number of defects in the whole film by the proportion of each type of defect in the sample.

[0067] Step S203: The sampling defect points of the target wafer are re-inspected by the second scanning device. The number of standard defect points is identified and recorded from the sampling defect points of the target wafer as the third quantity.

[0068] The second scanning device is an inspection device used for verifying imaging and fine classification of sampled defect points. The second scanning device can be a scanning electron microscope, a transmission electron microscope, or other electron beam imaging equipment.

[0069] The sampled defect points are sent to the second scanning device, which images each sampled defect point to obtain a clear defect morphology image. Through image analysis, it is determined whether each sampled defect point belongs to the standard defect point generated by the standard defect pattern. The number of standard defect points is counted and recorded as the third quantity.

[0070] The first scanning device is an optical scanner, which rapidly scans the entire wafer based on optical scattering signals, providing wide coverage for quickly detecting suspected defects. The second scanning device is an electronic scanner, which uses signals generated by the interaction of an electron beam with the wafer surface to image and verify sampled defect points point by point, confirming the authenticity of defects and accurately classifying them. The optical scanner is fast and can cover the entire wafer, but it has a false alarm rate and cannot accurately detect defects or distinguish defect types. The electronic scanner is slower and can only process a small number of samples, but it provides finer imaging and can accurately identify defect types and standard defect points. Using these two devices in conjunction improves detection accuracy while maintaining efficiency.

[0071] In this embodiment, by using standard defect patterns as known references for detection, and with the sample size compressed, the overall detection deviation can be estimated by the detection ratio of standard defect patterns, thereby correcting the sampling statistics and improving the accuracy of defect rate estimation and the reliability of yield risk assessment.

[0072] Based on the above embodiments of this application, in the second embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter. In addition, the sixth quantity includes the quantity of each type of process defect point among the sampled defect points of the wafer to be inspected; the estimated quantity of process defect points includes the estimated quantity of each type of process defect point. Step S403, which involves correcting the estimated number of process defect points based on the number of standard defect patterns, the first number, the second number, the third number, and a preset correction model to obtain the corrected number of process defect points, includes: Step S4031: For each type of process defect point, the estimated number of each type of process defect point is corrected based on the number of standard defect patterns, the first number, the second number, the third number, and the preset correction model, so as to obtain the corrected number of each type of process defect point.

[0073] In this embodiment, the sixth quantity includes the quantity of each type of process defect. The sample proportion is calculated and extrapolated for each type of process defect. The estimated quantity of process defect includes the estimated quantity of each type of process defect in the wafer to be inspected, such as the estimated quantity of bridging defects, particle defects, and void defects. The specific calculation process of the estimated quantity of each type of process defect is described in step S402, and will not be repeated here.

[0074] For each type of process defect, based on the estimated number of such defects in the wafer under inspection, the number of standard defect patterns, and the first, second, and third quantities, a pre-set correction calculation of the pre-set correction model is performed independently to obtain the corrected number of such process defects in the wafer under inspection. The correction processes for each type of process defect do not affect each other. The specific correction logic depends on the form of the pre-set correction model and is not limited here.

[0075] For example, in one feasible implementation, when the preset correction model is the first correction model, all types of process defects share the same correction coefficient. That is, the ratio of the number of standard defect patterns to the estimated number of standard defect points in the entire target wafer is used as the correction coefficient. The correction coefficient is multiplied by the estimated number of each type of process defect point in the wafer to be inspected to obtain the corrected number of each type of process defect point in the wafer to be inspected. This implementation is applicable to situations where the influence of the system deviation of the wafer defect inspection equipment on the degree of various process defects is homogeneous and proportional. In another feasible implementation, when the preset correction model is the second correction model, a prior distribution is established for each type of process defect, a likelihood function is constructed, and a posterior probability distribution is calculated. The expected value of the posterior probability distribution of the number of each type of process defect in the wafer to be inspected is used as the corrected number of each type of process defect point. The corrected number of each type of process defect point is allowed to have different correction ranges. This implementation is applicable to situations where the influence of the system deviation on various process defects is heterogeneous. Using the numerical example above, if the correction factor is 1.25, the corrected number of bridging defects is 250, the corrected number of particle defects is 375, and the corrected number of void defects is 125. The corrected number of various process defects in the wafer under inspection together constitutes the defect detection result of the wafer under inspection, which is used to classify and calculate the defect density of various process defects and predict the wafer yield level.

[0076] In one feasible embodiment, step S403, which involves correcting the estimated number of process defect points based on the number of standard defect patterns, the first number, the second number, the third number, and a preset correction model to obtain the corrected number of process defect points, includes: Step S4032: If the wafer to be inspected meets the preset homogeneity condition, then the correction coefficient is determined based on the number of standard defect patterns, the first number, the second number and the third number. The estimated number of process defect points is corrected by the correction coefficient and the preset first correction model to obtain the corrected number of process defect points. The first correction model is a multiplicative correction statistical model.

[0077] The homogeneity condition means that the impact of systematic deviations in wafer defect detection equipment on process defects is homogeneous and proportional. Under the same detection conditions and the same process level, the false negative rate, sampling deviation, and systematic error of process defects are proportionally related. When the homogeneity condition is met, the detection sensitivity of the central and edge regions of the wafer is basically the same, and the generation mechanism and distribution characteristics of process defects do not show significant regional differences.

[0078] The homogeneity condition is essentially a determination of the nature of the deviation of the first scanning device. When parameters such as the light source intensity, lens cleanliness, and algorithm threshold of the first scanning device drift, the impact of these drifts on all defects is uniform and proportional. In this case, the system deviation is homogeneous. For example, a 10% attenuation of the light source leads to a 10% reduction in the detection signal of standard defects, while the detection signals of particulate defects and bridging defects also decrease by about 10%. Conversely, if bridging defects are severely missed in the central area due to optical aberrations, while particulate defects are severely missed in the edge area due to uneven coating, then the system deviation is not homogeneous.

[0079] The method for determining whether a wafer under inspection meets the preset homogeneity conditions is not limited here. For example, an inspection engineer can input the homogeneity judgment result based on the empirical patterns of historical inspection data; alternatively, it can be automated using a first scanning device. In one feasible embodiment, the process of automated judgment using the first scanning device can be as follows: if the difference in the detection rate of standard defects between the center area and the edge area of ​​any wafer is less than a preset threshold, and the detection ratio of various process defects in historical inspection data fluctuates little with batches, then the homogeneity conditions are deemed to be met. Conversely, if any of the above conditions are not met, then the homogeneity conditions are deemed not to be met.

[0080] If the wafer to be inspected meets the preset homogeneity condition, the detection deviation of the first scanning device for process defects can be corrected using the same proportional coefficient, meaning the missed detection ratio of standard defects is the same as the missed detection ratio of process defects. In this case, the correction coefficient calculated from the standard defect pattern can be directly applied to the estimated number of process defects without needing to establish a separate correction model for each type of defect. Therefore, in this embodiment, the first correction model is a statistical model that proportionally corrects the estimated number of defects using multiplication operations. The specific form of the first correction model is not limited; feasible models include, but are not limited to, linear normalization models and scaling models. For example, a linear normalization model multiplies the estimated number of process defect points in the wafer to be inspected by a correction coefficient to obtain the corrected number of process defect points in the wafer. The core feature of the first correction model is that it uses a single correction coefficient to proportionally correct all types of defects, making it suitable for scenarios where system deviations are homogeneous.

[0081] A correction coefficient is determined based on the number of standard defect patterns, a first quantity, a second quantity, and a third quantity. This correction coefficient, along with a preset first correction model, is used to correct the estimated number of process defects in the wafer under inspection, resulting in a corrected number of process defects. Specifically, the ratio of the third quantity to the second quantity reflects the detection ratio of standard defects in the sample. The product of the first quantity and the aforementioned ratio reflects the estimated number of standard defects across the entire target wafer. The ratio of the number of standard defect patterns to the aforementioned estimated number is the correction coefficient. A correction coefficient greater than 1 indicates that some defects were not identified by the first scanning device; a coefficient less than 1 indicates that the first scanning device identified non-defects as defects. Multiplying the correction coefficient by the estimated number of process defects in the wafer under inspection compensates for system bias, yielding a corrected number of process defects in the wafer under inspection that is closer to the true value.

[0082] Step S4033: If the wafer to be inspected does not meet the homogeneity condition, the corrected number of process defect points is determined based on the number of standard defect patterns, the sixth number, and the preset second correction model. The second correction model is a statistical model based on Bayes' theorem.

[0083] If the wafer under inspection does not meet the homogeneity condition, it indicates that the detection deviation of the first scanning equipment for process defects is heterogeneous. That is, different regions or different types of defects have different missed detection mechanisms. For example, optical aberrations in the central area lead to severe missed detection of small-sized particle defects, while uneven coating thickness in the edge area leads to severe missed detection of bridging defects. In this case, a uniform correction coefficient cannot be used to correct all defects. It is necessary to establish a probability model for each type of defect, that is, to establish a second correction model for each type of process defect. The second correction model is a statistical model based on Bayes' theorem, i.e., a Bayesian model.

[0084] In this embodiment, the specific form of the Bayesian model is not limited; feasible models include the Naive Bayesian model, the Bayesian network model, and the Markov chain Monte Carlo model. The core feature of the Bayesian model is that it uses the defect estimate without standard defect constraints as the prior distribution, the probability characteristics of the detection equipment as the likelihood function, and the known number of standard defect patterns as a hard constraint. It then calculates the posterior probability distribution using Bayes' theorem to obtain a probabilistic estimate of the number of defects.

[0085] The corrected number of process defects in the wafer under inspection is determined based on the number of standard defect patterns, the sixth quantity, and a pre-defined second correction model. A prior distribution of the true number of process defects in the wafer under inspection is established based on the number of standard defect patterns and confidence weights. This prior distribution reflects an initial estimate of the true number of process defects based on prior information determined by the number of standard defect patterns before the current inspection data is observed. A likelihood function is constructed based on the sixth quantity, representing the probability of observing the sixth quantity through sampling verification given a determined true number of process defects in the wafer under inspection. Based on Bayes' theorem, the posterior probability distribution of the true number of process defects in the wafer under inspection is calculated using the likelihood function and the prior distribution. The expected value of the posterior probability distribution is taken as the corrected number of process defects in the wafer under inspection. The specific correction process depends on the form of the second correction model and is not limited here.

[0086] By determining whether the wafer under test meets the homogeneity condition, a first correction model with multiplicative correction is adopted when the influence of system deviation on process defects is homogeneous and proportional. When the homogeneity condition is not met, a second correction model based on Bayes' theorem is adopted. This makes the correction method adaptable to the actual defect distribution characteristics of the wafer, avoids the systematic deviation of a single correction model under different defect distribution scenarios, and improves the applicability of the correction model to different types of wafers.

[0087] In one feasible embodiment, the first correction model is a linear normalized model. Step S4032, which involves determining correction coefficients based on the number of standard defect patterns, the first number, the second number, and the third number, and correcting the estimated number of process defect points using the correction coefficients and the preset first correction model, includes: Step S40321: Calculate the ratio of the third quantity to the second quantity, which is used as the sample proportion of standard defect points.

[0088] The second quantity is the total number of sampled defects on the target wafer, i.e., the total number of samples sent to the second scanning device for inspection. The third quantity is the number of standard defects among the sampled defects on the target wafer. By dividing the third quantity by the second quantity, the result represents the proportion of standard defects in the sample. For example, if the second quantity is 50 and the third quantity is 10, then the proportion of standard defects in the sample is 0.2.

[0089] Step S40322: Based on the first quantity and the sample proportion of standard defect points, determine the estimated quantity of standard defect points.

[0090] The first quantity is the total number of suspected defects after a full-area scan of the target wafer. Multiplying the first quantity by the sample proportion of standard defects yields an estimated number of standard defects across the entire target wafer.

[0091] Step S40323: Calculate the ratio between the number of standard defect patterns and the estimated number of standard defect points, and use it as a correction coefficient.

[0092] The correction coefficient is obtained by dividing the number of standard defect patterns by the estimated number of standard defect points across the entire target wafer. The number of standard defect patterns is a set value, while the estimated number of standard defect points across the entire target wafer is calculated based on the numbers detected by the first and second scanning devices. The ratio between the two values ​​quantifies the degree of detection deviation of the first scanning device in detecting standard defects. A correction coefficient less than 1 indicates that the first scanning device identifies non-defects as defects, while a coefficient greater than 1 indicates that the first scanning device fails to detect some defects.

[0093] Step S40324: Input the correction coefficient and the estimated number of process defects into the linear normalization model, and scale the estimated number of process defects using the correction coefficient to obtain the corrected number of process defects.

[0094] Under the same testing conditions, the detection deviation of the first scanning device for standard defects is the same as its detection deviation for process defects. Therefore, the correction coefficient for standard defects can be used to correct the estimated number of process defects in the wafer under test, compensating for the system bias of the first scanning device. Specifically, the correction coefficient is multiplied by the estimated number of process defects in the wafer under test to obtain the corrected number of process defects in the wafer under test.

[0095] By scaling the estimated number of process defects using a linear normalization model, the deviation between the known number and the estimated number of standard defect patterns is used to directly quantify the missed detections and sampling bias of the detection system. The deviation is then transferred to the estimated number of process defects through linear scaling. Compared to correcting for each type of process defect, this embodiment improves the efficiency and accuracy of wafer defect detection.

[0096] In one feasible embodiment, the second correction model is a Bayesian model, and step S4033, the step of determining the corrected number of process defect points based on the number of standard defect patterns, the sixth number, and the preset second correction model, includes: Step S40331: Establish a prior distribution of the true number of process defect points based on the number of standard defect patterns and the confidence weight, wherein the confidence weight represents the confidence level of prior information determined by the number of standard defect patterns used to estimate the true number of process defect points.

[0097] The prior distribution is an initial estimate of the true number of process defects in the wafer to be inspected before the current inspection data is observed. A prior distribution of the true number of process defects is established based on the number of standard defect patterns and confidence weights. The number of standard defect patterns determines the known sample size upon which the prior distribution is based, while the confidence weights adjust the influence of the prior information determined by the number of standard defect patterns in subsequent Bayesian updates. Prior pseudo-counts can be determined based on the confidence weights and the number of standard defect patterns. A larger confidence weight indicates a stronger influence of the prior distribution on subsequent correction results; a smaller confidence weight indicates a stronger influence of subsequent observational information obtained from sampling inspection results on the correction results.

[0098] In one feasible implementation, the actual process defects of the wafer to be inspected include multiple types of process defect points. Let the actual number of each type of process defect point in the wafer to be inspected be N = (N1, N2, ..., N...). k Assuming the sampling process follows a multivariate hypergeometric distribution without replacement, the prior distribution is a Dirichlet-Multinomial conjugate prior distribution: P(N)~Dirichlet-Multinomial(N,α1,α2,…,α k ) Among them, the prior pseudo-count α of the k-th type of process defect point k =c·Nstd, where Nstd is the number of standard defect patterns and c is the confidence weight. The confidence weight characterizes the reliability of using prior information determined by the number of standard defect patterns to estimate the true number of process defects in the wafer under inspection. The larger c is, the higher the reliability of the above prior information, and the higher the weight of the prior distribution in the Bayesian update; the smaller c is, the more the posterior probability distribution is determined by the likelihood function constructed based on the sixth quantity.

[0099] Step S40332: Construct a likelihood function based on the sixth quantity, where the likelihood function represents the probability of observing the sixth quantity given that the actual number of process defect points is determined.

[0100] In Bayesian statistics, the likelihood function represents the probability of observing the current sampled verification data (i.e., the sixth number) given the true number of process defects in the wafer under inspection. The likelihood function is constructed by using the number of process defects identified in the sampled defect points as the overall observation result. Given that sampling inspection has been completed, the larger the true number of process defects across the entire wafer under inspection, the higher the probability of observing more process defects in the sampled defect points; conversely, the smaller the true number of process defects across the entire wafer under inspection, the higher the probability of observing fewer process defects in the sampled defect points. Therefore, the likelihood function reflects the correspondence between the true number across the entire wafer under inspection and the sixth number observed in the sampling.

[0101] In one feasible implementation, the actual process defects of the wafer to be inspected include multiple types of process defect points. Assume that n samples are drawn without replacement from the total defect population of the wafer to be inspected, and the number of each type of process defect point in the samples is n = (n1, n2, ..., nn). k If the likelihood function P(n|N) is described by a Dirichlet-Multinomial distribution, then the likelihood function is established based on the statistical regularities of the sampling verification process. It does not restrict the specific probability distribution form and can be set according to actual needs.

[0102] Step S40333: Based on Bayes' theorem, calculate the posterior probability distribution of the true number of process defects according to the likelihood function and the prior distribution, and use the expected value of the posterior probability distribution as the corrected number of process defects.

[0103] The likelihood function and prior distribution are input into the Bayesian model, and a probability update operation is performed according to Bayes' theorem to obtain the posterior probability distribution of the true number of process defects in the wafer to be inspected. The posterior probability distribution is proportional to the product of the likelihood function and the prior distribution. When the influence of the prior distribution is strong, the corrected number is closer to the prior estimate determined by the number of standard defect patterns; when the influence of the prior distribution is weak, the corrected number is closer to the sampling observation result reflected by the sixth quantity.

[0104] In this embodiment, the specific numerical algorithm is not limited; it can be analytical solution, numerical integration, or Markov chain Monte Carlo sampling, and can be set according to actual needs. The posterior probability distribution is the probability distribution of the true number of process defect points in the wafer to be inspected taking various possible values ​​after combining prior information determined by the number and confidence weight of standard defect patterns and sampled observation data determined by the sixth quantity. The sampled observation data and the above-mentioned prior information are used together for Bayesian update, so the variance of the posterior probability distribution is usually smaller than that of the prior distribution, and the uncertainty is reduced.

[0105] Statistical features are extracted from the posterior probability distribution, and its expected value is calculated. This expected value is used as a point estimate of the true number of process defects in the wafer under inspection. The expected value represents the optimal estimate of the true number of process defects in the wafer under inspection after considering all available information. For example, if the posterior probability distribution shows that the probability of the true number of process defects in the wafer under inspection is 0.3 (100), 0.5 (101), and 0.2 (102), then the expected value is 100.9. This value, rounded down or retained as a decimal, is used as the corrected number of process defects in the wafer under inspection.

[0106] By establishing a prior distribution based on the number of standard defect patterns, constructing a likelihood function based on sampled verification data, and then obtaining the posterior probability distribution through a Bayesian model, the expected value is used as the corrected number of process defect points in the wafer to be inspected. When the defect distribution does not satisfy the homogeneity assumption, Bayesian inference is used to integrate the prior knowledge of standard defect patterns and actual inspection data, so that the correction results still have statistical robustness when the defect distribution is complex or the sample size is limited.

[0107] Based on the above embodiments of this application, in the third embodiment of this application, the content that is the same as or similar to the above embodiments can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 3 After step S40, which determines the defect detection result of the wafer to be inspected based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and the preset correction model, the method further includes: Step S50: Obtain the actual detection data of the current batch of wafers, wherein the actual detection data includes data detected in at least one step of wafer defect detection.

[0108] Actual detection data refers to the data actually collected and recorded from one or more stages of the wafer defect detection process during the current batch of wafers. Actual detection data is the raw data output by the detection equipment after actual operation or data that has undergone preliminary processing. The content of actual detection data is not limited in specific form; for example, it may include a list of suspected defect point coordinates and signal strengths reported by the first scanning device in the full-area scanning stage, defect images and classification results captured by the second scanning device in the sampling verification stage, the number and location distribution of standard defect points, and the number and type identification of process defect points. Actual detection data may also include auxiliary information such as detection time, equipment number, and process batch number.

[0109] After the current batch of wafers undergoes the testing process, the data processing system extracts data generated from one or more steps from the first scanning device, the second scanning device, or the testing database.

[0110] Step S60: Add the actual detected data to the observation set, update the model parameters of the calibration model based on the observation set, and obtain the updated calibration model.

[0111] An observation set is a collection of data used to store and accumulate historical inspection data. The observation set includes actual inspection data from the current batch and all previous batches of wafers, and may also include historical inspection data from wafers at different process layers. Historical inspection data includes defect type, quantity, and location information. The data structure of the observation set is not limited to any specific form; it can be a table in a database, a data file in a file system, or a data array in memory.

[0112] The actual detected data of the current batch is appended to the existing observation set, increasing the data volume of the observation set. The appending operation includes, but is not limited to, data format conversion, data cleaning, and data alignment, ensuring that the new data is consistent with the historical data in terms of field definitions and units.

[0113] The model parameters of the calibration model are updated based on the observation set to obtain the updated calibration model. The specific update process is set according to the form of the calibration model and is not restricted here.

[0114] In one feasible implementation, if the preset correction model is a first correction model, which is a linear normalized model, and the core parameter of the first correction model is the correction coefficient, during the update, the data processing system extracts the first, second, and third quantities of target wafers from multiple batches in the observation set, recalculates the sample proportion of standard defect points and the estimated number of standard defect points, and then calculates the correction coefficient. Since the observation set contains data from multiple batches, the calculation can use a rolling average or a weighted average method, so that the correction coefficient reflects the long-term drift trend of the first scanning device rather than a single fluctuation. The updated correction coefficient is applied to the defect detection of the next batch of wafers.

[0115] In another feasible implementation, if the preset correction model is a second correction model, which is a Bayesian model, the core parameters of the second correction model include the parameters of the prior distribution (e.g., confidence weights and prior pseudo-counts of various process defects) and the parameters of the likelihood function. During the update, the data processing system extracts the detection records and sampling verification records of multiple batches of standard defect points from the observation set, uses the posterior probability distribution calculated for the current batch as the prior distribution for the next batch of detection, and repeats the Bayesian update step. As the amount of data in the observation set increases, the estimation accuracy of the probability parameters improves, and the variance decreases. Simultaneously, the parameters of the prior distribution can also be updated using maximum likelihood estimation or moment estimation of historical data. The updated prior distribution and likelihood function are applied to the Bayesian probability update of the next batch of wafers.

[0116] Step S70: Based on the updated calibration model, perform wafer defect detection on the next batch of wafers.

[0117] After the calibration model parameters are updated, the updated calibration model replaces the original preset calibration model, and the wafer defect detection process is performed on subsequent production batches of wafers. Specifically, when the next batch of wafers enters the inspection station, the data processing system calls the updated calibration model and uses the updated calibration coefficients (in the case of the first calibration model) or the updated prior distribution and likelihood function (in the case of the second calibration model) to process the first, second, third, fourth, fifth, and sixth quantities of wafers obtained in the next batch to determine the defect detection results of the next batch of wafers.

[0118] After determining the defect detection results, the actual detection data of the current batch of wafers is obtained and the sampled detection data is added to the observation set. The model parameters of the calibration model are updated based on the observation set. Then, the next batch of wafers is tested based on the updated calibration model. This allows the calibration model to be continuously optimized according to the actual detection data, gradually reducing the calibration deviation caused by equipment drift or process changes, and improving the accuracy and stability of defect detection in subsequent batches of wafers.

[0119] In one feasible embodiment, step S60, the step of adding the actual detected data to the observation set, includes: Step S601: Remove abnormal data from the actual detected data and add the processed actual detected data to the observation set; wherein, the abnormal data includes wafer sample data in the sampled defect points where standard defect points were not detected, and detection data of wafers whose full-domain scan was not completed and was abnormally terminated.

[0120] Abnormal data refers to detection data that cannot reflect the statistical regularity under normal detection conditions. Adding abnormal data to the observation set will cause systematic bias in the model parameters of the correction model updated based on the observation set. Therefore, it needs to be removed before the actual detected data is added to the observation set. In this embodiment, abnormal data includes two categories: The first category of abnormal data is wafer sample data in which no standard defect points were detected in the sampled defect points. The standard defect pattern is formed in the non-functional area of ​​the wafer and its number is known. Under normal detection conditions, it is a high-probability event to detect standard defect points in the sampled defect points. If no standard defect point is detected in the sampled defect points of a wafer, it indicates that there is a serious abnormality in the detection process of the wafer. For example, the sampling range does not cover the non-functional area, the signal acquisition of the full-area scan is faulty, or the sampling review is not performed normally. This type of wafer sample data cannot reflect the normal detection statistical regularity and cannot be used to update the correction model parameters. The second type of abnormal data is the inspection data of wafers that were abnormally terminated due to incomplete full-domain scanning. When full-domain scanning is abnormally terminated, the first quantity is only the number of suspected defect points in a part of the wafer. Using the incomplete first quantity as the overall scale for extrapolation of the sample proportion will cause serious distortion in the estimated number of process defect points and the corrected number. This type of inspection data also cannot be used to update the correction model parameters.

[0121] The method for removing outlier data is not limited here. For example, in one feasible implementation, integrity verification and standard defect detection verification are performed on the actual detected data of each wafer. Integrity verification includes determining whether the full-domain scan was performed completely, and standard defect detection verification includes determining whether a standard defect point was detected among the sampled defect points. The actual detected data of a wafer that fails any verification is determined to be outlier data and is removed. The actual detected data of a wafer that passes all verifications is retained and added to the observation set. The preprocessing operations such as data format conversion, data cleaning, and data alignment when adding data to the observation set will not be described in detail here.

[0122] In one feasible implementation, after removing abnormal data, if the number of valid wafer samples in the observation set is insufficient for the model update, the actual detected data of subsequent batches will continue to be accumulated until the number of valid wafer samples in the observation set reaches the number required for the model update before the model parameters are updated, so as to avoid the instability of the updated calibration model due to insufficient number of valid samples.

[0123] In this embodiment, by removing abnormal data before adding actual detected data to the observation set, abnormal samples are avoided from contaminating the observation set, thereby improving the accuracy and reliability of the model parameter update of the calibration model and thus improving the accuracy of subsequent batch wafer defect detection.

[0124] In one feasible embodiment, the wafer defect detection method further includes: Step S80: For any preset detection cycle, determine the equipment capture rate of the standard defect pattern based on the number of standard defect patterns, the first number, the second number, and the third number; The inspection cycle is a pre-set time interval during which the status of the first scanning equipment is periodically evaluated. The inspection cycle can be set at fixed intervals, such as every 24 or 72 hours; or it can be set based on fixed inspection batches, such as every 50 or 100 wafers inspected. The specific value of the inspection cycle is determined based on the production line's stability requirements, equipment maintenance plan, and historical drift data. During the inspection cycle, the first scanning equipment's ability to detect standard defect patterns is continuously monitored to promptly identify changes in equipment status.

[0125] The ratio of the third quantity to the second quantity is calculated to obtain the sample proportion of standard defect points. Next, the product of the first quantity and the sample proportion of standard defect points is calculated to obtain the estimated number of standard defect points. Finally, the ratio of the estimated number of standard defect points to the number of standard defect patterns is calculated to obtain the equipment capture rate. The equipment capture rate characterizes the overall detection capability of the first scanning equipment for standard defect patterns within the current detection cycle, and its value ranges from zero to one.

[0126] In one feasible implementation, standard defect patterns can also be generated on an offline control wafer. By inspecting the standard defect patterns on the offline control wafer in different inspection cycles, a trend chart of the number of standard defects detected or the equipment capture rate is plotted for statistical process control management. Control limits (i.e., preset threshold ranges) for the equipment capture rate are set for different inspection equipment, and preset discrepancy criteria (e.g., the equipment capture rate exceeds the control limit, the equipment capture rate is on the same side of the center line for multiple consecutive inspection cycles, etc.) are applied to identify the threshold deviation of the equipment capture rate. Once the equipment capture rate deviates from the threshold, equipment maintenance is triggered or the defect detection results of recently inspected wafers are retrospectively corrected, instead of directly using a fixed calibration coefficient.

[0127] Step S90: In response to the fact that the capture rate of the device is not within the preset threshold range, the defect detection results of the wafers detected in the current detection cycle are corrected.

[0128] The preset threshold range is a pre-defined normal range for the device capture rate, defined by an upper and lower limit. The preset threshold range can be set based on the average and standard deviation of the device capture rate obtained from historical testing data, as well as the required detection accuracy according to process specifications. For example, the preset threshold range can be set to 0.8 to 1.2, indicating that the first scanning device is considered to be in normal condition when the device capture rate is within this range. In specific implementations, the preset threshold range can also be adjusted according to the specific process level and device model; different process levels may use different threshold ranges.

[0129] When the device capture rate is determined to be below the preset lower threshold or above the preset upper threshold, a backtracking correction mechanism is triggered. A capture rate below the lower threshold indicates that the first scanning device has missed detections, and the defect detection results of the wafers inspected in the current inspection cycle may underestimate the actual number of defects. A capture rate above the upper threshold indicates that the first scanning device has false alarms or that the standard defect pattern size does not match the resolution limit, and the defect detection results of the wafers inspected in the current inspection cycle may overestimate the actual number of defects. In both cases, the defect detection results of the wafers inspected in the current inspection cycle need to be recalibrated to compensate for the system bias caused by the malfunction of the first scanning device.

[0130] The method for correcting the defect detection results of wafers inspected in the current inspection cycle is not limited here. For example, the updated correction coefficients from the previous inspection cycle can be used to recalculate the defect detection results of wafers inspected in the current inspection cycle; alternatively, the average correction coefficients from multiple normal inspection cycles in the historical observation set can be used to recalculate the defect detection results of wafers inspected in the current inspection cycle. These methods reduce the interference of single fluctuations through averaging. After retrospective correction, the updated defect detection results are obtained, and the updated defect detection results are overwritten or recorded in parallel in the inspection report.

[0131] In this embodiment, by periodically monitoring the detection ratio of standard defect patterns, the performance drift or abnormality of the detection system can be detected in a timely manner, and the historical detection results of the inspected wafers can be traced and corrected to avoid systematic distortion of the defect detection results of batch wafers due to changes in the status of the first scanning equipment.

[0132] For example, to help understand the implementation flow of the wafer defect detection method obtained by combining this embodiment with the above embodiment one, please refer to... Figure 4 , Figure 4 A simplified flowchart of a wafer defect detection method is provided, specifically: In the data processing of semiconductor wafer defect detection, a standard defect pattern is first formed in the non-functional area of ​​the target wafer. The specific implementation of forming the standard defect pattern is as follows: a standard defect pattern is set on the mask at the position corresponding to the non-functional area of ​​the target wafer. The standard defect pattern is a two-dimensional periodic grating array structure with an asymmetric staggered distribution. The standard defect pattern is transferred to the non-functional area through the device layer process executed by the semiconductor process equipment to form a standard defect pattern consistent with the current device layer process and material. The number of standard defect patterns is denoted as N0.

[0133] Step S1: In response to the defect detection command, data acquisition is performed. The following operations are performed on the target wafer: A full-area scan is performed using a first scanning device (e.g., an optical inspection device), and the number of all suspected defect points is measured and recorded, denoted as the first quantity M.

[0134] According to the principle of random sampling, a portion of the suspected defect points are selected from the suspected defect points as sampled defect points, and the total number of sampled defect points is recorded as the second quantity m.

[0135] The sampled defect points are checked and verified using a second scanning device (which may be a scanning electron microscope). The number of points that belong to the standard defect pattern is identified and recorded, and is denoted as the third quantity m0.

[0136] For any wafer to be tested, the following is also obtained: The total number of suspected defect points in the full-domain scan is denoted as the fourth quantity M'. The total number of sampled defect points is denoted as the fifth quantity m'. The number of each type of process defect in the sampled defect points, for example, the number of the i-th type of process defect points is denoted as m. i (That is, the sixth quantity).

[0137] Step S2: Based on the collected data and the preset calibration model, determine the defect detection results of the wafer to be inspected. Specifically, determine whether the wafer to be inspected meets the homogeneity condition, where the homogeneity condition is: under the same inspection conditions and the same process level, the detection miss rate, sampling deviation, and systematic error of various types of wafer defects are proportionally related, that is, the influence of the systematic deviation of the wafer defect inspection equipment on various types of process defects is homogeneous and proportional. If it is met, proceed to S21; if it is not met, proceed to S22.

[0138] S21, when the wafer under inspection meets the homogeneity condition, the first correction model is used for correction. This involves calculating the global deviation correction coefficient by the ratio of the actual number of standard defects to the sampled estimate. This coefficient is then used to scale the sampled extrapolated estimates of various defects, achieving quantitative compensation for system deviation and improving the fit between the defect quantity estimate and the actual value. First, the correction coefficient is calculated using the data from the target wafer. Let N0 be the actual number of standard defect patterns, M be the total number of suspected defect points in the full-area scan of the target wafer, m be the total number of sampled defect points, and m0 be the number of standard defect points detected in the sampling. Then: The sample proportion of standard defect points is calculated as p0 = m0 / m.

[0139] Calculate the estimated number of standard defect points Ñ0=M p0.

[0140] The ratio between the number of standard defect patterns N0 and the estimated number of standard defect points Ñ0 is calculated and used as the correction coefficient K = N0 / Ñ0. The correction coefficient K reflects the degree of detection deviation of the first scanning device for standard defects; in a feasible embodiment, the correction coefficient K can also be solved by fitting, that is, solving for the K value that minimizes the difference between the actual number of standard defect patterns N0 and the corrected estimated number of standard defect points K·Ñ0.

[0141] To correct for type i process defects in the wafer under inspection, let the total number of suspected defect points in the full-area scan of the wafer be M', the total number of sampled defect points be m', and the number of type i process defects detected in the sampling be m. i '.but: Calculate the sample proportion p of the i-th type of process defect. i =m i ' / m'.

[0142] Calculate the estimated number of process defects of type i. i =M' p i .

[0143] The correction coefficient K and the estimated number of the i-th type of process defect point Ñ i Input a linear normalized model, and scale the estimated number of process defects of type i using a correction coefficient K to obtain the corrected number N of process defects of type i. i =K Ñ i Output the corrected number N of the i-th type of process defect. i The defect detection results are determined based on the corrected number of various process defect points.

[0144] Furthermore, the error propagation of the corrected quantity satisfies: Var(Ñi ,corr)=K² Var(Ñi)+Ñ i ² Var(K); Among them, Var(Ñ i ,corr) is the variance of the estimated number of process defects of type i, and Var(K) is the variance of the correction coefficient, both of which are derived from sampling error.

[0145] S22, when the wafer to be inspected does not meet the preset homogeneity condition, the estimated number of process defect points is corrected based on the preset second correction model, that is, based on non-proportional correction. In this embodiment, the second correction model is a Bayesian model, that is, a statistical model based on Bayes' theorem.

[0146] First, a priori distribution of the number of various process defects is established based on the number of standard defect patterns. Let the number of various process defects in the actual wafer defects be N = (N1, N2, ..., N). k ), where k is the total number of process defect categories, and the normalized proportion of each category satisfies Σp i =1, where p i =Ñ i / N total N total This represents the total number of defects on the wafer. The Bayesian formula is: P(N|n) = P(n|N)·P(N) / P(n); where P(N) is the prior distribution, obtained from the standard defect pattern; P(n|N) is the likelihood function, determined by the sampling data from the verification inspection; P(N|n) is the posterior probability distribution, the final optimized result used for correction; and P(n) is the evidence factor, which serves a normalization function. Specifically: First, a prior distribution of the number of various process defects is established based on the number of standard defect patterns. Assuming that the sampling process conforms to a multivariate hypergeometric distribution without replacement, the prior distribution adopts a Dirichlet-Multinomial distribution: P(N) ~ Dirichlet-Multinomial(N,α1,α2,…,α) k ), where α k Let α be the prior pseudo-count of the k-th type of process defect. The prior pseudo-count of each type of process defect is determined based on the confidence weight and the number of standard defect patterns. k =c·N0, where N0 is the number of standard defect patterns and c is the confidence weight. The confidence weight characterizes the confidence level of using prior information determined by the number of standard defect patterns to estimate the true number of process defect points in the wafer to be inspected.

[0147] Then, a likelihood function is constructed based on the number of each type of defect point in the sampled defect points. Given a fixed actual number N of each type of process defect, the likelihood function is derived from N...total From a defect, n samples are drawn without replacement, and the number of each type of defect point observed in the sampled defect points is n = (n1, n2, ..., nn). k The probability of n is characterized by the likelihood function P(n|N), which follows a Dirichlet-Multinomial distribution, i.e., P(n|N) ~ Dirichlet-Multinomial(n1,n2,…,n). k ).

[0148] Finally, based on Bayes' theorem, the posterior probability distribution of the number of various process defects is calculated according to the likelihood function and prior distribution, and used as an estimate of the final defect detection result, denoted as P(N|n): P(N|n1,n2,…,n k )∝P(n1,n2,…,n k |N)·P(N), that is, the posterior probability distribution is proportional to the product of the likelihood function and the prior distribution. Normalizing the product of the likelihood function and the prior distribution yields the posterior probability distribution. The expected value of the posterior probability distribution (the minimum mean square error estimate) is used as the final calculated value of various process defects, that is, the corrected number N of various process defects. k calc =E[N k |n1,n2,…,n k ].

[0149] Step S3: Iterative optimization of the model.

[0150] After completing defect inspection of a batch of wafers, the actual detection data for the current batch is acquired, including full-domain scan results, sampling verification results, and the number of detected standard defect patterns. For the Bayesian model, the actual detection data of the current batch of wafers is added to the observation set, and the posterior probability distribution calculated for the current batch is used as the prior distribution for the next batch of inspections. The Bayesian update steps described above are repeated to continuously correct the defect number estimate. For the linear normalization model, the correction coefficient K is recalculated using the standard defect detection data of the new batch, enabling dynamic adjustment of the model parameters.

[0151] Step S4: Performance monitoring and retrospective correction of the first scanning device. For any preset inspection cycle (e.g., daily or per batch), the device capture rate is calculated based on the standard defect pattern on the target wafer or standard monitoring wafer (offline control wafer), and compared with a preset threshold range. If the device capture rate exceeds the preset threshold range, it indicates that the first scanning device has drifted, such as due to light source attenuation, lens contamination, or algorithm threshold deviation. In this case, an equipment maintenance alarm is generated, and retrospective correction is triggered for the defect detection results of all inspected wafers in the current inspection cycle. That is, the number of defects on each wafer is recalculated using the last normal correction coefficient before the first scanning device malfunctions, thereby avoiding erroneous yield judgments based on data from failed equipment.

[0152] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the wafer defect detection method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0153] This application also provides a wafer defect detection device. The wafer defect detection device provided by this application, employing the wafer defect detection method in the above embodiments, can solve the technical problems of inaccurate defect rate estimation and decreased reliability of yield risk assessment caused by the compression of the sampling sample size. Compared with the prior art, the beneficial effects of the wafer defect detection device provided by this application are the same as those of the wafer defect detection method provided in the above embodiments, and other technical features in the wafer defect detection device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0154] This application provides a wafer defect detection device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the wafer defect detection method in the above embodiment 1.

[0155] The following is for reference. Figure 5 The diagram illustrates a structural schematic of a wafer defect detection device suitable for implementing embodiments of this application. The wafer defect detection device in the embodiments of this application may include, but is not limited to, mobile terminals such as laptops, PDAs (Personal Digital Assistants), PADs (Portable Application Description), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The wafer defect detection equipment shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this application.

[0156] like Figure 5 As shown, the wafer defect inspection device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the wafer defect inspection device. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An input / output interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a display, speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. The communication device 1009 allows the wafer defect inspection device to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show wafer defect inspection equipment with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented alternatively.

[0157] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0158] The wafer defect detection equipment provided in this application, employing the wafer defect detection method described in the above embodiments, can solve the technical problems of inaccurate defect rate estimation and decreased reliability of yield risk assessment caused by the compression of the sampling sample size. Compared with the prior art, the beneficial effects of the wafer defect detection equipment provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and other technical features of this wafer defect detection equipment are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0159] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0160] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0161] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the wafer defect detection method in the above embodiments.

[0162] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0163] The aforementioned computer-readable storage medium may be included in the wafer defect detection equipment; or it may exist independently and not assembled into the wafer defect detection equipment.

[0164] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the wafer defect detection device, enable the wafer defect detection device to implement the wafer defect detection methods of the various embodiments described above.

[0165] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0166] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0167] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0168] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described wafer defect detection method. This solves the technical problem of inaccurate defect rate estimation and decreased reliability of yield risk assessment in wafer defect detection due to the compression of the sampling sample size. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and will not be repeated here.

[0169] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the wafer defect detection method described above.

[0170] The computer program product provided in this application can solve the technical problem that the inaccurate estimation of defect rate and the decreased reliability of yield risk assessment in wafer defect detection are caused by the compression of the sampling sample size. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and will not be repeated here.

[0171] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for detecting wafer defects, characterized in that, The wafer defect detection method includes: Standard defect patterns are formed in the non-functional regions of the target wafer; In response to a defect detection command, a first quantity, a second quantity, and a third quantity are obtained, wherein the first quantity is the number of suspected defect points measured by full-area scanning of the target wafer, the second quantity is the number of sampled defect points obtained by sampling the suspected defect points of the target wafer, and the third quantity is the number of standard defect points among the sampled defect points of the target wafer. For any wafer to be inspected, a fourth quantity, a fifth quantity, and a sixth quantity are obtained, wherein the fourth quantity is the number of suspected defect points measured by full-area scanning of the wafer to be inspected, the fifth quantity is the number of sampled defect points obtained by sampling the suspected defect points of the wafer to be inspected, and the sixth quantity is the number of process defect points among the sampled defect points of the wafer to be inspected. Based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model, the defect detection result of the wafer to be inspected is determined; The step of determining the defect detection result of the wafer to be inspected based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model includes: Calculate the ratio of the sixth quantity to the fifth quantity to obtain the sample proportion of the process defect points; Calculate the product of the fourth quantity and the sample proportion of the process defect points to obtain the estimated number of the process defect points; The estimated number of process defect points is corrected based on the number of standard defect patterns, the first number, the second number, the third number, and the preset correction model to obtain the corrected number of process defect points. The defect detection result is determined based on the corrected number of the process defect points.

2. The wafer defect detection method as described in claim 1, characterized in that, The step of forming a standard defect pattern in the non-functional area of ​​the target wafer includes: A standard defect pattern is set on the mask at a position corresponding to the non-functional area of ​​the target wafer, wherein the standard defect pattern is a two-dimensional periodic grating array structure and adopts an asymmetric misaligned distribution; The standard defect pattern of the mask is transferred to the non-functional area of ​​the target wafer by a device layer process performed by semiconductor process equipment to form a standard defect pattern.

3. The wafer defect detection method as described in claim 1, characterized in that, The steps for obtaining the first quantity, the second quantity, and the third quantity include: The target wafer is scanned across the entire area using a first scanning device to identify and record the number of suspected defect points on the target wafer, which is taken as the first number. According to the random sampling principle, defect points are selected from the suspected defect points of the target wafer as sampling defect points, and the number of sampling defect points on the target wafer is recorded as the second quantity. The sampling defect points of the target wafer are checked and inspected by a second scanning device. The number of standard defect points is identified and recorded from the sampling defect points of the target wafer as the third quantity.

4. The wafer defect detection method as described in claim 1, characterized in that, The sixth quantity includes the quantity of each type of process defect point among the sampled defect points of the wafer to be inspected; the estimated quantity of process defect points includes the estimated quantity of each type of process defect point. The step of correcting the estimated number of process defect points based on the number of standard defect patterns, the first number, the second number, the third number, and a preset correction model to obtain the corrected number of process defect points includes: For each type of process defect, the estimated number of each type of process defect is corrected based on the number of standard defect patterns, the first number, the second number, the third number, and a preset correction model, to obtain the corrected number of each type of process defect.

5. The wafer defect detection method as described in claim 1, characterized in that, The step of correcting the estimated number of process defect points based on the number of standard defect patterns, the first number, the second number, the third number, and a preset correction model to obtain the corrected number of process defect points includes: If the wafer to be inspected meets the preset homogeneity condition, then a correction coefficient is determined based on the number of standard defect patterns, the first number, the second number, and the third number. The estimated number of process defect points is corrected by the correction coefficient and the preset first correction model to obtain the corrected number of process defect points. The first correction model is a multiplicative correction statistical model. If the wafer to be inspected does not meet the homogeneity condition, the corrected number of process defect points is determined based on the number of standard defect patterns, the sixth number, and the preset second correction model, wherein the second correction model is a statistical model based on Bayes' theorem.

6. The wafer defect detection method as described in claim 5, characterized in that, The first correction model is a linear normalization model. The step of determining correction coefficients based on the number of standard defect patterns, the first number, the second number, and the third number, and correcting the estimated number of process defect points using the correction coefficients and the preset first correction model includes: Calculate the ratio of the third quantity to the second quantity, and use it as the sample proportion of the standard defect points; Based on the first quantity and the sample proportion of the standard defect points, the estimated quantity of the standard defect points is determined; The ratio between the number of standard defect patterns and the estimated number of standard defect points is calculated and used as a correction coefficient. The correction coefficient and the estimated number of process defects are input into the linear normalization model. The estimated number of process defects is scaled using the correction coefficient to obtain the corrected number of process defects.

7. The wafer defect detection method as described in claim 5, characterized in that, The second correction model is a Bayesian model. The step of determining the corrected number of process defect points based on the number of standard defect patterns, the sixth number, and the preset second correction model includes: A prior distribution of the true number of process defect points is established based on the number of standard defect patterns and the confidence weight, wherein the confidence weight represents the confidence level of prior information determined by the number of standard defect patterns used to estimate the true number of process defect points. A likelihood function is constructed based on the sixth quantity, wherein the likelihood function represents the probability of observing the sixth quantity given that the actual number of process defect points is determined; Based on Bayes' theorem, the posterior probability distribution of the true number of process defects is calculated according to the likelihood function and the prior distribution, and the expected value of the posterior probability distribution is used as the corrected number of process defects.

8. The wafer defect detection method as described in claim 1, characterized in that, After the step of determining the defect detection result of the wafer to be inspected based on the number of standard defect patterns, the first number, the second number, the third number, the fourth number, the fifth number, the sixth number, and a preset correction model, the method further includes: Obtain the actual detection data of the current batch of wafers, wherein the actual detection data includes data detected in at least one step of wafer defect detection; The actual detected data is added to the observation set, and the model parameters of the correction model are updated based on the observation set to obtain the updated correction model. Based on the updated correction model, wafer defect detection is performed on the next batch of wafers.

9. The wafer defect detection method as described in claim 8, characterized in that, The step of adding the actual detected data to the observation set includes: Abnormal data is removed from the actual detected data, and the processed actual detected data is added to the observation set; wherein, the abnormal data includes wafer sample data in which standard defect points were not detected in the sampled defect points, and detection data of wafers whose full-domain scan was not completed and was abnormally terminated.

10. The wafer defect detection method as described in claim 1, characterized in that, The wafer defect detection method further includes: For any preset detection cycle, the equipment capture rate of the standard defect pattern is determined based on the number of standard defect patterns, the first number, the second number, and the third number. In response to the device's capture rate being outside the preset threshold range, the defect detection results of the wafers inspected in the current detection cycle are corrected.

11. A wafer defect detection device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the wafer defect detection method as described in any one of claims 1 to 10.

12. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the wafer defect detection method as described in any one of claims 1 to 10.

13. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the wafer defect detection method as described in any one of claims 1 to 10.

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