Electronic device with detection circuitry

Abstract

The present disclosure provides an electronic device with a detection circuit, comprising a substrate comprising an active region; a first data line disposed on the substrate and extending along a first direction; a first pixel unit disposed on the substrate within the active region and electrically connected to the first data line; a second pixel unit disposed on the substrate within the active region and electrically connected to the first data line; and a detection circuit disposed on the substrate within the active region. The detection circuit comprises a first signal line, a first switching element disposed between the first pixel unit and the second pixel unit and electrically connected to the first signal line and the first data line, and a first control line electrically connected to a control terminal of the first switching element.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device having a detection circuit. Background Technology

[0002] With the continuous advancement of the technology industry, display devices have been widely used in various products such as televisions, computers, and mobile phones. In recent years, narrow-bezel monitors have become the mainstream trend in the development of high-quality display devices due to their advantages such as a simple and aesthetically pleasing appearance and increased display area within a given panel size. However, the arrangement of various components in the display area is limited by the available space. Therefore, further improvements are needed to integrate some components that were originally located in the peripheral area into the display area to meet current or future needs. Summary of the Invention

[0003] According to one embodiment of this disclosure, an electronic device includes a substrate, the substrate including an active region; a first data line disposed on the substrate and extending along a first direction; a first pixel unit disposed within the active region on the substrate and electrically connected to the first data line; a second pixel unit disposed within the active region on the substrate and electrically connected to the first data line; and a detection circuit disposed within the active region on the substrate. The detection circuit includes a first signal line, a first switching element electrically connected to the first signal line and the first data line and disposed between the first pixel unit and the second pixel unit, and a first control line electrically connected to a control terminal of the first switching element.

[0004] To better understand the features and advantages of this disclosure, several embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of an electronic device according to a first embodiment of the present disclosure;

[0006] Figure 2 This is a circuit diagram of a detection circuit according to an embodiment of the present disclosure;

[0007] Figure 3 This is a top view schematic diagram of a detection circuit according to an embodiment of the present disclosure;

[0008] Figure 4 According to an embodiment of this disclosure, along Figure 3 A cross-sectional view of line A-A' in the middle;

[0009] Figure 5 According to an embodiment of this disclosure, along Figure 3 A schematic diagram of the cross section of line B-B' in the middle;

[0010] Figure 6This is a schematic diagram of an electronic device according to a second embodiment of the present disclosure;

[0011] Figure 7 This is a schematic diagram of an electronic device according to a third embodiment of the present disclosure;

[0012] Figure 8 This is an enlarged schematic diagram of the first region of an electronic device according to a third embodiment of the present disclosure;

[0013] Figure 9 This is an enlarged schematic diagram of the second region of an electronic device according to a third embodiment of the present disclosure;

[0014] Figure 10 This is an enlarged schematic diagram of the third region of an electronic device according to a third embodiment of the present disclosure;

[0015] Figure 11 This is a schematic diagram of an electronic device according to a fourth embodiment of the present disclosure;

[0016] Figure 12 This is a schematic diagram of an electronic device according to a fifth embodiment of the present disclosure;

[0017] Figure 13 This is a schematic diagram of an electronic device according to a sixth embodiment of the present disclosure;

[0018] Figure 14 This is a schematic diagram of an additional detection circuit according to an embodiment of the present disclosure;

[0019] Figure 15 This is a schematic diagram of an electronic device according to the seventh embodiment of the present disclosure. Detailed Implementation

[0020] The electronic device may be or include a rollable display device, a flexible display device, a freeform display device, or a tiled display device, but this disclosure is not limited thereto. The electronic device may include a non-self-emissive panel (e.g., a liquid crystal panel) or other self-emissive panels, but this disclosure is not limited thereto.

[0021] Figure 1 This is a schematic diagram of an electronic device according to a first embodiment of the present disclosure. Figure 2 This is a circuit diagram of a detection circuit according to an embodiment of the present disclosure. Figure 3 This is a top view schematic diagram of a detection circuit according to an embodiment of the present disclosure. Figure 4 According to an embodiment of this disclosure, along Figure 3 A cross-sectional view of line A-A' in the middle. Figure 5 According to an embodiment of this disclosure, along Figure 3 A cross-sectional view of line B-B' in the middle.

[0022] Please refer to Figure 1The electronic device disclosed herein (e.g., electronic device 10) includes a substrate SUB1 having an active region AA1 and a peripheral region PR1. The peripheral region PR1 is adjacent to the active region AA1. In some embodiments, the peripheral region PR1 may surround the active region AA1. In some embodiments, the electronic device may be a display device, such as a light-emitting diode display device.

[0023] exist Figure 1 In the illustrative embodiment shown, the electronic device 10 includes a detection circuit 100, multiple data lines DL, multiple scan lines SCL, and multiple pixel units PU disposed on a substrate SUB1. The multiple data lines DL can extend along a first direction Y, and the multiple scan lines SCL can extend along a second direction X different from the first direction Y. For ease of explanation, Figure 1 Only two scan lines SCL1 and SCL2 are shown, but this does not limit the scope of this application. Multiple data lines DL may intersect with multiple scan lines SCL. The multiple data lines may include a first data line DL1, a second data line DL2, and a third data line DL3 that are adjacent to each other along the second direction X. Multiple pixel units PU are disposed in the active area AA on the substrate SUB1, and there are no pixel units in the peripheral area PR. The multiple pixel units PU may include a first pixel unit PU1 and a second pixel unit PU2. Each pixel unit (e.g., the first pixel unit PU1) may include a first pixel (or sub-pixel) PX1 electrically connected to the first data line DL1, a second pixel (or sub-pixel) PX2 electrically connected to the second data line DL2, and a third pixel (or sub-pixel) PX3 electrically connected to the third data line DL3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged adjacent to each other along the first direction Y. In some embodiments, the first direction may intersect with the second direction. In some alternative embodiments, the first direction may be perpendicular to the second direction.

[0024] Please refer to Figure 1 The detection circuit 100 can be disposed within the active area AA1 on the substrate SUB1. The detection circuit 100 may include a first scan line SCL1, a first switching element T1, and a first control line CL1. The plurality of pixel units PU can be divided into pixel units in a first row 110 electrically connected to the first scan line SCL1 and pixel units in a second row 220 electrically connected to the second scan line SCL2. Specifically, the detection circuit 100 can be disposed between the pixel units in the first row 110 and the pixel units in the second row 220.

[0025] Please refer to Figure 1 In some embodiments, the pixel unit PU may include electronic components DE1, such as... Figure 14As illustrated in the simplified diagram. Specifically, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may contain electronic components. For example, the first pixel PX1 may contain electronic component DE1. This electronic component may contain active components, passive components, electrodes, conductive wiring, or combinations thereof. Active components may contain switching elements (e.g., transistors TX (e.g., thin-film transistors (TFTs))) and light-emitting elements, quantum dots (QDs), fluorescent materials, phosphorescent materials, other suitable materials, or combinations thereof. Active components may contain driving transistors. Passive devices may contain capacitors, resistors, inductors, or combinations thereof. The light-emitting element may be a light-emitting diode. This light-emitting diode may include, for example, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes, mini-LEDs, micro-LEDs, or quantum dot light-emitting diodes (QLEDs, QDLEDs), but is not limited to these. Conductive wiring may contain signal lines, such as data lines, scan lines, or combinations thereof.

[0026] Please refer to Figure 1 In a pixel unit PU, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can display different colors. For example, the first pixel PX1 displays a first color, the second pixel PX2 displays a second color, and the third pixel PX3 displays a third color. The first color, the second color, and the third color are not the same. For example, the first color may be red, the second color may be green, and the third color may be blue, but the scope of this disclosure is not limited thereto. In some embodiments, the first pixel PX1 may include a light-emitting diode of the first color, the second pixel PX2 may include a light-emitting diode of the second color, and the third pixel PX3 may include a light-emitting diode of the third color.

[0027] exist Figure 1 In the illustrative embodiments shown, for ease of understanding, Figure 1 Only one transistor TX in one pixel PX is shown, but this does not limit the scope of this application. For example, Figure 1 Only one transistor TX1 is shown in the first pixel PX1. Each pixel PX may contain one or more transistors. Transistor TX1 is disposed in the first pixel PX1 and electrically connected to the first data line DL1, transistor TX2 is disposed in the second pixel PX2 and electrically connected to the second data line DL2, and transistor TX3 is disposed in the third pixel PX3 and electrically connected to the third data line DL3. The pixel units of the first column 110 are electrically connected to the first scan line SCL1. For example, in the first column 110, transistors TX1, TX2, and TX3 are electrically connected to the first scan line SCL1. In some embodiments, transistor TX includes a node ND, which is electrically connected to an electrode or light-emitting element in the corresponding pixel PX. For clarity, Figure 1Only the node ND of transistor TX3 in pixel PX3 is displayed.

[0028] Please refer to Figure 1 The detection circuit 100 includes a signal line (e.g., a first signal line SL1), a switching element (e.g., a first switching element T1) electrically connected to the signal line and a data line (e.g., DL1) and disposed between a first pixel unit PU1 and a second pixel unit PU2, and a control line (e.g., a first control line CL1) electrically connected to the control terminal of the switching element T1. In some embodiments, at least a portion of the signal line and at least a portion of the control line extend along a second direction.

[0029] exist Figure 1 and Figure 2 In the illustrated embodiment, the detection circuit 100 includes multiple signal lines and multiple switching elements. The multiple signal lines include a first signal line SL1, a second signal line SL2, and a third signal line SL3 that are adjacent to each other and extend along a second direction X. The multiple switching elements include a first switching element T1 electrically connected to the first data line DL1 and the first signal line SL1, a second switching element T2 electrically connected to the second data line DL2 and the second signal line SL2, and a third switching element T3 electrically connected to the third data line DL3 and the third signal line SL3. In some embodiments, the first switching element T1, the second switching element T2, and the third switching element T3 may be transistors, such as TFTs, but this disclosure is not limited thereto. Figure 1 In the illustrated embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 are adjacent to each other in the first direction Y and located on the same side of the first data line DL1, the second data line DL2, and the third data line DL3. For example, the first data line DL1 has a first side ds1 and a second side ds2 disposed opposite to each other. The second side ds2 is closer to the second data line DL2 than the first side ds1, and the first switching element T1 and the second switching element T2 are located on the first side ds1 of the first data line DL1. The second switching element T2 is disposed between the first pixel unit PU1 and the second pixel unit PU2.

[0030] Please refer to Figure 1In the detection mode, a control signal is provided to the first control line CL1 to turn on the first switching element T1, and a test signal is provided to the first signal line. Therefore, the first data line DL1, electrically connected to the first switching element T1, receives the test signal and controls the corresponding pixel PX1 to be enabled, thereby achieving electrical testing. That is, at least one switching element is electrically connected to each data line, at least one signal line is electrically connected to one end of the switching element, and at least one control line is electrically connected to the control terminal of the switching element, thereby achieving electrical testing. Similarly, the second data line DL2 and the third data line DL3 can each receive the corresponding test signal; repeated descriptions are omitted here. In the detection mode, multiple scan lines SCL can be scanned sequentially from the first scan line to the last scan line, thereby achieving electrical testing of all pixel units (pixel units in all columns) on the substrate SUB1. In some embodiments, for pixels containing light-emitting elements, this electrical test can be a lighting test. Since the detection circuit is located in the active area AA1, rather than in the peripheral area, the area of ​​the peripheral area can be minimized, thereby achieving a narrow bezel or bezel-less design. Furthermore, for a given substrate size, pixel units can occupy a larger area of ​​the substrate, thereby achieving greater utilization of the substrate.

[0031] Please refer to Figure 1 The electronic device 100 includes an array substrate 10A. The array substrate 10A includes a substrate SUB1, multiple data lines, multiple scan lines, multiple pixel units, and a detection circuit 100. After electrical testing of the array substrate 10A is completed by the detection circuit 100, other components (e.g., a circuit board (not shown)) can be integrated with the array substrate 10A. The circuit board can be a printed circuit board and / or a flexible circuit board. For example, the circuit board may include a data driver (not shown) electrically connected to the multiple data lines and providing data signals to these data lines in a driving mode.

[0032] exist Figure 1 and Figure 2In the illustrative embodiment shown, when the driving mode of the first pixel PX1 to the third pixel PX3 is activated, the first switching element T1 to the third switching element T3 in the detection circuit 100 are in a turned-off state to isolate the detection circuit 100 from the first data lines DL1 to the third data lines DL3. In some embodiments, when the driving mode is activated, the first signal lines SL1 to the third signal lines SL3 of the detection circuit 100 are in a floating state, and a turn-off voltage is provided to the first control line CL1 of the detection circuit 100 according to the transistor type of the first switching element T1 to the third switching element T3 to control the first switching element T1 to the third switching element T3 to be in a turned-off state. In some embodiments, the first switching element T1 to the third switching element T3 may be or include n-type transistors, thus improving the reliability of the detection circuit 100. For example, n-type transistors with normally-off characteristics help maintain the turned-off state of the first switching element T1 to the third switching element T3 during the driving mode. Figure 1 and Figure 2 In the illustrative embodiment shown, when the detection mode of the first pixel PX1 to the third pixel PX3 is activated, the first switching element T1 to the third switching element T3 are in a conducting state, causing the detection circuit 100 to be electrically connected to the first data line DL1 to the third data line DL3. In some embodiments, when the detection mode is activated, a test voltage is applied to the first signal line SL1 to the third signal line SL3 according to various detection purposes, and a conduction voltage is provided to the first control line CL1 according to the transistor type of the first switching element T1 to the third switching element T3 to control the first switching element T1 to the third switching element T3 to be in a conducting state. For ease of explanation, the figures only show that the switching elements T1~T3 in the detection circuit and the transistors TX1~TX3 in the pixel unit PU1 are n-type transistors. In some embodiments, the switching elements T1~T3 and the transistors TX1~TX3 may be p-type transistors.

[0033] Please refer to Figure 1 and Figure 3 The detection circuit 100 includes a common gate line CGL, which electrically connects the control line CL1 to the first switching element T1, the second switching element T2, and the third switching element T3. That is, the first control line CL1 is electrically connected to the control terminals of the first switching element T1 to the third switching element T3. In this embodiment, the common gate line CGL extends along the first direction Y.

[0034] exist Figure 3 and Figure 4In the illustrated embodiment, substrate SUB1 includes a first surface (e.g., front surface) FS1 and a second surface (e.g., back surface) disposed opposite to each other. Detection circuit 100 is disposed on the first surface FS1 of substrate SUB1. Wiring layers WL1, WL2, WL3, and WL4 are sequentially disposed on the first surface FS1 of substrate SUB1. Semiconductor layer SE is disposed above or below wiring layer WL1. Insulating layer 71 is disposed between wiring layers WL1 and WL2, insulating layer 72 is disposed between wiring layers WL2 and WL3, insulating layer 73 is disposed between wiring layers WL3 and WL4, and insulating layer 74 is disposed above wiring layer WL4. Wiring layers WL1-WL4 and semiconductor layer SE are patterned as needed to obtain detection circuit 100. Figure 4 The first switching element T1 can be a top-gate thin-film transistor. In the first switching element T1, the first gate G1 of the wiring layer WL1 is disposed on the first semiconductor layer SE1. An insulating layer 70 is disposed between the first gate G1 and the first semiconductor layer SE1. However, a bottom-gate thin-film transistor or other types of transistors can be used, and all are within the scope of this application. The aforementioned insulating layer can be a single layer or multiple layers. The insulating layer can contain organic layers, inorganic layers, or combinations thereof. For example, the insulating layer can be silicon oxide, silicon nitride, or combinations thereof, but this disclosure is not limited thereto.

[0035] Please refer to Figure 3 and Figure 4 The first semiconductor layer SE1 includes a source terminal S1 and a drain terminal D1 located on opposite sides of the first gate G1. The first semiconductor layer SE1 may contain a suitable semiconductor material, such as monocrystalline silicon, amorphous silicon, polycrystalline silicon, metal oxides, or mixtures thereof. A suitable metal oxide may be IGZO (indium gallium zinc oxide). Wiring layers WL1 to WL4 may contain any suitable conductive material. For example, the conductive material may be a metal, such as copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), their alloys, combinations thereof, or other metallic materials with good conductivity, but is not limited thereto. Wiring layers WL1 to WL4 may contain the same or different materials. Each of wiring layers WL1 to WL4 may consist of a single layer or multiple layers.

[0036] Please refer to Figures 3 to 5In some embodiments, wiring layer WL1 may include gates G1-G3. Wiring layer WL3 may include a common gate line CGL and data lines DL1-DL3. Wiring layer WL4 may include a control line CL. Signal lines SL1-SL3 may be on the same layer as the control line CL, or on a different layer. For example, wiring layer WL4 may include the control line CL and signal lines SL1-SL3. In some embodiments, the data lines, signal lines, control lines, common gate lines, and gates may be wiring layers different from those described above. For example, the control line CL may be wiring layer WL3 instead of wiring layer WL4. Other variations to the wiring layers are possible; for clarity, detailed descriptions are omitted.

[0037] Please refer to Figures 3 to 5 In the first switching element T1, the first gate G1 is electrically connected to the control line CL1 via a common gate line CGL. Specifically, the first gate G1 of wiring layer WL1 is electrically connected to a portion of wiring WL2 via a via in insulating layer 71, electrically connected to the common gate line CGL of wiring layer WL3 via a via in insulating layer 72, and electrically connected to the control line CL1 of wiring layer WL4 via a via in insulating layer 73. Figure 3 The image shows multiple cross symbols, which can indicate through holes in the insulating layer.

[0038] Please refer to Figures 3 to 5 In the first switching element T1, the source terminal S1 of the first semiconductor layer SE1 is electrically connected to the first signal line SL1 through wiring layers WL2 and WL3. Specifically, the source terminal S1 is electrically connected to a portion of wiring WL2 through a via in insulating layer 71, to a portion of wiring WL3 through a via in insulating layer 72, and to the first signal line SL1 of wiring layer WL4 through a via in insulating layer 73. The drain terminal D1 of the first semiconductor layer SE1 is electrically connected to the first data line DL1 (see reference) through wiring layers WL2, WL3, and WL4. Figure 4 The diagram shows WL2(D1), WL3(D1), and WL4(D1). The drain terminal D1 is electrically connected to the first data line DL1 of the wiring layer WL3. The drain terminal D1 can extend along the second direction X, and the data line DL1 can extend along the first direction Y. Figures 3 to 5 The design of switching elements T2 and T3 shown can be referred to the above description of switching element T1. For clarity, redundant detailed descriptions are omitted.

[0039] Figure 6 This is a schematic diagram of an electronic device according to a second embodiment of the present disclosure. Figure 6 The electronic device 20 shown is Figure 1The main difference between the electronic devices 10 shown lies in the configuration of the detection circuit 200 included in electronic device 20. Electronic device 20 also includes a third pixel unit PU3, which is disposed within the active region AA1 on substrate SUB1 and electrically connected to the first data line DL1. Figure 6 In the detection circuit 200 shown, the second switching element T2 is disposed between the second pixel unit PU2 and the third pixel unit PU3, the first switching element T1 is disposed between the first pixel unit PU1 and the second pixel unit PU2, and the third pixel unit PU3 is disposed between the second switching element T2 and the third switching element T3. In the first direction Y, the first switching element T1 can be arranged between the first signal line SL1 and the second signal line SL2, the second switching element T2 can be arranged between the second signal line SL2 and the third signal line SL3, and the third signal line SL3 can be arranged between the second switching element T2 and the third switching element T3.

[0040] Please refer to Figure 6 The control line CL1 may include a first segment (connection portion) extending along the first direction Y and a second segment (body portion) extending along the second direction X. Each switching element may have its own control line. For example, the control terminals of switching elements T1, T2, and T3 are electrically connected to control lines QL1, QL2, and QL3, respectively. Specifically, the control line CL1 may include a control line QLc (first segment) extending along the first direction Y and control lines QL1~QL3 (second segments) extending along the second direction X. Control lines QL1~QL3 are electrically connected to control line QLc, and the control signal can be provided by control line QLc. Similarly, the signal line SL1 may include a first segment (connection portion) SL11 extending along the first direction Y and a second segment (body portion) SL12 extending along the second direction X. Similarly, signal line SL2 may include a segment SL21 extending in the Y direction and a segment SL22 extending in the X direction, and signal line SL3 may include a segment SL31 extending in the Y direction and a segment SL32 extending in the X direction. The connection of signal lines SL1 to SL3 can be referred to the above description; for clarity, detailed descriptions are omitted. A first switching element T1 is arranged between signal line SL1 and control line QL1, a second switching element T2 is arranged between signal line SL2 and control line QL2, and a third switching element T3 is arranged between signal line SL3 and control line QL3.

[0041] Figure 7 This is a schematic diagram of an electronic device according to a third embodiment of the present disclosure. Figure 7In this embodiment, electronic device 30 includes a substrate SUB1 having a free shape (e.g., a non-rectangular shape). For example, substrate SUB1 includes a first edge EG1, a second edge EG2, a third edge EG3, and a fourth edge EG4 connected to each other. In some embodiments, the second edge EG2 and the third edge EG3 may be parallel and extend along a second direction X. The first edge EG1 and the fourth edge EG4 may have irregular contours, for example, neither parallel to the first direction Y nor parallel to the second direction X. Substrate SUB1 includes a first region RA, a second region RB, and a third region RC, with the second region RB disposed between the first region RA and the third region RC. In this embodiment, the first region RA may be an irregular region, such as a non-rectangular region having an edge EG1 with an irregular contour (e.g., a curved contour). The third region RC may be an irregular region, such as a non-rectangular region having an edge EG4 with an irregular contour (e.g., a slanted line contour). The second region RB may be a rectangular region.

[0042] Please refer to Figure 7 The detection circuit 300 may include a first detection circuit 300a disposed in the first region RA, a second detection circuit 300b disposed in the second region RB, and a third detection circuit 300c disposed in the third region RC. In the electronic device 30, multiple data lines may be disposed on the substrate SUB1. However, for clarity, only data line DL3 is shown. As described above, multiple data lines DL1 to DL3 are disposed on the substrate SUB1, such as... Figure 8 As shown. Data line DL3 is a data line electrically connected to pixel PX3 in pixel unit PU. Detailed description is omitted here. For ease of explanation, data line DL3 may be referred to as the first data line below.

[0043] Figure 8 It is a display Figure 7 A magnified diagram of the first region RA. Please refer to... Figure 7 and Figure 8 The first detection circuit 300a includes first to third signal lines SL1a-SL3a, first to third switching elements T1a-T3a, and a control line CL1a electrically connected to the first to third switching elements T1a-T3a. The first to third switching elements T1a-T3a may be arranged along a second direction X. In some embodiments, in the detection circuit, the signal lines may include a first signal segment (e.g., a connecting portion SL1a1, SL2a1, or SL3a1) extending along a first direction Y and a second signal segment (e.g., a main body portion SL1a2, SL2a2, or SL3a2) extending along a second direction X. In some embodiments, the control line may include a first control segment (e.g., a connecting portion CL1a1) extending along a first direction Y and a second control segment (e.g., a main body portion CL1a2) extending along a second direction X. Please refer to... Figure 8The signal line connection portions SL1a1 to SL3a1 are configured to receive test signals transmitted from the edge (e.g., edge EG2) of the substrate SUB1, and the main body portions SL1a2 to SL3a2 of the signal lines are electrically connected between the first to third switching elements T1a to T3a and the connection portions SL1a1 to SL3a1, respectively. Test signals can be transmitted to the main body portions SL1a2 to SL3a2 via the connection portions SL1a1 to SL3a1. The control line connection portion CL1a1 is configured to receive control signals transmitted from the edge (e.g., edge EG2) of the substrate SUB1, and the main body portion CL1a2 of the control line is electrically connected between the control terminals of the first to third switching elements T1a to T3a and the connection portion CL1a1, respectively. Control signals can be transmitted to the main body portion CL1a2 via the connection portion CL1a1.

[0044] exist Figure 8 In this circuit, a portion of the detection circuit 300a can be located in an irregular area. For ease of explanation, data line DL3 is used as an example, and it can be referred to as the first data line. The connections between the switching elements, control lines, and signal lines in the detection circuit 300a can be referred to in the above description of the detection circuit 100; detailed descriptions are omitted here. Figure 8 In this configuration, due to the irregular contour of edge EG1, the data line closest to edge EG1 can be divided into two segments, such as DL31 and DL32. Therefore, switching element T3a1 is electrically connected to data line segment DL31, and switching element T3a2 is electrically connected to data line segment DL32. One end of switching element T3a1 is electrically connected to signal line SL3ax1, and one end of switching element T3a2 is electrically connected to signal line SL3ax2. The control terminals of switching elements T3a1 and T3a2 are electrically connected to control lines CLax1 and Clax2, respectively. Control lines CLax1 and Clax2 can extend along the second direction X, and control line CLa1 extending along the direction Y can be electrically connected to control lines CLax1 and CLax2. Figure 7 In the area RA shown, control lines CLax1 and CLax2 are electrically connected to control line CL1a, which contains segments CLy51 and CLy52. Segment CLy51 is closer to edge EG2 than segment CLy52, and segment CLy52 is connected between control segments CLax1 and CLax2.

[0045] Figure 9 It is a display Figure 7 A magnified diagram of the second region RB. Please refer to... Figure 7 and Figure 9In the upper half, the second detection circuit 300b may include first to third signal lines SL1b~SL3b, first to third switching elements T1b~T3b, and a control line CL1b electrically connected to the first to third switching elements T1b~T3b. The first to third signal lines SL1b~SL3b may include connecting portions SL1b1, SL2b1, and SL3b1 extending along a first direction Y, configured to receive test signals transmitted from the edge EG2 of the substrate SUB1, and main bodies SL1b2, SL2b2, and SL3b2 extending along a second direction X and electrically connected to the first to third switching elements T1b~T3b and connecting portions SL1b1~SL3b1, respectively. The test signal is transmitted to the main bodies SL1b2~SL3b2 through the connecting portions SL1b1~SL3b1. The control line CL1b may include a connecting portion CL1b1 extending in the Y direction, configured to receive a control signal transmitted from the edge EG2 of the substrate SUB1, and a main body portion CL1b2 extending in the X direction and electrically connected to the first to third switching elements T1b~T3b and the connecting portion CL1b1, respectively. The control signal is transmitted to the main body portion CL1b2 through the connecting portion CL1b1. Taking the data line DL3 (DL3s) as an example, the number of switching elements T3b electrically connected to the data line DL3 (DL3s) may be singular, thereby achieving single-drive operation.

[0046] In some embodiments, please refer to Figure 9 The additional detection circuit 300b2 can be disposed within the active region AA on the substrate SUB1. (Refer to the additional detection circuit 300b2) Figure 9 The lower half may include control line CLbx2, first to third signal lines SL1b2~SL3b2, and first to third switching elements T1b2~T3b2 electrically connected to the first to third signal lines SL1b2~SL3b2 and control line CLbx2 (see reference). Figure 9(Lower left corner). Taking data line DL3 (DL3m) as an example, the number of switching elements T3b electrically connected to data line DL3 (DL3m) can be multiple. Two or more switching elements can be electrically connected to one data line to achieve multiple drives. For example, two detection circuits 300b and 300b2 are electrically connected to one data line DL3m, and two switching elements T3b1 and T3b2 are electrically connected to one data line DL3m. The additional detection circuit 300b may include switching element T3b2, a corresponding signal line SL3bx2, and a corresponding control line CLbx2. A control terminal of switching element T3b1 is electrically connected to control line CLbx1, and a control terminal of switching element T3b2 is electrically connected to control line CLbx2. The terminals of switching elements T3b1 and T3b2 are electrically connected to signal lines SL3bx1 and SL3bx2, respectively. The control lines CLbx1 and CLbx2 of detection circuit 300b2 can be electrically connected by control line CL1b1. That is, control line CL1b1 can be shared by detection circuits 300b and 300b2. Similarly, the signal lines SL3bx1 and SL3bx2 of detection circuit 300b2 can be electrically connected by signal line SL3b1. That is, signal line SL3b1 can be shared by detection circuits 300b and 300b2.

[0047] Figure 10 It is a display Figure 7 An enlarged schematic diagram of the third region RC. (Compared to...) Figure 9 Similarly, in Figure 10 In this circuit, the detection circuit is positioned within an irregular RC region. Please refer to... Figure 7 and Figure 10 The third detection circuit 300c (refer to) Figure 10 The upper part includes the first to third signal lines SL1c~SL3c, the first to third switching elements T1c~T3c, and the control line CL1c. Figure 10 The arrangement of the detection circuit 300c and Figure 9 The detection circuit is similar to that in 300b, and a detailed description is omitted here.

[0048] and Figure 9 Similarly, in Figure 10 In the middle, an additional detection circuit 300c2 (refer to...) Figure 10 The lower half of the detection circuit (DL3) is disposed within the active region AA on the substrate SUB1. Taking data line DL3 (DL3m) as an example, the detection circuit 300c includes a switching element T3c1 (refer to...). Figure 10 (top left corner), and the additional detection circuit 300c2 includes a switching element T3c2 (see reference). Figure 10(Lower left corner). Switching elements T3c1 and T3c2 are electrically connected to a data line DL3m. The control terminals of switching elements T3c1 and T3c2 are electrically connected to control lines CLcx1 and CLcx2, respectively. The terminals of switching elements T3c1 and T3c2 are electrically connected to signal lines SL3cx1 and SL3cx2, respectively. Signal lines SL3cx1 and SL3cx2 can extend along the second direction X and can be electrically connected to signal line SL3c1 extending along the first direction Y. Control lines CLcx1 and CLcx2 can extend along the second direction X and can be electrically connected to control line CL1c1 extending along the first direction Y. Figure 10 The arrangement of the additional detection circuit 300c2 and Figure 9 The additional detection circuit 300b2 is similar; a detailed description is omitted here. Please refer to [link / reference]. Figure 7 In region RC, control line CL1c may include control segment CLy6 extending along the first direction Y and electrically connected to control line CLcx2 of additional detection circuit 300c2.

[0049] Please refer to Figure 10 Because edge EG4 has an irregular profile, the detection circuit can be modified to detect the data line closest to edge EG4. Specifically, for the data line DL3r closest to edge EG4 (refer to...), Figure 10 (Lower right corner), the data line DL3r can be electrically connected to the additional detection circuit 300c2 for detection. For the data line DL3r, the corresponding signal line can be SL3cx2, and the corresponding control line can be CLcx2. The connections between the switching elements, signal lines, and control lines are as described above; detailed descriptions are omitted here. Figures 8 to 10 In this configuration, switching elements T1a, T1b, or T1c can be positioned between data line DL1 and data line DL2, switching elements T2a, T2b, or T2c (second switching elements) can be positioned between data line DL2 (second data line) and data line DL3 (first data line), and data line DL3 can be positioned between switching elements T2a, T2b, or T2c and switching elements T3a, T3b, or T3c.

[0050] Figure 11 This is a schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. The shape and area of ​​the substrate SUB1 can be referred to... Figure 7 Detailed description omitted here. Figure 11 and Figure 7 The main difference lies in the design of the detection circuit in region RB. Figure 11 The detection circuit layout for the middle region RA and the region RC can be referenced. Figure 7 Detailed description omitted here. Figure 11In the middle, the electronic device includes a detection circuit 300d and an additional detection circuit 300e.

[0051] Please refer to Figure 11 Multiple data lines DL, multiple switching elements, multiple signal lines SL (SL1d, SL2d, SL3d, SL1e, SL2e, SL3e), and multiple control lines CL are disposed on substrate SUB1 in region RB. For ease of explanation, data lines DL3d and DL3e are used as examples. Switching element T3d is electrically connected to signal line SL3d, control line CL1d, and data line DL3d. For clarity, data lines DL2 and DL1, as well as other switching elements connected to signal lines SL1d and SL2d respectively, are omitted. Control line CL1d may include a control segment CLx3 extending in the X direction and CLy3 extending in the Y direction. Similarly, signal line SL3d may include a signal segment SL3dy extending in the first direction Y and a signal segment SL3dx extending in the second direction X.

[0052] Please refer to Figure 11 Switching element T3e is electrically connected to signal line SL3e, control line CL1e, and data line DL3e. For clarity, data lines DL2 and DL1, as well as other switching elements connected to signal lines SL1e and SL2e respectively, are omitted. Similarly, control line CL1e may include a control segment CLx4 extending along the second direction X and a control segment CLy4 extending along the first direction Y.

[0053] Can be Figure 11 This design is modified. In some embodiments, the signal segments extending along the second direction X in regions RA, RB, and RC may be identical, and the control segments extending along the second direction X in regions RA, RB, and RC may be identical. Specifically, the signal segment SL3dx in region RB is electrically connected to the signal segment SL3ax2 in region RA and the signal segment SL3cx2 in region RC. Similarly, the control segment CLx3 in region RB is electrically connected to the control segment CLax2 in region RA and the control segment CLcx2 in region RC. In this case, at least a control segment extending along the Y direction is provided. That is, a control segment including CLy51 and CLy52 and at least one of the control segments CLy3 and CLy6 extending along the first direction Y are provided. Specifically, in some variations, control segment CLy3 is provided, while control segments CLy51, CLy52, and CLy6 are omitted. In other variations, control segments CLy3 and CLy52 are provided, while control segments CLy51 and CLy6 are omitted. Among other changes, control sections CLy51 and CLy52 and control section CLy6 were set up, while control section CLy3 was omitted.

[0054] Please refer to Figure 11 The control terminal of switching element T3d is connected to control line CL1d, and the control terminal of switching element T3e is connected to control line CL1e, and control lines CL1d and CL1e are electrically insulated. Specifically, control lines CLx3 and CLx4 are electrically insulated. Control section CLx4 and control section CLy3 are electrically insulated. Data line DL3d may be disposed adjacent to data line DL3e. In some embodiments, there are no other data lines between data line DL3d and data line DL3e. Alternatively, in other embodiments, data lines DL1 and / or DL2 may be disposed between data line DL3d and data line DL3e, but no other data line DL3 may be disposed between data line DL3d and data line DL3e. Switching elements T3d and T3e may be arranged along the first direction Y.

[0055] Please refer to the following: Figure 11 In other embodiments, the control lines extending along the second direction X in the three regions RA, RB, and RC can be different; that is, the control line CLax2 in region RA, the control line CLx3 in region RB, and the control line CLcx2 in region RC are different and not continuously connected. Each region will have its own control line extending along the first direction Y.

[0056] Figure 12 This is a schematic diagram of an electronic device according to a fifth embodiment of the present disclosure. Figure 12 China Electronics Device 40 and Figure 6 The main difference between the electronic devices 20 is that each control line electrically connected to the switching element includes two segments extending in different directions. Specifically, the control line electrically connected to the switching element T1 includes a first segment (connection portion) QL11 extending along a first direction Y and a second segment (body portion) QL1 extending along a second direction X. Control signals can be provided from the edge of the substrate SUB1 (not shown) through the connection portion QL11. Similarly, the control line electrically connected to the switching element T2 may include two segments QL21 and QL2, and the control line electrically connected to the switching element T3 may include two segments QL31 and QL3. For clarity, detailed descriptions are omitted here.

[0057] Figure 13This is a schematic diagram of an electronic device according to a sixth embodiment of the present disclosure. The electronic device 50 may be or include a monochrome display device. That is, multiple pixel units PU disposed on the substrate SUB1 can emit the same single color. A detection circuit 500 including multiple switching elements T1 is disposed in the active area on the substrate SUB1. Taking one switching element T1 as an example, the switching element T1 is electrically connected to a signal line SL and a data line DL. A control line CL is electrically connected to a control terminal of the switching element T1. The signal line SL may include a connecting portion SLa1 extending along a first direction Y and a main body portion SLa2 extending along a second direction X. The control line CL may include a connecting portion CLa1 extending along the first direction Y and a main body portion CLa2 extending along the second direction X. The switching element T1 is disposed between two adjacent pixel units PX. The connection relationships between the switching elements, control lines, signal lines, and data lines can be referred to the above description, and redundant explanations are omitted here.

[0058] Please refer to Figure 14 The electronic device 60 also includes a test circuit 600. As described above, a pixel PX in the pixel unit PU may contain one or more electronic components, such as a transistor TX1 in pixel PX1. Figure 14 In this context, the symbol DE1 represents an electronic component disposed in a pixel unit PU. Examples of such electronic components can be found above. For instance, the first pixel unit PU may include a driving transistor as an example of electronic component DE1. Test circuit 600 may be electrically connected to the driving transistor DE1. In some embodiments, test circuit 600 may include test pads FB1, FB2, FB3, FB4, FB5, and FB6, electrically connected to the driving transistor DE1 for electrical measurements. For example, test pads FB1 and FB2 may be used to measure electrical characteristics related to the gate of the driving transistor DE1 (e.g., Vg or Vgs-in), test pads FB3 and FB4 may be used to measure electrical characteristics related to the source of the driving transistor DE1 (e.g., Ids or Vs), and test pads FB5 and FB6 may be used to measure electrical characteristics related to the drain of the driving transistor DE1 (e.g., Ids or Vd). In some embodiments, test circuit 600 may be electrically connected to an electronic component disposed in detection circuit 100, such as a first switching element T1 disposed in detection circuit 100. Test pads FB1 to FB6 may be disposed outside the edge of substrate SUB1, for example, on a circuit board, such as a flexible printed circuit (not shown). In some embodiments, test circuit 600 and test pads may be disposed on the first surface FS1 of substrate SUB1, or on the back surface BS2 of substrate SUB1.

[0059] Please refer to Figure 15The electronic device also includes a test circuit 602 disposed within an active region on the substrate SUB1. Specifically, the test circuit 602 may be disposed in the active region AA1, for example, between pixel units PU, for example, between a first pixel PU and a second pixel PU. The test circuit 602 may include test pads TP1, and the number of test pads TP1 may be multiple. In some embodiments, the test circuit 602 may be electrically connected to electronic components disposed in the detection circuit 100, for example, a first switching element T1 disposed in the detection circuit 100.

[0060] In summary, in the electronic device described in the above embodiments, the detection circuit is disposed within the active area on the substrate, thus minimizing the area of ​​the surrounding area of ​​the active area, thereby providing advantages for narrow bezel or bezel-less designs.

Claims

1. An electronic device, characterized in that, Include: The substrate includes an active region; A first data line is disposed on the substrate and extends along a first direction; The first pixel unit is disposed in the active area on the substrate and electrically connected to the first data line; The second pixel unit is disposed in the active area on the substrate and electrically connected to the first data line; as well as A detection circuit is disposed within the active region on the substrate, wherein the detection circuit includes: First signal line; A first switching element is disposed between the first pixel unit and the second pixel unit and electrically connected to the first signal line and the first data line; and The first control line is electrically connected to the control terminal of the first switching element.

2. The electronic device according to claim 1, further comprising: A second data line is disposed on the substrate and extends along the first direction, wherein the first pixel unit and the second pixel unit each include a first pixel and a second pixel, the first pixel is electrically connected to the first data line, and the second pixel is electrically connected to the second data line.

3. The electronic device according to claim 2, wherein the detection circuit further comprises: The second signal line extends along a second direction different from the first direction; and The second switching element is electrically connected to the second data line and the second signal line.

4. The electronic device of claim 3, wherein the first control line is electrically connected to the control terminal of the second switching element, and the detection circuit further includes a common gate line electrically connected to the first control line, the first switching element, and the second switching element.

5. The electronic device of claim 3, wherein the first data line has a first side and a second side disposed opposite to each other, and the second side is closer to the second data line than the first side, wherein the first switching element and the second switching element are located on the first side of the first data line and are arranged along the first direction.

6. The electronic device of claim 3, wherein the second switching element is disposed between the first data line and the second data line, and the first switching element and the second switching element are arranged along the second direction.

7. The electronic device of claim 1, wherein the first signal line includes a first body portion extending along a second direction different from the first direction and a first connection portion extending along a direction different from the second direction, the first body portion being electrically connected between the first switching element and the first connection portion, and wherein the first control line includes a second body portion extending along the second direction and a second connection portion extending along a direction different from the second direction, the second body portion being electrically connected between the control terminal of the first switching element and the second connection portion.

8. The electronic device of claim 1, wherein the substrate includes an irregular region having an edge with an irregular profile, and a portion of the detection circuit is disposed in the irregular region.

9. The electronic device of claim 1, further comprising: An additional detection circuit is disposed on the substrate and located within the active region, wherein the additional detection circuit includes an additional signal line, an additional switching element electrically connected to the additional signal line and the first data line, and an additional control line electrically connected to the control terminal of the additional switching element.

10. The electronic device of claim 1, wherein the first pixel unit comprises electronic components, and the electronic device comprises a test circuit electrically connected to at least one of the first switching element of the detection circuit and the electronic components of the first pixel unit.

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