A display device

Abstract

The application provides a display device, which comprises a display panel, a driving chip and a power supply chip, the display panel comprises a first scanning circuit and a pixel driving circuit, the first scanning circuit provides a scanning signal to the pixel driving circuit, the pixel driving circuit comprises a driving transistor and a switching transistor; the driving chip provides a first scanning control signal to the first scanning circuit; the driving chip is configured to: when an interface power supply signal is powered off to a threshold voltage, judge whether an analog power supply signal is powered off, and trigger a protection mode when the analog power supply signal is not powered off; wherein the interface power supply signal supplies power to the driving chip, and the analog power supply signal supplies power to the power supply chip; in the protection mode, the first scanning control signal controls the waveform of the scanning signal output by the first scanning circuit, and the switching transistor connected with the gate of the driving transistor is turned off. When the display device is abnormally powered off, the problem that the display device produces abnormal display such as bright lines can be avoided.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display device. Background Technology

[0002] TFT (Thin Film Transistor) displays are the mainstream display devices in various laptops and desktops. Each pixel on this type of display is driven by a thin film transistor integrated behind the pixel. A TFT display typically includes a driver chip and a screen. The driver chip controls the operating state of the thin film transistors, thereby enabling the screen to display the corresponding image.

[0003] An abnormal power outage of the display device will cause display abnormalities. Summary of the Invention

[0004] This invention provides a display device that can avoid abnormal display problems such as flashing lines when the display device is abnormally powered off.

[0005] This invention provides a display device, including a display panel, a driver chip, and a power chip. The display panel includes a first scanning circuit and a pixel driving circuit. The first scanning circuit provides a scanning signal to the pixel driving circuit. The pixel driving circuit includes a driving transistor and a switching transistor.

[0006] The power chip is electrically connected to the driver chip and the pixel driver circuit, and supplies power to the driver chip and the pixel driver circuit; the driver chip is electrically connected to the first scanning circuit and the pixel driver circuit, and provides a first scanning control signal to the first scanning circuit;

[0007] The driver chip is configured to: determine whether the analog power signal is powered down when the interface power supply signal drops to a threshold voltage, and trigger a protection mode when the analog power signal is not powered down; wherein the interface power supply signal supplies power to the driver chip, and the analog power signal supplies power to the power chip.

[0008] In the protection mode, the first scan control signal controls the waveform of the scan signal output by the first scan circuit, thereby turning off the switching transistor connected to the gate of the driving transistor.

[0009] Optionally, the driver chip is configured to: determine whether a preset instruction has been received; and if the preset instruction has not been received, determine whether the interface power supply signal has dropped to the threshold voltage.

[0010] When the driver chip receives the preset instruction, it enters sleep mode.

[0011] Optionally, the threshold voltage is greater than or equal to 1.4V and less than or equal to 1.6V.

[0012] Optionally, the plurality of switching transistors include a threshold compensation transistor and a first reset transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor; the first terminal of the first reset transistor is connected to either the first terminal of the threshold compensation transistor or the second terminal of the threshold compensation transistor.

[0013] The gate of the threshold compensation transistor and / or the gate of the first reset transistor are electrically connected to the first scan circuit.

[0014] When the threshold compensation transistor and the first reset transistor are N-type transistors, in the protection mode, the first scan control signal is a first voltage; when the threshold compensation transistor and the first reset transistor are P-type transistors, in the protection mode, the first scan control signal is a second voltage; the first voltage is less than the second voltage.

[0015] Preferably, the first scan control signal generates a rising edge or falling edge of the voltage at the moment the protection mode is triggered.

[0016] Optionally, the display panel further includes a second scanning circuit, which provides a light emission control signal to the pixel driving circuit;

[0017] The driving chip is electrically connected to the second scanning circuit; the driving chip provides a second scanning control signal to the second scanning circuit; in the protection mode, the second scanning control signal controls the waveform of the light emission control signal, turning off the switching transistor connected to the first terminal and / or the second terminal of the driving transistor.

[0018] Optionally, the plurality of switching transistors include a first light-emitting control transistor and a second light-emitting control transistor, wherein the first terminal of the first light-emitting control transistor receives a first power supply voltage, and the second terminal of the first light-emitting control transistor is electrically connected to the second terminal of the driving transistor; the first terminal of the second light-emitting control transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is electrically connected to the anode of the light-emitting element.

[0019] The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the second scanning circuit.

[0020] When the first light-emitting control transistor and the second light-emitting control transistor are N-type transistors, in the protection mode, the second scan control signal is a first voltage; when the first light-emitting control transistor and the second light-emitting control transistor are P-type transistors, in the protection mode, the second scan control signal is a second voltage; the first voltage is less than the second voltage.

[0021] Optionally, the display panel further includes a third scanning circuit that provides a scanning signal to the pixel driving circuit;

[0022] The driver chip is electrically connected to the third scanning circuit; the driver chip provides a third scanning control signal to the third scanning circuit;

[0023] The switching transistor includes a data writing transistor, the first terminal of which is electrically connected to the second terminal of the driving transistor, and the gate of which is electrically connected to the third scanning circuit.

[0024] In the protection mode, the third scan control signal controls the waveform of the scan signal output by the third scan circuit and turns off the data writing transistor.

[0025] Optionally, when the data writing transistor is an N-type transistor, in the protection mode, the third scan control signal is a first voltage; when the data writing transistor is a P-type transistor, in the protection mode, the third scan control signal is a second voltage; the first voltage is less than the second voltage.

[0026] Preferably, the third scan control signal generates a rising edge or falling edge of the voltage at the moment the protection mode is triggered.

[0027] Optionally, the first terminal of the data writing transistor is electrically connected to the data signal terminal; in the protection mode, the driver chip provides a ground voltage to the data signal terminal.

[0028] Optionally, the plurality of switching transistors include a threshold compensation transistor and a first reset transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor; the first terminal of the first reset transistor is connected to either the first terminal of the threshold compensation transistor or the second terminal of the threshold compensation transistor.

[0029] The gate of the threshold compensation transistor and / or the gate of the first reset transistor are electrically connected to the first scan circuit.

[0030] In the protection mode, the first reset voltage provided by the driver chip to the second terminal of the first reset transistor is set to ground voltage.

[0031] In the display device provided in this embodiment of the invention, the driver chip detects the interface power supply signal and the analog power signal. When the display device abnormally powers down, i.e., the interface power supply signal powers down before the analog power signal, a protection mode is triggered. In the protection mode, the driver chip controls the waveform of the first scan control signal, causing the first scan control signal to control the waveform of the scan signal output by the first scan circuit. This, in turn, turns off the switching transistor connected to the gate of the driving transistor, blocking the signal path to the gate of the driving transistor, thereby preventing abnormal display problems such as flashing lines from occurring in the display device. Attached Figure Description

[0032] Figure 1 This is a timing diagram illustrating the normal power-down process of a display device.

[0033] Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0035] Figure 4 A timing diagram illustrating an abnormal power-down provided in an embodiment of the present invention;

[0036] Figure 5 A flowchart of a control method for abnormal power-off provided in an embodiment of the present invention;

[0037] Figure 6 A timing diagram illustrating another abnormal power-down provided in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of another display device provided in an embodiment of the present invention;

[0039] Figure 8 A schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0040] Figure 9 A timing diagram illustrating another abnormal power-down provided in an embodiment of the present invention;

[0041] Figure 10 This is a timing diagram illustrating another abnormal power-down provided in an embodiment of the present invention. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0043] Figure 1 This is a timing diagram illustrating the normal power-down process of a display device, for reference. Figure 1 When the display device powers down normally, such as when the user clicks the power button, the display device first enters sleep mode and then powers off. Upon receiving instructions 28 and 10, the driver chip first executes the power-down of the analog power signal VCI, and then executes the power-down of the interface power signal VDDIO. Since the power-down of the analog power signal VCI is completed when the interface power signal VDDIO is powered down, there is no power signal to provide power to the pixel driving circuit, and therefore no image is displayed, thus preventing abnormal display.

[0044] When the display device experiences an abnormal power-down, the interface power supply signal VDDIO fails before the analog power signal VCI, causing abnormal display issues such as flashing lines. This abnormal power-down can also be caused by the user forcibly pressing the power button to shut down the display when it freezes.

[0045] Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. Figure 4 This is a timing diagram illustrating an abnormal power-down provided in an embodiment of the present invention, with reference to... Figures 2-4 The display device includes a display panel 100, a driver chip 31, and a power supply chip 32. The display panel 100 includes a first scanning circuit 21 and a pixel driving circuit 102. The first scanning circuit 21 provides scanning signals to the pixel driving circuit 102, which includes a driving transistor T1 and a switching transistor. The driving transistor T1 is used to provide driving current to the light-emitting element LD.

[0046] Power chip 32 is electrically connected to driver chip 31 and pixel driver circuit 102, supplying power to both. Power chip 32 provides driver chip 31 with digital power supply voltage DVDD. The power signal provided by power chip 32 to pixel driver circuit 102 includes a first power supply voltage ELVDD and a second power supply voltage ELVSS. The voltage value of the first power supply voltage ELVDD is greater than the voltage value of the second power supply voltage ELVSS. Driver chip 31 is electrically connected to first scanning circuit 21 and pixel driver circuit 102, providing first scanning control signal SIN-N to first scanning circuit 21. Driver chip 31 provides data signal Source to pixel driver circuit 102. In some embodiments, driver chip 31 also provides at least one reset voltage to pixel driver circuit 102.

[0047] The driver chip 31 is configured to: when the interface power supply signal VDDIO drops to the threshold voltage Vth, determine whether the analog power supply signal VCI has been powered down, and trigger the protection mode if the analog power supply signal VCI has not been powered down. The interface power supply signal VDDIO supplies power to the driver chip 31, and the analog power supply signal VCI supplies power to the power supply chip 32.

[0048] In protection mode, the first scan control signal SIN-N controls the waveform of the scan signal output by the first scan circuit 21, turning off the switching transistor connected to the gate of the driving transistor T1.

[0049] In the display device provided in this embodiment of the invention, the driver chip 31 detects the interface power supply signal VDDIO and the analog power signal VCI. When the display device abnormally powers down, i.e., when the interface power supply signal VDDIO powers down before the analog power signal VCI, a protection mode is triggered. In the protection mode, the driver chip 31 controls the waveform of the first scan control signal SIN-N, so that the first scan control signal SIN-N controls the waveform of the scan signal output by the first scan circuit 21, thereby turning off the switching transistor connected to the gate of the driving transistor T1, blocking the signal path to the gate of the driving transistor T1, and thus avoiding abnormal display problems such as flashing lines in the display device.

[0050] Figure 5 A flowchart of a control method for abnormal power-off provided in an embodiment of the present invention is shown below. Figures 2-5 The abnormal power-down control method is executed by the driver chip 31. This method includes:

[0051] S101. Determine whether a preset instruction has been received.

[0052] In this step, the driver chip 31 enters sleep mode upon receiving a preset instruction. This preset instruction can be instruction 28 or 10. Upon receiving instruction 28 or 10, the driver chip first powers down the analog power signal VCI, and then powers down the interface power supply signal VDDIO.

[0053] S102. When no preset instruction is received, determine whether the interface power supply signal has dropped to the threshold voltage.

[0054] In this step, the driver chip 31 detects the voltage value of the interface power supply signal VDDIO and compares the detected voltage value of the interface power supply signal VDDIO with the threshold voltage Vth to determine whether the interface power supply signal VDDIO has dropped to the threshold voltage Vth.

[0055] S103. When the interface power supply signal drops to the threshold voltage, determine whether the analog power supply signal is powered off.

[0056] In this step, the driver chip 31 detects the voltage value of the analog power signal VCI to determine whether the analog power signal VCI is powered down. Powering down means that the voltage value changes to the ground voltage GND.

[0057] S104. When the analog power signal is not powered off, the protection mode is triggered.

[0058] In this step, when the analog power signal VCI is not powered down, the interface power supply signal VDDIO powers down before the analog power signal VCI, causing the display device to power down abnormally. Therefore, the protection mode is triggered as soon as the interface power supply signal VDDIO begins to drop to the threshold voltage Vth. During the process of the interface power supply signal VDDIO dropping from the threshold voltage Vth to the ground voltage GND, the protection mode prevents abnormal display issues such as flashing lines from occurring on the display device.

[0059] S105. When the analog power signal is turned off, the protection mode is not triggered.

[0060] In this step, as the interface power supply signal VDDIO drops from the threshold voltage Vth to the ground voltage GND, the analog power signal VCI has already been powered down. The power chip 32 no longer supplies the first power supply voltage ELVDD and the second power supply voltage ELVSS to the pixel driving circuit 102. The light-emitting element LD will not emit light. The display panel 100 will not display any image, thus preventing any abnormal display.

[0061] Optionally, refer to Figures 2-4The threshold voltage Vth is greater than or equal to 1.4V and less than or equal to 1.6V. Typically, the operating voltage of the interface power supply signal VDDIO is 1.8V. If the threshold voltage Vth is set too high, a protection mode will be triggered when the voltage of the interface power supply signal VDDIO fluctuates normally, causing the display panel 100 to fail to display correctly. If the threshold voltage Vth is set too low, abnormal display may easily occur when the interface power supply signal VDDIO drops to the threshold voltage Vth. This embodiment of the invention sets the threshold voltage Vth to be greater than or equal to 1.4V and less than or equal to 1.6V. This avoids both abnormal display caused by normal fluctuations in the voltage of the interface power supply signal VDDIO and abnormal display during the process of the interface power supply signal VDDIO dropping to the threshold voltage Vth.

[0062] Optionally, refer to Figures 2-4 The plurality of switching transistors includes a threshold compensation transistor T3 and a first reset transistor T4. The first terminal of the threshold compensation transistor T3 is electrically connected to the first terminal of the driving transistor T1, and the second terminal of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1. The first terminal of the first reset transistor T4 is connected to the second terminal of the threshold compensation transistor T3. In other embodiments, the first terminal of the first reset transistor T4 may also be connected to the first terminal of the threshold compensation transistor T3.

[0063] The gate of threshold compensation transistor T3 and / or the gate of first reset transistor T4 are electrically connected to the first scan circuit 21. That is, the first scan circuit 21 includes multiple cascaded shift registers. The output of each shift register in the first scan circuit 21 provides a first-type scan signal, ScanN, to the pixel driving circuit 102. The first-type scan signal ScanN is applied to the first scan signal terminal S1 and / or the third scan signal terminal S3. The gate of threshold compensation transistor T3 is electrically connected to the third scan signal terminal S3, and the gate of first reset transistor T4 is electrically connected to the first scan signal terminal S1.

[0064] exist Figure 3 The illustration uses N-type transistors, specifically threshold compensation transistor T3 and first reset transistor T4, as an example, but is not limited to this. When threshold compensation transistor T3 and first reset transistor T4 are N-type transistors, in protection mode, the first scan control signal SIN-N is a first voltage, which is lower than a second voltage; therefore, the first voltage is a low voltage. In other embodiments, when threshold compensation transistor T3 and first reset transistor T4 are P-type transistors, in protection mode, the first scan control signal SIN-N is a second voltage, which is a high voltage.

[0065] Preferably, the first scan control signal SIN-N generates a rising edge or falling edge of the voltage at the moment the protection mode is triggered. For example... Figure 3 As shown, taking N-type transistors as an example, with threshold compensation transistor T3 and first reset transistor T4, at the first moment K1, the driver chip 31 triggers the protection mode, and the first scan control signal SIN-N generates a falling edge of the voltage. It can be understood that if threshold compensation transistor T3 and first reset transistor T4 were P-type transistors, then at the first moment K1, the first scan control signal SIN-N generates a rising edge of the voltage.

[0066] For example, refer to Figures 2-4 The second terminal of the first reset transistor T4 receives the first reset voltage VREF1. When the display device is abnormally powered down, a protection mode is triggered, and the first scan control signal SIN-N controls the first reset transistor T4 to turn off through the first scan circuit 21. This blocks the signal path of the first reset voltage VREF1 to the gate of the driving transistor T1, preventing abnormal display problems such as flashing lines from occurring on the display device.

[0067] Optionally, refer to Figures 2-4 The display panel 100 also includes a second scanning circuit 22, which provides a light emission control signal EM to the pixel driving circuit 102. The driving chip 31 is electrically connected to the second scanning circuit 22. The driving chip 31 provides a second scanning control signal EIN to the second scanning circuit 22. In protection mode, the second scanning control signal EIN controls the waveform of the light emission control signal EM, turning off the switching transistor connected to the first and / or second terminals of the driving transistor T1. This blocks the propagation path of the driving current through the driving transistor T1, thereby preventing abnormal display problems such as flashing lines from occurring in the display device.

[0068] Optionally, refer to Figures 2-4 The system includes multiple switching transistors, including a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The first terminal of the first light-emitting control transistor T5 receives a first power supply voltage ELVDD, and its second terminal is electrically connected to the second terminal of a driving transistor T1. The first terminal of the second light-emitting control transistor T6 is electrically connected to the first terminal of the driving transistor T1, and its second terminal is electrically connected to the anode of the light-emitting element LD. The cathode of the light-emitting element LD receives a second power supply voltage ELVSS.

[0069] The gates of both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are electrically connected to the second scanning circuit 22. That is, the second scanning circuit 22 includes multiple cascaded shift registers, and the outputs of these shift registers provide a light-emitting control signal EM to the pixel driving circuit 102. The light-emitting control signal EM is applied to the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6.

[0070] When the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type transistors, in protection mode, the second scan control signal EIN is a second voltage. The second voltage is a high voltage. In other embodiments, when the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are N-type transistors, in protection mode, the second scan control signal EIN is a first voltage, the first voltage is less than the second voltage, and the first voltage is a low voltage.

[0071] For example, such as Figure 3 As shown, taking the first light-emitting control transistor T5 and the second light-emitting control transistor T6 as P-type transistors, at the first moment K1, the driver chip 31 triggers the protection mode, and the second scan control signal EIN continues the previous high voltage (for example, it can be the second voltage).

[0072] In one embodiment, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are N-type transistors. At the first moment K1, the driver chip 31 triggers the protection mode, and the second scan control signal EIN continues the previous low voltage (for example, it can be the first voltage).

[0073] In another embodiment, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are N-type transistors. At the first moment K1, the driver chip 31 triggers the protection mode, and the second scan control signal EIN generates the rising edge of the voltage.

[0074] Optionally, refer to Figures 2-4The display panel 100 also includes a third scanning circuit 23, which provides a scanning signal to the pixel driving circuit 102. The driving chip 31 is electrically connected to the third scanning circuit 23. The driving chip 31 provides a third scanning control signal SIN-P to the third scanning circuit 23. The switching transistor includes a data writing transistor T2, whose first terminal is electrically connected to the second terminal of the driving transistor T1, and whose gate is electrically connected to the third scanning circuit 23. That is, the third scanning circuit 23 includes multiple cascaded shift registers. The output of the shift registers in the third scanning circuit 23 provides a second-type scanning signal, ScanP, to the pixel driving circuit 102. The second-type scanning signal ScanP is applied to the second scanning signal terminal S2. The gate of the data writing transistor T2 is electrically connected to the second scanning signal terminal S2. In protection mode, the third scanning control signal SIN-P controls the waveform of the scanning signal output by the third scanning circuit 23, turning off the data writing transistor T2. This blocks the propagation path of the data signal Source through the data writing transistor T2, preventing abnormal display problems such as flashing lines from appearing on the display device.

[0075] Furthermore, the switching transistor in the pixel driving circuit 102 also includes a second reset transistor T7. The first terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element LD, and the second terminal of the second reset transistor T7 receives a first reset voltage VREF1. In other embodiments, the second terminal of the second reset transistor T7 may also receive a reset voltage different from the first reset voltage VREF1. The gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal S4, which receives a second type of scan signal ScanP. In protection mode, the third scan control signal SIN-P controls the waveform of the scan signal output by the third scan circuit 23, turning off the second reset transistor T7. This blocks the path of the first reset voltage VREF1 propagating through the second reset transistor T7, preventing abnormal display problems such as flashing lines from occurring on the display device.

[0076] Optionally, refer to Figures 2-4 ,exist Figure 3 The illustration uses a P-type transistor as an example for data writing transistor T2, but it is not limited to this. When data writing transistor T2 is a P-type transistor, in protection mode, the third scan control signal SIN-P is the second voltage, the first voltage is less than the second voltage, and the second voltage is a high voltage. In other embodiments, when data writing transistor T2 is an N-type transistor, in protection mode, the third scan control signal SIN-P is the first voltage. The first voltage is a low voltage.

[0077] Preferably, the third scan control signal SIN-P generates a rising or falling edge of the voltage at the moment the protection mode is triggered. For example... Figure 3 As shown, taking the data writing transistor T2 as a P-type transistor as an example, at the first moment K1, the driver chip 31 triggers the protection mode, and the third scan control signal SIN-P generates a rising edge of the voltage. It can be understood that if the data writing transistor T2 is an N-type transistor, then at the first moment K1, the third scan control signal SIN-P generates a falling edge of the voltage.

[0078] Figure 6 This is another timing diagram of abnormal power-down provided in an embodiment of the present invention, referred to... Figure 2 , Figure 3 and Figure 6 The first terminal of the data writing transistor T2 is electrically connected to the data signal terminal DATA. The data signal terminal DATA receives the data signal Source sent from the driver chip 31. In one embodiment, the data signal terminal DATA can be directly connected to the driver chip 31. In another embodiment, the data signal terminal DATA can be connected to the driver chip 31 through a multiplexer circuit. One input terminal of the multiplexer circuit is connected to an interface of the driver chip 31, and one output terminal of the multiplexer circuit is connected to a data line (in...). Figure 2 (Not shown in the image), one input terminal corresponds to at least two output terminals. In protection mode, the driver chip 31 provides a ground voltage GND to the data signal terminal DATA. That is, in protection mode, when the data signal Source is powered down, the driver chip 31 does not provide a positive data signal Source to the data signal terminal DATA. Even if the data writing transistor T2 is mistakenly turned on, and the ground voltage GND is written to the second terminal of the driver transistor T1 through the turned-on data writing transistor T2, it will not cause abnormal display problems.

[0079] Optionally, refer to Figure 2 , Figure 3 and Figure 6 In protection mode, the driver chip 31 provides a first reset voltage VREF1 to the second terminal of the first reset transistor T4. The first reset voltage VREF1 is set to ground voltage GND. That is, in protection mode, the first reset voltage VREF1 is de-energized, and the driver chip 31 does not provide a negative first reset voltage VREF1 to the second terminal of the first reset transistor T4. Even if the first reset transistor T4 is mistakenly turned on, and the ground voltage GND is written to the gate of the driver transistor T1 through the turned-on first reset transistor T4, it will not cause abnormal display problems.

[0080] For example, the pixel driving circuit 102 further includes a capacitor Cst, the first plate of which is electrically connected to the first electrode of the first light-emitting control transistor T5, and the second plate of which is electrically connected to the gate of the driving transistor T1.

[0081] The above embodiments illustrate the pixel driving circuit 102 as a 7T1C, but are not limited thereto. In other embodiments, the pixel driving circuit 102 may have other numbers of transistors, capacitors, and / or other connection relationships.

[0082] Figure 7 This is a schematic diagram of another display device provided in an embodiment of the present invention. Figure 7 The omitted power chip 32 and other structures can be arranged according to... Figure 2 Configure it as shown. Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Figure 9 This is another timing diagram of abnormal power-down provided in an embodiment of the present invention, referred to... Figures 7-9 The two first scanning circuits 21 include a first sub-scanning circuit 211 and a second sub-scanning circuit 212. Correspondingly, the first scan control signal SIN-N applied to the first sub-scanning circuit 211 is the first sub-scanning control signal SIN-N1, and the first scan control signal SIN-N applied to the second sub-scanning circuit 212 is the second sub-scanning control signal SIN-N2. The two third scanning circuits 23 include a third sub-scanning circuit 231 and a fourth sub-scanning circuit 232. Correspondingly, the third scan control signal SIN-P applied to the third sub-scanning circuit 231 is the third sub-scanning control signal SIN-P1, and the third scan control signal SIN-P applied to the fourth sub-scanning circuit 232 is the fourth sub-scanning control signal SIN-P2.

[0083] The first terminal of the first reset transistor T4 is connected to the first terminal of the threshold compensation transistor T3. The gate of the first reset transistor T4 is electrically connected to the first scan signal terminal S1, and the gate of the threshold compensation transistor T3 is electrically connected to the third scan signal terminal S3. The first sub-scan circuit 211 is electrically connected to the first scan signal terminal S1. The second sub-scan circuit 211 is electrically connected to the third scan signal terminal S3. When the display device is abnormally powered down, a protection mode is triggered. The first sub-scan control signal SIN-N1 controls the first reset transistor T4 to turn off through the first sub-scan circuit 211. The second sub-scan control signal SIN-N2 controls the threshold compensation transistor T3 to turn off through the second sub-scan circuit 212. This blocks the propagation path of the first reset voltage VREF1 to the gate of the driving transistor T1, preventing abnormal display problems such as flashing lines from occurring on the display device.

[0084] The second terminal of the second reset transistor T7 receives the second reset voltage VREF2. The pixel driving circuit 102 also includes a third reset transistor T8, the first terminal of which is electrically connected to the first terminal of the driving transistor T1, and the second terminal of the third reset transistor T8 receives the third reset voltage VREF3.

[0085] The gate of data writing transistor T2 is electrically connected to the second scan signal terminal S2. The gates of the second reset transistor T7 and the third reset transistor T8 are both electrically connected to the fourth scan signal terminal S4. The third sub-scan circuit 231 is electrically connected to the second scan signal terminal S2. The fourth sub-scan circuit 231 is electrically connected to the fourth scan signal terminal S4. When the display device is abnormally powered down, a protection mode is triggered. The third sub-scan control signal SIN-P1 controls the data writing transistor T2 to turn off through the third sub-scan circuit 231. This blocks the propagation path of the data signal Source, preventing abnormal display problems such as flashing lines. The fourth sub-scan control signal SIN-P2 controls the second reset transistor T7 and the third reset transistor T8 to turn off through the fourth sub-scan circuit 232. This blocks the propagation path of the second reset voltage VREF2 and the third reset voltage VREF3, preventing abnormal display problems such as flashing lines.

[0086] For example, such as Figure 9 As shown, the first sub-scan control signal SIN-N1 and the second sub-scan control signal SIN-N2 have the same pulse width at the first time point K1. In other embodiments, at the first time point K1, the pulse width of the second sub-scan control signal SIN-N2 is greater than the pulse width of the first sub-scan control signal SIN-N1.

[0087] Figure 10 This is another timing diagram of abnormal power-down provided in an embodiment of the present invention, referred to... Figures 7-10 In protection mode, the first reset voltage VREF1, the second reset voltage VREF2, and the third reset voltage VREF3 are set to ground voltage GND. Even if the threshold compensation transistor T3, the first reset transistor T4, the second reset transistor T7, and the third reset transistor T8 are mistakenly turned on, it will not cause abnormal display problems. The first reset voltage VREF1, the second reset voltage VREF2, and the third reset voltage VREF3 are provided by the driver chip 31.

[0088] For example, refer to Figure 2The display panel 100 also includes a substrate 101, on which a pixel driving circuit 102, a first scanning circuit 21, a second scanning circuit 22, and a third scanning circuit 23 are disposed. The driving chip 31 can be bonded to the substrate 101, or disposed on a flexible circuit board and bonded to the substrate 101 via the flexible circuit board. The power chip 32 can be bonded to the substrate 101, or disposed on a flexible circuit board and bonded to the substrate 101 via the flexible circuit board.

[0089] The display panel 100 includes a display area AA and a non-display area NAA. Multiple pixel driving circuits 102 are arranged in an array in the display area AA. A first scanning circuit 21, a second scanning circuit 22, and a third scanning circuit 23 are located in the non-display area NAA.

[0090] Figure 2 The diagram exemplarily illustrates that the driver chip 31 provides an on-gate voltage VGH and an off-gate voltage VGL to the first scanning circuit 21. The driver chip 31 can provide the on-gate voltage VGH and off-gate voltage VGL to the first scanning circuit 21, the second scanning circuit 22, and the third scanning circuit 23, where the on-gate voltage VGH is greater than the off-gate voltage VGL. The driver chip 31 can also provide a clock signal CLOCK to the first scanning circuit 21, the second scanning circuit 22, and the third scanning circuit 23. The on-gate voltage VGH, the off-gate voltage VGL, the clock signal CLOCK, and the first scan control signal SIN-N jointly control the waveform of the output signal of the first scanning circuit 21. The on-gate voltage VGH, the off-gate voltage VGL, the clock signal CLOCK, and the second scan control signal EIN jointly control the waveform of the output signal of the second scanning circuit 22. The on-gate voltage VGH, the off-gate voltage VGL, the clock signal CLOCK, and the third scan control signal SIN-P jointly control the waveform of the output signal of the third scanning circuit 23.

[0091] For example, the display device further includes a motherboard 33, which provides an analog power signal VCI to a power chip 32. The power chip 32 generates a first power supply voltage ELVDD and a second power supply voltage ELVSS based on the analog power signal VCI. The motherboard 33 provides an interface power supply signal VDDIO to a driver chip 31.

[0092] For example, refer to Figures 2-4 At the second moment K2, the voltage of the interface power supply signal VDDIO changes to ground voltage GND, and the interface power supply signal VDDIO is powered down. The protection mode is turned off at or after the second moment K2. Therefore, before the interface power supply signal VDDIO becomes ground voltage GND, the protection mode can prevent abnormal display.

[0093] At the third moment K3, the analog power signal VCI changes to ground voltage GND, and the analog power signal VCI is powered down. The first scan control signal SIN-N, the second scan control signal EIN, and the third scan control signal SIN-P begin to power down, and eventually power down to ground voltage GND.

[0094] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display device, characterized in that, The device includes a display panel, a driver chip, and a power chip. The display panel includes a first scanning circuit and a pixel driving circuit. The first scanning circuit provides a scanning signal to the pixel driving circuit. The pixel driving circuit includes a driving transistor and a switching transistor. The power chip is electrically connected to the driver chip and the pixel driver circuit, and supplies power to the driver chip and the pixel driver circuit; the driver chip is electrically connected to the first scanning circuit and the pixel driver circuit, and provides a first scanning control signal to the first scanning circuit; The driver chip is configured to: determine whether the analog power signal is powered down when the interface power supply signal drops to a threshold voltage, and trigger a protection mode when the analog power signal is not powered down; wherein the interface power supply signal supplies power to the driver chip, and the analog power signal supplies power to the power chip. In the protection mode, the first scan control signal controls the waveform of the scan signal output by the first scan circuit, thereby turning off the switching transistor connected to the gate of the driving transistor.

2. The display device according to claim 1, characterized in that, The driver chip is configured to: determine whether a preset instruction has been received; and if the preset instruction has not been received, determine whether the interface power supply signal has dropped to the threshold voltage. When the driver chip receives the preset instruction, it enters sleep mode.

3. The display device according to claim 1, characterized in that, The threshold voltage is greater than or equal to 1.4V and less than or equal to 1.6V.

4. The display device according to claim 1, characterized in that, The plurality of switching transistors include a threshold compensation transistor and a first reset transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor; the first terminal of the first reset transistor is connected to either the first terminal of the threshold compensation transistor or the second terminal of the threshold compensation transistor. The gate of the threshold compensation transistor and / or the gate of the first reset transistor are electrically connected to the first scan circuit. When the threshold compensation transistor and the first reset transistor are N-type transistors, in the protection mode, the first scan control signal is a first voltage; when the threshold compensation transistor and the first reset transistor are P-type transistors, in the protection mode, the first scan control signal is a second voltage; the first voltage is less than the second voltage. Preferably, the first scan control signal generates a rising edge or falling edge of the voltage at the moment the protection mode is triggered.

5. The display device according to claim 1, characterized in that, The display panel further includes a second scanning circuit, which provides a light emission control signal to the pixel driving circuit. The driver chip is electrically connected to the second scanning circuit; the driver chip provides a second scanning control signal to the second scanning circuit; In the protection mode, the second scan control signal controls the waveform of the light emission control signal to turn off the switching transistor connected to the first terminal and / or the second terminal of the driving transistor.

6. The display device according to claim 5, characterized in that, The plurality of switching transistors include a first light-emitting control transistor and a second light-emitting control transistor, wherein the first terminal of the first light-emitting control transistor receives a first power supply voltage, and the second terminal of the first light-emitting control transistor is electrically connected to the second terminal of the driving transistor; The first terminal of the second light-emitting control transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is electrically connected to the anode of the light-emitting element; The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the second scanning circuit. When the first light-emitting control transistor and the second light-emitting control transistor are N-type transistors, in the protection mode, the second scan control signal is a first voltage; when the first light-emitting control transistor and the second light-emitting control transistor are P-type transistors, in the protection mode, the second scan control signal is a second voltage; the first voltage is less than the second voltage.

7. The display device according to claim 1, characterized in that, The display panel further includes a third scanning circuit, which provides a scanning signal to the pixel driving circuit. The driver chip is electrically connected to the third scanning circuit; the driver chip provides a third scanning control signal to the third scanning circuit; The switching transistor includes a data writing transistor, the first terminal of which is electrically connected to the second terminal of the driving transistor, and the gate of which is electrically connected to the third scanning circuit. In the protection mode, the third scan control signal controls the waveform of the scan signal output by the third scan circuit and turns off the data writing transistor.

8. The display device according to claim 7, characterized in that, When the data writing transistor is an N-type transistor, in the protection mode, the third scan control signal is a first voltage; when the data writing transistor is a P-type transistor, in the protection mode, the third scan control signal is a second voltage; the first voltage is less than the second voltage. Preferably, the third scan control signal generates a rising edge or falling edge of the voltage at the moment the protection mode is triggered.

9. The display device according to claim 7, characterized in that, The first terminal of the data writing transistor is electrically connected to the data signal terminal; in the protection mode, the driver chip provides a ground voltage to the data signal terminal.

10. The display device according to claim 1, characterized in that, The plurality of switching transistors include a threshold compensation transistor and a first reset transistor, wherein the first terminal of the threshold compensation transistor is electrically connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor; the first terminal of the first reset transistor is connected to either the first terminal of the threshold compensation transistor or the second terminal of the threshold compensation transistor. The gate of the threshold compensation transistor and / or the gate of the first reset transistor are electrically connected to the first scan circuit. In the protection mode, the first reset voltage provided by the driver chip to the second terminal of the first reset transistor is set to the ground voltage.

Images